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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_top_apbreg IS
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
39 nb_burst_available_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
41 delta_snapshot_size : INTEGER := 16;
42 delta_f2_f0_size : INTEGER := 10;
42 delta_f2_f0_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
43 delta_f2_f1_size : INTEGER := 10;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq : INTEGER := 0);
48 pirq : INTEGER := 0);
49 PORT (
49 PORT (
50 -- AMBA AHB system signals
50 -- AMBA AHB system signals
51 HCLK : IN STD_ULOGIC;
51 HCLK : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
52 HRESETn : IN STD_ULOGIC;
53
53
54 -- AMBA APB Slave Interface
54 -- AMBA APB Slave Interface
55 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
56 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
57
57
58 ---------------------------------------------------------------------------
58 ---------------------------------------------------------------------------
59 -- Spectral Matrix Reg
59 -- Spectral Matrix Reg
60 -- IN
60 -- IN
61 ready_matrix_f0_0 : IN STD_LOGIC;
61 ready_matrix_f0_0 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
62 ready_matrix_f0_1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
63 ready_matrix_f1 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
64 ready_matrix_f2 : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
65 error_anticipating_empty_fifo : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
66 error_bad_component_error : IN STD_LOGIC;
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68
68
69 -- OUT
69 -- OUT
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
70 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
71 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
72 status_ready_matrix_f1 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
73 status_ready_matrix_f2 : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
74 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
75 status_error_bad_component_error : OUT STD_LOGIC;
76
76
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
78 config_active_interruption_onError : OUT STD_LOGIC;
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
84 ---------------------------------------------------------------------------
85 -- WaveForm picker Reg
85 -- WaveForm picker Reg
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90
90
91 -- OUT
91 -- OUT
92 data_shaping_BW : OUT STD_LOGIC;
92 data_shaping_BW : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
93 data_shaping_SP0 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
94 data_shaping_SP1 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
95 data_shaping_R0 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
96 data_shaping_R1 : OUT STD_LOGIC;
97
97
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
98 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
99 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
99 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
100 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
100 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
101 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
101 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
102 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
102 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
103
103
104 enable_f0 : OUT STD_LOGIC;
104 enable_f0 : OUT STD_LOGIC;
105 enable_f1 : OUT STD_LOGIC;
105 enable_f1 : OUT STD_LOGIC;
106 enable_f2 : OUT STD_LOGIC;
106 enable_f2 : OUT STD_LOGIC;
107 enable_f3 : OUT STD_LOGIC;
107 enable_f3 : OUT STD_LOGIC;
108
108
109 burst_f0 : OUT STD_LOGIC;
109 burst_f0 : OUT STD_LOGIC;
110 burst_f1 : OUT STD_LOGIC;
110 burst_f1 : OUT STD_LOGIC;
111 burst_f2 : OUT STD_LOGIC;
111 burst_f2 : OUT STD_LOGIC;
112
112
113 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
116 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
117
117
118 ---------------------------------------------------------------------------
118 ---------------------------------------------------------------------------
119 );
119 );
120
120
121 END lpp_top_apbreg;
121 END lpp_top_apbreg;
122
122
123 ARCHITECTURE beh OF lpp_top_apbreg IS
123 ARCHITECTURE beh OF lpp_top_apbreg IS
124
124
125 CONSTANT REVISION : INTEGER := 1;
125 CONSTANT REVISION : INTEGER := 1;
126
126
127 CONSTANT pconfig : apb_config_type := (
127 CONSTANT pconfig : apb_config_type := (
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
128 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
129 1 => apb_iobar(paddr, pmask));
129 1 => apb_iobar(paddr, pmask));
130
130
131 TYPE lpp_SpectralMatrix_regs IS RECORD
131 TYPE lpp_SpectralMatrix_regs IS RECORD
132 config_active_interruption_onNewMatrix : STD_LOGIC;
132 config_active_interruption_onNewMatrix : STD_LOGIC;
133 config_active_interruption_onError : STD_LOGIC;
133 config_active_interruption_onError : STD_LOGIC;
134 status_ready_matrix_f0_0 : STD_LOGIC;
134 status_ready_matrix_f0_0 : STD_LOGIC;
135 status_ready_matrix_f0_1 : STD_LOGIC;
135 status_ready_matrix_f0_1 : STD_LOGIC;
136 status_ready_matrix_f1 : STD_LOGIC;
136 status_ready_matrix_f1 : STD_LOGIC;
137 status_ready_matrix_f2 : STD_LOGIC;
137 status_ready_matrix_f2 : STD_LOGIC;
138 status_error_anticipating_empty_fifo : STD_LOGIC;
138 status_error_anticipating_empty_fifo : STD_LOGIC;
139 status_error_bad_component_error : STD_LOGIC;
139 status_error_bad_component_error : STD_LOGIC;
140 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 END RECORD;
144 END RECORD;
145 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
145 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
146
146
147 TYPE lpp_WaveformPicker_regs IS RECORD
147 TYPE lpp_WaveformPicker_regs IS RECORD
148 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
148 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 data_shaping_BW : STD_LOGIC;
151 data_shaping_BW : STD_LOGIC;
152 data_shaping_SP0 : STD_LOGIC;
152 data_shaping_SP0 : STD_LOGIC;
153 data_shaping_SP1 : STD_LOGIC;
153 data_shaping_SP1 : STD_LOGIC;
154 data_shaping_R0 : STD_LOGIC;
154 data_shaping_R0 : STD_LOGIC;
155 data_shaping_R1 : STD_LOGIC;
155 data_shaping_R1 : STD_LOGIC;
156 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
156 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
157 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
157 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
158 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
158 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
159 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
159 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
160 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
160 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
161 enable_f0 : STD_LOGIC;
161 enable_f0 : STD_LOGIC;
162 enable_f1 : STD_LOGIC;
162 enable_f1 : STD_LOGIC;
163 enable_f2 : STD_LOGIC;
163 enable_f2 : STD_LOGIC;
164 enable_f3 : STD_LOGIC;
164 enable_f3 : STD_LOGIC;
165 burst_f0 : STD_LOGIC;
165 burst_f0 : STD_LOGIC;
166 burst_f1 : STD_LOGIC;
166 burst_f1 : STD_LOGIC;
167 burst_f2 : STD_LOGIC;
167 burst_f2 : STD_LOGIC;
168 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 END RECORD;
172 END RECORD;
173 SIGNAL reg_wp : lpp_WaveformPicker_regs;
173 SIGNAL reg_wp : lpp_WaveformPicker_regs;
174
174
175 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
176
176
177 BEGIN -- beh
177 BEGIN -- beh
178
178
179 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
179 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
180 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
180 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
181 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
181 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
182 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
182 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
183 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
183 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
184 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
184 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
185
185
186 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
186 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
187 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
187 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
188 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
188 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
189 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
189 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
190 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
190 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
191 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
191 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
192
192
193
193
194
194
195
196 data_shaping_BW <= reg_wp.data_shaping_BW;
197 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
198 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
199 data_shaping_R0 <= reg_wp.data_shaping_R0;
200 data_shaping_R1 <= reg_wp.data_shaping_R1;
201
195
202 delta_snapshot <= reg_wp.delta_snapshot;
196 data_shaping_BW <= reg_wp.data_shaping_BW;
203 delta_f2_f1 <= reg_wp.delta_f2_f1;
197 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
204 delta_f2_f0 <= reg_wp.delta_f2_f0;
198 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
205 nb_burst_available <= reg_wp.nb_burst_available;
199 data_shaping_R0 <= reg_wp.data_shaping_R0;
206 nb_snapshot_param <= reg_wp.nb_snapshot_param;
200 data_shaping_R1 <= reg_wp.data_shaping_R1;
201
202 delta_snapshot <= reg_wp.delta_snapshot;
203 delta_f2_f1 <= reg_wp.delta_f2_f1;
204 delta_f2_f0 <= reg_wp.delta_f2_f0;
205 nb_burst_available <= reg_wp.nb_burst_available;
206 nb_snapshot_param <= reg_wp.nb_snapshot_param;
207
207
208 enable_f0 <= reg_wp.enable_f0;
208 enable_f0 <= reg_wp.enable_f0;
209 enable_f1 <= reg_wp.enable_f1;
209 enable_f1 <= reg_wp.enable_f1;
210 enable_f2 <= reg_wp.enable_f2;
210 enable_f2 <= reg_wp.enable_f2;
211 enable_f3 <= reg_wp.enable_f3;
211 enable_f3 <= reg_wp.enable_f3;
212
212
213 burst_f0 <= reg_wp.burst_f0;
213 burst_f0 <= reg_wp.burst_f0;
214 burst_f1 <= reg_wp.burst_f1;
214 burst_f1 <= reg_wp.burst_f1;
215 burst_f2 <= reg_wp.burst_f2;
215 burst_f2 <= reg_wp.burst_f2;
216
216
217 addr_data_f0 <= reg_wp.addr_data_f0;
217 addr_data_f0 <= reg_wp.addr_data_f0;
218 addr_data_f1 <= reg_wp.addr_data_f1;
218 addr_data_f1 <= reg_wp.addr_data_f1;
219 addr_data_f2 <= reg_wp.addr_data_f2;
219 addr_data_f2 <= reg_wp.addr_data_f2;
220 addr_data_f3 <= reg_wp.addr_data_f3;
220 addr_data_f3 <= reg_wp.addr_data_f3;
221
221
222 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
222 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
223 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
223 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
224 BEGIN -- PROCESS lpp_dma_top
224 BEGIN -- PROCESS lpp_dma_top
225 IF HRESETn = '0' THEN -- asynchronous reset (active low)
225 IF HRESETn = '0' THEN -- asynchronous reset (active low)
226 reg_sp.config_active_interruption_onNewMatrix <= '0';
226 reg_sp.config_active_interruption_onNewMatrix <= '0';
227 reg_sp.config_active_interruption_onError <= '0';
227 reg_sp.config_active_interruption_onError <= '0';
228 reg_sp.status_ready_matrix_f0_0 <= '0';
228 reg_sp.status_ready_matrix_f0_0 <= '0';
229 reg_sp.status_ready_matrix_f0_1 <= '0';
229 reg_sp.status_ready_matrix_f0_1 <= '0';
230 reg_sp.status_ready_matrix_f1 <= '0';
230 reg_sp.status_ready_matrix_f1 <= '0';
231 reg_sp.status_ready_matrix_f2 <= '0';
231 reg_sp.status_ready_matrix_f2 <= '0';
232 reg_sp.status_error_anticipating_empty_fifo <= '0';
232 reg_sp.status_error_anticipating_empty_fifo <= '0';
233 reg_sp.status_error_bad_component_error <= '0';
233 reg_sp.status_error_bad_component_error <= '0';
234 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
234 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
235 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
235 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
236 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
236 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
237 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
237 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
238 prdata <= (OTHERS => '0');
238 prdata <= (OTHERS => '0');
239
239
240 apbo.pirq <= (OTHERS => '0');
240 apbo.pirq <= (OTHERS => '0');
241
241
242 status_full_ack <= (OTHERS => '0');
242 status_full_ack <= (OTHERS => '0');
243
243
244 reg_wp.data_shaping_BW <= '0';
244 reg_wp.data_shaping_BW <= '0';
245 reg_wp.data_shaping_SP0 <= '0';
245 reg_wp.data_shaping_SP0 <= '0';
246 reg_wp.data_shaping_SP1 <= '0';
246 reg_wp.data_shaping_SP1 <= '0';
247 reg_wp.data_shaping_R0 <= '0';
247 reg_wp.data_shaping_R0 <= '0';
248 reg_wp.data_shaping_R1 <= '0';
248 reg_wp.data_shaping_R1 <= '0';
249 reg_wp.enable_f0 <= '0';
249 reg_wp.enable_f0 <= '0';
250 reg_wp.enable_f1 <= '0';
250 reg_wp.enable_f1 <= '0';
251 reg_wp.enable_f2 <= '0';
251 reg_wp.enable_f2 <= '0';
252 reg_wp.enable_f3 <= '0';
252 reg_wp.enable_f3 <= '0';
253 reg_wp.burst_f0 <= '0';
253 reg_wp.burst_f0 <= '0';
254 reg_wp.burst_f1 <= '0';
254 reg_wp.burst_f1 <= '0';
255 reg_wp.burst_f2 <= '0';
255 reg_wp.burst_f2 <= '0';
256 reg_wp.addr_data_f0 <= (OTHERS => '0');
256 reg_wp.addr_data_f0 <= (OTHERS => '0');
257 reg_wp.addr_data_f1 <= (OTHERS => '0');
257 reg_wp.addr_data_f1 <= (OTHERS => '0');
258 reg_wp.addr_data_f2 <= (OTHERS => '0');
258 reg_wp.addr_data_f2 <= (OTHERS => '0');
259 reg_wp.addr_data_f3 <= (OTHERS => '0');
259 reg_wp.addr_data_f3 <= (OTHERS => '0');
260 reg_wp.status_full <= (OTHERS => '0');
260 reg_wp.status_full <= (OTHERS => '0');
261 reg_wp.status_full_err <= (OTHERS => '0');
261 reg_wp.status_full_err <= (OTHERS => '0');
262 reg_wp.status_new_err <= (OTHERS => '0');
262 reg_wp.status_new_err <= (OTHERS => '0');
263 reg_wp.delta_snapshot <= (OTHERS => '0');
263 reg_wp.delta_snapshot <= (OTHERS => '0');
264 reg_wp.delta_f2_f1 <= (OTHERS => '0');
264 reg_wp.delta_f2_f1 <= (OTHERS => '0');
265 reg_wp.delta_f2_f0 <= (OTHERS => '0');
265 reg_wp.delta_f2_f0 <= (OTHERS => '0');
266 reg_wp.nb_burst_available <= (OTHERS => '0');
266 reg_wp.nb_burst_available <= (OTHERS => '0');
267 reg_wp.nb_snapshot_param <= (OTHERS => '0');
267 reg_wp.nb_snapshot_param <= (OTHERS => '0');
268
268
269 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
269 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
270 status_full_ack <= (OTHERS => '0');
270 status_full_ack <= (OTHERS => '0');
271
271
272 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
272 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
273 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
273 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
274 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
274 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
275 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
275 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
276
276
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
277 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
278 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
279
279
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
280 reg_wp.status_full <= reg_wp.status_full OR status_full;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
281 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
282 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
283
283
284 paddr := "000000";
284 paddr := "000000";
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
285 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
286 prdata <= (OTHERS => '0');
286 prdata <= (OTHERS => '0');
287 IF apbi.psel(pindex) = '1' THEN
287 IF apbi.psel(pindex) = '1' THEN
288 -- APB DMA READ --
288 -- APB DMA READ --
289 CASE paddr(7 DOWNTO 2) IS
289 CASE paddr(7 DOWNTO 2) IS
290 --
290 --
291 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
291 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
292 prdata(1) <= reg_sp.config_active_interruption_onError;
292 prdata(1) <= reg_sp.config_active_interruption_onError;
293 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
293 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
294 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
294 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
295 prdata(2) <= reg_sp.status_ready_matrix_f1;
295 prdata(2) <= reg_sp.status_ready_matrix_f1;
296 prdata(3) <= reg_sp.status_ready_matrix_f2;
296 prdata(3) <= reg_sp.status_ready_matrix_f2;
297 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
297 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
298 prdata(5) <= reg_sp.status_error_bad_component_error;
298 prdata(5) <= reg_sp.status_error_bad_component_error;
299 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
299 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
300 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
300 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
301 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
301 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
302 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
302 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
303 WHEN "000110" => prdata <= debug_reg;
303 WHEN "000110" => prdata <= debug_reg;
304 --
304 --
305 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
305 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
306 prdata(1) <= reg_wp.data_shaping_SP0;
306 prdata(1) <= reg_wp.data_shaping_SP0;
307 prdata(2) <= reg_wp.data_shaping_SP1;
307 prdata(2) <= reg_wp.data_shaping_SP1;
308 prdata(3) <= reg_wp.data_shaping_R0;
308 prdata(3) <= reg_wp.data_shaping_R0;
309 prdata(4) <= reg_wp.data_shaping_R1;
309 prdata(4) <= reg_wp.data_shaping_R1;
310 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
310 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
311 prdata(1) <= reg_wp.enable_f1;
311 prdata(1) <= reg_wp.enable_f1;
312 prdata(2) <= reg_wp.enable_f2;
312 prdata(2) <= reg_wp.enable_f2;
313 prdata(3) <= reg_wp.enable_f3;
313 prdata(3) <= reg_wp.enable_f3;
314 prdata(4) <= reg_wp.burst_f0;
314 prdata(4) <= reg_wp.burst_f0;
315 prdata(5) <= reg_wp.burst_f1;
315 prdata(5) <= reg_wp.burst_f1;
316 prdata(6) <= reg_wp.burst_f2;
316 prdata(6) <= reg_wp.burst_f2;
317 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
317 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
318 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
318 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
319 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
319 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
320 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
320 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
321 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
321 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
322 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
322 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
323 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
323 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
324 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
324 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
325 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
325 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
326 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
326 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
327 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
327 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
328 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
328 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
329 --
329 --
330 WHEN OTHERS => NULL;
330 WHEN OTHERS => NULL;
331 END CASE;
331 END CASE;
332 IF (apbi.pwrite AND apbi.penable) = '1' THEN
332 IF (apbi.pwrite AND apbi.penable) = '1' THEN
333 -- APB DMA WRITE --
333 -- APB DMA WRITE --
334 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
335 --
335 --
336 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
336 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
337 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
337 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
338 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
338 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
339 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
339 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
340 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
340 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
341 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
341 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
342 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
342 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
343 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
343 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
344 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
344 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
345 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
345 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
346 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
346 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
347 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
347 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
348 --
348 --
349 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
349 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
350 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
350 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
351 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
351 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
352 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
352 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
353 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
353 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
354 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
354 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
355 reg_wp.enable_f1 <= apbi.pwdata(1);
355 reg_wp.enable_f1 <= apbi.pwdata(1);
356 reg_wp.enable_f2 <= apbi.pwdata(2);
356 reg_wp.enable_f2 <= apbi.pwdata(2);
357 reg_wp.enable_f3 <= apbi.pwdata(3);
357 reg_wp.enable_f3 <= apbi.pwdata(3);
358 reg_wp.burst_f0 <= apbi.pwdata(4);
358 reg_wp.burst_f0 <= apbi.pwdata(4);
359 reg_wp.burst_f1 <= apbi.pwdata(5);
359 reg_wp.burst_f1 <= apbi.pwdata(5);
360 reg_wp.burst_f2 <= apbi.pwdata(6);
360 reg_wp.burst_f2 <= apbi.pwdata(6);
361 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
361 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
362 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
362 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
363 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
363 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
364 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
364 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
365 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
365 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
366 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
366 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
367 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
367 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
368 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
368 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
369 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
369 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
370 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
370 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
371 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
371 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
372 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
372 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
373 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
373 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
374 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
374 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
375 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
375 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
376 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
376 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
377 --
377 --
378 WHEN OTHERS => NULL;
378 WHEN OTHERS => NULL;
379 END CASE;
379 END CASE;
380 END IF;
380 END IF;
381 END IF;
381 END IF;
382
382
383 apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
383 apbo.pirq(pirq) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
384 ready_matrix_f0_1 OR
384 ready_matrix_f0_1 OR
385 ready_matrix_f1 OR
385 ready_matrix_f1 OR
386 ready_matrix_f2)
386 ready_matrix_f2)
387 )
387 )
388 OR
388 OR
389 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
389 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
390 error_bad_component_error)
390 error_bad_component_error)
391 )
391 )
392 OR
392 OR
393 (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
393 (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
394 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
394 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
395 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
395 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
396 status_full(3) OR status_full_err(3) OR status_new_err(3)
396 status_full(3) OR status_full_err(3) OR status_new_err(3)
397 );
397 );
398
398
399
399
400 END IF;
400 END IF;
401 END PROCESS lpp_top_apbreg;
401 END PROCESS lpp_top_apbreg;
402
402
403 apbo.pindex <= pindex;
403 apbo.pindex <= pindex;
404 apbo.pconfig <= pconfig;
404 apbo.pconfig <= pconfig;
405 apbo.prdata <= prdata;
405 apbo.prdata <= prdata;
406
406
407
407
408 END beh;
408 END beh;
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