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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0
57 57 );
58 58
59 59 PORT (
60 60 clk50MHz : IN STD_ULOGIC;
61 61 clk49_152MHz : IN STD_ULOGIC;
62 62 reset : IN STD_ULOGIC;
63 63
64 64 -- TAG --------------------------------------------------------------------
65 65 TAG1 : IN STD_ULOGIC; -- DSU rx data
66 66 TAG3 : OUT STD_ULOGIC; -- DSU tx data
67 67 -- UART APB ---------------------------------------------------------------
68 68 TAG2 : IN STD_ULOGIC; -- UART1 rx data
69 69 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
70 70 -- RAM --------------------------------------------------------------------
71 71 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
72 72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73
74 74 nSRAM_MBE : INOUT STD_LOGIC; -- new
75 75 nSRAM_E1 : OUT STD_LOGIC; -- new
76 76 nSRAM_E2 : OUT STD_LOGIC; -- new
77 77 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
78 78 nSRAM_W : OUT STD_LOGIC; -- new
79 79 nSRAM_G : OUT STD_LOGIC; -- new
80 80 nSRAM_BUSY : IN STD_LOGIC; -- new
81 81 -- SPW --------------------------------------------------------------------
82 82 spw1_en : OUT STD_LOGIC; -- new
83 83 spw1_din : IN STD_LOGIC;
84 84 spw1_sin : IN STD_LOGIC;
85 85 spw1_dout : OUT STD_LOGIC;
86 86 spw1_sout : OUT STD_LOGIC;
87 87 spw2_en : OUT STD_LOGIC; -- new
88 88 spw2_din : IN STD_LOGIC;
89 89 spw2_sin : IN STD_LOGIC;
90 90 spw2_dout : OUT STD_LOGIC;
91 91 spw2_sout : OUT STD_LOGIC;
92 92 -- ADC --------------------------------------------------------------------
93 93 bias_fail_sw : OUT STD_LOGIC;
94 94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 95 ADC_smpclk : OUT STD_LOGIC;
96 96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97 97 -- DAC --------------------------------------------------------------------
98 98 DAC_SDO : OUT STD_LOGIC;
99 99 DAC_SCK : OUT STD_LOGIC;
100 100 DAC_SYNC : OUT STD_LOGIC;
101 101 DAC_CAL_EN : OUT STD_LOGIC;
102 102 -- HK ---------------------------------------------------------------------
103 103 HK_smpclk : OUT STD_LOGIC;
104 104 ADC_OEB_bar_HK : OUT STD_LOGIC;
105 105 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
106 106 ---------------------------------------------------------------------------
107 107 TAG8 : OUT STD_LOGIC
108 108 );
109 109
110 110 END LFR_EQM;
111 111
112 112
113 113 ARCHITECTURE beh OF LFR_EQM IS
114 114
115 115 SIGNAL clk_25 : STD_LOGIC := '0';
116 116 SIGNAL clk_24 : STD_LOGIC := '0';
117 117 -----------------------------------------------------------------------------
118 118 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 120
121 121 -- CONSTANTS
122 122 CONSTANT CFG_PADTECH : INTEGER := inferred;
123 123 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
124 124 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
125 125 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
126 126
127 127 SIGNAL apbi_ext : apb_slv_in_type;
128 128 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
129 129 SIGNAL ahbi_s_ext : ahb_slv_in_type;
130 130 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
131 131 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
132 132 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
133 133
134 134 -- Spacewire signals
135 135 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 136 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 137 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
138 138 SIGNAL spw_rxtxclk : STD_ULOGIC;
139 139 SIGNAL spw_rxclkn : STD_ULOGIC;
140 140 SIGNAL spw_clk : STD_LOGIC;
141 141 SIGNAL swni : grspw_in_type;
142 142 SIGNAL swno : grspw_out_type;
143 143
144 144 --GPIO
145 145 SIGNAL gpioi : gpio_in_type;
146 146 SIGNAL gpioo : gpio_out_type;
147 147
148 148 -- AD Converter ADS7886
149 149 SIGNAL sample : Samples14v(8 DOWNTO 0);
150 150 SIGNAL sample_s : Samples(8 DOWNTO 0);
151 151 SIGNAL sample_val : STD_LOGIC;
152 152 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
153 153
154 154 -----------------------------------------------------------------------------
155 155 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 156
157 157 -----------------------------------------------------------------------------
158 158 SIGNAL rstn_25 : STD_LOGIC;
159 159 SIGNAL rstn_24 : STD_LOGIC;
160 160
161 161 SIGNAL LFR_soft_rstn : STD_LOGIC;
162 162 SIGNAL LFR_rstn : STD_LOGIC;
163 163
164 164 SIGNAL ADC_smpclk_s : STD_LOGIC;
165 165
166 166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
167 167
168 168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
169 169 SIGNAL clk_25_int : STD_LOGIC := '0';
170 170
171 171 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
172 172
173 173 BEGIN -- beh
174 174
175 175 -----------------------------------------------------------------------------
176 176 -- CLK
177 177 -----------------------------------------------------------------------------
178 178 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
179 179 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
180 180
181 181 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
182 182 clk50MHz_int <= clk50MHz;
183 183
184 184 PROCESS(clk50MHz_int)
185 185 BEGIN
186 186 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
187 187 --clk_25_int <= NOT clk_25_int;
188 188 clk_25 <= NOT clk_25;
189 189 END IF;
190 190 END PROCESS;
191 191 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
192 192
193 193 PROCESS(clk49_152MHz)
194 194 BEGIN
195 195 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
196 196 clk_24 <= NOT clk_24;
197 197 END IF;
198 198 END PROCESS;
199 199
200 200 -----------------------------------------------------------------------------
201 201 --
202 202 leon3_soc_1 : leon3_soc
203 203 GENERIC MAP (
204 204 fabtech => apa3l,
205 205 memtech => apa3l,
206 206 padtech => inferred,
207 207 clktech => inferred,
208 208 disas => 0,
209 209 dbguart => 0,
210 210 pclow => 2,
211 211 clk_freq => 25000,
212 212 IS_RADHARD => 0,
213 213 NB_CPU => 1,
214 214 ENABLE_FPU => 1,
215 215 FPU_NETLIST => 0,
216 216 ENABLE_DSU => 1,
217 217 ENABLE_AHB_UART => 1,
218 218 ENABLE_APB_UART => 1,
219 219 ENABLE_IRQMP => 1,
220 220 ENABLE_GPT => 1,
221 221 NB_AHB_MASTER => NB_AHB_MASTER,
222 222 NB_AHB_SLAVE => NB_AHB_SLAVE,
223 223 NB_APB_SLAVE => NB_APB_SLAVE,
224 224 ADDRESS_SIZE => 19,
225 225 USES_IAP_MEMCTRLR => 1,
226 226 BYPASS_EDAC_MEMCTRLR => '0',
227 227 SRBANKSZ => 8)
228 228 PORT MAP (
229 229 clk => clk_25,
230 230 reset => rstn_25,
231 231 errorn => OPEN,
232 232
233 233 ahbrxd => TAG1,
234 234 ahbtxd => TAG3,
235 235 urxd1 => TAG2,
236 236 utxd1 => TAG4,
237 237
238 238 address => address,
239 239 data => data,
240 240 nSRAM_BE0 => OPEN,
241 241 nSRAM_BE1 => OPEN,
242 242 nSRAM_BE2 => OPEN,
243 243 nSRAM_BE3 => OPEN,
244 244 nSRAM_WE => nSRAM_W,
245 245 nSRAM_CE => nSRAM_CE,
246 246 nSRAM_OE => nSRAM_G,
247 247 nSRAM_READY => nSRAM_BUSY,
248 248 SRAM_MBE => nSRAM_MBE,
249 249
250 250 apbi_ext => apbi_ext,
251 251 apbo_ext => apbo_ext,
252 252 ahbi_s_ext => ahbi_s_ext,
253 253 ahbo_s_ext => ahbo_s_ext,
254 254 ahbi_m_ext => ahbi_m_ext,
255 255 ahbo_m_ext => ahbo_m_ext);
256 256
257 257
258 258 nSRAM_E1 <= nSRAM_CE(0);
259 259 nSRAM_E2 <= nSRAM_CE(1);
260 260
261 261 -------------------------------------------------------------------------------
262 262 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
263 263 -------------------------------------------------------------------------------
264 264 apb_lfr_management_1 : apb_lfr_management
265 265 GENERIC MAP (
266 266 tech => apa3l,
267 267 pindex => 6,
268 268 paddr => 6,
269 269 pmask => 16#fff#,
270 270 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
271 271 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
272 272 PORT MAP (
273 273 clk25MHz => clk_25,
274 274 resetn_25MHz => rstn_25, -- TODO
275 275 --clk24_576MHz => clk_24, -- 49.152MHz/2
276 276 --resetn_24_576MHz => rstn_24, -- TODO
277 277
278 278 grspw_tick => swno.tickout,
279 279 apbi => apbi_ext,
280 280 apbo => apbo_ext(6),
281 281
282 282 HK_sample => sample_s(8),
283 283 HK_val => sample_val,
284 284 HK_sel => HK_SEL,
285 285
286 286 DAC_SDO => DAC_SDO,
287 287 DAC_SCK => DAC_SCK,
288 288 DAC_SYNC => DAC_SYNC,
289 289 DAC_CAL_EN => DAC_CAL_EN,
290 290
291 291 coarse_time => coarse_time,
292 292 fine_time => fine_time,
293 293 LFR_soft_rstn => LFR_soft_rstn
294 294 );
295 295
296 296 -----------------------------------------------------------------------
297 297 --- SpaceWire --------------------------------------------------------
298 298 -----------------------------------------------------------------------
299 299
300 300 ------------------------------------------------------------------------------
301 301 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
302 302 ------------------------------------------------------------------------------
303 303 spw1_en <= '1';
304 304 spw2_en <= '1';
305 305 ------------------------------------------------------------------------------
306 306 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
307 307 ------------------------------------------------------------------------------
308 308
309 309 --spw_clk <= clk50MHz;
310 310 --spw_rxtxclk <= spw_clk;
311 311 --spw_rxclkn <= NOT spw_rxtxclk;
312 312
313 313 -- PADS for SPW1
314 314 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
315 315 PORT MAP (spw1_din, dtmp(0));
316 316 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
317 317 PORT MAP (spw1_sin, stmp(0));
318 318 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
319 319 PORT MAP (spw1_dout, swno.d(0));
320 320 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
321 321 PORT MAP (spw1_sout, swno.s(0));
322 322 -- PADS FOR SPW2
323 323 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
324 324 PORT MAP (spw2_din, dtmp(1));
325 325 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
326 326 PORT MAP (spw2_sin, stmp(1));
327 327 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
328 328 PORT MAP (spw2_dout, swno.d(1));
329 329 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
330 330 PORT MAP (spw2_sout, swno.s(1));
331 331
332 332 -- GRSPW PHY
333 333 --spw1_input: if CFG_SPW_GRSPW = 1 generate
334 334 spw_inputloop : FOR j IN 0 TO 1 GENERATE
335 335 spw_phy0 : grspw_phy
336 336 GENERIC MAP(
337 337 tech => apa3l,
338 338 rxclkbuftype => 1,
339 339 scantest => 0)
340 340 PORT MAP(
341 341 rxrst => swno.rxrst,
342 342 di => dtmp(j),
343 343 si => stmp(j),
344 344 rxclko => spw_rxclk(j),
345 345 do => swni.d(j),
346 346 ndo => swni.nd(j*5+4 DOWNTO j*5),
347 347 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
348 348 END GENERATE spw_inputloop;
349 349
350 350 -- SPW core
351 351 sw0 : grspwm GENERIC MAP(
352 352 tech => apa3l,
353 353 hindex => 1,
354 354 pindex => 5,
355 355 paddr => 5,
356 356 pirq => 11,
357 357 sysfreq => 25000, -- CPU_FREQ
358 358 rmap => 1,
359 359 rmapcrc => 1,
360 360 fifosize1 => 16,
361 361 fifosize2 => 16,
362 362 rxclkbuftype => 1,
363 363 rxunaligned => 0,
364 364 rmapbufs => 4,
365 365 ft => 0,
366 366 netlist => 0,
367 367 ports => 2,
368 368 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
369 369 memtech => apa3l,
370 370 destkey => 2,
371 371 spwcore => 1
372 372 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
373 373 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
374 374 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
375 375 )
376 376 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
377 377 spw_rxclk(1),
378 378 clk50MHz_int,
379 379 clk50MHz_int,
380 380 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
381 381 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
382 382 swni, swno);
383 383
384 384 swni.tickin <= '0';
385 385 swni.rmapen <= '1';
386 386 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
387 387 swni.tickinraw <= '0';
388 388 swni.timein <= (OTHERS => '0');
389 389 swni.dcrstval <= (OTHERS => '0');
390 390 swni.timerrstval <= (OTHERS => '0');
391 391
392 392 -------------------------------------------------------------------------------
393 393 -- LFR ------------------------------------------------------------------------
394 394 -------------------------------------------------------------------------------
395 395 LFR_rstn <= LFR_soft_rstn AND rstn_25;
396 396
397 397 lpp_lfr_1 : lpp_lfr
398 398 GENERIC MAP (
399 399 Mem_use => Mem_use,
400 400 nb_data_by_buffer_size => 32,
401 401 --nb_word_by_buffer_size => 30,
402 402 nb_snapshot_param_size => 32,
403 403 delta_vector_size => 32,
404 404 delta_vector_size_f0_2 => 7, -- log2(96)
405 405 pindex => 15,
406 406 paddr => 15,
407 407 pmask => 16#fff#,
408 408 pirq_ms => 6,
409 409 pirq_wfp => 14,
410 410 hindex => 2,
411 top_lfr_version => X"020146") -- aa.bb.cc version
411 top_lfr_version => X"020147") -- aa.bb.cc version
412 412 -- AA : BOARD NUMBER
413 413 -- 0 => MINI_LFR
414 414 -- 1 => EM
415 415 -- 2 => EQM (with A3PE3000)
416 416 PORT MAP (
417 417 clk => clk_25,
418 418 rstn => LFR_rstn,
419 419 sample_B => sample_s(2 DOWNTO 0),
420 420 sample_E => sample_s(7 DOWNTO 3),
421 421 sample_val => sample_val,
422 422 apbi => apbi_ext,
423 423 apbo => apbo_ext(15),
424 424 ahbi => ahbi_m_ext,
425 425 ahbo => ahbo_m_ext(2),
426 426 coarse_time => coarse_time,
427 427 fine_time => fine_time,
428 428 data_shaping_BW => bias_fail_sw,
429 429 debug_vector => OPEN,
430 430 debug_vector_ms => OPEN); --,
431 431 --observation_vector_0 => OPEN,
432 432 --observation_vector_1 => OPEN,
433 433 --observation_reg => observation_reg);
434 434
435 435
436 436 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
437 437 sample_s(I) <= sample(I) & '0' & '0';
438 438 END GENERATE all_sample;
439 439 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
440 440
441 441 -----------------------------------------------------------------------------
442 442 --
443 443 -----------------------------------------------------------------------------
444 444 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
445 445 GENERIC MAP (
446 446 ChanelCount => 9,
447 447 ncycle_cnv_high => 13,
448 448 ncycle_cnv => 25,
449 449 FILTER_ENABLED => 16#FF#)
450 450 PORT MAP (
451 451 cnv_clk => clk_24,
452 452 cnv_rstn => rstn_24,
453 453 cnv => ADC_smpclk_s,
454 454 clk => clk_25,
455 455 rstn => rstn_25,
456 456 ADC_data => ADC_data,
457 457 ADC_nOE => ADC_OEB_bar_CH_s,
458 458 sample => sample,
459 459 sample_val => sample_val);
460 460
461 461 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
462 462
463 463 ADC_smpclk <= ADC_smpclk_s;
464 464 HK_smpclk <= ADC_smpclk_s;
465 465
466 466 TAG8 <= nSRAM_BUSY;
467 467
468 468 -----------------------------------------------------------------------------
469 469 -- HK
470 470 -----------------------------------------------------------------------------
471 471 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
472 472
473 473 -----------------------------------------------------------------------------
474 474 --
475 475 -----------------------------------------------------------------------------
476 476 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
477 477 lpp_bootloader_1: lpp_bootloader
478 478 GENERIC MAP (
479 479 pindex => 13,
480 480 paddr => 13,
481 481 pmask => 16#fff#,
482 482 hindex => 3,
483 483 haddr => 0,
484 484 hmask => 16#fff#)
485 485 PORT MAP (
486 486 HCLK => clk_25,
487 487 HRESETn => rstn_25,
488 488 apbi => apbi_ext,
489 489 apbo => apbo_ext(13),
490 490 ahbsi => ahbi_s_ext,
491 491 ahbso => ahbo_s_ext(3));
492 492 END GENERATE inst_bootloader;
493 493 END beh;
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