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Update MS TIME_APB_REG and Fsm_DMA
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r375:e477c8d5d09b (MINI-LFR) WFP_MS-0-1-15 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 -----------------------------------------------------------------------------
176 176
177 177 BEGIN -- beh
178 178
179 179 -----------------------------------------------------------------------------
180 180 -- CLK
181 181 -----------------------------------------------------------------------------
182 182
183 183 PROCESS(clk_50)
184 184 BEGIN
185 185 IF clk_50'EVENT AND clk_50 = '1' THEN
186 186 clk_50_s <= NOT clk_50_s;
187 187 END IF;
188 188 END PROCESS;
189 189
190 190 PROCESS(clk_50_s)
191 191 BEGIN
192 192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
193 193 clk_25 <= NOT clk_25;
194 194 END IF;
195 195 END PROCESS;
196 196
197 197 PROCESS(clk_49)
198 198 BEGIN
199 199 IF clk_49'EVENT AND clk_49 = '1' THEN
200 200 clk_24 <= NOT clk_24;
201 201 END IF;
202 202 END PROCESS;
203 203
204 204 -----------------------------------------------------------------------------
205 205
206 206 PROCESS (clk_25, reset)
207 207 BEGIN -- PROCESS
208 208 IF reset = '0' THEN -- asynchronous reset (active low)
209 209 LED0 <= '0';
210 210 LED1 <= '0';
211 211 LED2 <= '0';
212 212 --IO1 <= '0';
213 213 --IO2 <= '1';
214 214 --IO3 <= '0';
215 215 --IO4 <= '0';
216 216 --IO5 <= '0';
217 217 --IO6 <= '0';
218 218 --IO7 <= '0';
219 219 --IO8 <= '0';
220 220 --IO9 <= '0';
221 221 --IO10 <= '0';
222 222 --IO11 <= '0';
223 223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
224 224 LED0 <= '0';
225 225 LED1 <= '1';
226 226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
227 227 --IO1 <= '1';
228 228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
229 229 --IO3 <= ADC_SDO(0);
230 230 --IO4 <= ADC_SDO(1);
231 231 --IO5 <= ADC_SDO(2);
232 232 --IO6 <= ADC_SDO(3);
233 233 --IO7 <= ADC_SDO(4);
234 234 --IO8 <= ADC_SDO(5);
235 235 --IO9 <= ADC_SDO(6);
236 236 --IO10 <= ADC_SDO(7);
237 237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
238 238 END IF;
239 239 END PROCESS;
240 240
241 241 PROCESS (clk_24, reset)
242 242 BEGIN -- PROCESS
243 243 IF reset = '0' THEN -- asynchronous reset (active low)
244 244 I00_s <= '0';
245 245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
246 246 I00_s <= NOT I00_s ;
247 247 END IF;
248 248 END PROCESS;
249 249 -- IO0 <= I00_s;
250 250
251 251 --UARTs
252 252 nCTS1 <= '1';
253 253 nCTS2 <= '1';
254 254 nDCD2 <= '1';
255 255
256 256 --EXT CONNECTOR
257 257
258 258 --SPACE WIRE
259 259
260 260 leon3_soc_1 : leon3_soc
261 261 GENERIC MAP (
262 262 fabtech => apa3e,
263 263 memtech => apa3e,
264 264 padtech => inferred,
265 265 clktech => inferred,
266 266 disas => 0,
267 267 dbguart => 0,
268 268 pclow => 2,
269 269 clk_freq => 25000,
270 270 NB_CPU => 1,
271 271 ENABLE_FPU => 1,
272 272 FPU_NETLIST => 0,
273 273 ENABLE_DSU => 1,
274 274 ENABLE_AHB_UART => 1,
275 275 ENABLE_APB_UART => 1,
276 276 ENABLE_IRQMP => 1,
277 277 ENABLE_GPT => 1,
278 278 NB_AHB_MASTER => NB_AHB_MASTER,
279 279 NB_AHB_SLAVE => NB_AHB_SLAVE,
280 280 NB_APB_SLAVE => NB_APB_SLAVE)
281 281 PORT MAP (
282 282 clk => clk_25,
283 283 reset => reset,
284 284 errorn => errorn,
285 285 ahbrxd => TXD1,
286 286 ahbtxd => RXD1,
287 287 urxd1 => TXD2,
288 288 utxd1 => RXD2,
289 289 address => SRAM_A,
290 290 data => SRAM_DQ,
291 291 nSRAM_BE0 => SRAM_nBE(0),
292 292 nSRAM_BE1 => SRAM_nBE(1),
293 293 nSRAM_BE2 => SRAM_nBE(2),
294 294 nSRAM_BE3 => SRAM_nBE(3),
295 295 nSRAM_WE => SRAM_nWE,
296 296 nSRAM_CE => SRAM_CE,
297 297 nSRAM_OE => SRAM_nOE,
298 298
299 299 apbi_ext => apbi_ext,
300 300 apbo_ext => apbo_ext,
301 301 ahbi_s_ext => ahbi_s_ext,
302 302 ahbo_s_ext => ahbo_s_ext,
303 303 ahbi_m_ext => ahbi_m_ext,
304 304 ahbo_m_ext => ahbo_m_ext);
305 305
306 306 -------------------------------------------------------------------------------
307 307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
308 308 -------------------------------------------------------------------------------
309 309 apb_lfr_time_management_1 : apb_lfr_time_management
310 310 GENERIC MAP (
311 311 pindex => 6,
312 312 paddr => 6,
313 313 pmask => 16#fff#,
314 314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
315 315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
316 316 PORT MAP (
317 317 clk25MHz => clk_25,
318 318 clk24_576MHz => clk_24, -- 49.152MHz/2
319 319 resetn => reset,
320 320 grspw_tick => swno.tickout,
321 321 apbi => apbi_ext,
322 322 apbo => apbo_ext(6),
323 323 coarse_time => coarse_time,
324 324 fine_time => fine_time);
325 325
326 326 -----------------------------------------------------------------------
327 327 --- SpaceWire --------------------------------------------------------
328 328 -----------------------------------------------------------------------
329 329
330 330 SPW_EN <= '1';
331 331
332 332 spw_clk <= clk_50_s;
333 333 spw_rxtxclk <= spw_clk;
334 334 spw_rxclkn <= NOT spw_rxtxclk;
335 335
336 336 -- PADS for SPW1
337 337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
338 338 PORT MAP (SPW_NOM_DIN, dtmp(0));
339 339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_SIN, stmp(0));
341 341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
343 343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
344 344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
345 345 -- PADS FOR SPW2
346 346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 347 PORT MAP (SPW_RED_SIN, dtmp(1));
348 348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 349 PORT MAP (SPW_RED_DIN, stmp(1));
350 350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
351 351 PORT MAP (SPW_RED_DOUT, swno.d(1));
352 352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
353 353 PORT MAP (SPW_RED_SOUT, swno.s(1));
354 354
355 355 -- GRSPW PHY
356 356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
357 357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
358 358 spw_phy0 : grspw_phy
359 359 GENERIC MAP(
360 360 tech => apa3e,
361 361 rxclkbuftype => 1,
362 362 scantest => 0)
363 363 PORT MAP(
364 364 rxrst => swno.rxrst,
365 365 di => dtmp(j),
366 366 si => stmp(j),
367 367 rxclko => spw_rxclk(j),
368 368 do => swni.d(j),
369 369 ndo => swni.nd(j*5+4 DOWNTO j*5),
370 370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
371 371 END GENERATE spw_inputloop;
372 372
373 373 -- SPW core
374 374 sw0 : grspwm GENERIC MAP(
375 375 tech => apa3e,
376 376 hindex => 1,
377 377 pindex => 5,
378 378 paddr => 5,
379 379 pirq => 11,
380 380 sysfreq => 25000, -- CPU_FREQ
381 381 rmap => 1,
382 382 rmapcrc => 1,
383 383 fifosize1 => 16,
384 384 fifosize2 => 16,
385 385 rxclkbuftype => 1,
386 386 rxunaligned => 0,
387 387 rmapbufs => 4,
388 388 ft => 0,
389 389 netlist => 0,
390 390 ports => 2,
391 391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
392 392 memtech => apa3e,
393 393 destkey => 2,
394 394 spwcore => 1
395 395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
396 396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
397 397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
398 398 )
399 399 PORT MAP(reset, clk_25, spw_rxclk(0),
400 400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
401 401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
402 402 swni, swno);
403 403
404 404 swni.tickin <= '0';
405 405 swni.rmapen <= '1';
406 406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
407 407 swni.tickinraw <= '0';
408 408 swni.timein <= (OTHERS => '0');
409 409 swni.dcrstval <= (OTHERS => '0');
410 410 swni.timerrstval <= (OTHERS => '0');
411 411
412 412 -------------------------------------------------------------------------------
413 413 -- LFR ------------------------------------------------------------------------
414 414 -------------------------------------------------------------------------------
415 415 lpp_lfr_1 : lpp_lfr
416 416 GENERIC MAP (
417 417 Mem_use => use_RAM,
418 418 nb_data_by_buffer_size => 32,
419 419 nb_word_by_buffer_size => 30,
420 420 nb_snapshot_param_size => 32,
421 421 delta_vector_size => 32,
422 422 delta_vector_size_f0_2 => 7, -- log2(96)
423 423 pindex => 15,
424 424 paddr => 15,
425 425 pmask => 16#fff#,
426 426 pirq_ms => 6,
427 427 pirq_wfp => 14,
428 428 hindex => 2,
429 top_lfr_version => X"00010E") -- aa.bb.cc version
429 top_lfr_version => X"00010F") -- aa.bb.cc version
430 430 PORT MAP (
431 431 clk => clk_25,
432 432 rstn => reset,
433 433 sample_B => sample_s(2 DOWNTO 0),
434 434 sample_E => sample_s(7 DOWNTO 3),
435 435 sample_val => sample_val,
436 436 apbi => apbi_ext,
437 437 apbo => apbo_ext(15),
438 438 ahbi => ahbi_m_ext,
439 439 ahbo => ahbo_m_ext(2),
440 440 coarse_time => coarse_time,
441 441 fine_time => fine_time,
442 442 data_shaping_BW => bias_fail_sw_sig,
443 443 observation_reg => observation_reg);
444 444
445 445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 447 END GENERATE all_sample;
448 448
449 449
450 450
451 451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 452 GENERIC MAP(
453 453 ChannelCount => 8,
454 454 SampleNbBits => 14,
455 455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 457 PORT MAP (
458 458 -- CONV
459 459 cnv_clk => clk_24,
460 460 cnv_rstn => reset,
461 461 cnv => ADC_nCS_sig,
462 462 -- DATA
463 463 clk => clk_25,
464 464 rstn => reset,
465 465 sck => ADC_CLK_sig,
466 466 sdo => ADC_SDO_sig,
467 467 -- SAMPLE
468 468 sample => sample,
469 469 sample_val => sample_val);
470 470
471 471 --IO10 <= ADC_SDO_sig(5);
472 472 --IO9 <= ADC_SDO_sig(4);
473 473 --IO8 <= ADC_SDO_sig(3);
474 474
475 475 ADC_nCS <= ADC_nCS_sig;
476 476 ADC_CLK <= ADC_CLK_sig;
477 477 ADC_SDO_sig <= ADC_SDO;
478 478
479 479 ----------------------------------------------------------------------
480 480 --- GPIO -----------------------------------------------------------
481 481 ----------------------------------------------------------------------
482 482
483 483 grgpio0 : grgpio
484 484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486 486
487 487 --pio_pad_0 : iopad
488 488 -- GENERIC MAP (tech => CFG_PADTECH)
489 489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 490 --pio_pad_1 : iopad
491 491 -- GENERIC MAP (tech => CFG_PADTECH)
492 492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 493 --pio_pad_2 : iopad
494 494 -- GENERIC MAP (tech => CFG_PADTECH)
495 495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 496 --pio_pad_3 : iopad
497 497 -- GENERIC MAP (tech => CFG_PADTECH)
498 498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 499 --pio_pad_4 : iopad
500 500 -- GENERIC MAP (tech => CFG_PADTECH)
501 501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 502 --pio_pad_5 : iopad
503 503 -- GENERIC MAP (tech => CFG_PADTECH)
504 504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 505 --pio_pad_6 : iopad
506 506 -- GENERIC MAP (tech => CFG_PADTECH)
507 507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 508 --pio_pad_7 : iopad
509 509 -- GENERIC MAP (tech => CFG_PADTECH)
510 510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511 511
512 512 PROCESS (clk_25, reset)
513 513 BEGIN -- PROCESS
514 514 IF reset = '0' THEN -- asynchronous reset (active low)
515 515 IO0 <= '0';
516 516 IO1 <= '0';
517 517 IO2 <= '0';
518 518 IO3 <= '0';
519 519 IO4 <= '0';
520 520 IO5 <= '0';
521 521 IO6 <= '0';
522 522 IO7 <= '0';
523 523 IO8 <= '0';
524 524 IO9 <= '0';
525 525 IO10 <= '0';
526 526 IO11 <= '0';
527 527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 528 CASE gpioo.dout(1 DOWNTO 0) IS
529 529 WHEN "00" =>
530 530 IO0 <= observation_reg(0 );
531 531 IO1 <= observation_reg(1 );
532 532 IO2 <= observation_reg(2 );
533 533 IO3 <= observation_reg(3 );
534 534 IO4 <= observation_reg(4 );
535 535 IO5 <= observation_reg(5 );
536 536 IO6 <= observation_reg(6 );
537 537 IO7 <= observation_reg(7 );
538 538 IO8 <= observation_reg(8 );
539 539 IO9 <= observation_reg(9 );
540 540 IO10 <= observation_reg(10);
541 541 IO11 <= observation_reg(11);
542 542 WHEN "01" =>
543 543 IO0 <= observation_reg(0 + 12);
544 544 IO1 <= observation_reg(1 + 12);
545 545 IO2 <= observation_reg(2 + 12);
546 546 IO3 <= observation_reg(3 + 12);
547 547 IO4 <= observation_reg(4 + 12);
548 548 IO5 <= observation_reg(5 + 12);
549 549 IO6 <= observation_reg(6 + 12);
550 550 IO7 <= observation_reg(7 + 12);
551 551 IO8 <= observation_reg(8 + 12);
552 552 IO9 <= observation_reg(9 + 12);
553 553 IO10 <= observation_reg(10 + 12);
554 554 IO11 <= observation_reg(11 + 12);
555 555 WHEN "10" =>
556 556 IO0 <= observation_reg(0 + 12 + 12);
557 557 IO1 <= observation_reg(1 + 12 + 12);
558 558 IO2 <= observation_reg(2 + 12 + 12);
559 559 IO3 <= observation_reg(3 + 12 + 12);
560 560 IO4 <= observation_reg(4 + 12 + 12);
561 561 IO5 <= observation_reg(5 + 12 + 12);
562 562 IO6 <= observation_reg(6 + 12 + 12);
563 563 IO7 <= observation_reg(7 + 12 + 12);
564 564 IO8 <= '0';
565 565 IO9 <= '0';
566 566 IO10 <= '0';
567 567 IO11 <= '0';
568 568 WHEN "11" =>
569 569 IO0 <= '0';
570 570 IO1 <= '0';
571 571 IO2 <= '0';
572 572 IO3 <= '0';
573 573 IO4 <= '0';
574 574 IO5 <= '0';
575 575 IO6 <= '0';
576 576 IO7 <= '0';
577 577 IO8 <= '0';
578 578 IO9 <= '0';
579 579 IO10 <= '0';
580 580 IO11 <= '0';
581 581 WHEN OTHERS => NULL;
582 582 END CASE;
583 583
584 584 END IF;
585 585 END PROCESS;
586 586
587 587 END beh;
Show file before | Show file after | Hide comments
@@ -1,422 +1,432
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.lpp_lfr_pkg.ALL;
29 29 USE lpp.lpp_memory.ALL;
30 30 USE lpp.iir_filter.ALL;
31 31 USE lpp.spectral_matrix_package.ALL;
32 32 use lpp.lpp_fft.all;
33 33 use lpp.fft_components.all;
34 34
35 35 LIBRARY grlib;
36 36 USE grlib.amba.ALL;
37 37 USE grlib.stdlib.ALL;
38 38 USE grlib.devices.ALL;
39 39 USE GRLIB.DMA2AHB_Package.ALL;
40 40
41 41 ENTITY TB IS
42 42
43 43
44 44 END TB;
45 45
46 46
47 47 ARCHITECTURE beh OF TB IS
48 48
49 49 -----------------------------------------------------------------------------
50 50 SIGNAL clk25MHz : STD_LOGIC := '0';
51 51 SIGNAL rstn : STD_LOGIC := '0';
52 52
53 53 -----------------------------------------------------------------------------
54 54 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
55 55 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
56 56 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
57 57 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 58 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
59 59 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 60 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 61 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 62 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 63 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 SIGNAL dma_valid : STD_LOGIC;
65 65 SIGNAL dma_valid_burst : STD_LOGIC;
66 66 SIGNAL dma_ren : STD_LOGIC;
67 67 SIGNAL dma_done : STD_LOGIC;
68 68 SIGNAL ready_matrix_f0 : STD_LOGIC;
69 69 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 70 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 71 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 72 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 73 SIGNAL error_bad_component_error : STD_LOGIC;
74 74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 75 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
76 76 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 79 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 80 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
81 81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 82 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 83 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
88 88 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
89 89 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
90 90 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
91 91
92 92 -----------------------------------------------------------------------------
93 93 SIGNAL clk49_152MHz : STD_LOGIC := '0';
94 94 SIGNAL sample_counter_24k : INTEGER;
95 95 SIGNAL s_24576Hz : STD_LOGIC;
96 96
97 97 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
98 98 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
99 99
100 100 SIGNAL s_24576Hz_sync : STD_LOGIC;
101 101
102 102 SIGNAL sample_counter_f1 : INTEGER;
103 103 SIGNAL sample_counter_f2 : INTEGER;
104 104 --
105 105 SIGNAL sample_f0_val : STD_LOGIC;
106 106 SIGNAL sample_f1_val : STD_LOGIC;
107 107 SIGNAL sample_f2_val : STD_LOGIC;
108 108
109 109 -----------------------------------------------------------------------------
110 110 SIGNAL ren_counter : INTEGER;
111 111
112 112 SIGNAL error_buffer_full : STD_LOGIC;
113 113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 114 -----------------------------------------------------------------------------
115 115 SIGNAL apbi : apb_slv_in_type;
116 116 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 117 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 118 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 119 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 120
121 121 BEGIN -- beh
122 122
123 123 clk25MHz <= NOT clk25MHz AFTER 20 ns;
124 124 clk25MHz <= NOT clk25MHz AFTER 20 ns;
125 125 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
126 126
127 127 PROCESS
128 128 BEGIN -- PROCESS
129 129 WAIT UNTIL clk25MHz = '1';
130 130 WAIT UNTIL clk25MHz = '1';
131 131 WAIT UNTIL clk25MHz = '1';
132 132 rstn <= '1';
133 133 WAIT UNTIL clk25MHz = '1';
134 134
135 135
136 136 WAIT FOR 100 ms;
137 137
138 138 REPORT "*** END simulation ***" SEVERITY failure;
139 139 WAIT;
140 140
141 141 END PROCESS;
142 142
143 143
144 144 -----------------------------------------------------------------------------
145 145 PROCESS (clk49_152MHz, rstn)
146 146 BEGIN -- PROCESS
147 147 IF rstn = '0' THEN -- asynchronous reset (active low)
148 148 sample_counter_24k <= 0;
149 149 s_24576Hz <= '0';
150 150 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
151 151 IF sample_counter_24k = 0 THEN
152 152 sample_counter_24k <= 2000;
153 153 s_24576Hz <= NOT s_24576Hz;
154 154 ELSE
155 155 sample_counter_24k <= sample_counter_24k - 1;
156 156 END IF;
157 157 END IF;
158 158 END PROCESS;
159 159
160 160 PROCESS (clk25MHz, rstn)
161 161 BEGIN -- PROCESS
162 162 IF rstn = '0' THEN -- asynchronous reset (active low)
163 163 s_24_sync_reg_0 <= '0';
164 164 s_24_sync_reg_1 <= '0';
165 165 s_24576Hz_sync <= '0';
166 166 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
167 167 s_24_sync_reg_0 <= s_24576Hz;
168 168 s_24_sync_reg_1 <= s_24_sync_reg_0;
169 169 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
170 170 END IF;
171 171 END PROCESS;
172 172
173 173 PROCESS (clk25MHz, rstn)
174 174 BEGIN -- PROCESS
175 175 IF rstn = '0' THEN -- asynchronous reset (active low)
176 176 sample_f0_val <= '0';
177 177 sample_f1_val <= '0';
178 178 sample_f2_val <= '0';
179 179
180 180 sample_counter_f1 <= 0;
181 181 sample_counter_f2 <= 0;
182 182 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
183 183 IF s_24576Hz_sync = '1' THEN
184 184 sample_f0_val <= '1';
185 185 IF sample_counter_f1 = 0 THEN
186 186 sample_f1_val <= '1';
187 187 sample_counter_f1 <= 5;
188 188 ELSE
189 189 sample_f1_val <= '0';
190 190 sample_counter_f1 <= sample_counter_f1 -1;
191 191 END IF;
192 192 IF sample_counter_f2 = 0 THEN
193 193 sample_f2_val <= '1';
194 194 sample_counter_f2 <= 95;
195 195 ELSE
196 196 sample_f2_val <= '0';
197 197 sample_counter_f2 <= sample_counter_f2 -1;
198 198 END IF;
199 199 ELSE
200 200 sample_f0_val <= '0';
201 201 sample_f1_val <= '0';
202 202 sample_f2_val <= '0';
203 203 END IF;
204 204 END IF;
205 205 END PROCESS;
206 206
207 207
208 208
209 209 -----------------------------------------------------------------------------
210 coarse_time <= (OTHERS => '0');
211 fine_time <= (OTHERS => '0');
210 coarse_time <= (OTHERS => '1');
211
212 PROCESS (clk25MHz, rstn)
213 BEGIN
214 IF rstn = '0' THEN
215 fine_time <= (OTHERS => '0');
216 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
217 fine_time <= fine_time + 1;
218 END IF;
219 END PROCESS;
220
212 221
213 222 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
214 223 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
215 224 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
216 225
217 226 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
218 227 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
219 228 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
220 229 -----------------------------------------------------------------------------
221 230
222 231 lpp_lfr_ms_1: lpp_lfr_ms
223 232 GENERIC MAP (
224 233 Mem_use => use_CEL)
225 234 PORT MAP (
226 235 clk => clk25MHz,
227 236 rstn => rstn,
228 237 --
229 238 coarse_time => coarse_time,
230 239 fine_time => fine_time,
231 240 --
232 241 sample_f0_wen => sample_f0_wen,
233 242 sample_f0_wdata => sample_f0_wdata,
234 243 sample_f1_wen => sample_f1_wen,
235 244 sample_f1_wdata => sample_f1_wdata,
236 245 sample_f2_wen => sample_f2_wen,
237 246 sample_f2_wdata => sample_f2_wdata,
238 247 --
239 248 dma_addr => dma_addr,
240 249 dma_data => dma_data,
241 250 dma_valid => dma_valid,
242 251 dma_valid_burst => dma_valid_burst,
243 252 dma_ren => dma_ren,
244 253 dma_done => dma_done,
245 254
246 255 ready_matrix_f0 => ready_matrix_f0,
247 256 -- ready_matrix_f0_1 => ready_matrix_f0_1,
248 257 ready_matrix_f1 => ready_matrix_f1,
249 258 ready_matrix_f2 => ready_matrix_f2,
250 259 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
251 260 error_bad_component_error => error_bad_component_error,
252 261 error_buffer_full => error_buffer_full,
253 262 error_input_fifo_write => error_input_fifo_write,
254 263
255 264 debug_reg => debug_reg,
256 265 status_ready_matrix_f0 => status_ready_matrix_f0,
257 266 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
258 267 status_ready_matrix_f1 => status_ready_matrix_f1,
259 268 status_ready_matrix_f2 => status_ready_matrix_f2,
260 269 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
261 270 -- status_error_bad_component_error => status_error_bad_component_error,
262 271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
263 272 config_active_interruption_onError => config_active_interruption_onError,
264 273 addr_matrix_f0 => addr_matrix_f0,
265 274 -- addr_matrix_f0_1 => addr_matrix_f0_1,
266 275 addr_matrix_f1 => addr_matrix_f1,
267 276 addr_matrix_f2 => addr_matrix_f2,
268 277 matrix_time_f0 => matrix_time_f0,
269 278 -- matrix_time_f0_1 => matrix_time_f0_1,
270 279 matrix_time_f1 => matrix_time_f1,
271 280 matrix_time_f2 => matrix_time_f2);
272 281
273 282
274 283
284 apbi.psel(4) <= '0';
275 285
276 286 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
277 287 GENERIC MAP (
278 288 nb_data_by_buffer_size => 11,
279 289 nb_word_by_buffer_size => 11,
280 290 nb_snapshot_param_size => 11,
281 291 delta_vector_size => 20,
282 292 delta_vector_size_f0_2 => 7,
283 293 pindex => 4,
284 294 paddr => 4,
285 295 pmask => 16#fff#,
286 296 pirq_ms => 0,
287 297 pirq_wfp => 1,
288 298 top_lfr_version => (OTHERS => '0')
289 299 )
290 300 PORT MAP (
291 301 HCLK => clk25MHz,
292 302 HRESETn => rstn,
293 303 apbi => apbi,
294 304 apbo => OPEN,
295 305
296 306 run_ms => OPEN,
297 307
298 308 ready_matrix_f0 => ready_matrix_f0,
299 309 ready_matrix_f1 => ready_matrix_f1,
300 310 ready_matrix_f2 => ready_matrix_f2,
301 311 error_bad_component_error => error_bad_component_error,
302 312 error_buffer_full => error_buffer_full, -- TODO
303 313 error_input_fifo_write => error_input_fifo_write, -- TODO
304 314 status_ready_matrix_f0 => status_ready_matrix_f0,
305 315 status_ready_matrix_f1 => status_ready_matrix_f1,
306 316 status_ready_matrix_f2 => status_ready_matrix_f2,
307 317 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
308 318 config_active_interruption_onError => config_active_interruption_onError,
309 319
310 320 matrix_time_f0 => matrix_time_f0,
311 321 matrix_time_f1 => matrix_time_f1,
312 matrix_time_f2 => matrix_time_f2,
322 matrix_time_f2 => matrix_time_f2,
313 323
314 324 addr_matrix_f0 => addr_matrix_f0,
315 325 addr_matrix_f1 => addr_matrix_f1,
316 326 addr_matrix_f2 => addr_matrix_f2,
317 327 -------------------------------------------------------------------------
318 328 status_full => status_full,
319 329 status_full_ack => status_full_ack,
320 330 status_full_err => status_full_err,
321 331 status_new_err => status_new_err,
322 332 data_shaping_BW => OPEN,
323 333 data_shaping_SP0 => OPEN,
324 334 data_shaping_SP1 => OPEN,
325 335 data_shaping_R0 => OPEN,
326 336 data_shaping_R1 => OPEN,
327 337 delta_snapshot => OPEN,
328 338 delta_f0 => OPEN,
329 339 delta_f0_2 => OPEN,
330 340 delta_f1 => OPEN,
331 341 delta_f2 => OPEN,
332 342 nb_data_by_buffer => OPEN,
333 343 nb_word_by_buffer => OPEN,
334 344 nb_snapshot_param => OPEN,
335 345 enable_f0 => OPEN,
336 346 enable_f1 => OPEN,
337 347 enable_f2 => OPEN,
338 348 enable_f3 => OPEN,
339 349 burst_f0 => OPEN,
340 350 burst_f1 => OPEN,
341 351 burst_f2 => OPEN,
342 352 run => OPEN,
343 353 addr_data_f0 => OPEN,
344 354 addr_data_f1 => OPEN,
345 355 addr_data_f2 => OPEN,
346 356 addr_data_f3 => OPEN,
347 357 start_date => OPEN);
348 358
349 359
350 360
351 361
352 362
353 363
354 364
355 365
356 366
357 367
358 368
359 369
360 370
361 371
362 372
363 373
364 374 -- PROCESS (clk25MHz, rstn)
365 375 -- BEGIN -- PROCESS
366 376 -- IF rstn = '0' THEN -- asynchronous reset (active low)
367 377 -- status_ready_matrix_f0 <= '0';
368 378 ---- status_ready_matrix_f0_1 <= '0';
369 379 -- status_ready_matrix_f1 <= '0';
370 380 -- status_ready_matrix_f2 <= '0';
371 381 -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
372 382 -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
373 383 ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
374 384 -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
375 385 -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
376 386 -- END IF;
377 387 -- END PROCESS;
378 388
379 389
380 390
381 391 -- status_error_anticipating_empty_fifo <= '0';
382 392 -- status_error_bad_component_error <= '0';
383 393
384 394 -- config_active_interruption_onNewMatrix <= '0';
385 395 -- config_active_interruption_onError <= '0';
386 396 -- addr_matrix_f0 <= (OTHERS => '0');
387 397 -- addr_matrix_f0_1 <= (OTHERS => '0');
388 398 -- addr_matrix_f1 <= (OTHERS => '0');
389 399 -- addr_matrix_f2 <= (OTHERS => '0');
390 400
391 401
392 402 PROCESS (clk25MHz, rstn)
393 403 BEGIN -- PROCESS
394 404 IF rstn = '0' THEN -- asynchronous reset (active low)
395 405
396 406 dma_ren <= '1';
397 407 dma_done <= '0';
398 408 ren_counter <= 0;
399 409 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
400 410 dma_ren <= '1';
401 411 dma_done <= '0';
402 412
403 413 IF dma_valid_burst = '1' THEN
404 414 ren_counter <= 17;
405 415 END IF;
406 416
407 417 IF ren_counter > 1 THEN
408 418 ren_counter <= ren_counter - 1;
409 419 dma_ren <= '0';
410 420 END IF;
411 421
412 422 IF ren_counter = 1 THEN
413 423 ren_counter <= 0;
414 424 dma_done <= '1';
415 425 END IF;
416 426
417 427 END IF;
418 428 END PROCESS;
419 429
420 430
421 431 END beh;
422 432
Show file before | Show file after | Hide comments
@@ -1,158 +1,212
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
6 6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
7 7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
8 8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
9 9 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
10 10 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
11 11 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
12 12 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
13 13 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 14 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
15 15 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
16 16 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
17 17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
18 18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
19 19 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
20 20 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
21 21 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
22 22 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
23 23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
24 24 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
25 25 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
26 26 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
27 27 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
28 28 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
29 29 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
30 30 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
31 31 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
32 32 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
33 33 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
34 34 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
35 35 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
36 36 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
37 37 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
38 38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
39 39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
40 40 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
41 41 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
42 42 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
43 43 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
44 44 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
45 45 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
46 46 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
47 47 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
48 48 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
49 49 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
50 50 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
51 51 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
52 52 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
53 53 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
54 54 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
55 55 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
56 56 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
57 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
58 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
59 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
60 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
61 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
62 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
63 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
64 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
65 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
66 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
67 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
68 add wave -noupdate -expand -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
69 add wave -noupdate -expand -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
57 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
58 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
59 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
60 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
61 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
62 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
63 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
64 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
65 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
66 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
67 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
68 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
69 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
70 70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
71 71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
72 72 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
73 73 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
74 74 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
75 75 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
76 76 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
77 77 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
78 78 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
79 79 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
80 80 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
81 81 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
82 82 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
83 83 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
84 84 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
85 85 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
86 86 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
87 87 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
88 88 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
89 89 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
90 90 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
91 91 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
92 92 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
93 93 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
94 94 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
95 95 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
96 96 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
97 97 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
98 98 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
99 99 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
100 100 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
101 101 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
102 102 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
103 103 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
104 104 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
105 105 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
106 106 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
107 107 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
108 108 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
109 109 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
110 110 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
111 111 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
112 112 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
113 113 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
114 114 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
115 add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
116 add wave -noupdate -expand -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
117 add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
118 add wave -noupdate -expand -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
119 add wave -noupdate -expand -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
120 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
121 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
122 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
123 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
124 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
125 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
126 add wave -noupdate -expand -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
127 add wave -noupdate -expand -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
128 add wave -noupdate -radix hexadecimal -subitemconfig {/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(0) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(3) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(4) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(5) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(6) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(7) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(8) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(9) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(10) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(11) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(12) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(13) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(14) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(15) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(16) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(17) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(18) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(19) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(20) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(21) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(22) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(23) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(24) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(25) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(26) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(27) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(28) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(29) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(30) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(31) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(32) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(33) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(34) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(35) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(36) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(37) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(38) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(39) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(40) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(41) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(42) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(43) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(44) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(45) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(46) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(47) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(48) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(49) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(50) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(51) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(52) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(53) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(54) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(55) {-height 15 -radix hexadecimal} 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/tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(168) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(169) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(170) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(171) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(172) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(173) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(174) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(175) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(176) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(177) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(178) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(179) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(180) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(181) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(182) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(183) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(184) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(185) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(186) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(187) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(188) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(189) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(190) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(191) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(192) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(193) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(194) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(195) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(196) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(197) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(198) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(199) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(200) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(201) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(202) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(203) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(204) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(205) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(206) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(207) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(208) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(209) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(210) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(211) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(212) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(213) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(214) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(215) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(216) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(217) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(218) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(219) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(220) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(221) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(222) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(223) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(224) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(225) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(226) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(227) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(228) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(229) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(230) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(231) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(232) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(233) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(234) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(235) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(236) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(237) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(238) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(239) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(240) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(241) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(242) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(243) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(244) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(245) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(246) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(247) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(248) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(249) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(250) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(251) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(252) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(253) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(254) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray(255) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
115 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
116 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
117 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
118 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
119 add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
120 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
121 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
122 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
123 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
124 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
125 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
126 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
127 add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
128 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
129 129 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
130 add wave -noupdate -expand -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
131 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
132 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
133 add wave -noupdate -expand -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
134 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
135 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
136 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
137 add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
138 add wave -noupdate -expand -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
139 add wave -noupdate -expand -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
130 add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
131 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
132 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
133 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
134 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
135 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
136 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
137 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
138 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
139 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
140 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp
141 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
142 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
143 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
144 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
145 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
146 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
147 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
148 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
149 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
150 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
151 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
152 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
153 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
154 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
155 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
156 add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time
157 add wave -noupdate /tb/lpp_lfr_ms_1/fine_time
158 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time
159 add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
160 add wave -noupdate /tb/lpp_lfr_ms_1/status_component
161 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
162 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
163 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms
164 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component
165 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel
166 add wave -noupdate /tb/lpp_lfr_ms_1/all_time
167 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a
168 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b
169 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1
170 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2
171 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen
172 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren
173 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata
174 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full
175 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty
176 add wave -noupdate /tb/matrix_time_f0
177 add wave -noupdate /tb/matrix_time_f1
178 add wave -noupdate /tb/matrix_time_f2
179 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
180 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
181 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
182 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
183 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
184 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
185 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
186 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
187 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
188 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
189 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
190 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
191 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
192 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
193 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
140 194 TreeUpdate [SetDefaultTree]
141 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {10435060000 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {99992359332 ps} 0}
142 configure wave -namecolwidth 469
195 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0}
196 configure wave -namecolwidth 486
143 197 configure wave -valuecolwidth 112
144 198 configure wave -justifyvalue left
145 199 configure wave -signalnamewidth 0
146 200 configure wave -snapdistance 10
147 201 configure wave -datasetprefix 0
148 202 configure wave -rowmargin 4
149 203 configure wave -childrowmargin 2
150 204 configure wave -gridoffset 0
151 205 configure wave -gridperiod 1
152 206 configure wave -griddelta 40
153 207 configure wave -timeline 0
154 208 configure wave -timelineunits ps
155 209 update
156 WaveRestoreZoom {10434939916 ps} {10435778196 ps}
210 WaveRestoreZoom {0 ps} {105000147 ns}
157 211 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
158 212 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,731 +1,735
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples(2 DOWNTO 0);
50 50 sample_E : IN Samples(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63 --
64 64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65 65
66 66 --debug
67 67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 --debug_f0_data_valid : OUT STD_LOGIC;
69 69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 --debug_f1_data_valid : OUT STD_LOGIC;
71 71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 --debug_f2_data_valid : OUT STD_LOGIC;
73 73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 74 --debug_f3_data_valid : OUT STD_LOGIC;
75 75
76 76 ---- debug FIFO_IN
77 77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85 85
86 86 ----debug FIFO OUT
87 87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95 95
96 96 ----debug DMA IN
97 97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 105 );
106 106 END lpp_lfr;
107 107
108 108 ARCHITECTURE beh OF lpp_lfr IS
109 109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 111 --
112 112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 116 --
117 117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 120 --
121 121 SIGNAL sample_f0_val : STD_LOGIC;
122 122 SIGNAL sample_f1_val : STD_LOGIC;
123 123 SIGNAL sample_f2_val : STD_LOGIC;
124 124 SIGNAL sample_f3_val : STD_LOGIC;
125 125 --
126 126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 130 --
131 131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134 134
135 135 -- SM
136 136 SIGNAL ready_matrix_f0 : STD_LOGIC;
137 137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 141 SIGNAL error_bad_component_error : STD_LOGIC;
142 142 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 143 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
144 144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
149 149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 151 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155
156 156 -- WFP
157 157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 166
167 167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 170 SIGNAL enable_f0 : STD_LOGIC;
171 171 SIGNAL enable_f1 : STD_LOGIC;
172 172 SIGNAL enable_f2 : STD_LOGIC;
173 173 SIGNAL enable_f3 : STD_LOGIC;
174 174 SIGNAL burst_f0 : STD_LOGIC;
175 175 SIGNAL burst_f1 : STD_LOGIC;
176 176 SIGNAL burst_f2 : STD_LOGIC;
177 177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181
182 182 SIGNAL run : STD_LOGIC;
183 183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184 184
185 185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 190 --f1
191 191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 196 --f2
197 197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 202 --f3
203 203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208 208
209 209 -----------------------------------------------------------------------------
210 210 --
211 211 -----------------------------------------------------------------------------
212 212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 215 --f1
216 216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 219 --f2
220 220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 223 --f3
224 224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227 227
228 228 -----------------------------------------------------------------------------
229 229 -- DMA RR
230 230 -----------------------------------------------------------------------------
231 231 SIGNAL dma_sel_valid : STD_LOGIC;
232 232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 236
237 237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239 239
240 240 -----------------------------------------------------------------------------
241 241 -- DMA_REG
242 242 -----------------------------------------------------------------------------
243 243 SIGNAL ongoing_reg : STD_LOGIC;
244 244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 245 SIGNAL dma_send_reg : STD_LOGIC;
246 246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249
250 250
251 251 -----------------------------------------------------------------------------
252 252 -- DMA
253 253 -----------------------------------------------------------------------------
254 254 SIGNAL dma_send : STD_LOGIC;
255 255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 256 SIGNAL dma_done : STD_LOGIC;
257 257 SIGNAL dma_ren : STD_LOGIC;
258 258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 261
262 262 -----------------------------------------------------------------------------
263 263 -- MS
264 264 -----------------------------------------------------------------------------
265 265
266 266 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 267 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 268 SIGNAL data_ms_valid : STD_LOGIC;
269 269 SIGNAL data_ms_valid_burst : STD_LOGIC;
270 270 SIGNAL data_ms_ren : STD_LOGIC;
271 271 SIGNAL data_ms_done : STD_LOGIC;
272 272 SIGNAL dma_ms_ongoing : STD_LOGIC;
273 273
274 274 SIGNAL run_ms : STD_LOGIC;
275 275 SIGNAL ms_softandhard_rstn : STD_LOGIC;
276 276
277 277 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
278 278 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
279 279 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
280 280 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
281 281
282 282
283 283 SIGNAL error_buffer_full : STD_LOGIC;
284 284 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
285 285
286 286 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
287 287
288 288 BEGIN
289 289
290 290 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
291 291 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
292 292
293 293 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
294 294 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
295 295 --END GENERATE all_channel;
296 296
297 297 -----------------------------------------------------------------------------
298 298 lpp_lfr_filter_1 : lpp_lfr_filter
299 299 GENERIC MAP (
300 300 Mem_use => Mem_use)
301 301 PORT MAP (
302 302 sample => sample_s,
303 303 sample_val => sample_val,
304 304 clk => clk,
305 305 rstn => rstn,
306 306 data_shaping_SP0 => data_shaping_SP0,
307 307 data_shaping_SP1 => data_shaping_SP1,
308 308 data_shaping_R0 => data_shaping_R0,
309 309 data_shaping_R1 => data_shaping_R1,
310 310 sample_f0_val => sample_f0_val,
311 311 sample_f1_val => sample_f1_val,
312 312 sample_f2_val => sample_f2_val,
313 313 sample_f3_val => sample_f3_val,
314 314 sample_f0_wdata => sample_f0_data,
315 315 sample_f1_wdata => sample_f1_data,
316 316 sample_f2_wdata => sample_f2_data,
317 317 sample_f3_wdata => sample_f3_data);
318 318
319 319 -----------------------------------------------------------------------------
320 320 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
321 321 GENERIC MAP (
322 322 nb_data_by_buffer_size => nb_data_by_buffer_size,
323 323 nb_word_by_buffer_size => nb_word_by_buffer_size,
324 324 nb_snapshot_param_size => nb_snapshot_param_size,
325 325 delta_vector_size => delta_vector_size,
326 326 delta_vector_size_f0_2 => delta_vector_size_f0_2,
327 327 pindex => pindex,
328 328 paddr => paddr,
329 329 pmask => pmask,
330 330 pirq_ms => pirq_ms,
331 331 pirq_wfp => pirq_wfp,
332 332 top_lfr_version => top_lfr_version)
333 333 PORT MAP (
334 334 HCLK => clk,
335 335 HRESETn => rstn,
336 336 apbi => apbi,
337 337 apbo => apbo,
338 338
339 339 run_ms => run_ms,
340 340
341 341 ready_matrix_f0 => ready_matrix_f0,
342 342 -- ready_matrix_f0_1 => ready_matrix_f0_1,
343 343 ready_matrix_f1 => ready_matrix_f1,
344 344 ready_matrix_f2 => ready_matrix_f2,
345 345 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
346 346 error_bad_component_error => error_bad_component_error,
347 347 error_buffer_full => error_buffer_full, -- TODO
348 348 error_input_fifo_write => error_input_fifo_write, -- TODO
349 349 -- debug_reg => debug_reg,
350 350 status_ready_matrix_f0 => status_ready_matrix_f0,
351 351 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
352 352 status_ready_matrix_f1 => status_ready_matrix_f1,
353 353 status_ready_matrix_f2 => status_ready_matrix_f2,
354 354 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
355 355 -- status_error_bad_component_error => status_error_bad_component_error,
356 356 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
357 357 config_active_interruption_onError => config_active_interruption_onError,
358 358
359 359 matrix_time_f0 => matrix_time_f0,
360 360 -- matrix_time_f0_1 => matrix_time_f0_1,
361 361 matrix_time_f1 => matrix_time_f1,
362 362 matrix_time_f2 => matrix_time_f2,
363 363
364 364 addr_matrix_f0 => addr_matrix_f0,
365 365 -- addr_matrix_f0_1 => addr_matrix_f0_1,
366 366 addr_matrix_f1 => addr_matrix_f1,
367 367 addr_matrix_f2 => addr_matrix_f2,
368 368 -------------------------------------------------------------------------
369 369 status_full => status_full,
370 370 status_full_ack => status_full_ack,
371 371 status_full_err => status_full_err,
372 372 status_new_err => status_new_err,
373 373 data_shaping_BW => data_shaping_BW,
374 374 data_shaping_SP0 => data_shaping_SP0,
375 375 data_shaping_SP1 => data_shaping_SP1,
376 376 data_shaping_R0 => data_shaping_R0,
377 377 data_shaping_R1 => data_shaping_R1,
378 378 delta_snapshot => delta_snapshot,
379 379 delta_f0 => delta_f0,
380 380 delta_f0_2 => delta_f0_2,
381 381 delta_f1 => delta_f1,
382 382 delta_f2 => delta_f2,
383 383 nb_data_by_buffer => nb_data_by_buffer,
384 384 nb_word_by_buffer => nb_word_by_buffer,
385 385 nb_snapshot_param => nb_snapshot_param,
386 386 enable_f0 => enable_f0,
387 387 enable_f1 => enable_f1,
388 388 enable_f2 => enable_f2,
389 389 enable_f3 => enable_f3,
390 390 burst_f0 => burst_f0,
391 391 burst_f1 => burst_f1,
392 392 burst_f2 => burst_f2,
393 393 run => run,
394 394 addr_data_f0 => addr_data_f0,
395 395 addr_data_f1 => addr_data_f1,
396 396 addr_data_f2 => addr_data_f2,
397 397 addr_data_f3 => addr_data_f3,
398 398 start_date => start_date);
399 399
400 400 -----------------------------------------------------------------------------
401 401 -----------------------------------------------------------------------------
402 402 lpp_waveform_1 : lpp_waveform
403 403 GENERIC MAP (
404 404 tech => inferred,
405 405 data_size => 6*16,
406 406 nb_data_by_buffer_size => nb_data_by_buffer_size,
407 407 nb_word_by_buffer_size => nb_word_by_buffer_size,
408 408 nb_snapshot_param_size => nb_snapshot_param_size,
409 409 delta_vector_size => delta_vector_size,
410 410 delta_vector_size_f0_2 => delta_vector_size_f0_2
411 411 )
412 412 PORT MAP (
413 413 clk => clk,
414 414 rstn => rstn,
415 415
416 416 reg_run => run,
417 417 reg_start_date => start_date,
418 418 reg_delta_snapshot => delta_snapshot,
419 419 reg_delta_f0 => delta_f0,
420 420 reg_delta_f0_2 => delta_f0_2,
421 421 reg_delta_f1 => delta_f1,
422 422 reg_delta_f2 => delta_f2,
423 423
424 424 enable_f0 => enable_f0,
425 425 enable_f1 => enable_f1,
426 426 enable_f2 => enable_f2,
427 427 enable_f3 => enable_f3,
428 428 burst_f0 => burst_f0,
429 429 burst_f1 => burst_f1,
430 430 burst_f2 => burst_f2,
431 431
432 432 nb_data_by_buffer => nb_data_by_buffer,
433 433 nb_word_by_buffer => nb_word_by_buffer,
434 434 nb_snapshot_param => nb_snapshot_param,
435 435 status_full => status_full,
436 436 status_full_ack => status_full_ack,
437 437 status_full_err => status_full_err,
438 438 status_new_err => status_new_err,
439 439
440 440 coarse_time => coarse_time,
441 441 fine_time => fine_time,
442 442
443 443 --f0
444 444 addr_data_f0 => addr_data_f0,
445 445 data_f0_in_valid => sample_f0_val,
446 446 data_f0_in => sample_f0_data,
447 447 --f1
448 448 addr_data_f1 => addr_data_f1,
449 449 data_f1_in_valid => sample_f1_val,
450 450 data_f1_in => sample_f1_data,
451 451 --f2
452 452 addr_data_f2 => addr_data_f2,
453 453 data_f2_in_valid => sample_f2_val,
454 454 data_f2_in => sample_f2_data,
455 455 --f3
456 456 addr_data_f3 => addr_data_f3,
457 457 data_f3_in_valid => sample_f3_val,
458 458 data_f3_in => sample_f3_data,
459 459 -- OUTPUT -- DMA interface
460 460 --f0
461 461 data_f0_addr_out => data_f0_addr_out_s,
462 462 data_f0_data_out => data_f0_data_out,
463 463 data_f0_data_out_valid => data_f0_data_out_valid_s,
464 464 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
465 465 data_f0_data_out_ren => data_f0_data_out_ren,
466 466 --f1
467 467 data_f1_addr_out => data_f1_addr_out_s,
468 468 data_f1_data_out => data_f1_data_out,
469 469 data_f1_data_out_valid => data_f1_data_out_valid_s,
470 470 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
471 471 data_f1_data_out_ren => data_f1_data_out_ren,
472 472 --f2
473 473 data_f2_addr_out => data_f2_addr_out_s,
474 474 data_f2_data_out => data_f2_data_out,
475 475 data_f2_data_out_valid => data_f2_data_out_valid_s,
476 476 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
477 477 data_f2_data_out_ren => data_f2_data_out_ren,
478 478 --f3
479 479 data_f3_addr_out => data_f3_addr_out_s,
480 480 data_f3_data_out => data_f3_data_out,
481 481 data_f3_data_out_valid => data_f3_data_out_valid_s,
482 482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
483 483 data_f3_data_out_ren => data_f3_data_out_ren ,
484 484
485 485 -------------------------------------------------------------------------
486 486 observation_reg => OPEN
487 487
488 488 );
489 489
490 490
491 491 -----------------------------------------------------------------------------
492 492 -- TEMP
493 493 -----------------------------------------------------------------------------
494 494
495 495 PROCESS (clk, rstn)
496 496 BEGIN -- PROCESS
497 497 IF rstn = '0' THEN -- asynchronous reset (active low)
498 498 data_f0_data_out_valid <= '0';
499 499 data_f0_data_out_valid_burst <= '0';
500 500 data_f1_data_out_valid <= '0';
501 501 data_f1_data_out_valid_burst <= '0';
502 502 data_f2_data_out_valid <= '0';
503 503 data_f2_data_out_valid_burst <= '0';
504 504 data_f3_data_out_valid <= '0';
505 505 data_f3_data_out_valid_burst <= '0';
506 506 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
507 507 data_f0_data_out_valid <= data_f0_data_out_valid_s;
508 508 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
509 509 data_f1_data_out_valid <= data_f1_data_out_valid_s;
510 510 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
511 511 data_f2_data_out_valid <= data_f2_data_out_valid_s;
512 512 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
513 513 data_f3_data_out_valid <= data_f3_data_out_valid_s;
514 514 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
515 515 END IF;
516 516 END PROCESS;
517 517
518 518 data_f0_addr_out <= data_f0_addr_out_s;
519 519 data_f1_addr_out <= data_f1_addr_out_s;
520 520 data_f2_addr_out <= data_f2_addr_out_s;
521 521 data_f3_addr_out <= data_f3_addr_out_s;
522 522
523 523 -----------------------------------------------------------------------------
524 524 -- RoundRobin Selection For DMA
525 525 -----------------------------------------------------------------------------
526 526
527 527 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
528 528 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
529 529 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
530 530 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
531 531
532 532 RR_Arbiter_4_1 : RR_Arbiter_4
533 533 PORT MAP (
534 534 clk => clk,
535 535 rstn => rstn,
536 536 in_valid => dma_rr_valid,
537 537 out_grant => dma_rr_grant_s);
538 538
539 539 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
540 540 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
541 541 dma_rr_valid_ms(2) <= '0';
542 542 dma_rr_valid_ms(3) <= '0';
543 543
544 544 RR_Arbiter_4_2 : RR_Arbiter_4
545 545 PORT MAP (
546 546 clk => clk,
547 547 rstn => rstn,
548 548 in_valid => dma_rr_valid_ms,
549 549 out_grant => dma_rr_grant_ms);
550 550
551 551 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
552 552
553 553
554 554 -----------------------------------------------------------------------------
555 555 -- in : dma_rr_grant
556 556 -- send
557 557 -- out : dma_sel
558 558 -- dma_valid_burst
559 559 -- dma_sel_valid
560 560 -----------------------------------------------------------------------------
561 561 PROCESS (clk, rstn)
562 562 BEGIN -- PROCESS
563 563 IF rstn = '0' THEN -- asynchronous reset (active low)
564 564 dma_sel <= (OTHERS => '0');
565 565 dma_send <= '0';
566 566 dma_valid_burst <= '0';
567 567 data_ms_done <= '0';
568 568 dma_ms_ongoing <= '0';
569 569 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
570 570 IF run = '1' THEN
571 571 data_ms_done <= '0';
572 572 IF dma_sel = "00000" OR dma_done = '1' THEN
573 573 dma_sel <= dma_rr_grant;
574 574 IF dma_rr_grant(0) = '1' THEN
575 575 dma_ms_ongoing <= '0';
576 576 dma_send <= '1';
577 577 dma_valid_burst <= data_f0_data_out_valid_burst;
578 578 dma_sel_valid <= data_f0_data_out_valid;
579 579 ELSIF dma_rr_grant(1) = '1' THEN
580 580 dma_ms_ongoing <= '0';
581 581 dma_send <= '1';
582 582 dma_valid_burst <= data_f1_data_out_valid_burst;
583 583 dma_sel_valid <= data_f1_data_out_valid;
584 584 ELSIF dma_rr_grant(2) = '1' THEN
585 585 dma_ms_ongoing <= '0';
586 586 dma_send <= '1';
587 587 dma_valid_burst <= data_f2_data_out_valid_burst;
588 588 dma_sel_valid <= data_f2_data_out_valid;
589 589 ELSIF dma_rr_grant(3) = '1' THEN
590 590 dma_ms_ongoing <= '0';
591 591 dma_send <= '1';
592 592 dma_valid_burst <= data_f3_data_out_valid_burst;
593 593 dma_sel_valid <= data_f3_data_out_valid;
594 594 ELSIF dma_rr_grant(4) = '1' THEN
595 595 dma_ms_ongoing <= '1';
596 596 dma_send <= '1';
597 597 dma_valid_burst <= data_ms_valid_burst;
598 598 dma_sel_valid <= data_ms_valid;
599 ELSE
600 dma_ms_ongoing <= '0';
599 --ELSE
600 --dma_ms_ongoing <= '0';
601 601 END IF;
602 602
603 IF dma_ms_ongoing = '1' THEN
603 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
604 604 data_ms_done <= '1';
605 605 END IF;
606 606 ELSE
607 607 dma_sel <= dma_sel;
608 608 dma_send <= '0';
609 609 END IF;
610 610 ELSE
611 611 data_ms_done <= '0';
612 612 dma_sel <= (OTHERS => '0');
613 613 dma_send <= '0';
614 614 dma_valid_burst <= '0';
615 615 END IF;
616 616 END IF;
617 617 END PROCESS;
618 618
619 619
620 620 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
621 621 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
622 622 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
623 623 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
624 624 data_ms_addr;
625 625
626 626 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
627 627 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
628 628 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
629 629 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
630 630 data_ms_data;
631 631
632 632 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
633 633 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
634 634 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
635 635 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
636 636 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
637 637
638 638 dma_data_2 <= dma_data;
639 639
640 640
641 641 -----------------------------------------------------------------------------
642 642 -- DMA
643 643 -----------------------------------------------------------------------------
644 644 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
645 645 GENERIC MAP (
646 646 tech => inferred,
647 647 hindex => hindex)
648 648 PORT MAP (
649 649 HCLK => clk,
650 650 HRESETn => rstn,
651 651 run => run,
652 652 AHB_Master_In => ahbi,
653 653 AHB_Master_Out => ahbo,
654 654
655 655 send => dma_send,
656 656 valid_burst => dma_valid_burst,
657 657 done => dma_done,
658 658 ren => dma_ren,
659 659 address => dma_address,
660 660 data => dma_data_2);
661 661
662 662 -----------------------------------------------------------------------------
663 663 -- Matrix Spectral
664 664 -----------------------------------------------------------------------------
665 665 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
666 666 NOT(sample_f0_val) & NOT(sample_f0_val);
667 667 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
668 668 NOT(sample_f1_val) & NOT(sample_f1_val);
669 669 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
670 670 NOT(sample_f3_val) & NOT(sample_f3_val);
671 671
672 672 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
673 673 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
674 674 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
675 675
676 676 -------------------------------------------------------------------------------
677 677
678 678 ms_softandhard_rstn <= rstn AND run_ms AND run;
679 679
680 680 -----------------------------------------------------------------------------
681 681 lpp_lfr_ms_1 : lpp_lfr_ms
682 682 GENERIC MAP (
683 683 Mem_use => Mem_use)
684 684 PORT MAP (
685 685 clk => clk,
686 686 rstn => ms_softandhard_rstn, --rstn,
687 687
688 688 coarse_time => coarse_time,
689 689 fine_time => fine_time,
690 690
691 691 sample_f0_wen => sample_f0_wen,
692 692 sample_f0_wdata => sample_f0_wdata,
693 693 sample_f1_wen => sample_f1_wen,
694 694 sample_f1_wdata => sample_f1_wdata,
695 695 sample_f2_wen => sample_f3_wen, -- TODO
696 696 sample_f2_wdata => sample_f3_wdata,-- TODO
697 697
698 698 dma_addr => data_ms_addr, --
699 699 dma_data => data_ms_data, --
700 700 dma_valid => data_ms_valid, --
701 701 dma_valid_burst => data_ms_valid_burst, --
702 702 dma_ren => data_ms_ren, --
703 703 dma_done => data_ms_done, --
704 704
705 705 ready_matrix_f0 => ready_matrix_f0,
706 706 ready_matrix_f1 => ready_matrix_f1,
707 707 ready_matrix_f2 => ready_matrix_f2,
708 708 error_bad_component_error => error_bad_component_error,
709 709 error_buffer_full => error_buffer_full,
710 710 error_input_fifo_write => error_input_fifo_write,
711 711
712 712 debug_reg => debug_ms,--observation_reg,
713 713
714 714 status_ready_matrix_f0 => status_ready_matrix_f0,
715 715 status_ready_matrix_f1 => status_ready_matrix_f1,
716 716 status_ready_matrix_f2 => status_ready_matrix_f2,
717 717 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
718 718 config_active_interruption_onError => config_active_interruption_onError,
719 719 addr_matrix_f0 => addr_matrix_f0,
720 720 addr_matrix_f1 => addr_matrix_f1,
721 721 addr_matrix_f2 => addr_matrix_f2,
722 722
723 723 matrix_time_f0 => matrix_time_f0,
724 724 matrix_time_f1 => matrix_time_f1,
725 725 matrix_time_f2 => matrix_time_f2);
726 726
727 727 -----------------------------------------------------------------------------
728 observation_reg(31 DOWNTO 0) <= debug_ms(30 DOWNTO 0) & ms_softandhard_rstn;
729
728 observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) &
729 dma_ms_ongoing & -- 8
730 data_ms_done & -- 7
731 dma_done & -- 6
732 dma_sel & -- 5 .. 1
733 ms_softandhard_rstn; -- 0
730 734
731 735 END beh;
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@@ -1,93 +1,96
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26
27 27 ENTITY lpp_apbreg_ms_pointer IS
28 28
29 29 PORT (
30 30 clk : IN STD_LOGIC;
31 31 rstn : IN STD_LOGIC;
32 32
33 33 -- REG 0
34 34 reg0_status_ready_matrix : IN STD_LOGIC;
35 35 reg0_ready_matrix : OUT STD_LOGIC;
36 36 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 37 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
38 38
39 39 -- REG 1
40 40 reg1_status_ready_matrix : IN STD_LOGIC;
41 41 reg1_ready_matrix : OUT STD_LOGIC;
42 42 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
43 43 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
44 44
45 45 -- SpectralMatrix
46 46 ready_matrix : IN STD_LOGIC;
47 47 status_ready_matrix : OUT STD_LOGIC;
48 48 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
50 50 );
51 51
52 52 END lpp_apbreg_ms_pointer;
53 53
54 54 ARCHITECTURE beh OF lpp_apbreg_ms_pointer IS
55 55
56 56 SIGNAL current_reg : STD_LOGIC;
57 57
58 58 BEGIN -- beh
59 59
60 60 PROCESS (clk, rstn)
61 61 BEGIN -- PROCESS
62 62 IF rstn = '0' THEN -- asynchronous reset (active low)
63 63 current_reg <= '0';
64 64 reg0_matrix_time <= (OTHERS => '0');
65 65 reg1_matrix_time <= (OTHERS => '0');
66 66
67 67 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
68 68 IF ready_matrix = '1' THEN
69 69 current_reg <= NOT current_reg;
70 END IF;
71 IF current_reg = '0' THEN
72 reg0_matrix_time <= matrix_time;
73 END IF;
74 IF current_reg = '1' THEN
75 reg1_matrix_time <= matrix_time;
70
71 IF current_reg = '0' THEN
72 reg0_matrix_time <= matrix_time;
73 END IF;
74
75 IF current_reg = '1' THEN
76 reg1_matrix_time <= matrix_time;
77 END IF;
78
76 79 END IF;
77 80
78 81 END IF;
79 82 END PROCESS;
80 83
81 84 addr_matrix <= reg0_addr_matrix WHEN current_reg = '0' ELSE
82 85 reg1_addr_matrix;
83 86
84 87 status_ready_matrix <= reg0_status_ready_matrix WHEN current_reg = '0' ELSE
85 88 reg1_status_ready_matrix;
86 89
87 90 reg0_ready_matrix <= ready_matrix WHEN current_reg = '0' ELSE '0';
88 91 reg1_ready_matrix <= ready_matrix WHEN current_reg = '1' ELSE '0';
89 92
90 93
91 94
92 95
93 96 END beh;
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@@ -1,943 +1,929
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0 : OUT STD_LOGIC;
53 53 ready_matrix_f1 : OUT STD_LOGIC;
54 54 ready_matrix_f2 : OUT STD_LOGIC;
55 55 error_bad_component_error : OUT STD_LOGIC;
56 56 error_buffer_full : OUT STD_LOGIC;
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60
61 61 -- Reg In
62 62 status_ready_matrix_f0 : IN STD_LOGIC;
63 63 status_ready_matrix_f1 : IN STD_LOGIC;
64 64 status_ready_matrix_f2 : IN STD_LOGIC;
65 65
66 66 config_active_interruption_onNewMatrix : IN STD_LOGIC;
67 67 config_active_interruption_onError : IN STD_LOGIC;
68 68 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71
72 72 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
73 73 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
74 74 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
75 75
76 76 );
77 77 END;
78 78
79 79 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
80 80
81 81 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 82 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 83 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 84 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 85 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 86
87 87 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 88 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 90 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 91 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92
93 93 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 94 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 96 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 97
98 98 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99
100 100 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 101 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 103 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 104
105 105 SIGNAL error_wen_f0 : STD_LOGIC;
106 106 SIGNAL error_wen_f1 : STD_LOGIC;
107 107 SIGNAL error_wen_f2 : STD_LOGIC;
108 108
109 109 SIGNAL one_sample_f1_full : STD_LOGIC;
110 110 SIGNAL one_sample_f1_wen : STD_LOGIC;
111 111 SIGNAL one_sample_f2_full : STD_LOGIC;
112 112 SIGNAL one_sample_f2_wen : STD_LOGIC;
113 113
114 114 -----------------------------------------------------------------------------
115 115 -- FSM / SWITCH SELECT CHANNEL
116 116 -----------------------------------------------------------------------------
117 117 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
118 118 SIGNAL state_fsm_select_channel : fsm_select_channel;
119 119 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
120 120
121 121 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
122 122 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 123 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 124 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 125
126 126 -----------------------------------------------------------------------------
127 127 -- FSM LOAD FFT
128 128 -----------------------------------------------------------------------------
129 129 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
130 130 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
131 131 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
132 132
133 133 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 134 SIGNAL sample_load : STD_LOGIC;
135 135 SIGNAL sample_valid : STD_LOGIC;
136 136 SIGNAL sample_valid_r : STD_LOGIC;
137 137 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
138 138
139 139
140 140 -----------------------------------------------------------------------------
141 141 -- FFT
142 142 -----------------------------------------------------------------------------
143 143 SIGNAL fft_read : STD_LOGIC;
144 144 SIGNAL fft_pong : STD_LOGIC;
145 145 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
146 146 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
147 147 SIGNAL fft_data_valid : STD_LOGIC;
148 148 SIGNAL fft_ready : STD_LOGIC;
149 149 -----------------------------------------------------------------------------
150 150 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
151 151 -----------------------------------------------------------------------------
152 152 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
153 153 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
154 154 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 155 SIGNAL current_fifo_empty : STD_LOGIC;
156 156 SIGNAL current_fifo_locked : STD_LOGIC;
157 157 SIGNAL current_fifo_full : STD_LOGIC;
158 158 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
159 159
160 160 -----------------------------------------------------------------------------
161 161 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 162 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 163 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 164 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 169 -----------------------------------------------------------------------------
170 170 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
171 171 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
172 172 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 173
174 174 SIGNAL SM_correlation_start : STD_LOGIC;
175 175 SIGNAL SM_correlation_auto : STD_LOGIC;
176 176 SIGNAL SM_correlation_done : STD_LOGIC;
177 177 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
178 178 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
179 179 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
180 180 SIGNAL SM_correlation_begin : STD_LOGIC;
181 181
182 182 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
183 183 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 184 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
185 185
186 186 SIGNAL current_matrix_write : STD_LOGIC;
187 187 SIGNAL current_matrix_wait_empty : STD_LOGIC;
188 188 -----------------------------------------------------------------------------
189 189 SIGNAL fifo_0_ready : STD_LOGIC;
190 190 SIGNAL fifo_1_ready : STD_LOGIC;
191 191 SIGNAL fifo_ongoing : STD_LOGIC;
192 192
193 193 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
194 194 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
195 195 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
197 197 -----------------------------------------------------------------------------
198 198 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
199 199 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
200 200 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 201 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
202 202 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 203 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- TIME REG & INFOs
207 207 -----------------------------------------------------------------------------
208 208 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
209 209
210 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
211 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
212 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
214
210 215 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 216 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 217 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
213 218 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
214 219
215 SIGNAL time_update_f0_A : STD_LOGIC;
216 SIGNAL time_update_f0_B : STD_LOGIC;
217 SIGNAL time_update_f1 : STD_LOGIC;
218 SIGNAL time_update_f2 : STD_LOGIC;
220 --SIGNAL time_update_f0_A : STD_LOGIC;
221 --SIGNAL time_update_f0_B : STD_LOGIC;
222 --SIGNAL time_update_f1 : STD_LOGIC;
223 --SIGNAL time_update_f2 : STD_LOGIC;
219 224 --
220 225 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
221 226 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
222 227 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
223 228
224 229 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
225 230 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
226 231 SIGNAL status_component_fifo_0_end : STD_LOGIC;
227 232 SIGNAL status_component_fifo_1_end : STD_LOGIC;
228 233 -----------------------------------------------------------------------------
229 234
230 235 BEGIN
231 236
232 237
233 238 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
234 239
235 240
236 241 switch_f0_inst : spectral_matrix_switch_f0
237 242 PORT MAP (
238 243 clk => clk,
239 244 rstn => rstn,
240 245
241 246 sample_wen => sample_f0_wen,
242 247
243 248 fifo_A_empty => sample_f0_A_empty,
244 249 fifo_A_full => sample_f0_A_full,
245 250 fifo_A_wen => sample_f0_A_wen,
246 251
247 252 fifo_B_empty => sample_f0_B_empty,
248 253 fifo_B_full => sample_f0_B_full,
249 254 fifo_B_wen => sample_f0_B_wen,
250 255
251 256 error_wen => error_wen_f0); -- TODO
252 257
253 258 -----------------------------------------------------------------------------
254 259 -- FIFO IN
255 260 -----------------------------------------------------------------------------
256 261 lppFIFOxN_f0_a : lppFIFOxN
257 262 GENERIC MAP (
258 263 tech => 0,
259 264 Mem_use => Mem_use,
260 265 Data_sz => 16,
261 266 Addr_sz => 8,
262 267 FifoCnt => 5)
263 268 PORT MAP (
264 269 clk => clk,
265 270 rstn => rstn,
266 271
267 272 ReUse => (OTHERS => '0'),
268 273
269 274 wen => sample_f0_A_wen,
270 275 wdata => sample_f0_wdata,
271 276
272 277 ren => sample_f0_A_ren,
273 278 rdata => sample_f0_A_rdata,
274 279
275 280 empty => sample_f0_A_empty,
276 281 full => sample_f0_A_full,
277 282 almost_full => OPEN);
278 283
279 284 lppFIFOxN_f0_b : lppFIFOxN
280 285 GENERIC MAP (
281 286 tech => 0,
282 287 Mem_use => Mem_use,
283 288 Data_sz => 16,
284 289 Addr_sz => 8,
285 290 FifoCnt => 5)
286 291 PORT MAP (
287 292 clk => clk,
288 293 rstn => rstn,
289 294
290 295 ReUse => (OTHERS => '0'),
291 296
292 297 wen => sample_f0_B_wen,
293 298 wdata => sample_f0_wdata,
294 299 ren => sample_f0_B_ren,
295 300 rdata => sample_f0_B_rdata,
296 301 empty => sample_f0_B_empty,
297 302 full => sample_f0_B_full,
298 303 almost_full => OPEN);
299 304
300 305 lppFIFOxN_f1 : lppFIFOxN
301 306 GENERIC MAP (
302 307 tech => 0,
303 308 Mem_use => Mem_use,
304 309 Data_sz => 16,
305 310 Addr_sz => 8,
306 311 FifoCnt => 5)
307 312 PORT MAP (
308 313 clk => clk,
309 314 rstn => rstn,
310 315
311 316 ReUse => (OTHERS => '0'),
312 317
313 318 wen => sample_f1_wen,
314 319 wdata => sample_f1_wdata,
315 320 ren => sample_f1_ren,
316 321 rdata => sample_f1_rdata,
317 322 empty => sample_f1_empty,
318 323 full => sample_f1_full,
319 324 almost_full => sample_f1_almost_full);
320 325
321 326
322 327 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
323 328
324 329 PROCESS (clk, rstn)
325 330 BEGIN -- PROCESS
326 331 IF rstn = '0' THEN -- asynchronous reset (active low)
327 332 one_sample_f1_full <= '0';
328 333 error_wen_f1 <= '0';
329 334 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
330 335 IF sample_f1_full = "00000" THEN
331 336 one_sample_f1_full <= '0';
332 337 ELSE
333 338 one_sample_f1_full <= '1';
334 339 END IF;
335 340 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
336 341 END IF;
337 342 END PROCESS;
338 343
339 344
340 345 lppFIFOxN_f2 : lppFIFOxN
341 346 GENERIC MAP (
342 347 tech => 0,
343 348 Mem_use => Mem_use,
344 349 Data_sz => 16,
345 350 Addr_sz => 8,
346 351 FifoCnt => 5)
347 352 PORT MAP (
348 353 clk => clk,
349 354 rstn => rstn,
350 355
351 356 ReUse => (OTHERS => '0'),
352 357
353 358 wen => sample_f2_wen,
354 359 wdata => sample_f2_wdata,
355 360 ren => sample_f2_ren,
356 361 rdata => sample_f2_rdata,
357 362 empty => sample_f2_empty,
358 363 full => sample_f2_full,
359 364 almost_full => OPEN);
360 365
361 366
362 367 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
363 368
364 369 PROCESS (clk, rstn)
365 370 BEGIN -- PROCESS
366 371 IF rstn = '0' THEN -- asynchronous reset (active low)
367 372 one_sample_f2_full <= '0';
368 373 error_wen_f2 <= '0';
369 374 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
370 375 IF sample_f2_full = "00000" THEN
371 376 one_sample_f2_full <= '0';
372 377 ELSE
373 378 one_sample_f2_full <= '1';
374 379 END IF;
375 380 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
376 381 END IF;
377 382 END PROCESS;
378 383
379 384 -----------------------------------------------------------------------------
380 385 -- FSM SELECT CHANNEL
381 386 -----------------------------------------------------------------------------
382 387 PROCESS (clk, rstn)
383 388 BEGIN
384 389 IF rstn = '0' THEN
385 390 state_fsm_select_channel <= IDLE;
386 391 ELSIF clk'EVENT AND clk = '1' THEN
387 392 CASE state_fsm_select_channel IS
388 393 WHEN IDLE =>
389 394 IF sample_f1_full = "11111" THEN
390 395 state_fsm_select_channel <= SWITCH_F1;
391 396 ELSIF sample_f1_almost_full = "00000" THEN
392 397 IF sample_f0_A_full = "11111" THEN
393 398 state_fsm_select_channel <= SWITCH_F0_A;
394 399 ELSIF sample_f0_B_full = "11111" THEN
395 400 state_fsm_select_channel <= SWITCH_F0_B;
396 401 ELSIF sample_f2_full = "11111" THEN
397 402 state_fsm_select_channel <= SWITCH_F2;
398 403 END IF;
399 404 END IF;
400 405
401 406 WHEN SWITCH_F0_A =>
402 407 IF sample_f0_A_empty = "11111" THEN
403 408 state_fsm_select_channel <= IDLE;
404 409 END IF;
405 410 WHEN SWITCH_F0_B =>
406 411 IF sample_f0_B_empty = "11111" THEN
407 412 state_fsm_select_channel <= IDLE;
408 413 END IF;
409 414 WHEN SWITCH_F1 =>
410 415 IF sample_f1_empty = "11111" THEN
411 416 state_fsm_select_channel <= IDLE;
412 417 END IF;
413 418 WHEN SWITCH_F2 =>
414 419 IF sample_f2_empty = "11111" THEN
415 420 state_fsm_select_channel <= IDLE;
416 421 END IF;
417 422 WHEN OTHERS => NULL;
418 423 END CASE;
419 424
420 425 END IF;
421 426 END PROCESS;
422 427
423 428 PROCESS (clk, rstn)
424 429 BEGIN
425 430 IF rstn = '0' THEN
426 431 pre_state_fsm_select_channel <= IDLE;
427 432 ELSIF clk'EVENT AND clk = '1' THEN
428 433 pre_state_fsm_select_channel <= state_fsm_select_channel;
429 434 END IF;
430 435 END PROCESS;
431 436
432 437
433 438 -----------------------------------------------------------------------------
434 439 -- SWITCH SELECT CHANNEL
435 440 -----------------------------------------------------------------------------
436 441 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
437 442 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
438 443 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
439 444 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
440 445 (OTHERS => '1');
441 446
442 447 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
443 448 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
444 449 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
445 450 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
446 451 (OTHERS => '0');
447 452
448 453 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
449 454 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
450 455 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
451 456 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
452 457
453 458
454 459 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
455 460 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
456 461 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
457 462 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
458 463
459 464
460 465 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
461 466 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
462 467 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
463 468 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
464 469
465 470 -----------------------------------------------------------------------------
466 471 -- FSM LOAD FFT
467 472 -----------------------------------------------------------------------------
468 473
469 474 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
470 475
471 476 PROCESS (clk, rstn)
472 477 BEGIN
473 478 IF rstn = '0' THEN
474 479 sample_ren_s <= (OTHERS => '1');
475 480 state_fsm_load_FFT <= IDLE;
476 481 status_MS_input <= (OTHERS => '0');
477 482 --next_state_fsm_load_FFT <= IDLE;
478 483 --sample_valid <= '0';
479 484 ELSIF clk'EVENT AND clk = '1' THEN
480 485 CASE state_fsm_load_FFT IS
481 486 WHEN IDLE =>
482 487 --sample_valid <= '0';
483 488 sample_ren_s <= (OTHERS => '1');
484 489 IF sample_full = "11111" AND sample_load = '1' THEN
485 490 state_fsm_load_FFT <= FIFO_1;
486 491 status_MS_input <= status_channel;
487 492 END IF;
488 493
489 494 WHEN FIFO_1 =>
490 495 sample_ren_s <= "1111" & NOT(sample_load);
491 496 IF sample_empty(0) = '1' THEN
492 497 sample_ren_s <= (OTHERS => '1');
493 498 state_fsm_load_FFT <= FIFO_2;
494 499 END IF;
495 500
496 501 WHEN FIFO_2 =>
497 502 sample_ren_s <= "111" & NOT(sample_load) & '1';
498 503 IF sample_empty(1) = '1' THEN
499 504 sample_ren_s <= (OTHERS => '1');
500 505 state_fsm_load_FFT <= FIFO_3;
501 506 END IF;
502 507
503 508 WHEN FIFO_3 =>
504 509 sample_ren_s <= "11" & NOT(sample_load) & "11";
505 510 IF sample_empty(2) = '1' THEN
506 511 sample_ren_s <= (OTHERS => '1');
507 512 state_fsm_load_FFT <= FIFO_4;
508 513 END IF;
509 514
510 515 WHEN FIFO_4 =>
511 516 sample_ren_s <= '1' & NOT(sample_load) & "111";
512 517 IF sample_empty(3) = '1' THEN
513 518 sample_ren_s <= (OTHERS => '1');
514 519 state_fsm_load_FFT <= FIFO_5;
515 520 END IF;
516 521
517 522 WHEN FIFO_5 =>
518 523 sample_ren_s <= NOT(sample_load) & "1111";
519 524 IF sample_empty(4) = '1' THEN
520 525 sample_ren_s <= (OTHERS => '1');
521 526 state_fsm_load_FFT <= IDLE;
522 527 END IF;
523 528 WHEN OTHERS => NULL;
524 529 END CASE;
525 530 END IF;
526 531 END PROCESS;
527 532
528 533 PROCESS (clk, rstn)
529 534 BEGIN
530 535 IF rstn = '0' THEN
531 536 sample_valid_r <= '0';
532 537 next_state_fsm_load_FFT <= IDLE;
533 538 ELSIF clk'EVENT AND clk = '1' THEN
534 539 next_state_fsm_load_FFT <= state_fsm_load_FFT;
535 540 IF sample_ren_s = "11111" THEN
536 541 sample_valid_r <= '0';
537 542 ELSE
538 543 sample_valid_r <= '1';
539 544 END IF;
540 545 END IF;
541 546 END PROCESS;
542 547
543 548 sample_valid <= sample_valid_r AND sample_load;
544 549
545 550 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
546 551 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
547 552 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
548 553 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
549 554 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
550 555
551 556 -----------------------------------------------------------------------------
552 557 -- FFT
553 558 -----------------------------------------------------------------------------
554 559 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
555 560 PORT MAP (
556 561 clk => clk,
557 562 rstn => rstn,
558 563 sample_valid => sample_valid,
559 564 fft_read => fft_read,
560 565 sample_data => sample_data,
561 566 sample_load => sample_load,
562 567 fft_pong => fft_pong,
563 568 fft_data_im => fft_data_im,
564 569 fft_data_re => fft_data_re,
565 570 fft_data_valid => fft_data_valid,
566 571 fft_ready => fft_ready);
567 572
568 573 -----------------------------------------------------------------------------
569 574 PROCESS (clk, rstn)
570 575 BEGIN
571 576 IF rstn = '0' THEN
572 577 state_fsm_load_MS_memory <= IDLE;
573 578 current_fifo_load <= "00001";
574 579 ELSIF clk'EVENT AND clk = '1' THEN
575 580 CASE state_fsm_load_MS_memory IS
576 581 WHEN IDLE =>
577 582 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
578 583 state_fsm_load_MS_memory <= LOAD_FIFO;
579 584 END IF;
580 585 WHEN LOAD_FIFO =>
581 586 IF current_fifo_full = '1' THEN
582 587 state_fsm_load_MS_memory <= TRASH_FFT;
583 588 END IF;
584 589 WHEN TRASH_FFT =>
585 590 IF fft_ready = '0' THEN
586 591 state_fsm_load_MS_memory <= IDLE;
587 592 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
588 593 END IF;
589 594 WHEN OTHERS => NULL;
590 595 END CASE;
591 596
592 597 END IF;
593 598 END PROCESS;
594 599
595 600 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
596 601 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
597 602 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
598 603 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
599 604 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
600 605
601 606 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
602 607 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
603 608 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
604 609 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
605 610 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
606 611
607 612 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
608 613 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
609 614 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
610 615 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
611 616 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
612 617
613 618 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
614 619
615 620 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
616 621 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
617 622 AND state_fsm_load_MS_memory = LOAD_FIFO
618 623 AND current_fifo_load(I) = '1'
619 624 ELSE '1';
620 625 END GENERATE all_fifo;
621 626
622 627 PROCESS (clk, rstn)
623 628 BEGIN
624 629 IF rstn = '0' THEN
625 630 MEM_IN_SM_wen <= (OTHERS => '1');
626 631 ELSIF clk'EVENT AND clk = '1' THEN
627 632 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
628 633 END IF;
629 634 END PROCESS;
630 635
631 636 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
632 637 (fft_data_im & fft_data_re) &
633 638 (fft_data_im & fft_data_re) &
634 639 (fft_data_im & fft_data_re) &
635 640 (fft_data_im & fft_data_re);
636 641
637 642 -----------------------------------------------------------------------------
638 643 Mem_In_SpectralMatrix : lppFIFOxN
639 644 GENERIC MAP (
640 645 tech => 0,
641 646 Mem_use => Mem_use,
642 647 Data_sz => 32, --16,
643 648 Addr_sz => 7, --8
644 649 FifoCnt => 5)
645 650 PORT MAP (
646 651 clk => clk,
647 652 rstn => rstn,
648 653
649 654 ReUse => MEM_IN_SM_ReUse,
650 655
651 656 wen => MEM_IN_SM_wen,
652 657 wdata => MEM_IN_SM_wData,
653 658
654 659 ren => MEM_IN_SM_ren,
655 660 rdata => MEM_IN_SM_rData,
656 661 full => MEM_IN_SM_Full,
657 662 empty => MEM_IN_SM_Empty,
658 663 almost_full => OPEN);
659 664
660 665 -----------------------------------------------------------------------------
661 666 MS_control_1 : MS_control
662 667 PORT MAP (
663 668 clk => clk,
664 669 rstn => rstn,
665 670
666 671 current_status_ms => status_MS_input,
667 672
668 673 fifo_in_lock => MEM_IN_SM_locked,
669 674 fifo_in_data => MEM_IN_SM_rdata,
670 675 fifo_in_full => MEM_IN_SM_Full,
671 676 fifo_in_empty => MEM_IN_SM_Empty,
672 677 fifo_in_ren => MEM_IN_SM_ren,
673 678 fifo_in_reuse => MEM_IN_SM_ReUse,
674 679
675 680 fifo_out_data => SM_in_data,
676 681 fifo_out_ren => SM_in_ren,
677 682 fifo_out_empty => SM_in_empty,
678 683
679 684 current_status_component => status_component,
680 685
681 686 correlation_start => SM_correlation_start,
682 687 correlation_auto => SM_correlation_auto,
683 688 correlation_done => SM_correlation_done);
684 689
685 690
686 691 MS_calculation_1 : MS_calculation
687 692 PORT MAP (
688 693 clk => clk,
689 694 rstn => rstn,
690 695
691 696 fifo_in_data => SM_in_data,
692 697 fifo_in_ren => SM_in_ren,
693 698 fifo_in_empty => SM_in_empty,
694 699
695 700 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
696 701 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
697 702 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
698 703
699 704 correlation_start => SM_correlation_start,
700 705 correlation_auto => SM_correlation_auto,
701 706 correlation_begin => SM_correlation_begin,
702 707 correlation_done => SM_correlation_done);
703 708
704 709 -----------------------------------------------------------------------------
705 710 PROCESS (clk, rstn)
706 711 BEGIN -- PROCESS
707 712 IF rstn = '0' THEN -- asynchronous reset (active low)
708 713 current_matrix_write <= '0';
709 714 current_matrix_wait_empty <= '1';
710 715 status_component_fifo_0 <= (OTHERS => '0');
711 716 status_component_fifo_1 <= (OTHERS => '0');
712 717 status_component_fifo_0_end <= '0';
713 718 status_component_fifo_1_end <= '0';
714 719 SM_correlation_done_reg1 <= '0';
715 720 SM_correlation_done_reg2 <= '0';
716 721 SM_correlation_done_reg3 <= '0';
717 722
718 723 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
719 724 SM_correlation_done_reg1 <= SM_correlation_done;
720 725 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
721 726 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
722 727 status_component_fifo_0_end <= '0';
723 728 status_component_fifo_1_end <= '0';
724 729 IF SM_correlation_begin = '1' THEN
725 730 IF current_matrix_write = '0' THEN
726 731 status_component_fifo_0 <= status_component;
727 732 ELSE
728 733 status_component_fifo_1 <= status_component;
729 734 END IF;
730 735 END IF;
731 736
732 737 IF SM_correlation_done_reg3 = '1' THEN
733 738 IF current_matrix_write = '0' THEN
734 739 status_component_fifo_0_end <= '1';
735 740 ELSE
736 741 status_component_fifo_1_end <= '1';
737 742 END IF;
738 743 current_matrix_wait_empty <= '1';
739 744 current_matrix_write <= NOT current_matrix_write;
740 745 END IF;
741 746
742 747 IF current_matrix_wait_empty <= '1' THEN
743 748 IF current_matrix_write = '0' THEN
744 749 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
745 750 ELSE
746 751 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
747 752 END IF;
748 753 END IF;
749 754
750 755 END IF;
751 756 END PROCESS;
752 757
753 758 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
754 759 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
755 760 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
756 761 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
757 762 '1' WHEN current_matrix_wait_empty = '1' ELSE
758 763 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
759 764 MEM_OUT_SM_Full(1);
760 765
761 766 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
762 767 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
763 768
764 769 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
765 770 -----------------------------------------------------------------------------
766 771
767 772 Mem_Out_SpectralMatrix : lppFIFOxN
768 773 GENERIC MAP (
769 774 tech => 0,
770 775 Mem_use => Mem_use,
771 776 Data_sz => 32,
772 777 Addr_sz => 8,
773 778 FifoCnt => 2)
774 779 PORT MAP (
775 780 clk => clk,
776 781 rstn => rstn,
777 782
778 783 ReUse => (OTHERS => '0'),
779 784
780 785 wen => MEM_OUT_SM_Write,
781 786 wdata => MEM_OUT_SM_Data_in,
782 787
783 788 ren => MEM_OUT_SM_Read,
784 789 rdata => MEM_OUT_SM_Data_out,
785 790
786 791 full => MEM_OUT_SM_Full,
787 792 empty => MEM_OUT_SM_Empty,
788 793 almost_full => OPEN);
789 794
790 795 -----------------------------------------------------------------------------
791 796 -- MEM_OUT_SM_Read <= "00";
792 797 PROCESS (clk, rstn)
793 798 BEGIN
794 799 IF rstn = '0' THEN
795 800 fifo_0_ready <= '0';
796 801 fifo_1_ready <= '0';
797 802 fifo_ongoing <= '0';
798 803 ELSIF clk'EVENT AND clk = '1' THEN
799 804 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
800 805 fifo_ongoing <= '1';
801 806 fifo_0_ready <= '0';
802 807 ELSIF status_component_fifo_0_end = '1' THEN
803 808 fifo_0_ready <= '1';
804 809 END IF;
805 810
806 811 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
807 812 fifo_ongoing <= '0';
808 813 fifo_1_ready <= '0';
809 814 ELSIF status_component_fifo_1_end = '1' THEN
810 815 fifo_1_ready <= '1';
811 816 END IF;
812 817
813 818 END IF;
814 819 END PROCESS;
815 820
816 821 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
817 822 '1' WHEN fifo_0_ready = '0' ELSE
818 823 FSM_DMA_fifo_ren;
819 824
820 825 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
821 826 '1' WHEN fifo_1_ready = '0' ELSE
822 827 FSM_DMA_fifo_ren;
823 828
824 829 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
825 830 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
826 831 '1';
827 832
828 833 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
829 834 status_component_fifo_1;
830 835
831 836 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
832 837 MEM_OUT_SM_Data_out(63 DOWNTO 32);
833 838
834 839 -----------------------------------------------------------------------------
835 840 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
836 841 PORT MAP (
837 842 HCLK => clk,
838 843 HRESETn => rstn,
839 844
840 845 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
841 846 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
842 847 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
843 848 fifo_data => FSM_DMA_fifo_data,
844 849 fifo_empty => FSM_DMA_fifo_empty,
845 850 fifo_ren => FSM_DMA_fifo_ren,
846 851
847 852 dma_addr => dma_addr,
848 853 dma_data => dma_data,
849 854 dma_valid => dma_valid,
850 855 dma_valid_burst => dma_valid_burst,
851 856 dma_ren => dma_ren,
852 857 dma_done => dma_done,
853 858
854 859 ready_matrix_f0 => ready_matrix_f0,
855 860 ready_matrix_f1 => ready_matrix_f1,
856 861 ready_matrix_f2 => ready_matrix_f2,
857 862
858 863 error_bad_component_error => error_bad_component_error,
859 864 error_buffer_full => error_buffer_full,
860 865
861 866 debug_reg => debug_reg,
862 867 status_ready_matrix_f0 => status_ready_matrix_f0,
863 868 status_ready_matrix_f1 => status_ready_matrix_f1,
864 869 status_ready_matrix_f2 => status_ready_matrix_f2,
865 870
866 871 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
867 872 config_active_interruption_onError => config_active_interruption_onError,
868 873
869 874 addr_matrix_f0 => addr_matrix_f0,
870 875 addr_matrix_f1 => addr_matrix_f1,
871 876 addr_matrix_f2 => addr_matrix_f2,
872 877
873 878 matrix_time_f0 => matrix_time_f0,
874 879 matrix_time_f1 => matrix_time_f1,
875 880 matrix_time_f2 => matrix_time_f2
876 881 );
877 882 -----------------------------------------------------------------------------
878 883
879 884
880 885
881 886
882 887
883 888 -----------------------------------------------------------------------------
884 889 -- TIME MANAGMENT
885 890 -----------------------------------------------------------------------------
886 891 all_time <= coarse_time & fine_time;
887 892 --
888 time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
889 '1' WHEN sample_f0_A_empty = "11111" ELSE
890 '0';
893 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
894 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
895 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
896 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
891 897
892 s_m_t_m_f0_A : spectral_matrix_time_managment
893 PORT MAP (
894 clk => clk,
895 rstn => rstn,
896 time_in => all_time,
897 update_1 => time_update_f0_A,
898 time_out => time_reg_f0_A);
898 all_time_reg: FOR I IN 0 TO 3 GENERATE
899 899
900 --
901 time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
902 '1' WHEN sample_f0_B_empty = "11111" ELSE
903 '0';
904
905 s_m_t_m_f0_B : spectral_matrix_time_managment
906 PORT MAP (
907 clk => clk,
908 rstn => rstn,
909 time_in => all_time,
910 update_1 => time_update_f0_B,
911 time_out => time_reg_f0_B);
900 PROCESS (clk, rstn)
901 BEGIN
902 IF rstn = '0' THEN
903 f_empty_reg(I) <= '1';
904 ELSIF clk'event AND clk = '1' THEN
905 f_empty_reg(I) <= f_empty(I);
906 END IF;
907 END PROCESS;
912 908
913 --
914 time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
915 '1' WHEN sample_f1_empty = "11111" ELSE
916 '0';
917
918 s_m_t_m_f1 : spectral_matrix_time_managment
919 PORT MAP (
920 clk => clk,
921 rstn => rstn,
922 time_in => all_time,
923 update_1 => time_update_f1,
924 time_out => time_reg_f1);
909 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
925 910
926 --
927 time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
928 '1' WHEN sample_f2_empty = "11111" ELSE
929 '0';
930
931 s_m_t_m_f2 : spectral_matrix_time_managment
932 PORT MAP (
933 clk => clk,
934 rstn => rstn,
935 time_in => all_time,
936 update_1 => time_update_f2,
937 time_out => time_reg_f2);
911 s_m_t_m_f0_A : spectral_matrix_time_managment
912 PORT MAP (
913 clk => clk,
914 rstn => rstn,
915 time_in => all_time,
916 update_1 => time_update_f(I),
917 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
918 );
919
920 END GENERATE all_time_reg;
921
922 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
923 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
924 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
925 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
938 926
939 927 -----------------------------------------------------------------------------
940 928
941
942
943 929 END Behavioral;
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@@ -1,295 +1,298
1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.ALL;
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 USE lpp.lpp_dma_pkg.ALL;
37 37 LIBRARY techmap;
38 38 USE techmap.gencomp.ALL;
39 39
40 40
41 41 ENTITY lpp_lfr_ms_fsmdma IS
42 42 PORT (
43 43 -- AMBA AHB system signals
44 44 HCLK : IN STD_ULOGIC;
45 45 HRESETn : IN STD_ULOGIC;
46 46
47 47 ---------------------------------------------------------------------------
48 48 -- FIFO - IN
49 49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 53 fifo_empty : IN STD_LOGIC;
54 54 fifo_ren : OUT STD_LOGIC;
55 55
56 56 ---------------------------------------------------------------------------
57 57 -- DMA - OUT
58 58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 dma_valid : OUT STD_LOGIC;
61 61 dma_valid_burst : OUT STD_LOGIC;
62 62 dma_ren : IN STD_LOGIC;
63 63 dma_done : IN STD_LOGIC;
64 64
65 65 ---------------------------------------------------------------------------
66 66 -- Reg out
67 67 ready_matrix_f0 : OUT STD_LOGIC;
68 68 ready_matrix_f1 : OUT STD_LOGIC;
69 69 ready_matrix_f2 : OUT STD_LOGIC;
70 70
71 71 error_bad_component_error : OUT STD_LOGIC;
72 72 error_buffer_full : OUT STD_LOGIC;
73 73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 -- Reg In
76 76 status_ready_matrix_f0 : IN STD_LOGIC;
77 77 status_ready_matrix_f1 : IN STD_LOGIC;
78 78 status_ready_matrix_f2 : IN STD_LOGIC;
79 79
80 80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 81 config_active_interruption_onError : IN STD_LOGIC;
82 82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85
86 86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
89 89
90 90 );
91 91 END;
92 92
93 93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
94 94 -----------------------------------------------------------------------------
95 95 TYPE state_DMAWriteBurst IS (IDLE,
96 96 CHECK_COMPONENT_TYPE,
97 97 WRITE_COARSE_TIME,
98 98 WRITE_FINE_TIME,
99 99 TRASH_FIFO,
100 100 SEND_DATA,
101 101 WAIT_DATA_ACK
102 102 );
103 103 SIGNAL state : state_DMAWriteBurst;
104 104
105 105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
106 106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SIGNAL header_check_ok : STD_LOGIC;
109 109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 111 -----------------------------------------------------------------------------
112 112 -----------------------------------------------------------------------------
113 113
114 114 SIGNAL component_send : STD_LOGIC;
115 115 SIGNAL component_send_ok : STD_LOGIC;
116 116 -----------------------------------------------------------------------------
117 117 SIGNAL fifo_ren_trash : STD_LOGIC;
118 118
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 -----------------------------------------------------------------------------
122 122 SIGNAL log_empty_fifo : STD_LOGIC;
123 123 -----------------------------------------------------------------------------
124 124
125 125 SIGNAL matrix_buffer_ready : STD_LOGIC;
126 126 BEGIN
127 127
128 128 debug_reg <= debug_reg_s;
129 129
130 130
131 131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
132 132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
133 133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
134 134 '0';
135 135
136 136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
137 137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
138 138 '1' WHEN component_type = component_type_pre + "0001" ELSE
139 139 '0';
140 140
141 141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
142 142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
143 143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
144 144 (OTHERS => '0');
145 145
146 146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
147 147 -----------------------------------------------------------------------------
148 148 -- DMA control
149 149 -----------------------------------------------------------------------------
150 150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
151 151 BEGIN
152 152 IF HRESETn = '0' THEN
153 153 matrix_type <= (OTHERS => '0');
154 154 component_type <= (OTHERS => '0');
155 155 state <= IDLE;
156 156 ready_matrix_f0 <= '0';
157 157 ready_matrix_f1 <= '0';
158 158 ready_matrix_f2 <= '0';
159 159 error_bad_component_error <= '0';
160 160 error_buffer_full <= '0'; -- TODO
161 161 component_type_pre <= "0000";
162 162 fifo_ren_trash <= '1';
163 163 component_send <= '0';
164 164 address <= (OTHERS => '0');
165 165
166 166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
167 167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
168 168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
169 169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
171 171
172 172 log_empty_fifo <= '0';
173 173
174 174 matrix_time_f0 <= (OTHERS => '0');
175 175 matrix_time_f1 <= (OTHERS => '0');
176 176 matrix_time_f2 <= (OTHERS => '0');
177 177
178 178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
179 179 --
180 180 debug_reg_s(3) <= status_ready_matrix_f0;
181 181 debug_reg_s(4) <= status_ready_matrix_f1;
182 182 debug_reg_s(5) <= status_ready_matrix_f2;
183 183 debug_reg_s(6) <= '0';
184 184 debug_reg_s(7) <= '0';
185 185 debug_reg_s(8) <= '0';
186 186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
187 187 debug_reg_s(14 DOWNTO 11) <= component_type;
188 188
189 189 --
190 190
191 191
192 192
193 193 ready_matrix_f0 <= '0';
194 194 ready_matrix_f1 <= '0';
195 195 ready_matrix_f2 <= '0';
196 196 error_bad_component_error <= '0';
197 197 error_buffer_full <= '0';
198 198
199 199 CASE state IS
200 200 WHEN IDLE =>
201 201 debug_reg_s(2 DOWNTO 0) <= "000";
202 202 IF fifo_empty = '0' THEN
203 203 state <= CHECK_COMPONENT_TYPE;
204 204 matrix_type <= fifo_matrix_type;
205 205 component_type <= fifo_matrix_component;
206 206 component_type_pre <= component_type;
207 207 END IF;
208 208
209 209 log_empty_fifo <= '0';
210 210
211 211 WHEN CHECK_COMPONENT_TYPE =>
212 212 debug_reg_s(2 DOWNTO 0) <= "001";
213 213
214 214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
215 215 IF component_type = "0000" THEN
216 216 address <= address_matrix;
217 217 CASE matrix_type IS
218 218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
219 219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
220 220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
221 221 WHEN OTHERS => NULL;
222 222 END CASE;
223 223 component_send <= '1';
224 224 END IF;
225 225 state <= SEND_DATA;
226 226 --
227 227 ELSE
228 228 error_bad_component_error <= NOT header_check_ok;
229 229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
230 230 component_type_pre <= "0000";
231 231 state <= TRASH_FIFO;
232 232 END IF;
233 233
234 234 WHEN TRASH_FIFO =>
235 235 debug_reg_s(2 DOWNTO 0) <= "100";
236 236
237 237 error_bad_component_error <= '0';
238 238 IF fifo_empty = '1' THEN
239 239 state <= IDLE;
240 240 fifo_ren_trash <= '1';
241 241 ELSE
242 242 fifo_ren_trash <= '0';
243 243 END IF;
244 244
245 245 WHEN SEND_DATA =>
246 246 debug_reg_s(2 DOWNTO 0) <= "010";
247 247
248 248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
249 249 state <= IDLE;
250 250 IF component_type = "1110" THEN
251 251 CASE matrix_type IS
252 252 WHEN "00" =>
253 253 ready_matrix_f0 <= '1';
254 254 debug_reg_s(6) <= '1';
255 255 WHEN "01" =>
256 256 ready_matrix_f1 <= '1';
257 257 debug_reg_s(7) <= '1';
258 258 WHEN "10" =>
259 259 ready_matrix_f2 <= '1';
260 260 debug_reg_s(8) <= '1';
261 261 WHEN OTHERS => NULL;
262 262 END CASE;
263 263 END IF;
264 264 ELSE
265 265 component_send <= '1';
266 266 address <= address;
267 267 state <= WAIT_DATA_ACK;
268 268 END IF;
269 269
270 270 WHEN WAIT_DATA_ACK =>
271 271 log_empty_fifo <= fifo_empty OR log_empty_fifo;
272 272
273 273 debug_reg_s(2 DOWNTO 0) <= "011";
274 274
275 component_send <= '0';
275 IF dma_ren = '0' THEN
276 component_send <= '0';
277 END IF;
278
276 279 IF component_send_ok = '1' THEN
277 280 address <= address + 64;
278 281 state <= SEND_DATA;
279 282 END IF;
280 283
281 284 WHEN OTHERS => NULL;
282 285 END CASE;
283 286
284 287 END IF;
285 288 END PROCESS DMAWriteFSM_p;
286 289
287 290 dma_valid_burst <= component_send;
288 291 dma_valid <= '0';
289 292 dma_data <= fifo_data;
290 293 dma_addr <= address;
291 294 fifo_ren <= dma_ren AND fifo_ren_trash;
292 295
293 296 component_send_ok <= dma_done;
294 297
295 298 END Behavioral;
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