HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r334:df2e2cec05e6

Update APB_TIME_MANAGEMENT :...

pellion -

r334:df2e2cec05e6 (MINI-LFR) WFP_MS-0-1-8 JC

parent child

Context file:

r334:df2e2cec05e6

Collapse all files

lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +2 -2

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:17:05 07/02/2012
             -- Design Name:
             -- Module Name:    apb_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.apb_devices_list.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             ENTITY apb_lfr_time_management IS
               GENERIC(
                 pindex         : INTEGER := 0;        --! APB slave index
                 paddr          : INTEGER := 0;        --! ADDR field of the APB BAR
                 pmask          : INTEGER := 16#fff#;   --! MASK field of the APB BAR
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60
                 );
               PORT (
                 clk25MHz     : IN STD_LOGIC;        --! Clock
                 clk24_576MHz : IN STD_LOGIC;        --! secondary clock
                 resetn       : IN STD_LOGIC;        --! Reset
                 grspw_tick : IN STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                 apbi : IN  apb_slv_in_type;         --! APB slave input signals
                 apbo : OUT apb_slv_out_type;        --! APB slave output signals
                 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                 fine_time   : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)   --! fine time
                 );
             END apb_lfr_time_management;
             ARCHITECTURE Behavioral OF apb_lfr_time_management IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
 => apb_iobar(paddr, pmask)
                 );
               TYPE apb_lfr_time_management_Reg IS RECORD
                 ctrl             : STD_LOGIC;
                 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 coarse_time      : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               END RECORD;
               SIGNAL r                   : apb_lfr_time_management_Reg;
               SIGNAL Rdata               : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL force_tick          : STD_LOGIC;
               SIGNAL previous_force_tick : STD_LOGIC;
               SIGNAL soft_tick           : STD_LOGIC;
               SIGNAL coarsetime_reg_updated : STD_LOGIC;
               SIGNAL coarsetime_reg         : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL coarse_time_new    : STD_LOGIC;
               SIGNAL coarse_time_new_49 : STD_LOGIC;
               SIGNAL coarse_time_49     : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL coarse_time_s      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               --SIGNAL fine_time_new      : STD_LOGIC;
               --SIGNAL fine_time_new_temp : STD_LOGIC;
               SIGNAL fine_time_new_49   : STD_LOGIC;
               SIGNAL fine_time_49       : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fine_time_s        : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL tick               : STD_LOGIC;
               SIGNAL new_timecode       : STD_LOGIC;
               SIGNAL new_coarsetime     : STD_LOGIC;
               SIGNAL time_new_49 : STD_LOGIC;
               SIGNAL time_new    : STD_LOGIC;
             BEGIN
               PROCESS(resetn, clk25MHz)
               BEGIN
                 IF resetn = '0' THEN
                   Rdata               <= (OTHERS => '0');
                   r.coarse_time_load  <= x"80000000";
                   r.ctrl              <= '0';
                   force_tick          <= '0';
                   previous_force_tick <= '0';
                   soft_tick           <= '0';
                   coarsetime_reg_updated <= '0';
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
                   coarsetime_reg_updated <= '0';
                   force_tick          <= r.ctrl;
                   previous_force_tick <= force_tick;
                   IF (previous_force_tick = '0') AND (force_tick = '1') THEN
                     soft_tick <= '1';
                   ELSE
                     soft_tick <= '0';
                   END IF;
             --APB Write OP
                   IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
                     CASE apbi.paddr(7 DOWNTO 2) IS
                       WHEN "000000" =>
                         r.ctrl <= apbi.pwdata(0);
                       WHEN "000001" =>
                         r.coarse_time_load     <= apbi.pwdata(31 DOWNTO 0);
                         coarsetime_reg_updated <= '1';
                       WHEN OTHERS =>
                         NULL;
                     END CASE;
                   ELSIF r.ctrl = '1' THEN
                     r.ctrl <= '0';
                   END IF;
             --APB READ OP
                   IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
                     CASE apbi.paddr(7 DOWNTO 2) IS
                       WHEN "000000" =>
                         Rdata(0)            <= r.ctrl;
                         Rdata(31 DOWNTO 1)  <= (others => '0');
                       WHEN "000001" =>
                         Rdata(31 DOWNTO 0)  <= r.coarse_time_load(31 DOWNTO 0);
                       WHEN "000010" =>
                         Rdata(31 DOWNTO 0)  <= r.coarse_time(31 DOWNTO 0);
                       WHEN "000011" =>
                         Rdata(31 DOWNTO 16) <= (OTHERS => '0');
                         Rdata(15 DOWNTO 0)  <= r.fine_time(15 DOWNTO 0);
                       WHEN OTHERS =>
                         Rdata(31 DOWNTO 0)  <= (others => '0');
                     END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               apbo.prdata  <= Rdata;
               apbo.pconfig <= pconfig;
               apbo.pindex  <= pindex;
               -----------------------------------------------------------------------------
               -- IN
               coarse_time    <= r.coarse_time;
               fine_time      <= r.fine_time;
               coarsetime_reg <= r.coarse_time_load;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- OUT
               r.coarse_time  <= coarse_time_s;
               r.fine_time    <= fine_time_s;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               tick <= grspw_tick OR soft_tick;
               SYNC_VALID_BIT_1 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => tick,
                   sout    => new_timecode);
               SYNC_VALID_BIT_2 : SYNC_VALID_BIT
                 GENERIC MAP (
                   NB_FF_OF_SYNC => 2)
                 PORT MAP (
                   clk_in  => clk25MHz,
                   clk_out => clk24_576MHz,
                   rstn    => resetn,
                   sin     => coarsetime_reg_updated,
                   sout    => new_coarsetime);
               ----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --SYNC_FF_1 : SYNC_FF
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk    => clk25MHz,
               --    rstn   => resetn,
               --    A      => fine_time_new_49,
               --    A_sync => fine_time_new_temp);
               --lpp_front_detection_1 : lpp_front_detection
               --  PORT MAP (
               --    clk  => clk25MHz,
               --    rstn => resetn,
               --    sin  => fine_time_new_temp,
               --    sout => fine_time_new);
               --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
               --  GENERIC MAP (
               --    NB_FF_OF_SYNC => 2)
               --  PORT MAP (
               --    clk_in  => clk24_576MHz,
               --    clk_out => clk25MHz,
               --    rstn    => resetn,
               --    sin     => coarse_time_new_49,
               --    sout    => coarse_time_new);
               time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
               SYNC_VALID_BIT_4 : SYNC_VALID_BIT
                GENERIC MAP (
                  NB_FF_OF_SYNC => 2)
                PORT MAP (
                  clk_in  => clk24_576MHz,
                  clk_out => clk25MHz,
                  rstn    => resetn,
                  sin     => time_new_49,
                  sout    => time_new);
               PROCESS (clk25MHz, resetn)
               BEGIN  -- PROCESS
                 IF resetn = '0' THEN                -- asynchronous reset (active low)
                   fine_time_s   <= (OTHERS => '0');
                   coarse_time_s <= (OTHERS => '0');
                 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN  -- rising clock edge
                   IF time_new = '1' THEN
                     fine_time_s   <= fine_time_49;
                     coarse_time_s <= coarse_time_49;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- LFR_TIME_MANAGMENT
               -----------------------------------------------------------------------------
               lfr_time_management_1 : lfr_time_management
                 GENERIC MAP (
                   FIRST_DIVISION   => FIRST_DIVISION,
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC)
                 PORT MAP (
                   clk  => clk24_576MHz,
                   rstn => resetn,
                   tick           => new_timecode,
                   new_coarsetime => new_coarsetime,
-                  coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
+                  coarsetime_reg => coarsetime_reg(31 DOWNTO 0),
                   fine_time       => fine_time_49,
                   fine_time_new   => fine_time_new_49,
                   coarse_time     => coarse_time_49,
                   coarse_time_new => coarse_time_new_49);
-            END Behavioral;
  No newline at end of file
+            END Behavioral;

lib/lpp/lfr_time_management/coarse_time_counter.vhd +12 -4

             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
             USE lpp.general_purpose.ALL;
             ENTITY coarse_time_counter IS
               GENERIC (
                 NB_SECOND_DESYNC : INTEGER := 60);
               PORT (
                 clk           : IN STD_LOGIC;
                 rstn          : IN STD_LOGIC;
                 tick          : IN STD_LOGIC;
                 set_TCU       : IN STD_LOGIC;
-                set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
+                set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 CT_add1       : IN STD_LOGIC;
                 fsm_desync    : IN STD_LOGIC;
                 FT_max        : IN STD_LOGIC;
                 coarse_time   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 coarse_time_new   : OUT STD_LOGIC
                 );
             END coarse_time_counter;
             ARCHITECTURE beh OF coarse_time_counter IS
               SIGNAL add1_bit31 : STD_LOGIC;
               SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
               SIGNAL coarse_time_new_counter : STD_LOGIC;
               SIGNAL coarse_time_31 : STD_LOGIC;
               SIGNAL coarse_time_31_reg : STD_LOGIC;
+              SIGNAL set_synchronized       : STD_LOGIC;
+              SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
               --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
             BEGIN  -- beh
               counter_1 : general_counter
                 GENERIC MAP (
                   CYCLIC => '1',
                   NB_BITS_COUNTER => 31)
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   RST_VALUE => (OTHERS => '0'),
                   MAX_VALUE => "111" & X"FFFFFFF" ,
                   set       => set_TCU,
-                  set_value => set_TCU_value,
+                  set_value => set_TCU_value(30 DOWNTO 0),
                   add1      => CT_add1,
                   counter   => coarse_time(30 DOWNTO 0));
               add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
+              set_synchronized       <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
+              set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) =  '1' ELSE
+                                        (OTHERS => '0');
               counter_2 : general_counter
                 GENERIC MAP (
                   CYCLIC          => '0',
                   NB_BITS_COUNTER => 6)
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
                   MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
-                  set       => tick,
+                  set       => set_synchronized,
-                  set_value => (OTHERS => '0'),
+                  set_value => set_synchronized_value,
                   add1      => add1_bit31,
                   counter   => nb_second_counter);
               coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6))  ELSE '0';
               coarse_time(31) <= coarse_time_31;
               coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   coarse_time_new_counter <= '0';
                   coarse_time_31_reg <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   coarse_time_31_reg <= coarse_time_31;
                   IF set_TCU = '1' OR CT_add1 = '1' THEN
                     coarse_time_new_counter <= '1';
                   ELSE
                     coarse_time_new_counter <= '0';
                   END IF;
                 END IF;
               END PROCESS;
             END beh;

lib/lpp/lfr_time_management/lfr_time_management.vhd +1 -1

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    11:14:05 07/02/2012
             -- Design Name:
             -- Module Name:    lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             LIBRARY lpp;
             USE lpp.lpp_lfr_time_management.ALL;
             ENTITY lfr_time_management IS
               GENERIC (
                 FIRST_DIVISION   : INTEGER := 374;
                 NB_SECOND_DESYNC : INTEGER := 60);
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 tick           : IN STD_LOGIC;      -- transition signal information
                 new_coarsetime : IN STD_LOGIC;      -- transition signal information
-                coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
+                coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                 fine_time_new   : OUT STD_LOGIC;
                 coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 coarse_time_new : OUT STD_LOGIC
                 );
             END lfr_time_management;
             ARCHITECTURE Behavioral OF lfr_time_management IS
               SIGNAL FT_max : STD_LOGIC;
               SIGNAL FT_half : STD_LOGIC;
               SIGNAL FT_wait : STD_LOGIC;
               TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
               SIGNAL state : state_fsm_time_management;
               SIGNAL fsm_desync   : STD_LOGIC;
               SIGNAL fsm_transition : STD_LOGIC;
               SIGNAL set_TCU : STD_LOGIC;
               SIGNAL CT_add1 : STD_LOGIC;
               SIGNAL new_coarsetime_reg : STD_LOGIC;
             BEGIN
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   new_coarsetime_reg <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF new_coarsetime = '1' THEN
                     new_coarsetime_reg <= '1';
                   ELSIF tick = '1' THEN
                     new_coarsetime_reg <= '0';
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FINE_TIME
               -----------------------------------------------------------------------------
               fine_time_counter_1: fine_time_counter
                 GENERIC MAP (
                   WAITING_TIME => X"0040",
                   FIRST_DIVISION => FIRST_DIVISION)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   tick           => tick,
                   fsm_transition => fsm_transition,  -- todo
                   FT_max         => FT_max,
                   FT_half        => FT_half,
                   FT_wait        => FT_wait,
                   fine_time      => fine_time,
                   fine_time_new  => fine_time_new);
               -----------------------------------------------------------------------------
               -- COARSE_TIME
               -----------------------------------------------------------------------------
               coarse_time_counter_1: coarse_time_counter
                 GENERIC MAP(
                   NB_SECOND_DESYNC => NB_SECOND_DESYNC )
                 PORT MAP (
                   clk           => clk,
                   rstn          => rstn,
                   tick          => tick,
                   set_TCU       => set_TCU,         -- todo
                   set_TCU_value => coarsetime_reg,  -- todo
                   CT_add1       => CT_add1,         -- todo
                   fsm_desync    => fsm_desync,      -- todo
                   FT_max        => FT_max,
                   coarse_time   => coarse_time,
                   coarse_time_new   => coarse_time_new);
               -----------------------------------------------------------------------------
               -- FSM
               -----------------------------------------------------------------------------
               fsm_desync     <= '1' WHEN state = DESYNC     ELSE '0';
               fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   state <= DESYNC;
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   --CT_add1 <= '0';
                   set_TCU <= '0';
                   CASE state IS
                     WHEN DESYNC =>
                       IF tick = '1' THEN
                         state <= SYNC;
                         set_TCU <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' AND FT_half = '1' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       --ELSIF FT_max = '1' THEN
                       --  CT_add1 <= '1';
                       END IF;
                     WHEN TRANSITION =>
                       IF tick = '1' THEN
                         state         <= SYNC;
                         set_TCU       <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       ELSIF FT_wait = '1' THEN
                         --CT_add1 <= '1';
                         state         <= DESYNC;
                       END IF;
                     WHEN SYNC =>
                       IF tick = '1' THEN
                         set_TCU       <= new_coarsetime_reg;
                         --IF new_coarsetime = '0' THEN
                         --  CT_add1 <= '1';
                         --END IF;
                       ELSIF FT_max = '1' THEN
                         state         <= TRANSITION;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               CT_add1 <= '1' WHEN state = SYNC   AND tick = '1' AND new_coarsetime_reg = '0' ELSE
                          '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
                          '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
                          '1' WHEN state = TRANSITION AND  tick = '1' AND new_coarsetime_reg = '0' ELSE
                          '1' WHEN state = TRANSITION AND  tick = '0' AND FT_wait = '1' ELSE
                          '0';
             END Behavioral;

lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +2 -2

             ----------------------------------------------------------------------------------
             -- Company:
             -- Engineer:
             --
             -- Create Date:    13:04:01 07/02/2012
             -- Design Name:
             -- Module Name:    lpp_lfr_time_management - Behavioral
             -- Project Name:
             -- Target Devices:
             -- Tool versions:
             -- Description:
             --
             -- Dependencies:
             --
             -- Revision:
             -- Revision 0.01 - File Created
             -- Additional Comments:
             --
             ----------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             PACKAGE lpp_lfr_time_management IS
             --***************************
             -- APB_LFR_TIME_MANAGEMENT
               COMPONENT apb_lfr_time_management IS
                 GENERIC(
                   pindex            : INTEGER := 0;            --! APB slave index
                   paddr             : INTEGER := 0;            --! ADDR field of the APB BAR
                   pmask             : INTEGER := 16#fff#;       --! MASK field of the APB BAR
                   FIRST_DIVISION    : INTEGER;
                   NB_SECOND_DESYNC  : INTEGER);
                 PORT (
                   clk25MHz     : IN  STD_LOGIC;     --! Clock
                   clk24_576MHz : IN  STD_LOGIC;     --! secondary clock
                   resetn       : IN  STD_LOGIC;     --! Reset
                   grspw_tick   : IN  STD_LOGIC;  --! grspw signal asserted when a valid time-code is received
                   apbi         : IN  apb_slv_in_type;   --! APB slave input signals
                   apbo         : OUT apb_slv_out_type;  --! APB slave output signals
                   coarse_time  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --! coarse time
                   fine_time    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)   --! fine time
                   );
               END COMPONENT;
               COMPONENT lfr_time_management
                 GENERIC (
                   FIRST_DIVISION   : INTEGER;
                   NB_SECOND_DESYNC : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   new_coarsetime  : IN  STD_LOGIC;
-                  coarsetime_reg  : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
+                  coarsetime_reg  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new   : OUT STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT coarse_time_counter
                 GENERIC (
                   NB_SECOND_DESYNC : INTEGER );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   tick            : IN  STD_LOGIC;
                   set_TCU         : IN  STD_LOGIC;
-                  set_TCU_value   : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
+                  set_TCU_value   : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   CT_add1         : IN  STD_LOGIC;
                   fsm_desync      : IN  STD_LOGIC;
                   FT_max          : IN  STD_LOGIC;
                   coarse_time     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   coarse_time_new : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fine_time_counter
                 GENERIC (
                   WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
                   FIRST_DIVISION : INTEGER );
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   tick           : IN  STD_LOGIC;
                   fsm_transition : IN  STD_LOGIC;
                   FT_max         : OUT STD_LOGIC;
                   FT_half        : OUT STD_LOGIC;
                   FT_wait        : OUT STD_LOGIC;
                   fine_time      : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fine_time_new  : OUT STD_LOGIC);
               END COMPONENT;
             END lpp_lfr_time_management;

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages