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Update APB_TIME_MANAGEMENT :...
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r334:df2e2cec05e6 (MINI-LFR) WFP_MS-0-1-8 JC
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1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_time_management.ALL;
31 31
32 32 ENTITY apb_lfr_time_management IS
33 33
34 34 GENERIC(
35 35 pindex : INTEGER := 0; --! APB slave index
36 36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 38 FIRST_DIVISION : INTEGER := 374;
39 39 NB_SECOND_DESYNC : INTEGER := 60
40 40 );
41 41
42 42 PORT (
43 43 clk25MHz : IN STD_LOGIC; --! Clock
44 44 clk24_576MHz : IN STD_LOGIC; --! secondary clock
45 45 resetn : IN STD_LOGIC; --! Reset
46 46
47 47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
48 48
49 49 apbi : IN apb_slv_in_type; --! APB slave input signals
50 50 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 51
52 52 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
53 53 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
54 54 );
55 55
56 56 END apb_lfr_time_management;
57 57
58 58 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
59 59
60 60 CONSTANT REVISION : INTEGER := 1;
61 61 CONSTANT pconfig : apb_config_type := (
62 62 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0),
63 63 1 => apb_iobar(paddr, pmask)
64 64 );
65 65
66 66 TYPE apb_lfr_time_management_Reg IS RECORD
67 67 ctrl : STD_LOGIC;
68 68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 71 END RECORD;
72 72 SIGNAL r : apb_lfr_time_management_Reg;
73 73
74 74 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 75 SIGNAL force_tick : STD_LOGIC;
76 76 SIGNAL previous_force_tick : STD_LOGIC;
77 77 SIGNAL soft_tick : STD_LOGIC;
78 78
79 79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81
82 82 --SIGNAL coarse_time_new : STD_LOGIC;
83 83 SIGNAL coarse_time_new_49 : STD_LOGIC;
84 84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86
87 87 --SIGNAL fine_time_new : STD_LOGIC;
88 88 --SIGNAL fine_time_new_temp : STD_LOGIC;
89 89 SIGNAL fine_time_new_49 : STD_LOGIC;
90 90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 92 SIGNAL tick : STD_LOGIC;
93 93 SIGNAL new_timecode : STD_LOGIC;
94 94 SIGNAL new_coarsetime : STD_LOGIC;
95 95
96 96 SIGNAL time_new_49 : STD_LOGIC;
97 97 SIGNAL time_new : STD_LOGIC;
98 98
99 99 BEGIN
100 100
101 101 PROCESS(resetn, clk25MHz)
102 102 BEGIN
103 103
104 104 IF resetn = '0' THEN
105 105 Rdata <= (OTHERS => '0');
106 106 r.coarse_time_load <= x"80000000";
107 107 r.ctrl <= '0';
108 108 force_tick <= '0';
109 109 previous_force_tick <= '0';
110 110 soft_tick <= '0';
111 111
112 112 coarsetime_reg_updated <= '0';
113 113
114 114 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
115 115 coarsetime_reg_updated <= '0';
116 116
117 117 force_tick <= r.ctrl;
118 118 previous_force_tick <= force_tick;
119 119 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
120 120 soft_tick <= '1';
121 121 ELSE
122 122 soft_tick <= '0';
123 123 END IF;
124 124
125 125 --APB Write OP
126 126 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
127 127 CASE apbi.paddr(7 DOWNTO 2) IS
128 128 WHEN "000000" =>
129 129 r.ctrl <= apbi.pwdata(0);
130 130 WHEN "000001" =>
131 131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
132 132 coarsetime_reg_updated <= '1';
133 133 WHEN OTHERS =>
134 134 NULL;
135 135 END CASE;
136 136 ELSIF r.ctrl = '1' THEN
137 137 r.ctrl <= '0';
138 138 END IF;
139 139
140 140 --APB READ OP
141 141 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
142 142 CASE apbi.paddr(7 DOWNTO 2) IS
143 143 WHEN "000000" =>
144 144 Rdata(0) <= r.ctrl;
145 145 Rdata(31 DOWNTO 1) <= (others => '0');
146 146 WHEN "000001" =>
147 147 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
148 148 WHEN "000010" =>
149 149 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
150 150 WHEN "000011" =>
151 151 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
152 152 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
153 153 WHEN OTHERS =>
154 154 Rdata(31 DOWNTO 0) <= (others => '0');
155 155 END CASE;
156 156 END IF;
157 157
158 158 END IF;
159 159 END PROCESS;
160 160
161 161 apbo.prdata <= Rdata;
162 162 apbo.pconfig <= pconfig;
163 163 apbo.pindex <= pindex;
164 164
165 165 -----------------------------------------------------------------------------
166 166 -- IN
167 167 coarse_time <= r.coarse_time;
168 168 fine_time <= r.fine_time;
169 169 coarsetime_reg <= r.coarse_time_load;
170 170 -----------------------------------------------------------------------------
171 171
172 172 -----------------------------------------------------------------------------
173 173 -- OUT
174 174 r.coarse_time <= coarse_time_s;
175 175 r.fine_time <= fine_time_s;
176 176 -----------------------------------------------------------------------------
177 177
178 178 -----------------------------------------------------------------------------
179 179 tick <= grspw_tick OR soft_tick;
180 180
181 181 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
182 182 GENERIC MAP (
183 183 NB_FF_OF_SYNC => 2)
184 184 PORT MAP (
185 185 clk_in => clk25MHz,
186 186 clk_out => clk24_576MHz,
187 187 rstn => resetn,
188 188 sin => tick,
189 189 sout => new_timecode);
190 190
191 191 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
192 192 GENERIC MAP (
193 193 NB_FF_OF_SYNC => 2)
194 194 PORT MAP (
195 195 clk_in => clk25MHz,
196 196 clk_out => clk24_576MHz,
197 197 rstn => resetn,
198 198 sin => coarsetime_reg_updated,
199 199 sout => new_coarsetime);
200 200 ----------------------------------------------------------------------------
201 201
202 202 -----------------------------------------------------------------------------
203 203 --SYNC_FF_1 : SYNC_FF
204 204 -- GENERIC MAP (
205 205 -- NB_FF_OF_SYNC => 2)
206 206 -- PORT MAP (
207 207 -- clk => clk25MHz,
208 208 -- rstn => resetn,
209 209 -- A => fine_time_new_49,
210 210 -- A_sync => fine_time_new_temp);
211 211
212 212 --lpp_front_detection_1 : lpp_front_detection
213 213 -- PORT MAP (
214 214 -- clk => clk25MHz,
215 215 -- rstn => resetn,
216 216 -- sin => fine_time_new_temp,
217 217 -- sout => fine_time_new);
218 218
219 219 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
220 220 -- GENERIC MAP (
221 221 -- NB_FF_OF_SYNC => 2)
222 222 -- PORT MAP (
223 223 -- clk_in => clk24_576MHz,
224 224 -- clk_out => clk25MHz,
225 225 -- rstn => resetn,
226 226 -- sin => coarse_time_new_49,
227 227 -- sout => coarse_time_new);
228 228
229 229 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
230 230
231 231 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
232 232 GENERIC MAP (
233 233 NB_FF_OF_SYNC => 2)
234 234 PORT MAP (
235 235 clk_in => clk24_576MHz,
236 236 clk_out => clk25MHz,
237 237 rstn => resetn,
238 238 sin => time_new_49,
239 239 sout => time_new);
240 240
241 241
242 242
243 243 PROCESS (clk25MHz, resetn)
244 244 BEGIN -- PROCESS
245 245 IF resetn = '0' THEN -- asynchronous reset (active low)
246 246 fine_time_s <= (OTHERS => '0');
247 247 coarse_time_s <= (OTHERS => '0');
248 248 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
249 249 IF time_new = '1' THEN
250 250 fine_time_s <= fine_time_49;
251 251 coarse_time_s <= coarse_time_49;
252 252 END IF;
253 253 END IF;
254 254 END PROCESS;
255 255
256 256 -----------------------------------------------------------------------------
257 257 -- LFR_TIME_MANAGMENT
258 258 -----------------------------------------------------------------------------
259 259 lfr_time_management_1 : lfr_time_management
260 260 GENERIC MAP (
261 261 FIRST_DIVISION => FIRST_DIVISION,
262 262 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
263 263 PORT MAP (
264 264 clk => clk24_576MHz,
265 265 rstn => resetn,
266 266
267 267 tick => new_timecode,
268 268 new_coarsetime => new_coarsetime,
269 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
269 coarsetime_reg => coarsetime_reg(31 DOWNTO 0),
270 270
271 271 fine_time => fine_time_49,
272 272 fine_time_new => fine_time_new_49,
273 273 coarse_time => coarse_time_49,
274 274 coarse_time_new => coarse_time_new_49);
275 275
276 END Behavioral; No newline at end of file
276 END Behavioral;
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1 1 LIBRARY IEEE;
2 2 USE IEEE.STD_LOGIC_1164.ALL;
3 3 USE IEEE.NUMERIC_STD.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.general_purpose.ALL;
7 7
8 8 ENTITY coarse_time_counter IS
9 9 GENERIC (
10 10 NB_SECOND_DESYNC : INTEGER := 60);
11 11
12 12 PORT (
13 13 clk : IN STD_LOGIC;
14 14 rstn : IN STD_LOGIC;
15 15
16 16 tick : IN STD_LOGIC;
17 17 set_TCU : IN STD_LOGIC;
18 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
18 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
19 19 CT_add1 : IN STD_LOGIC;
20 20 fsm_desync : IN STD_LOGIC;
21 21 FT_max : IN STD_LOGIC;
22 22
23 23 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
24 24 coarse_time_new : OUT STD_LOGIC
25 25
26 26 );
27 27
28 28 END coarse_time_counter;
29 29
30 30 ARCHITECTURE beh OF coarse_time_counter IS
31 31
32 32 SIGNAL add1_bit31 : STD_LOGIC;
33 33 SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0);
34 34 SIGNAL coarse_time_new_counter : STD_LOGIC;
35 35 SIGNAL coarse_time_31 : STD_LOGIC;
36 36 SIGNAL coarse_time_31_reg : STD_LOGIC;
37 37
38 SIGNAL set_synchronized : STD_LOGIC;
39 SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0);
40
38 41 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
39 42 BEGIN -- beh
40 43
41 44 counter_1 : general_counter
42 45 GENERIC MAP (
43 46 CYCLIC => '1',
44 47 NB_BITS_COUNTER => 31)
45 48 PORT MAP (
46 49 clk => clk,
47 50 rstn => rstn,
48 51 RST_VALUE => (OTHERS => '0'),
49 52 MAX_VALUE => "111" & X"FFFFFFF" ,
50 53 set => set_TCU,
51 set_value => set_TCU_value,
54 set_value => set_TCU_value(30 DOWNTO 0),
52 55 add1 => CT_add1,
53 56 counter => coarse_time(30 DOWNTO 0));
54 57
55 58
56 59 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
57 60
61
62 set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
63 set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
64 (OTHERS => '0');
65
58 66 counter_2 : general_counter
59 67 GENERIC MAP (
60 68 CYCLIC => '0',
61 69 NB_BITS_COUNTER => 6)
62 70 PORT MAP (
63 71 clk => clk,
64 72 rstn => rstn,
65 73 RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
66 74 MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)),
67 set => tick,
68 set_value => (OTHERS => '0'),
75 set => set_synchronized,
76 set_value => set_synchronized_value,
69 77 add1 => add1_bit31,
70 78 counter => nb_second_counter);
71 79
72 80 coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0';
73 81 coarse_time(31) <= coarse_time_31;
74 82 coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg);
75 83
76 84 PROCESS (clk, rstn)
77 85 BEGIN -- PROCESS
78 86 IF rstn = '0' THEN -- asynchronous reset (active low)
79 87 coarse_time_new_counter <= '0';
80 88 coarse_time_31_reg <= '0';
81 89 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
82 90 coarse_time_31_reg <= coarse_time_31;
83 91 IF set_TCU = '1' OR CT_add1 = '1' THEN
84 92 coarse_time_new_counter <= '1';
85 93 ELSE
86 94 coarse_time_new_counter <= '0';
87 95 END IF;
88 96 END IF;
89 97 END PROCESS;
90 98
91 99 END beh;
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@@ -1,173 +1,173
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:14:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY lpp;
24 24 USE lpp.lpp_lfr_time_management.ALL;
25 25
26 26 ENTITY lfr_time_management IS
27 27 GENERIC (
28 28 FIRST_DIVISION : INTEGER := 374;
29 29 NB_SECOND_DESYNC : INTEGER := 60);
30 30 PORT (
31 31 clk : IN STD_LOGIC;
32 32 rstn : IN STD_LOGIC;
33 33
34 34 tick : IN STD_LOGIC; -- transition signal information
35 35
36 36 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
37 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
38 38
39 39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 40 fine_time_new : OUT STD_LOGIC;
41 41 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 42 coarse_time_new : OUT STD_LOGIC
43 43 );
44 44 END lfr_time_management;
45 45
46 46 ARCHITECTURE Behavioral OF lfr_time_management IS
47 47
48 48 SIGNAL FT_max : STD_LOGIC;
49 49 SIGNAL FT_half : STD_LOGIC;
50 50 SIGNAL FT_wait : STD_LOGIC;
51 51
52 52 TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC);
53 53 SIGNAL state : state_fsm_time_management;
54 54
55 55 SIGNAL fsm_desync : STD_LOGIC;
56 56 SIGNAL fsm_transition : STD_LOGIC;
57 57
58 58 SIGNAL set_TCU : STD_LOGIC;
59 59 SIGNAL CT_add1 : STD_LOGIC;
60 60
61 61 SIGNAL new_coarsetime_reg : STD_LOGIC;
62 62
63 63 BEGIN
64 64
65 65 -----------------------------------------------------------------------------
66 66 --
67 67 -----------------------------------------------------------------------------
68 68 PROCESS (clk, rstn)
69 69 BEGIN -- PROCESS
70 70 IF rstn = '0' THEN -- asynchronous reset (active low)
71 71 new_coarsetime_reg <= '0';
72 72 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
73 73 IF new_coarsetime = '1' THEN
74 74 new_coarsetime_reg <= '1';
75 75 ELSIF tick = '1' THEN
76 76 new_coarsetime_reg <= '0';
77 77 END IF;
78 78 END IF;
79 79 END PROCESS;
80 80
81 81 -----------------------------------------------------------------------------
82 82 -- FINE_TIME
83 83 -----------------------------------------------------------------------------
84 84 fine_time_counter_1: fine_time_counter
85 85 GENERIC MAP (
86 86 WAITING_TIME => X"0040",
87 87 FIRST_DIVISION => FIRST_DIVISION)
88 88 PORT MAP (
89 89 clk => clk,
90 90 rstn => rstn,
91 91 tick => tick,
92 92 fsm_transition => fsm_transition, -- todo
93 93 FT_max => FT_max,
94 94 FT_half => FT_half,
95 95 FT_wait => FT_wait,
96 96 fine_time => fine_time,
97 97 fine_time_new => fine_time_new);
98 98
99 99 -----------------------------------------------------------------------------
100 100 -- COARSE_TIME
101 101 -----------------------------------------------------------------------------
102 102 coarse_time_counter_1: coarse_time_counter
103 103 GENERIC MAP(
104 104 NB_SECOND_DESYNC => NB_SECOND_DESYNC )
105 105 PORT MAP (
106 106 clk => clk,
107 107 rstn => rstn,
108 108 tick => tick,
109 109 set_TCU => set_TCU, -- todo
110 110 set_TCU_value => coarsetime_reg, -- todo
111 111 CT_add1 => CT_add1, -- todo
112 112 fsm_desync => fsm_desync, -- todo
113 113 FT_max => FT_max,
114 114 coarse_time => coarse_time,
115 115 coarse_time_new => coarse_time_new);
116 116
117 117 -----------------------------------------------------------------------------
118 118 -- FSM
119 119 -----------------------------------------------------------------------------
120 120 fsm_desync <= '1' WHEN state = DESYNC ELSE '0';
121 121 fsm_transition <= '1' WHEN state = TRANSITION ELSE '0';
122 122
123 123 PROCESS (clk, rstn)
124 124 BEGIN -- PROCESS
125 125 IF rstn = '0' THEN -- asynchronous reset (active low)
126 126 state <= DESYNC;
127 127 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
128 128 --CT_add1 <= '0';
129 129 set_TCU <= '0';
130 130 CASE state IS
131 131 WHEN DESYNC =>
132 132 IF tick = '1' THEN
133 133 state <= SYNC;
134 134 set_TCU <= new_coarsetime_reg;
135 135 --IF new_coarsetime = '0' AND FT_half = '1' THEN
136 136 -- CT_add1 <= '1';
137 137 --END IF;
138 138 --ELSIF FT_max = '1' THEN
139 139 -- CT_add1 <= '1';
140 140 END IF;
141 141 WHEN TRANSITION =>
142 142 IF tick = '1' THEN
143 143 state <= SYNC;
144 144 set_TCU <= new_coarsetime_reg;
145 145 --IF new_coarsetime = '0' THEN
146 146 -- CT_add1 <= '1';
147 147 --END IF;
148 148 ELSIF FT_wait = '1' THEN
149 149 --CT_add1 <= '1';
150 150 state <= DESYNC;
151 151 END IF;
152 152 WHEN SYNC =>
153 153 IF tick = '1' THEN
154 154 set_TCU <= new_coarsetime_reg;
155 155 --IF new_coarsetime = '0' THEN
156 156 -- CT_add1 <= '1';
157 157 --END IF;
158 158 ELSIF FT_max = '1' THEN
159 159 state <= TRANSITION;
160 160 END IF;
161 161 WHEN OTHERS => NULL;
162 162 END CASE;
163 163 END IF;
164 164 END PROCESS;
165 165
166 166
167 167 CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE
168 168 '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE
169 169 '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE
170 170 '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE
171 171 '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE
172 172 '0';
173 173 END Behavioral;
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@@ -1,101 +1,101
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_time_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_TIME_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_time_management IS
33 33 GENERIC(
34 34 pindex : INTEGER := 0; --! APB slave index
35 35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 37 FIRST_DIVISION : INTEGER;
38 38 NB_SECOND_DESYNC : INTEGER);
39 39 PORT (
40 40 clk25MHz : IN STD_LOGIC; --! Clock
41 41 clk24_576MHz : IN STD_LOGIC; --! secondary clock
42 42 resetn : IN STD_LOGIC; --! Reset
43 43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
44 44 apbi : IN apb_slv_in_type; --! APB slave input signals
45 45 apbo : OUT apb_slv_out_type; --! APB slave output signals
46 46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
47 47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
48 48 );
49 49 END COMPONENT;
50 50
51 51 COMPONENT lfr_time_management
52 52 GENERIC (
53 53 FIRST_DIVISION : INTEGER;
54 54 NB_SECOND_DESYNC : INTEGER);
55 55 PORT (
56 56 clk : IN STD_LOGIC;
57 57 rstn : IN STD_LOGIC;
58 58 tick : IN STD_LOGIC;
59 59 new_coarsetime : IN STD_LOGIC;
60 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 62 fine_time_new : OUT STD_LOGIC;
63 63 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 coarse_time_new : OUT STD_LOGIC);
65 65 END COMPONENT;
66 66
67 67 COMPONENT coarse_time_counter
68 68 GENERIC (
69 69 NB_SECOND_DESYNC : INTEGER );
70 70 PORT (
71 71 clk : IN STD_LOGIC;
72 72 rstn : IN STD_LOGIC;
73 73 tick : IN STD_LOGIC;
74 74 set_TCU : IN STD_LOGIC;
75 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
75 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76 CT_add1 : IN STD_LOGIC;
77 77 fsm_desync : IN STD_LOGIC;
78 78 FT_max : IN STD_LOGIC;
79 79 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 coarse_time_new : OUT STD_LOGIC);
81 81 END COMPONENT;
82 82
83 83 COMPONENT fine_time_counter
84 84 GENERIC (
85 85 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
86 86 FIRST_DIVISION : INTEGER );
87 87 PORT (
88 88 clk : IN STD_LOGIC;
89 89 rstn : IN STD_LOGIC;
90 90 tick : IN STD_LOGIC;
91 91 fsm_transition : IN STD_LOGIC;
92 92 FT_max : OUT STD_LOGIC;
93 93 FT_half : OUT STD_LOGIC;
94 94 FT_wait : OUT STD_LOGIC;
95 95 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
96 96 fine_time_new : OUT STD_LOGIC);
97 97 END COMPONENT;
98 98
99 99
100 100 END lpp_lfr_time_management;
101 101
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