@@ -1,276 +1,276 | |||
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1 | 1 | ---------------------------------------------------------------------------------- |
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2 | 2 | -- Company: |
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3 | 3 | -- Engineer: |
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4 | 4 | -- |
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5 | 5 | -- Create Date: 11:17:05 07/02/2012 |
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6 | 6 | -- Design Name: |
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7 | 7 | -- Module Name: apb_lfr_time_management - Behavioral |
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8 | 8 | -- Project Name: |
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9 | 9 | -- Target Devices: |
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10 | 10 | -- Tool versions: |
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11 | 11 | -- Description: |
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12 | 12 | -- |
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13 | 13 | -- Dependencies: |
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14 | 14 | -- |
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15 | 15 | -- Revision: |
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16 | 16 | -- Revision 0.01 - File Created |
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17 | 17 | -- Additional Comments: |
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18 | 18 | -- |
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19 | 19 | ---------------------------------------------------------------------------------- |
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20 | 20 | LIBRARY IEEE; |
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21 | 21 | USE IEEE.STD_LOGIC_1164.ALL; |
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22 | 22 | USE IEEE.NUMERIC_STD.ALL; |
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23 | 23 | LIBRARY grlib; |
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24 | 24 | USE grlib.amba.ALL; |
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25 | 25 | USE grlib.stdlib.ALL; |
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26 | 26 | USE grlib.devices.ALL; |
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27 | 27 | LIBRARY lpp; |
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28 | 28 | USE lpp.apb_devices_list.ALL; |
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29 | 29 | USE lpp.general_purpose.ALL; |
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30 | 30 | USE lpp.lpp_lfr_time_management.ALL; |
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31 | 31 | |
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32 | 32 | ENTITY apb_lfr_time_management IS |
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33 | 33 | |
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34 | 34 | GENERIC( |
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35 | 35 | pindex : INTEGER := 0; --! APB slave index |
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36 | 36 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
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37 | 37 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
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38 | 38 | FIRST_DIVISION : INTEGER := 374; |
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39 | 39 | NB_SECOND_DESYNC : INTEGER := 60 |
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40 | 40 | ); |
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41 | 41 | |
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42 | 42 | PORT ( |
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43 | 43 | clk25MHz : IN STD_LOGIC; --! Clock |
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44 | 44 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
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45 | 45 | resetn : IN STD_LOGIC; --! Reset |
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46 | 46 | |
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47 | 47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
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48 | 48 | |
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49 | 49 | apbi : IN apb_slv_in_type; --! APB slave input signals |
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50 | 50 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
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51 | 51 | |
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52 | 52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
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53 | 53 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time |
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54 | 54 | ); |
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55 | 55 | |
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56 | 56 | END apb_lfr_time_management; |
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57 | 57 | |
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58 | 58 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS |
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59 | 59 | |
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60 | 60 | CONSTANT REVISION : INTEGER := 1; |
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61 | 61 | CONSTANT pconfig : apb_config_type := ( |
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62 | 62 | 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0), |
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63 | 63 | 1 => apb_iobar(paddr, pmask) |
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64 | 64 | ); |
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65 | 65 | |
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66 | 66 | TYPE apb_lfr_time_management_Reg IS RECORD |
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67 | 67 | ctrl : STD_LOGIC; |
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68 | 68 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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69 | 69 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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70 | 70 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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71 | 71 | END RECORD; |
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72 | 72 | SIGNAL r : apb_lfr_time_management_Reg; |
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73 | 73 | |
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74 | 74 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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75 | 75 | SIGNAL force_tick : STD_LOGIC; |
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76 | 76 | SIGNAL previous_force_tick : STD_LOGIC; |
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77 | 77 | SIGNAL soft_tick : STD_LOGIC; |
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78 | 78 | |
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79 | 79 | SIGNAL coarsetime_reg_updated : STD_LOGIC; |
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80 | 80 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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81 | 81 | |
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82 | 82 | --SIGNAL coarse_time_new : STD_LOGIC; |
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83 | 83 | SIGNAL coarse_time_new_49 : STD_LOGIC; |
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84 | 84 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | 85 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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86 | 86 | |
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87 | 87 | --SIGNAL fine_time_new : STD_LOGIC; |
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88 | 88 | --SIGNAL fine_time_new_temp : STD_LOGIC; |
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89 | 89 | SIGNAL fine_time_new_49 : STD_LOGIC; |
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90 | 90 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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91 | 91 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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92 | 92 | SIGNAL tick : STD_LOGIC; |
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93 | 93 | SIGNAL new_timecode : STD_LOGIC; |
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94 | 94 | SIGNAL new_coarsetime : STD_LOGIC; |
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95 | 95 | |
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96 | 96 | SIGNAL time_new_49 : STD_LOGIC; |
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97 | 97 | SIGNAL time_new : STD_LOGIC; |
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98 | 98 | |
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99 | 99 | BEGIN |
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100 | 100 | |
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101 | 101 | PROCESS(resetn, clk25MHz) |
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102 | 102 | BEGIN |
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103 | 103 | |
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104 | 104 | IF resetn = '0' THEN |
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105 | 105 | Rdata <= (OTHERS => '0'); |
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106 | 106 | r.coarse_time_load <= x"80000000"; |
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107 | 107 | r.ctrl <= '0'; |
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108 | 108 | force_tick <= '0'; |
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109 | 109 | previous_force_tick <= '0'; |
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110 | 110 | soft_tick <= '0'; |
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111 | 111 | |
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112 | 112 | coarsetime_reg_updated <= '0'; |
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113 | 113 | |
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114 | 114 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN |
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115 | 115 | coarsetime_reg_updated <= '0'; |
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116 | 116 | |
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117 | 117 | force_tick <= r.ctrl; |
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118 | 118 | previous_force_tick <= force_tick; |
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119 | 119 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN |
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120 | 120 | soft_tick <= '1'; |
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121 | 121 | ELSE |
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122 | 122 | soft_tick <= '0'; |
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123 | 123 | END IF; |
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124 | 124 | |
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125 | 125 | --APB Write OP |
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126 | 126 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN |
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127 | 127 | CASE apbi.paddr(7 DOWNTO 2) IS |
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128 | 128 | WHEN "000000" => |
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129 | 129 | r.ctrl <= apbi.pwdata(0); |
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130 | 130 | WHEN "000001" => |
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131 | 131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); |
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132 | 132 | coarsetime_reg_updated <= '1'; |
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133 | 133 | WHEN OTHERS => |
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134 | 134 | NULL; |
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135 | 135 | END CASE; |
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136 | 136 | ELSIF r.ctrl = '1' THEN |
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137 | 137 | r.ctrl <= '0'; |
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138 | 138 | END IF; |
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139 | 139 | |
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140 | 140 | --APB READ OP |
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141 | 141 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN |
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142 | 142 | CASE apbi.paddr(7 DOWNTO 2) IS |
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143 | 143 | WHEN "000000" => |
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144 | 144 | Rdata(0) <= r.ctrl; |
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145 | 145 | Rdata(31 DOWNTO 1) <= (others => '0'); |
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146 | 146 | WHEN "000001" => |
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147 | 147 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); |
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148 | 148 | WHEN "000010" => |
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149 | 149 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); |
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150 | 150 | WHEN "000011" => |
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151 | 151 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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152 | 152 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
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153 | 153 | WHEN OTHERS => |
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154 | 154 | Rdata(31 DOWNTO 0) <= (others => '0'); |
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155 | 155 | END CASE; |
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156 | 156 | END IF; |
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157 | 157 | |
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158 | 158 | END IF; |
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159 | 159 | END PROCESS; |
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160 | 160 | |
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161 | 161 | apbo.prdata <= Rdata; |
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162 | 162 | apbo.pconfig <= pconfig; |
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163 | 163 | apbo.pindex <= pindex; |
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164 | 164 | |
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165 | 165 | ----------------------------------------------------------------------------- |
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166 | 166 | -- IN |
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167 | 167 | coarse_time <= r.coarse_time; |
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168 | 168 | fine_time <= r.fine_time; |
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169 | 169 | coarsetime_reg <= r.coarse_time_load; |
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170 | 170 | ----------------------------------------------------------------------------- |
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171 | 171 | |
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172 | 172 | ----------------------------------------------------------------------------- |
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173 | 173 | -- OUT |
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174 | 174 | r.coarse_time <= coarse_time_s; |
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175 | 175 | r.fine_time <= fine_time_s; |
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176 | 176 | ----------------------------------------------------------------------------- |
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177 | 177 | |
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178 | 178 | ----------------------------------------------------------------------------- |
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179 | 179 | tick <= grspw_tick OR soft_tick; |
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180 | 180 | |
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181 | 181 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT |
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182 | 182 | GENERIC MAP ( |
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183 | 183 | NB_FF_OF_SYNC => 2) |
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184 | 184 | PORT MAP ( |
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185 | 185 | clk_in => clk25MHz, |
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186 | 186 | clk_out => clk24_576MHz, |
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187 | 187 | rstn => resetn, |
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188 | 188 | sin => tick, |
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189 | 189 | sout => new_timecode); |
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190 | 190 | |
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191 | 191 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT |
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192 | 192 | GENERIC MAP ( |
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193 | 193 | NB_FF_OF_SYNC => 2) |
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194 | 194 | PORT MAP ( |
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195 | 195 | clk_in => clk25MHz, |
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196 | 196 | clk_out => clk24_576MHz, |
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197 | 197 | rstn => resetn, |
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198 | 198 | sin => coarsetime_reg_updated, |
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199 | 199 | sout => new_coarsetime); |
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200 | 200 | ---------------------------------------------------------------------------- |
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201 | 201 | |
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202 | 202 | ----------------------------------------------------------------------------- |
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203 | 203 | --SYNC_FF_1 : SYNC_FF |
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204 | 204 | -- GENERIC MAP ( |
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205 | 205 | -- NB_FF_OF_SYNC => 2) |
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206 | 206 | -- PORT MAP ( |
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207 | 207 | -- clk => clk25MHz, |
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208 | 208 | -- rstn => resetn, |
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209 | 209 | -- A => fine_time_new_49, |
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210 | 210 | -- A_sync => fine_time_new_temp); |
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211 | 211 | |
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212 | 212 | --lpp_front_detection_1 : lpp_front_detection |
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213 | 213 | -- PORT MAP ( |
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214 | 214 | -- clk => clk25MHz, |
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215 | 215 | -- rstn => resetn, |
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216 | 216 | -- sin => fine_time_new_temp, |
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217 | 217 | -- sout => fine_time_new); |
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218 | 218 | |
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219 | 219 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
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220 | 220 | -- GENERIC MAP ( |
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221 | 221 | -- NB_FF_OF_SYNC => 2) |
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222 | 222 | -- PORT MAP ( |
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223 | 223 | -- clk_in => clk24_576MHz, |
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224 | 224 | -- clk_out => clk25MHz, |
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225 | 225 | -- rstn => resetn, |
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226 | 226 | -- sin => coarse_time_new_49, |
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227 | 227 | -- sout => coarse_time_new); |
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228 | 228 | |
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229 | 229 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; |
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230 | 230 | |
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231 | 231 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
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232 | 232 | GENERIC MAP ( |
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233 | 233 | NB_FF_OF_SYNC => 2) |
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234 | 234 | PORT MAP ( |
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235 | 235 | clk_in => clk24_576MHz, |
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236 | 236 | clk_out => clk25MHz, |
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237 | 237 | rstn => resetn, |
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238 | 238 | sin => time_new_49, |
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239 | 239 | sout => time_new); |
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240 | 240 | |
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241 | 241 | |
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242 | 242 | |
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243 | 243 | PROCESS (clk25MHz, resetn) |
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244 | 244 | BEGIN -- PROCESS |
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245 | 245 | IF resetn = '0' THEN -- asynchronous reset (active low) |
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246 | 246 | fine_time_s <= (OTHERS => '0'); |
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247 | 247 | coarse_time_s <= (OTHERS => '0'); |
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248 | 248 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
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249 | 249 | IF time_new = '1' THEN |
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250 | 250 | fine_time_s <= fine_time_49; |
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251 | 251 | coarse_time_s <= coarse_time_49; |
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252 | 252 | END IF; |
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253 | 253 | END IF; |
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254 | 254 | END PROCESS; |
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255 | 255 | |
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256 | 256 | ----------------------------------------------------------------------------- |
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257 | 257 | -- LFR_TIME_MANAGMENT |
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258 | 258 | ----------------------------------------------------------------------------- |
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259 | 259 | lfr_time_management_1 : lfr_time_management |
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260 | 260 | GENERIC MAP ( |
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261 | 261 | FIRST_DIVISION => FIRST_DIVISION, |
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262 | 262 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) |
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263 | 263 | PORT MAP ( |
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264 | 264 | clk => clk24_576MHz, |
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265 | 265 | rstn => resetn, |
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266 | 266 | |
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267 | 267 | tick => new_timecode, |
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268 | 268 | new_coarsetime => new_coarsetime, |
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269 |
coarsetime_reg => coarsetime_reg(3 |
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269 | coarsetime_reg => coarsetime_reg(31 DOWNTO 0), | |
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270 | 270 | |
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271 | 271 | fine_time => fine_time_49, |
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272 | 272 | fine_time_new => fine_time_new_49, |
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273 | 273 | coarse_time => coarse_time_49, |
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274 | 274 | coarse_time_new => coarse_time_new_49); |
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275 | 275 | |
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276 | END Behavioral; No newline at end of file | |
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276 | END Behavioral; |
@@ -1,91 +1,99 | |||
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1 | 1 | LIBRARY IEEE; |
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2 | 2 | USE IEEE.STD_LOGIC_1164.ALL; |
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3 | 3 | USE IEEE.NUMERIC_STD.ALL; |
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4 | 4 | |
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5 | 5 | LIBRARY lpp; |
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6 | 6 | USE lpp.general_purpose.ALL; |
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7 | 7 | |
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8 | 8 | ENTITY coarse_time_counter IS |
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9 | 9 | GENERIC ( |
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10 | 10 | NB_SECOND_DESYNC : INTEGER := 60); |
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11 | 11 | |
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12 | 12 | PORT ( |
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13 | 13 | clk : IN STD_LOGIC; |
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14 | 14 | rstn : IN STD_LOGIC; |
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15 | 15 | |
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16 | 16 | tick : IN STD_LOGIC; |
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17 | 17 | set_TCU : IN STD_LOGIC; |
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18 |
set_TCU_value : IN STD_LOGIC_VECTOR(3 |
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18 | set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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19 | 19 | CT_add1 : IN STD_LOGIC; |
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20 | 20 | fsm_desync : IN STD_LOGIC; |
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21 | 21 | FT_max : IN STD_LOGIC; |
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22 | 22 | |
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23 | 23 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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24 | 24 | coarse_time_new : OUT STD_LOGIC |
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25 | 25 | |
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26 | 26 | ); |
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27 | 27 | |
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28 | 28 | END coarse_time_counter; |
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29 | 29 | |
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30 | 30 | ARCHITECTURE beh OF coarse_time_counter IS |
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31 | 31 | |
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32 | 32 | SIGNAL add1_bit31 : STD_LOGIC; |
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33 | 33 | SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0); |
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34 | 34 | SIGNAL coarse_time_new_counter : STD_LOGIC; |
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35 | 35 | SIGNAL coarse_time_31 : STD_LOGIC; |
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36 | 36 | SIGNAL coarse_time_31_reg : STD_LOGIC; |
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37 | ||
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38 | SIGNAL set_synchronized : STD_LOGIC; | |
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39 | SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
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37 | 40 | |
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38 | 41 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 |
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39 | 42 | BEGIN -- beh |
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40 | 43 | |
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41 | 44 | counter_1 : general_counter |
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42 | 45 | GENERIC MAP ( |
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43 | 46 | CYCLIC => '1', |
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44 | 47 | NB_BITS_COUNTER => 31) |
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45 | 48 | PORT MAP ( |
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46 | 49 | clk => clk, |
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47 | 50 | rstn => rstn, |
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48 | 51 | RST_VALUE => (OTHERS => '0'), |
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49 | 52 | MAX_VALUE => "111" & X"FFFFFFF" , |
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50 | 53 | set => set_TCU, |
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51 | set_value => set_TCU_value, | |
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54 | set_value => set_TCU_value(30 DOWNTO 0), | |
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52 | 55 | add1 => CT_add1, |
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53 | 56 | counter => coarse_time(30 DOWNTO 0)); |
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54 | 57 | |
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55 | 58 | |
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56 | 59 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; |
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60 | ||
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61 | ||
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62 | set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU); | |
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63 | set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE | |
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64 | (OTHERS => '0'); | |
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57 | 65 | |
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58 | 66 | counter_2 : general_counter |
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59 | 67 | GENERIC MAP ( |
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60 | 68 | CYCLIC => '0', |
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61 | 69 | NB_BITS_COUNTER => 6) |
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62 | 70 | PORT MAP ( |
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63 | 71 | clk => clk, |
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64 | 72 | rstn => rstn, |
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65 | 73 | RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), |
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66 | 74 | MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), |
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67 |
set => |
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68 | set_value => (OTHERS => '0'), | |
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75 | set => set_synchronized, | |
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76 | set_value => set_synchronized_value, | |
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69 | 77 | add1 => add1_bit31, |
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70 | 78 | counter => nb_second_counter); |
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71 | 79 | |
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72 | 80 | coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0'; |
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73 | 81 | coarse_time(31) <= coarse_time_31; |
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74 | 82 | coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg); |
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75 | 83 | |
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76 | 84 | PROCESS (clk, rstn) |
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77 | 85 | BEGIN -- PROCESS |
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78 | 86 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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79 | 87 | coarse_time_new_counter <= '0'; |
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80 | 88 | coarse_time_31_reg <= '0'; |
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81 | 89 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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82 | 90 | coarse_time_31_reg <= coarse_time_31; |
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83 | 91 | IF set_TCU = '1' OR CT_add1 = '1' THEN |
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84 | 92 | coarse_time_new_counter <= '1'; |
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85 | 93 | ELSE |
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86 | 94 | coarse_time_new_counter <= '0'; |
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87 | 95 | END IF; |
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88 | 96 | END IF; |
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89 | 97 | END PROCESS; |
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90 | 98 | |
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91 | 99 | END beh; |
@@ -1,173 +1,173 | |||
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1 | 1 | ---------------------------------------------------------------------------------- |
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2 | 2 | -- Company: |
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3 | 3 | -- Engineer: |
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4 | 4 | -- |
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5 | 5 | -- Create Date: 11:14:05 07/02/2012 |
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6 | 6 | -- Design Name: |
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7 | 7 | -- Module Name: lfr_time_management - Behavioral |
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8 | 8 | -- Project Name: |
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9 | 9 | -- Target Devices: |
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10 | 10 | -- Tool versions: |
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11 | 11 | -- Description: |
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12 | 12 | -- |
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13 | 13 | -- Dependencies: |
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14 | 14 | -- |
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15 | 15 | -- Revision: |
|
16 | 16 | -- Revision 0.01 - File Created |
|
17 | 17 | -- Additional Comments: |
|
18 | 18 | -- |
|
19 | 19 | ---------------------------------------------------------------------------------- |
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20 | 20 | LIBRARY IEEE; |
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21 | 21 | USE IEEE.STD_LOGIC_1164.ALL; |
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22 | 22 | USE IEEE.NUMERIC_STD.ALL; |
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23 | 23 | LIBRARY lpp; |
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24 | 24 | USE lpp.lpp_lfr_time_management.ALL; |
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25 | 25 | |
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26 | 26 | ENTITY lfr_time_management IS |
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27 | 27 | GENERIC ( |
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28 | 28 | FIRST_DIVISION : INTEGER := 374; |
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29 | 29 | NB_SECOND_DESYNC : INTEGER := 60); |
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30 | 30 | PORT ( |
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31 | 31 | clk : IN STD_LOGIC; |
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32 | 32 | rstn : IN STD_LOGIC; |
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33 | 33 | |
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34 | 34 | tick : IN STD_LOGIC; -- transition signal information |
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35 | 35 | |
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36 | 36 | new_coarsetime : IN STD_LOGIC; -- transition signal information |
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37 |
coarsetime_reg : IN STD_LOGIC_VECTOR(3 |
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37 | coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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38 | 38 | |
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39 | 39 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
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40 | 40 | fine_time_new : OUT STD_LOGIC; |
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41 | 41 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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42 | 42 | coarse_time_new : OUT STD_LOGIC |
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43 | 43 | ); |
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44 | 44 | END lfr_time_management; |
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45 | 45 | |
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46 | 46 | ARCHITECTURE Behavioral OF lfr_time_management IS |
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47 | 47 | |
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48 | 48 | SIGNAL FT_max : STD_LOGIC; |
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49 | 49 | SIGNAL FT_half : STD_LOGIC; |
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50 | 50 | SIGNAL FT_wait : STD_LOGIC; |
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51 | 51 | |
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52 | 52 | TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC); |
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53 | 53 | SIGNAL state : state_fsm_time_management; |
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54 | 54 | |
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55 | 55 | SIGNAL fsm_desync : STD_LOGIC; |
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56 | 56 | SIGNAL fsm_transition : STD_LOGIC; |
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57 | 57 | |
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58 | 58 | SIGNAL set_TCU : STD_LOGIC; |
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59 | 59 | SIGNAL CT_add1 : STD_LOGIC; |
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60 | 60 | |
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61 | 61 | SIGNAL new_coarsetime_reg : STD_LOGIC; |
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62 | 62 | |
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63 | 63 | BEGIN |
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64 | 64 | |
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65 | 65 | ----------------------------------------------------------------------------- |
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66 | 66 | -- |
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67 | 67 | ----------------------------------------------------------------------------- |
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68 | 68 | PROCESS (clk, rstn) |
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69 | 69 | BEGIN -- PROCESS |
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70 | 70 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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71 | 71 | new_coarsetime_reg <= '0'; |
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72 | 72 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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73 | 73 | IF new_coarsetime = '1' THEN |
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74 | 74 | new_coarsetime_reg <= '1'; |
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75 | 75 | ELSIF tick = '1' THEN |
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76 | 76 | new_coarsetime_reg <= '0'; |
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77 | 77 | END IF; |
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78 | 78 | END IF; |
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79 | 79 | END PROCESS; |
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80 | 80 | |
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81 | 81 | ----------------------------------------------------------------------------- |
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82 | 82 | -- FINE_TIME |
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83 | 83 | ----------------------------------------------------------------------------- |
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84 | 84 | fine_time_counter_1: fine_time_counter |
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85 | 85 | GENERIC MAP ( |
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86 | 86 | WAITING_TIME => X"0040", |
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87 | 87 | FIRST_DIVISION => FIRST_DIVISION) |
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88 | 88 | PORT MAP ( |
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89 | 89 | clk => clk, |
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90 | 90 | rstn => rstn, |
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91 | 91 | tick => tick, |
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92 | 92 | fsm_transition => fsm_transition, -- todo |
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93 | 93 | FT_max => FT_max, |
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94 | 94 | FT_half => FT_half, |
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95 | 95 | FT_wait => FT_wait, |
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96 | 96 | fine_time => fine_time, |
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97 | 97 | fine_time_new => fine_time_new); |
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98 | 98 | |
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99 | 99 | ----------------------------------------------------------------------------- |
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100 | 100 | -- COARSE_TIME |
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101 | 101 | ----------------------------------------------------------------------------- |
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102 | 102 | coarse_time_counter_1: coarse_time_counter |
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103 | 103 | GENERIC MAP( |
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104 | 104 | NB_SECOND_DESYNC => NB_SECOND_DESYNC ) |
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105 | 105 | PORT MAP ( |
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106 | 106 | clk => clk, |
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107 | 107 | rstn => rstn, |
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108 | 108 | tick => tick, |
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109 | 109 | set_TCU => set_TCU, -- todo |
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110 | 110 | set_TCU_value => coarsetime_reg, -- todo |
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111 | 111 | CT_add1 => CT_add1, -- todo |
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112 | 112 | fsm_desync => fsm_desync, -- todo |
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113 | 113 | FT_max => FT_max, |
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114 | 114 | coarse_time => coarse_time, |
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115 | 115 | coarse_time_new => coarse_time_new); |
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116 | 116 | |
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117 | 117 | ----------------------------------------------------------------------------- |
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118 | 118 | -- FSM |
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119 | 119 | ----------------------------------------------------------------------------- |
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120 | 120 | fsm_desync <= '1' WHEN state = DESYNC ELSE '0'; |
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121 | 121 | fsm_transition <= '1' WHEN state = TRANSITION ELSE '0'; |
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122 | 122 | |
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123 | 123 | PROCESS (clk, rstn) |
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124 | 124 | BEGIN -- PROCESS |
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125 | 125 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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126 | 126 | state <= DESYNC; |
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127 | 127 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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128 | 128 | --CT_add1 <= '0'; |
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129 | 129 | set_TCU <= '0'; |
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130 | 130 | CASE state IS |
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131 | 131 | WHEN DESYNC => |
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132 | 132 | IF tick = '1' THEN |
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133 | 133 | state <= SYNC; |
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134 | 134 | set_TCU <= new_coarsetime_reg; |
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135 | 135 | --IF new_coarsetime = '0' AND FT_half = '1' THEN |
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136 | 136 | -- CT_add1 <= '1'; |
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137 | 137 | --END IF; |
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138 | 138 | --ELSIF FT_max = '1' THEN |
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139 | 139 | -- CT_add1 <= '1'; |
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140 | 140 | END IF; |
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141 | 141 | WHEN TRANSITION => |
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142 | 142 | IF tick = '1' THEN |
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143 | 143 | state <= SYNC; |
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144 | 144 | set_TCU <= new_coarsetime_reg; |
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145 | 145 | --IF new_coarsetime = '0' THEN |
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146 | 146 | -- CT_add1 <= '1'; |
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147 | 147 | --END IF; |
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148 | 148 | ELSIF FT_wait = '1' THEN |
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149 | 149 | --CT_add1 <= '1'; |
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150 | 150 | state <= DESYNC; |
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151 | 151 | END IF; |
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152 | 152 | WHEN SYNC => |
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153 | 153 | IF tick = '1' THEN |
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154 | 154 | set_TCU <= new_coarsetime_reg; |
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155 | 155 | --IF new_coarsetime = '0' THEN |
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156 | 156 | -- CT_add1 <= '1'; |
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157 | 157 | --END IF; |
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158 | 158 | ELSIF FT_max = '1' THEN |
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159 | 159 | state <= TRANSITION; |
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160 | 160 | END IF; |
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161 | 161 | WHEN OTHERS => NULL; |
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162 | 162 | END CASE; |
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163 | 163 | END IF; |
|
164 | 164 | END PROCESS; |
|
165 | 165 | |
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166 | 166 | |
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167 | 167 | CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
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168 | 168 | '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE |
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169 | 169 | '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE |
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170 | 170 | '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
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171 | 171 | '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE |
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172 | 172 | '0'; |
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173 | 173 | END Behavioral; |
@@ -1,101 +1,101 | |||
|
1 | 1 | ---------------------------------------------------------------------------------- |
|
2 | 2 | -- Company: |
|
3 | 3 | -- Engineer: |
|
4 | 4 | -- |
|
5 | 5 | -- Create Date: 13:04:01 07/02/2012 |
|
6 | 6 | -- Design Name: |
|
7 | 7 | -- Module Name: lpp_lfr_time_management - Behavioral |
|
8 | 8 | -- Project Name: |
|
9 | 9 | -- Target Devices: |
|
10 | 10 | -- Tool versions: |
|
11 | 11 | -- Description: |
|
12 | 12 | -- |
|
13 | 13 | -- Dependencies: |
|
14 | 14 | -- |
|
15 | 15 | -- Revision: |
|
16 | 16 | -- Revision 0.01 - File Created |
|
17 | 17 | -- Additional Comments: |
|
18 | 18 | -- |
|
19 | 19 | ---------------------------------------------------------------------------------- |
|
20 | 20 | LIBRARY IEEE; |
|
21 | 21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
22 | 22 | LIBRARY grlib; |
|
23 | 23 | USE grlib.amba.ALL; |
|
24 | 24 | USE grlib.stdlib.ALL; |
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25 | 25 | USE grlib.devices.ALL; |
|
26 | 26 | |
|
27 | 27 | PACKAGE lpp_lfr_time_management IS |
|
28 | 28 | |
|
29 | 29 | --*************************** |
|
30 | 30 | -- APB_LFR_TIME_MANAGEMENT |
|
31 | 31 | |
|
32 | 32 | COMPONENT apb_lfr_time_management IS |
|
33 | 33 | GENERIC( |
|
34 | 34 | pindex : INTEGER := 0; --! APB slave index |
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35 | 35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
|
36 | 36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
|
37 | 37 | FIRST_DIVISION : INTEGER; |
|
38 | 38 | NB_SECOND_DESYNC : INTEGER); |
|
39 | 39 | PORT ( |
|
40 | 40 | clk25MHz : IN STD_LOGIC; --! Clock |
|
41 | 41 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
|
42 | 42 | resetn : IN STD_LOGIC; --! Reset |
|
43 | 43 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
|
44 | 44 | apbi : IN apb_slv_in_type; --! APB slave input signals |
|
45 | 45 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
|
46 | 46 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
|
47 | 47 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time |
|
48 | 48 | ); |
|
49 | 49 | END COMPONENT; |
|
50 | 50 | |
|
51 | 51 | COMPONENT lfr_time_management |
|
52 | 52 | GENERIC ( |
|
53 | 53 | FIRST_DIVISION : INTEGER; |
|
54 | 54 | NB_SECOND_DESYNC : INTEGER); |
|
55 | 55 | PORT ( |
|
56 | 56 | clk : IN STD_LOGIC; |
|
57 | 57 | rstn : IN STD_LOGIC; |
|
58 | 58 | tick : IN STD_LOGIC; |
|
59 | 59 | new_coarsetime : IN STD_LOGIC; |
|
60 |
coarsetime_reg : IN STD_LOGIC_VECTOR(3 |
|
|
60 | coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
61 | 61 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
62 | 62 | fine_time_new : OUT STD_LOGIC; |
|
63 | 63 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | coarse_time_new : OUT STD_LOGIC); |
|
65 | 65 | END COMPONENT; |
|
66 | 66 | |
|
67 | 67 | COMPONENT coarse_time_counter |
|
68 | 68 | GENERIC ( |
|
69 | 69 | NB_SECOND_DESYNC : INTEGER ); |
|
70 | 70 | PORT ( |
|
71 | 71 | clk : IN STD_LOGIC; |
|
72 | 72 | rstn : IN STD_LOGIC; |
|
73 | 73 | tick : IN STD_LOGIC; |
|
74 | 74 | set_TCU : IN STD_LOGIC; |
|
75 |
set_TCU_value : IN STD_LOGIC_VECTOR(3 |
|
|
75 | set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
76 | 76 | CT_add1 : IN STD_LOGIC; |
|
77 | 77 | fsm_desync : IN STD_LOGIC; |
|
78 | 78 | FT_max : IN STD_LOGIC; |
|
79 | 79 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | 80 | coarse_time_new : OUT STD_LOGIC); |
|
81 | 81 | END COMPONENT; |
|
82 | 82 | |
|
83 | 83 | COMPONENT fine_time_counter |
|
84 | 84 | GENERIC ( |
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85 | 85 | WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
86 | 86 | FIRST_DIVISION : INTEGER ); |
|
87 | 87 | PORT ( |
|
88 | 88 | clk : IN STD_LOGIC; |
|
89 | 89 | rstn : IN STD_LOGIC; |
|
90 | 90 | tick : IN STD_LOGIC; |
|
91 | 91 | fsm_transition : IN STD_LOGIC; |
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92 | 92 | FT_max : OUT STD_LOGIC; |
|
93 | 93 | FT_half : OUT STD_LOGIC; |
|
94 | 94 | FT_wait : OUT STD_LOGIC; |
|
95 | 95 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
96 | 96 | fine_time_new : OUT STD_LOGIC); |
|
97 | 97 | END COMPONENT; |
|
98 | 98 | |
|
99 | 99 | |
|
100 | 100 | END lpp_lfr_time_management; |
|
101 | 101 |
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