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1 | ---------------------------------------------------------------------------------- |
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1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
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2 | -- Company: | |
3 | -- Engineer: |
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3 | -- Engineer: | |
4 | -- |
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4 | -- | |
5 | -- Create Date: 11:17:05 07/02/2012 |
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5 | -- Create Date: 11:17:05 07/02/2012 | |
6 | -- Design Name: |
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6 | -- Design Name: | |
7 | -- Module Name: apb_lfr_time_management - Behavioral |
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7 | -- Module Name: apb_lfr_time_management - Behavioral | |
8 | -- Project Name: |
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8 | -- Project Name: | |
9 | -- Target Devices: |
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9 | -- Target Devices: | |
10 | -- Tool versions: |
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10 | -- Tool versions: | |
11 | -- Description: |
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11 | -- Description: | |
12 | -- |
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12 | -- | |
13 | -- Dependencies: |
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13 | -- Dependencies: | |
14 | -- |
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14 | -- | |
15 | -- Revision: |
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15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
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16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
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17 | -- Additional Comments: | |
18 | -- |
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18 | -- | |
19 | ---------------------------------------------------------------------------------- |
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19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
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20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
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21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | USE IEEE.NUMERIC_STD.ALL; |
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22 | USE IEEE.NUMERIC_STD.ALL; | |
23 | LIBRARY grlib; |
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23 | LIBRARY grlib; | |
24 | USE grlib.amba.ALL; |
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24 | USE grlib.amba.ALL; | |
25 | USE grlib.stdlib.ALL; |
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25 | USE grlib.stdlib.ALL; | |
26 | USE grlib.devices.ALL; |
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26 | USE grlib.devices.ALL; | |
27 | LIBRARY lpp; |
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27 | LIBRARY lpp; | |
28 | USE lpp.apb_devices_list.ALL; |
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28 | USE lpp.apb_devices_list.ALL; | |
29 | USE lpp.general_purpose.ALL; |
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29 | USE lpp.general_purpose.ALL; | |
30 | USE lpp.lpp_lfr_time_management.ALL; |
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30 | USE lpp.lpp_lfr_time_management.ALL; | |
31 |
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31 | |||
32 | ENTITY apb_lfr_time_management IS |
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32 | ENTITY apb_lfr_time_management IS | |
33 |
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33 | |||
34 | GENERIC( |
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34 | GENERIC( | |
35 | pindex : INTEGER := 0; --! APB slave index |
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35 | pindex : INTEGER := 0; --! APB slave index | |
36 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
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36 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
37 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
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37 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
38 | FIRST_DIVISION : INTEGER := 374; |
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38 | FIRST_DIVISION : INTEGER := 374; | |
39 | NB_SECOND_DESYNC : INTEGER := 60 |
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39 | NB_SECOND_DESYNC : INTEGER := 60 | |
40 | ); |
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40 | ); | |
41 |
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41 | |||
42 | PORT ( |
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42 | PORT ( | |
43 | clk25MHz : IN STD_LOGIC; --! Clock |
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43 | clk25MHz : IN STD_LOGIC; --! Clock | |
44 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
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44 | clk24_576MHz : IN STD_LOGIC; --! secondary clock | |
45 | resetn : IN STD_LOGIC; --! Reset |
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45 | resetn : IN STD_LOGIC; --! Reset | |
46 |
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46 | |||
47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
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47 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
48 |
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48 | |||
49 | apbi : IN apb_slv_in_type; --! APB slave input signals |
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49 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
50 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
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50 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
51 |
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51 | |||
52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
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52 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
53 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time |
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53 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time | |
54 | ); |
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54 | ); | |
55 |
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55 | |||
56 | END apb_lfr_time_management; |
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56 | END apb_lfr_time_management; | |
57 |
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57 | |||
58 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS |
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58 | ARCHITECTURE Behavioral OF apb_lfr_time_management IS | |
59 |
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59 | |||
60 | CONSTANT REVISION : INTEGER := 1; |
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60 | CONSTANT REVISION : INTEGER := 1; | |
61 | CONSTANT pconfig : apb_config_type := ( |
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61 | CONSTANT pconfig : apb_config_type := ( | |
62 | 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0), |
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62 | 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, 0), | |
63 | 1 => apb_iobar(paddr, pmask) |
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63 | 1 => apb_iobar(paddr, pmask) | |
64 | ); |
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64 | ); | |
65 |
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65 | |||
66 | TYPE apb_lfr_time_management_Reg IS RECORD |
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66 | TYPE apb_lfr_time_management_Reg IS RECORD | |
67 | ctrl : STD_LOGIC; |
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67 | ctrl : STD_LOGIC; | |
68 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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68 | coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
69 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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69 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
70 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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70 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
71 | END RECORD; |
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71 | END RECORD; | |
72 | SIGNAL r : apb_lfr_time_management_Reg; |
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72 | SIGNAL r : apb_lfr_time_management_Reg; | |
73 |
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73 | |||
74 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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74 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
75 | SIGNAL force_tick : STD_LOGIC; |
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75 | SIGNAL force_tick : STD_LOGIC; | |
76 | SIGNAL previous_force_tick : STD_LOGIC; |
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76 | SIGNAL previous_force_tick : STD_LOGIC; | |
77 | SIGNAL soft_tick : STD_LOGIC; |
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77 | SIGNAL soft_tick : STD_LOGIC; | |
78 |
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78 | |||
79 | SIGNAL coarsetime_reg_updated : STD_LOGIC; |
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79 | SIGNAL coarsetime_reg_updated : STD_LOGIC; | |
80 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
81 |
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81 | |||
82 | --SIGNAL coarse_time_new : STD_LOGIC; |
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82 | --SIGNAL coarse_time_new : STD_LOGIC; | |
83 | SIGNAL coarse_time_new_49 : STD_LOGIC; |
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83 | SIGNAL coarse_time_new_49 : STD_LOGIC; | |
84 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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84 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
85 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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85 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
86 |
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86 | |||
87 | --SIGNAL fine_time_new : STD_LOGIC; |
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87 | --SIGNAL fine_time_new : STD_LOGIC; | |
88 | --SIGNAL fine_time_new_temp : STD_LOGIC; |
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88 | --SIGNAL fine_time_new_temp : STD_LOGIC; | |
89 | SIGNAL fine_time_new_49 : STD_LOGIC; |
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89 | SIGNAL fine_time_new_49 : STD_LOGIC; | |
90 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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90 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
91 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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91 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
92 | SIGNAL tick : STD_LOGIC; |
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92 | SIGNAL tick : STD_LOGIC; | |
93 | SIGNAL new_timecode : STD_LOGIC; |
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93 | SIGNAL new_timecode : STD_LOGIC; | |
94 | SIGNAL new_coarsetime : STD_LOGIC; |
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94 | SIGNAL new_coarsetime : STD_LOGIC; | |
95 |
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95 | |||
96 | SIGNAL time_new_49 : STD_LOGIC; |
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96 | SIGNAL time_new_49 : STD_LOGIC; | |
97 | SIGNAL time_new : STD_LOGIC; |
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97 | SIGNAL time_new : STD_LOGIC; | |
98 |
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98 | |||
99 | BEGIN |
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99 | BEGIN | |
100 |
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100 | |||
101 | PROCESS(resetn, clk25MHz) |
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101 | PROCESS(resetn, clk25MHz) | |
102 | BEGIN |
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102 | BEGIN | |
103 |
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103 | |||
104 | IF resetn = '0' THEN |
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104 | IF resetn = '0' THEN | |
105 | Rdata <= (OTHERS => '0'); |
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105 | Rdata <= (OTHERS => '0'); | |
106 | r.coarse_time_load <= x"80000000"; |
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106 | r.coarse_time_load <= x"80000000"; | |
107 | r.ctrl <= '0'; |
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107 | r.ctrl <= '0'; | |
108 | force_tick <= '0'; |
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108 | force_tick <= '0'; | |
109 | previous_force_tick <= '0'; |
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109 | previous_force_tick <= '0'; | |
110 | soft_tick <= '0'; |
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110 | soft_tick <= '0'; | |
111 |
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111 | |||
112 | coarsetime_reg_updated <= '0'; |
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112 | coarsetime_reg_updated <= '0'; | |
113 |
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113 | |||
114 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN |
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114 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN | |
115 | coarsetime_reg_updated <= '0'; |
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115 | coarsetime_reg_updated <= '0'; | |
116 |
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116 | |||
117 | force_tick <= r.ctrl; |
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117 | force_tick <= r.ctrl; | |
118 | previous_force_tick <= force_tick; |
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118 | previous_force_tick <= force_tick; | |
119 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN |
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119 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN | |
120 | soft_tick <= '1'; |
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120 | soft_tick <= '1'; | |
121 | ELSE |
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121 | ELSE | |
122 | soft_tick <= '0'; |
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122 | soft_tick <= '0'; | |
123 | END IF; |
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123 | END IF; | |
124 |
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124 | |||
125 | --APB Write OP |
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125 | --APB Write OP | |
126 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN |
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126 | IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN | |
127 | CASE apbi.paddr(7 DOWNTO 2) IS |
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127 | CASE apbi.paddr(7 DOWNTO 2) IS | |
128 | WHEN "000000" => |
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128 | WHEN "000000" => | |
129 | r.ctrl <= apbi.pwdata(0); |
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129 | r.ctrl <= apbi.pwdata(0); | |
130 | WHEN "000001" => |
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130 | WHEN "000001" => | |
131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); |
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131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
132 | coarsetime_reg_updated <= '1'; |
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132 | coarsetime_reg_updated <= '1'; | |
133 | WHEN OTHERS => |
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133 | WHEN OTHERS => | |
134 | NULL; |
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134 | NULL; | |
135 | END CASE; |
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135 | END CASE; | |
136 | ELSIF r.ctrl = '1' THEN |
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136 | ELSIF r.ctrl = '1' THEN | |
137 | r.ctrl <= '0'; |
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137 | r.ctrl <= '0'; | |
138 | END IF; |
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138 | END IF; | |
139 |
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139 | |||
140 | --APB READ OP |
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140 | --APB READ OP | |
141 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN |
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141 | IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN | |
142 | CASE apbi.paddr(7 DOWNTO 2) IS |
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142 | CASE apbi.paddr(7 DOWNTO 2) IS | |
143 | WHEN "000000" => |
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143 | WHEN "000000" => | |
144 | Rdata(0) <= r.ctrl; |
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144 | Rdata(0) <= r.ctrl; | |
145 | Rdata(31 DOWNTO 1) <= (others => '0'); |
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145 | Rdata(31 DOWNTO 1) <= (others => '0'); | |
146 | WHEN "000001" => |
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146 | WHEN "000001" => | |
147 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); |
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147 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); | |
148 | WHEN "000010" => |
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148 | WHEN "000010" => | |
149 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); |
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149 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); | |
150 | WHEN "000011" => |
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150 | WHEN "000011" => | |
151 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
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151 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
152 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
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152 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); | |
153 | WHEN OTHERS => |
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153 | WHEN OTHERS => | |
154 | Rdata(31 DOWNTO 0) <= (others => '0'); |
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154 | Rdata(31 DOWNTO 0) <= (others => '0'); | |
155 | END CASE; |
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155 | END CASE; | |
156 | END IF; |
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156 | END IF; | |
157 |
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157 | |||
158 | END IF; |
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158 | END IF; | |
159 | END PROCESS; |
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159 | END PROCESS; | |
160 |
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160 | |||
161 | apbo.prdata <= Rdata; |
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161 | apbo.prdata <= Rdata; | |
162 | apbo.pconfig <= pconfig; |
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162 | apbo.pconfig <= pconfig; | |
163 | apbo.pindex <= pindex; |
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163 | apbo.pindex <= pindex; | |
164 |
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164 | |||
165 | ----------------------------------------------------------------------------- |
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165 | ----------------------------------------------------------------------------- | |
166 | -- IN |
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166 | -- IN | |
167 | coarse_time <= r.coarse_time; |
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167 | coarse_time <= r.coarse_time; | |
168 | fine_time <= r.fine_time; |
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168 | fine_time <= r.fine_time; | |
169 | coarsetime_reg <= r.coarse_time_load; |
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169 | coarsetime_reg <= r.coarse_time_load; | |
170 | ----------------------------------------------------------------------------- |
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170 | ----------------------------------------------------------------------------- | |
171 |
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171 | |||
172 | ----------------------------------------------------------------------------- |
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172 | ----------------------------------------------------------------------------- | |
173 | -- OUT |
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173 | -- OUT | |
174 | r.coarse_time <= coarse_time_s; |
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174 | r.coarse_time <= coarse_time_s; | |
175 | r.fine_time <= fine_time_s; |
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175 | r.fine_time <= fine_time_s; | |
176 | ----------------------------------------------------------------------------- |
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176 | ----------------------------------------------------------------------------- | |
177 |
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177 | |||
178 | ----------------------------------------------------------------------------- |
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178 | ----------------------------------------------------------------------------- | |
179 | tick <= grspw_tick OR soft_tick; |
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179 | tick <= grspw_tick OR soft_tick; | |
180 |
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180 | |||
181 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT |
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181 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT | |
182 | GENERIC MAP ( |
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182 | GENERIC MAP ( | |
183 | NB_FF_OF_SYNC => 2) |
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183 | NB_FF_OF_SYNC => 2) | |
184 | PORT MAP ( |
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184 | PORT MAP ( | |
185 | clk_in => clk25MHz, |
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185 | clk_in => clk25MHz, | |
186 | clk_out => clk24_576MHz, |
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186 | clk_out => clk24_576MHz, | |
187 | rstn => resetn, |
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187 | rstn => resetn, | |
188 | sin => tick, |
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188 | sin => tick, | |
189 | sout => new_timecode); |
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189 | sout => new_timecode); | |
190 |
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190 | |||
191 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT |
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191 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT | |
192 | GENERIC MAP ( |
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192 | GENERIC MAP ( | |
193 | NB_FF_OF_SYNC => 2) |
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193 | NB_FF_OF_SYNC => 2) | |
194 | PORT MAP ( |
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194 | PORT MAP ( | |
195 | clk_in => clk25MHz, |
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195 | clk_in => clk25MHz, | |
196 | clk_out => clk24_576MHz, |
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196 | clk_out => clk24_576MHz, | |
197 | rstn => resetn, |
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197 | rstn => resetn, | |
198 | sin => coarsetime_reg_updated, |
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198 | sin => coarsetime_reg_updated, | |
199 | sout => new_coarsetime); |
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199 | sout => new_coarsetime); | |
200 | ---------------------------------------------------------------------------- |
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200 | ---------------------------------------------------------------------------- | |
201 |
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201 | |||
202 | ----------------------------------------------------------------------------- |
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202 | ----------------------------------------------------------------------------- | |
203 | --SYNC_FF_1 : SYNC_FF |
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203 | --SYNC_FF_1 : SYNC_FF | |
204 | -- GENERIC MAP ( |
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204 | -- GENERIC MAP ( | |
205 | -- NB_FF_OF_SYNC => 2) |
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205 | -- NB_FF_OF_SYNC => 2) | |
206 | -- PORT MAP ( |
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206 | -- PORT MAP ( | |
207 | -- clk => clk25MHz, |
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207 | -- clk => clk25MHz, | |
208 | -- rstn => resetn, |
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208 | -- rstn => resetn, | |
209 | -- A => fine_time_new_49, |
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209 | -- A => fine_time_new_49, | |
210 | -- A_sync => fine_time_new_temp); |
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210 | -- A_sync => fine_time_new_temp); | |
211 |
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211 | |||
212 | --lpp_front_detection_1 : lpp_front_detection |
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212 | --lpp_front_detection_1 : lpp_front_detection | |
213 | -- PORT MAP ( |
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213 | -- PORT MAP ( | |
214 | -- clk => clk25MHz, |
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214 | -- clk => clk25MHz, | |
215 | -- rstn => resetn, |
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215 | -- rstn => resetn, | |
216 | -- sin => fine_time_new_temp, |
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216 | -- sin => fine_time_new_temp, | |
217 | -- sout => fine_time_new); |
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217 | -- sout => fine_time_new); | |
218 |
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218 | |||
219 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
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219 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT | |
220 | -- GENERIC MAP ( |
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220 | -- GENERIC MAP ( | |
221 | -- NB_FF_OF_SYNC => 2) |
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221 | -- NB_FF_OF_SYNC => 2) | |
222 | -- PORT MAP ( |
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222 | -- PORT MAP ( | |
223 | -- clk_in => clk24_576MHz, |
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223 | -- clk_in => clk24_576MHz, | |
224 | -- clk_out => clk25MHz, |
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224 | -- clk_out => clk25MHz, | |
225 | -- rstn => resetn, |
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225 | -- rstn => resetn, | |
226 | -- sin => coarse_time_new_49, |
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226 | -- sin => coarse_time_new_49, | |
227 | -- sout => coarse_time_new); |
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227 | -- sout => coarse_time_new); | |
228 |
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228 | |||
229 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; |
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229 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; | |
230 |
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230 | |||
231 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
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231 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT | |
232 | GENERIC MAP ( |
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232 | GENERIC MAP ( | |
233 | NB_FF_OF_SYNC => 2) |
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233 | NB_FF_OF_SYNC => 2) | |
234 | PORT MAP ( |
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234 | PORT MAP ( | |
235 | clk_in => clk24_576MHz, |
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235 | clk_in => clk24_576MHz, | |
236 | clk_out => clk25MHz, |
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236 | clk_out => clk25MHz, | |
237 | rstn => resetn, |
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237 | rstn => resetn, | |
238 | sin => time_new_49, |
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238 | sin => time_new_49, | |
239 | sout => time_new); |
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239 | sout => time_new); | |
240 |
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240 | |||
241 |
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241 | |||
242 |
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242 | |||
243 | PROCESS (clk25MHz, resetn) |
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243 | PROCESS (clk25MHz, resetn) | |
244 | BEGIN -- PROCESS |
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244 | BEGIN -- PROCESS | |
245 | IF resetn = '0' THEN -- asynchronous reset (active low) |
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245 | IF resetn = '0' THEN -- asynchronous reset (active low) | |
246 | fine_time_s <= (OTHERS => '0'); |
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246 | fine_time_s <= (OTHERS => '0'); | |
247 | coarse_time_s <= (OTHERS => '0'); |
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247 | coarse_time_s <= (OTHERS => '0'); | |
248 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
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248 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge | |
249 | IF time_new = '1' THEN |
|
249 | IF time_new = '1' THEN | |
250 | fine_time_s <= fine_time_49; |
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250 | fine_time_s <= fine_time_49; | |
251 | coarse_time_s <= coarse_time_49; |
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251 | coarse_time_s <= coarse_time_49; | |
252 | END IF; |
|
252 | END IF; | |
253 | END IF; |
|
253 | END IF; | |
254 | END PROCESS; |
|
254 | END PROCESS; | |
255 |
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255 | |||
256 | ----------------------------------------------------------------------------- |
|
256 | ----------------------------------------------------------------------------- | |
257 | -- LFR_TIME_MANAGMENT |
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257 | -- LFR_TIME_MANAGMENT | |
258 | ----------------------------------------------------------------------------- |
|
258 | ----------------------------------------------------------------------------- | |
259 | lfr_time_management_1 : lfr_time_management |
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259 | lfr_time_management_1 : lfr_time_management | |
260 | GENERIC MAP ( |
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260 | GENERIC MAP ( | |
261 | FIRST_DIVISION => FIRST_DIVISION, |
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261 | FIRST_DIVISION => FIRST_DIVISION, | |
262 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) |
|
262 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) | |
263 | PORT MAP ( |
|
263 | PORT MAP ( | |
264 | clk => clk24_576MHz, |
|
264 | clk => clk24_576MHz, | |
265 | rstn => resetn, |
|
265 | rstn => resetn, | |
266 |
|
266 | |||
267 | tick => new_timecode, |
|
267 | tick => new_timecode, | |
268 | new_coarsetime => new_coarsetime, |
|
268 | new_coarsetime => new_coarsetime, | |
269 |
coarsetime_reg => coarsetime_reg(3 |
|
269 | coarsetime_reg => coarsetime_reg(31 DOWNTO 0), | |
270 |
|
270 | |||
271 | fine_time => fine_time_49, |
|
271 | fine_time => fine_time_49, | |
272 | fine_time_new => fine_time_new_49, |
|
272 | fine_time_new => fine_time_new_49, | |
273 | coarse_time => coarse_time_49, |
|
273 | coarse_time => coarse_time_49, | |
274 | coarse_time_new => coarse_time_new_49); |
|
274 | coarse_time_new => coarse_time_new_49); | |
275 |
|
275 | |||
276 | END Behavioral; No newline at end of file |
|
276 | END Behavioral; |
@@ -1,91 +1,99 | |||||
1 | LIBRARY IEEE; |
|
1 | LIBRARY IEEE; | |
2 | USE IEEE.STD_LOGIC_1164.ALL; |
|
2 | USE IEEE.STD_LOGIC_1164.ALL; | |
3 | USE IEEE.NUMERIC_STD.ALL; |
|
3 | USE IEEE.NUMERIC_STD.ALL; | |
4 |
|
4 | |||
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.general_purpose.ALL; |
|
6 | USE lpp.general_purpose.ALL; | |
7 |
|
7 | |||
8 | ENTITY coarse_time_counter IS |
|
8 | ENTITY coarse_time_counter IS | |
9 | GENERIC ( |
|
9 | GENERIC ( | |
10 | NB_SECOND_DESYNC : INTEGER := 60); |
|
10 | NB_SECOND_DESYNC : INTEGER := 60); | |
11 |
|
11 | |||
12 | PORT ( |
|
12 | PORT ( | |
13 | clk : IN STD_LOGIC; |
|
13 | clk : IN STD_LOGIC; | |
14 | rstn : IN STD_LOGIC; |
|
14 | rstn : IN STD_LOGIC; | |
15 |
|
15 | |||
16 | tick : IN STD_LOGIC; |
|
16 | tick : IN STD_LOGIC; | |
17 | set_TCU : IN STD_LOGIC; |
|
17 | set_TCU : IN STD_LOGIC; | |
18 |
set_TCU_value : IN STD_LOGIC_VECTOR(3 |
|
18 | set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
19 | CT_add1 : IN STD_LOGIC; |
|
19 | CT_add1 : IN STD_LOGIC; | |
20 | fsm_desync : IN STD_LOGIC; |
|
20 | fsm_desync : IN STD_LOGIC; | |
21 | FT_max : IN STD_LOGIC; |
|
21 | FT_max : IN STD_LOGIC; | |
22 |
|
22 | |||
23 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
23 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
24 | coarse_time_new : OUT STD_LOGIC |
|
24 | coarse_time_new : OUT STD_LOGIC | |
25 |
|
25 | |||
26 | ); |
|
26 | ); | |
27 |
|
27 | |||
28 | END coarse_time_counter; |
|
28 | END coarse_time_counter; | |
29 |
|
29 | |||
30 | ARCHITECTURE beh OF coarse_time_counter IS |
|
30 | ARCHITECTURE beh OF coarse_time_counter IS | |
31 |
|
31 | |||
32 | SIGNAL add1_bit31 : STD_LOGIC; |
|
32 | SIGNAL add1_bit31 : STD_LOGIC; | |
33 | SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0); |
|
33 | SIGNAL nb_second_counter : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
34 | SIGNAL coarse_time_new_counter : STD_LOGIC; |
|
34 | SIGNAL coarse_time_new_counter : STD_LOGIC; | |
35 | SIGNAL coarse_time_31 : STD_LOGIC; |
|
35 | SIGNAL coarse_time_31 : STD_LOGIC; | |
36 | SIGNAL coarse_time_31_reg : STD_LOGIC; |
|
36 | SIGNAL coarse_time_31_reg : STD_LOGIC; | |
|
37 | ||||
|
38 | SIGNAL set_synchronized : STD_LOGIC; | |||
|
39 | SIGNAL set_synchronized_value : STD_LOGIC_VECTOR(5 DOWNTO 0); | |||
37 |
|
40 | |||
38 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 |
|
41 | --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 | |
39 | BEGIN -- beh |
|
42 | BEGIN -- beh | |
40 |
|
43 | |||
41 | counter_1 : general_counter |
|
44 | counter_1 : general_counter | |
42 | GENERIC MAP ( |
|
45 | GENERIC MAP ( | |
43 | CYCLIC => '1', |
|
46 | CYCLIC => '1', | |
44 | NB_BITS_COUNTER => 31) |
|
47 | NB_BITS_COUNTER => 31) | |
45 | PORT MAP ( |
|
48 | PORT MAP ( | |
46 | clk => clk, |
|
49 | clk => clk, | |
47 | rstn => rstn, |
|
50 | rstn => rstn, | |
48 | RST_VALUE => (OTHERS => '0'), |
|
51 | RST_VALUE => (OTHERS => '0'), | |
49 | MAX_VALUE => "111" & X"FFFFFFF" , |
|
52 | MAX_VALUE => "111" & X"FFFFFFF" , | |
50 | set => set_TCU, |
|
53 | set => set_TCU, | |
51 | set_value => set_TCU_value, |
|
54 | set_value => set_TCU_value(30 DOWNTO 0), | |
52 | add1 => CT_add1, |
|
55 | add1 => CT_add1, | |
53 | counter => coarse_time(30 DOWNTO 0)); |
|
56 | counter => coarse_time(30 DOWNTO 0)); | |
54 |
|
57 | |||
55 |
|
58 | |||
56 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; |
|
59 | add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; | |
|
60 | ||||
|
61 | ||||
|
62 | set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU); | |||
|
63 | set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE | |||
|
64 | (OTHERS => '0'); | |||
57 |
|
65 | |||
58 | counter_2 : general_counter |
|
66 | counter_2 : general_counter | |
59 | GENERIC MAP ( |
|
67 | GENERIC MAP ( | |
60 | CYCLIC => '0', |
|
68 | CYCLIC => '0', | |
61 | NB_BITS_COUNTER => 6) |
|
69 | NB_BITS_COUNTER => 6) | |
62 | PORT MAP ( |
|
70 | PORT MAP ( | |
63 | clk => clk, |
|
71 | clk => clk, | |
64 | rstn => rstn, |
|
72 | rstn => rstn, | |
65 | RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), |
|
73 | RST_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), | |
66 | MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), |
|
74 | MAX_VALUE => STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)), | |
67 |
set => |
|
75 | set => set_synchronized, | |
68 | set_value => (OTHERS => '0'), |
|
76 | set_value => set_synchronized_value, | |
69 | add1 => add1_bit31, |
|
77 | add1 => add1_bit31, | |
70 | counter => nb_second_counter); |
|
78 | counter => nb_second_counter); | |
71 |
|
79 | |||
72 | coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0'; |
|
80 | coarse_time_31 <= '1' WHEN nb_second_counter = STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) ELSE '0'; | |
73 | coarse_time(31) <= coarse_time_31; |
|
81 | coarse_time(31) <= coarse_time_31; | |
74 | coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg); |
|
82 | coarse_time_new <= coarse_time_new_counter OR (coarse_time_31 XOR coarse_time_31_reg); | |
75 |
|
83 | |||
76 | PROCESS (clk, rstn) |
|
84 | PROCESS (clk, rstn) | |
77 | BEGIN -- PROCESS |
|
85 | BEGIN -- PROCESS | |
78 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
86 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
79 | coarse_time_new_counter <= '0'; |
|
87 | coarse_time_new_counter <= '0'; | |
80 | coarse_time_31_reg <= '0'; |
|
88 | coarse_time_31_reg <= '0'; | |
81 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
89 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
82 | coarse_time_31_reg <= coarse_time_31; |
|
90 | coarse_time_31_reg <= coarse_time_31; | |
83 | IF set_TCU = '1' OR CT_add1 = '1' THEN |
|
91 | IF set_TCU = '1' OR CT_add1 = '1' THEN | |
84 | coarse_time_new_counter <= '1'; |
|
92 | coarse_time_new_counter <= '1'; | |
85 | ELSE |
|
93 | ELSE | |
86 | coarse_time_new_counter <= '0'; |
|
94 | coarse_time_new_counter <= '0'; | |
87 | END IF; |
|
95 | END IF; | |
88 | END IF; |
|
96 | END IF; | |
89 | END PROCESS; |
|
97 | END PROCESS; | |
90 |
|
98 | |||
91 | END beh; |
|
99 | END beh; |
@@ -1,173 +1,173 | |||||
1 | ---------------------------------------------------------------------------------- |
|
1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
|
2 | -- Company: | |
3 | -- Engineer: |
|
3 | -- Engineer: | |
4 | -- |
|
4 | -- | |
5 | -- Create Date: 11:14:05 07/02/2012 |
|
5 | -- Create Date: 11:14:05 07/02/2012 | |
6 | -- Design Name: |
|
6 | -- Design Name: | |
7 | -- Module Name: lfr_time_management - Behavioral |
|
7 | -- Module Name: lfr_time_management - Behavioral | |
8 | -- Project Name: |
|
8 | -- Project Name: | |
9 | -- Target Devices: |
|
9 | -- Target Devices: | |
10 | -- Tool versions: |
|
10 | -- Tool versions: | |
11 | -- Description: |
|
11 | -- Description: | |
12 | -- |
|
12 | -- | |
13 | -- Dependencies: |
|
13 | -- Dependencies: | |
14 | -- |
|
14 | -- | |
15 | -- Revision: |
|
15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
|
16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
18 | -- |
|
18 | -- | |
19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
|
20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | USE IEEE.NUMERIC_STD.ALL; |
|
22 | USE IEEE.NUMERIC_STD.ALL; | |
23 | LIBRARY lpp; |
|
23 | LIBRARY lpp; | |
24 | USE lpp.lpp_lfr_time_management.ALL; |
|
24 | USE lpp.lpp_lfr_time_management.ALL; | |
25 |
|
25 | |||
26 | ENTITY lfr_time_management IS |
|
26 | ENTITY lfr_time_management IS | |
27 | GENERIC ( |
|
27 | GENERIC ( | |
28 | FIRST_DIVISION : INTEGER := 374; |
|
28 | FIRST_DIVISION : INTEGER := 374; | |
29 | NB_SECOND_DESYNC : INTEGER := 60); |
|
29 | NB_SECOND_DESYNC : INTEGER := 60); | |
30 | PORT ( |
|
30 | PORT ( | |
31 | clk : IN STD_LOGIC; |
|
31 | clk : IN STD_LOGIC; | |
32 | rstn : IN STD_LOGIC; |
|
32 | rstn : IN STD_LOGIC; | |
33 |
|
33 | |||
34 | tick : IN STD_LOGIC; -- transition signal information |
|
34 | tick : IN STD_LOGIC; -- transition signal information | |
35 |
|
35 | |||
36 | new_coarsetime : IN STD_LOGIC; -- transition signal information |
|
36 | new_coarsetime : IN STD_LOGIC; -- transition signal information | |
37 |
coarsetime_reg : IN STD_LOGIC_VECTOR(3 |
|
37 | coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
38 |
|
38 | |||
39 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
39 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
40 | fine_time_new : OUT STD_LOGIC; |
|
40 | fine_time_new : OUT STD_LOGIC; | |
41 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
41 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
42 | coarse_time_new : OUT STD_LOGIC |
|
42 | coarse_time_new : OUT STD_LOGIC | |
43 | ); |
|
43 | ); | |
44 | END lfr_time_management; |
|
44 | END lfr_time_management; | |
45 |
|
45 | |||
46 | ARCHITECTURE Behavioral OF lfr_time_management IS |
|
46 | ARCHITECTURE Behavioral OF lfr_time_management IS | |
47 |
|
47 | |||
48 | SIGNAL FT_max : STD_LOGIC; |
|
48 | SIGNAL FT_max : STD_LOGIC; | |
49 | SIGNAL FT_half : STD_LOGIC; |
|
49 | SIGNAL FT_half : STD_LOGIC; | |
50 | SIGNAL FT_wait : STD_LOGIC; |
|
50 | SIGNAL FT_wait : STD_LOGIC; | |
51 |
|
51 | |||
52 | TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC); |
|
52 | TYPE state_fsm_time_management IS (DESYNC, TRANSITION, SYNC); | |
53 | SIGNAL state : state_fsm_time_management; |
|
53 | SIGNAL state : state_fsm_time_management; | |
54 |
|
54 | |||
55 | SIGNAL fsm_desync : STD_LOGIC; |
|
55 | SIGNAL fsm_desync : STD_LOGIC; | |
56 | SIGNAL fsm_transition : STD_LOGIC; |
|
56 | SIGNAL fsm_transition : STD_LOGIC; | |
57 |
|
57 | |||
58 | SIGNAL set_TCU : STD_LOGIC; |
|
58 | SIGNAL set_TCU : STD_LOGIC; | |
59 | SIGNAL CT_add1 : STD_LOGIC; |
|
59 | SIGNAL CT_add1 : STD_LOGIC; | |
60 |
|
60 | |||
61 | SIGNAL new_coarsetime_reg : STD_LOGIC; |
|
61 | SIGNAL new_coarsetime_reg : STD_LOGIC; | |
62 |
|
62 | |||
63 | BEGIN |
|
63 | BEGIN | |
64 |
|
64 | |||
65 | ----------------------------------------------------------------------------- |
|
65 | ----------------------------------------------------------------------------- | |
66 | -- |
|
66 | -- | |
67 | ----------------------------------------------------------------------------- |
|
67 | ----------------------------------------------------------------------------- | |
68 | PROCESS (clk, rstn) |
|
68 | PROCESS (clk, rstn) | |
69 | BEGIN -- PROCESS |
|
69 | BEGIN -- PROCESS | |
70 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
70 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
71 | new_coarsetime_reg <= '0'; |
|
71 | new_coarsetime_reg <= '0'; | |
72 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
72 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
73 | IF new_coarsetime = '1' THEN |
|
73 | IF new_coarsetime = '1' THEN | |
74 | new_coarsetime_reg <= '1'; |
|
74 | new_coarsetime_reg <= '1'; | |
75 | ELSIF tick = '1' THEN |
|
75 | ELSIF tick = '1' THEN | |
76 | new_coarsetime_reg <= '0'; |
|
76 | new_coarsetime_reg <= '0'; | |
77 | END IF; |
|
77 | END IF; | |
78 | END IF; |
|
78 | END IF; | |
79 | END PROCESS; |
|
79 | END PROCESS; | |
80 |
|
80 | |||
81 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
82 | -- FINE_TIME |
|
82 | -- FINE_TIME | |
83 | ----------------------------------------------------------------------------- |
|
83 | ----------------------------------------------------------------------------- | |
84 | fine_time_counter_1: fine_time_counter |
|
84 | fine_time_counter_1: fine_time_counter | |
85 | GENERIC MAP ( |
|
85 | GENERIC MAP ( | |
86 | WAITING_TIME => X"0040", |
|
86 | WAITING_TIME => X"0040", | |
87 | FIRST_DIVISION => FIRST_DIVISION) |
|
87 | FIRST_DIVISION => FIRST_DIVISION) | |
88 | PORT MAP ( |
|
88 | PORT MAP ( | |
89 | clk => clk, |
|
89 | clk => clk, | |
90 | rstn => rstn, |
|
90 | rstn => rstn, | |
91 | tick => tick, |
|
91 | tick => tick, | |
92 | fsm_transition => fsm_transition, -- todo |
|
92 | fsm_transition => fsm_transition, -- todo | |
93 | FT_max => FT_max, |
|
93 | FT_max => FT_max, | |
94 | FT_half => FT_half, |
|
94 | FT_half => FT_half, | |
95 | FT_wait => FT_wait, |
|
95 | FT_wait => FT_wait, | |
96 | fine_time => fine_time, |
|
96 | fine_time => fine_time, | |
97 | fine_time_new => fine_time_new); |
|
97 | fine_time_new => fine_time_new); | |
98 |
|
98 | |||
99 | ----------------------------------------------------------------------------- |
|
99 | ----------------------------------------------------------------------------- | |
100 | -- COARSE_TIME |
|
100 | -- COARSE_TIME | |
101 | ----------------------------------------------------------------------------- |
|
101 | ----------------------------------------------------------------------------- | |
102 | coarse_time_counter_1: coarse_time_counter |
|
102 | coarse_time_counter_1: coarse_time_counter | |
103 | GENERIC MAP( |
|
103 | GENERIC MAP( | |
104 | NB_SECOND_DESYNC => NB_SECOND_DESYNC ) |
|
104 | NB_SECOND_DESYNC => NB_SECOND_DESYNC ) | |
105 | PORT MAP ( |
|
105 | PORT MAP ( | |
106 | clk => clk, |
|
106 | clk => clk, | |
107 | rstn => rstn, |
|
107 | rstn => rstn, | |
108 | tick => tick, |
|
108 | tick => tick, | |
109 | set_TCU => set_TCU, -- todo |
|
109 | set_TCU => set_TCU, -- todo | |
110 | set_TCU_value => coarsetime_reg, -- todo |
|
110 | set_TCU_value => coarsetime_reg, -- todo | |
111 | CT_add1 => CT_add1, -- todo |
|
111 | CT_add1 => CT_add1, -- todo | |
112 | fsm_desync => fsm_desync, -- todo |
|
112 | fsm_desync => fsm_desync, -- todo | |
113 | FT_max => FT_max, |
|
113 | FT_max => FT_max, | |
114 | coarse_time => coarse_time, |
|
114 | coarse_time => coarse_time, | |
115 | coarse_time_new => coarse_time_new); |
|
115 | coarse_time_new => coarse_time_new); | |
116 |
|
116 | |||
117 | ----------------------------------------------------------------------------- |
|
117 | ----------------------------------------------------------------------------- | |
118 | -- FSM |
|
118 | -- FSM | |
119 | ----------------------------------------------------------------------------- |
|
119 | ----------------------------------------------------------------------------- | |
120 | fsm_desync <= '1' WHEN state = DESYNC ELSE '0'; |
|
120 | fsm_desync <= '1' WHEN state = DESYNC ELSE '0'; | |
121 | fsm_transition <= '1' WHEN state = TRANSITION ELSE '0'; |
|
121 | fsm_transition <= '1' WHEN state = TRANSITION ELSE '0'; | |
122 |
|
122 | |||
123 | PROCESS (clk, rstn) |
|
123 | PROCESS (clk, rstn) | |
124 | BEGIN -- PROCESS |
|
124 | BEGIN -- PROCESS | |
125 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
125 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
126 | state <= DESYNC; |
|
126 | state <= DESYNC; | |
127 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
127 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
128 | --CT_add1 <= '0'; |
|
128 | --CT_add1 <= '0'; | |
129 | set_TCU <= '0'; |
|
129 | set_TCU <= '0'; | |
130 | CASE state IS |
|
130 | CASE state IS | |
131 | WHEN DESYNC => |
|
131 | WHEN DESYNC => | |
132 | IF tick = '1' THEN |
|
132 | IF tick = '1' THEN | |
133 | state <= SYNC; |
|
133 | state <= SYNC; | |
134 | set_TCU <= new_coarsetime_reg; |
|
134 | set_TCU <= new_coarsetime_reg; | |
135 | --IF new_coarsetime = '0' AND FT_half = '1' THEN |
|
135 | --IF new_coarsetime = '0' AND FT_half = '1' THEN | |
136 | -- CT_add1 <= '1'; |
|
136 | -- CT_add1 <= '1'; | |
137 | --END IF; |
|
137 | --END IF; | |
138 | --ELSIF FT_max = '1' THEN |
|
138 | --ELSIF FT_max = '1' THEN | |
139 | -- CT_add1 <= '1'; |
|
139 | -- CT_add1 <= '1'; | |
140 | END IF; |
|
140 | END IF; | |
141 | WHEN TRANSITION => |
|
141 | WHEN TRANSITION => | |
142 | IF tick = '1' THEN |
|
142 | IF tick = '1' THEN | |
143 | state <= SYNC; |
|
143 | state <= SYNC; | |
144 | set_TCU <= new_coarsetime_reg; |
|
144 | set_TCU <= new_coarsetime_reg; | |
145 | --IF new_coarsetime = '0' THEN |
|
145 | --IF new_coarsetime = '0' THEN | |
146 | -- CT_add1 <= '1'; |
|
146 | -- CT_add1 <= '1'; | |
147 | --END IF; |
|
147 | --END IF; | |
148 | ELSIF FT_wait = '1' THEN |
|
148 | ELSIF FT_wait = '1' THEN | |
149 | --CT_add1 <= '1'; |
|
149 | --CT_add1 <= '1'; | |
150 | state <= DESYNC; |
|
150 | state <= DESYNC; | |
151 | END IF; |
|
151 | END IF; | |
152 | WHEN SYNC => |
|
152 | WHEN SYNC => | |
153 | IF tick = '1' THEN |
|
153 | IF tick = '1' THEN | |
154 | set_TCU <= new_coarsetime_reg; |
|
154 | set_TCU <= new_coarsetime_reg; | |
155 | --IF new_coarsetime = '0' THEN |
|
155 | --IF new_coarsetime = '0' THEN | |
156 | -- CT_add1 <= '1'; |
|
156 | -- CT_add1 <= '1'; | |
157 | --END IF; |
|
157 | --END IF; | |
158 | ELSIF FT_max = '1' THEN |
|
158 | ELSIF FT_max = '1' THEN | |
159 | state <= TRANSITION; |
|
159 | state <= TRANSITION; | |
160 | END IF; |
|
160 | END IF; | |
161 | WHEN OTHERS => NULL; |
|
161 | WHEN OTHERS => NULL; | |
162 | END CASE; |
|
162 | END CASE; | |
163 | END IF; |
|
163 | END IF; | |
164 | END PROCESS; |
|
164 | END PROCESS; | |
165 |
|
165 | |||
166 |
|
166 | |||
167 | CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
|
167 | CT_add1 <= '1' WHEN state = SYNC AND tick = '1' AND new_coarsetime_reg = '0' ELSE | |
168 | '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE |
|
168 | '1' WHEN state = DESYNC AND tick = '1' AND new_coarsetime_reg = '0' AND FT_half = '1' ELSE | |
169 | '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE |
|
169 | '1' WHEN state = DESYNC AND tick = '0' AND FT_max = '1' ELSE | |
170 | '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE |
|
170 | '1' WHEN state = TRANSITION AND tick = '1' AND new_coarsetime_reg = '0' ELSE | |
171 | '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE |
|
171 | '1' WHEN state = TRANSITION AND tick = '0' AND FT_wait = '1' ELSE | |
172 | '0'; |
|
172 | '0'; | |
173 | END Behavioral; |
|
173 | END Behavioral; |
@@ -1,101 +1,101 | |||||
1 | ---------------------------------------------------------------------------------- |
|
1 | ---------------------------------------------------------------------------------- | |
2 | -- Company: |
|
2 | -- Company: | |
3 | -- Engineer: |
|
3 | -- Engineer: | |
4 | -- |
|
4 | -- | |
5 | -- Create Date: 13:04:01 07/02/2012 |
|
5 | -- Create Date: 13:04:01 07/02/2012 | |
6 | -- Design Name: |
|
6 | -- Design Name: | |
7 | -- Module Name: lpp_lfr_time_management - Behavioral |
|
7 | -- Module Name: lpp_lfr_time_management - Behavioral | |
8 | -- Project Name: |
|
8 | -- Project Name: | |
9 | -- Target Devices: |
|
9 | -- Target Devices: | |
10 | -- Tool versions: |
|
10 | -- Tool versions: | |
11 | -- Description: |
|
11 | -- Description: | |
12 | -- |
|
12 | -- | |
13 | -- Dependencies: |
|
13 | -- Dependencies: | |
14 | -- |
|
14 | -- | |
15 | -- Revision: |
|
15 | -- Revision: | |
16 | -- Revision 0.01 - File Created |
|
16 | -- Revision 0.01 - File Created | |
17 | -- Additional Comments: |
|
17 | -- Additional Comments: | |
18 | -- |
|
18 | -- | |
19 | ---------------------------------------------------------------------------------- |
|
19 | ---------------------------------------------------------------------------------- | |
20 | LIBRARY IEEE; |
|
20 | LIBRARY IEEE; | |
21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
21 | USE IEEE.STD_LOGIC_1164.ALL; | |
22 | LIBRARY grlib; |
|
22 | LIBRARY grlib; | |
23 | USE grlib.amba.ALL; |
|
23 | USE grlib.amba.ALL; | |
24 | USE grlib.stdlib.ALL; |
|
24 | USE grlib.stdlib.ALL; | |
25 | USE grlib.devices.ALL; |
|
25 | USE grlib.devices.ALL; | |
26 |
|
26 | |||
27 | PACKAGE lpp_lfr_time_management IS |
|
27 | PACKAGE lpp_lfr_time_management IS | |
28 |
|
28 | |||
29 | --*************************** |
|
29 | --*************************** | |
30 | -- APB_LFR_TIME_MANAGEMENT |
|
30 | -- APB_LFR_TIME_MANAGEMENT | |
31 |
|
31 | |||
32 | COMPONENT apb_lfr_time_management IS |
|
32 | COMPONENT apb_lfr_time_management IS | |
33 | GENERIC( |
|
33 | GENERIC( | |
34 | pindex : INTEGER := 0; --! APB slave index |
|
34 | pindex : INTEGER := 0; --! APB slave index | |
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
|
35 | paddr : INTEGER := 0; --! ADDR field of the APB BAR | |
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
|
36 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR | |
37 | FIRST_DIVISION : INTEGER; |
|
37 | FIRST_DIVISION : INTEGER; | |
38 | NB_SECOND_DESYNC : INTEGER); |
|
38 | NB_SECOND_DESYNC : INTEGER); | |
39 | PORT ( |
|
39 | PORT ( | |
40 | clk25MHz : IN STD_LOGIC; --! Clock |
|
40 | clk25MHz : IN STD_LOGIC; --! Clock | |
41 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
|
41 | clk24_576MHz : IN STD_LOGIC; --! secondary clock | |
42 | resetn : IN STD_LOGIC; --! Reset |
|
42 | resetn : IN STD_LOGIC; --! Reset | |
43 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
|
43 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received | |
44 | apbi : IN apb_slv_in_type; --! APB slave input signals |
|
44 | apbi : IN apb_slv_in_type; --! APB slave input signals | |
45 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
|
45 | apbo : OUT apb_slv_out_type; --! APB slave output signals | |
46 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
|
46 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time | |
47 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time |
|
47 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time | |
48 | ); |
|
48 | ); | |
49 | END COMPONENT; |
|
49 | END COMPONENT; | |
50 |
|
50 | |||
51 | COMPONENT lfr_time_management |
|
51 | COMPONENT lfr_time_management | |
52 | GENERIC ( |
|
52 | GENERIC ( | |
53 | FIRST_DIVISION : INTEGER; |
|
53 | FIRST_DIVISION : INTEGER; | |
54 | NB_SECOND_DESYNC : INTEGER); |
|
54 | NB_SECOND_DESYNC : INTEGER); | |
55 | PORT ( |
|
55 | PORT ( | |
56 | clk : IN STD_LOGIC; |
|
56 | clk : IN STD_LOGIC; | |
57 | rstn : IN STD_LOGIC; |
|
57 | rstn : IN STD_LOGIC; | |
58 | tick : IN STD_LOGIC; |
|
58 | tick : IN STD_LOGIC; | |
59 | new_coarsetime : IN STD_LOGIC; |
|
59 | new_coarsetime : IN STD_LOGIC; | |
60 |
coarsetime_reg : IN STD_LOGIC_VECTOR(3 |
|
60 | coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
61 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
61 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
62 | fine_time_new : OUT STD_LOGIC; |
|
62 | fine_time_new : OUT STD_LOGIC; | |
63 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
64 | coarse_time_new : OUT STD_LOGIC); |
|
64 | coarse_time_new : OUT STD_LOGIC); | |
65 | END COMPONENT; |
|
65 | END COMPONENT; | |
66 |
|
66 | |||
67 | COMPONENT coarse_time_counter |
|
67 | COMPONENT coarse_time_counter | |
68 | GENERIC ( |
|
68 | GENERIC ( | |
69 | NB_SECOND_DESYNC : INTEGER ); |
|
69 | NB_SECOND_DESYNC : INTEGER ); | |
70 | PORT ( |
|
70 | PORT ( | |
71 | clk : IN STD_LOGIC; |
|
71 | clk : IN STD_LOGIC; | |
72 | rstn : IN STD_LOGIC; |
|
72 | rstn : IN STD_LOGIC; | |
73 | tick : IN STD_LOGIC; |
|
73 | tick : IN STD_LOGIC; | |
74 | set_TCU : IN STD_LOGIC; |
|
74 | set_TCU : IN STD_LOGIC; | |
75 |
set_TCU_value : IN STD_LOGIC_VECTOR(3 |
|
75 | set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 | CT_add1 : IN STD_LOGIC; |
|
76 | CT_add1 : IN STD_LOGIC; | |
77 | fsm_desync : IN STD_LOGIC; |
|
77 | fsm_desync : IN STD_LOGIC; | |
78 | FT_max : IN STD_LOGIC; |
|
78 | FT_max : IN STD_LOGIC; | |
79 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 | coarse_time_new : OUT STD_LOGIC); |
|
80 | coarse_time_new : OUT STD_LOGIC); | |
81 | END COMPONENT; |
|
81 | END COMPONENT; | |
82 |
|
82 | |||
83 | COMPONENT fine_time_counter |
|
83 | COMPONENT fine_time_counter | |
84 | GENERIC ( |
|
84 | GENERIC ( | |
85 | WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
85 | WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
86 | FIRST_DIVISION : INTEGER ); |
|
86 | FIRST_DIVISION : INTEGER ); | |
87 | PORT ( |
|
87 | PORT ( | |
88 | clk : IN STD_LOGIC; |
|
88 | clk : IN STD_LOGIC; | |
89 | rstn : IN STD_LOGIC; |
|
89 | rstn : IN STD_LOGIC; | |
90 | tick : IN STD_LOGIC; |
|
90 | tick : IN STD_LOGIC; | |
91 | fsm_transition : IN STD_LOGIC; |
|
91 | fsm_transition : IN STD_LOGIC; | |
92 | FT_max : OUT STD_LOGIC; |
|
92 | FT_max : OUT STD_LOGIC; | |
93 | FT_half : OUT STD_LOGIC; |
|
93 | FT_half : OUT STD_LOGIC; | |
94 | FT_wait : OUT STD_LOGIC; |
|
94 | FT_wait : OUT STD_LOGIC; | |
95 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
95 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); | |
96 | fine_time_new : OUT STD_LOGIC); |
|
96 | fine_time_new : OUT STD_LOGIC); | |
97 | END COMPONENT; |
|
97 | END COMPONENT; | |
98 |
|
98 | |||
99 |
|
99 | |||
100 | END lpp_lfr_time_management; |
|
100 | END lpp_lfr_time_management; | |
101 |
|
101 |
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