@@ -1,343 +1,343 | |||||
1 | library IEEE; |
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1 | library IEEE; | |
2 | use IEEE.STD_LOGIC_1164.ALL; |
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2 | use IEEE.STD_LOGIC_1164.ALL; | |
3 | use IEEE.NUMERIC_STD.ALL; |
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3 | use IEEE.NUMERIC_STD.ALL; | |
4 | library lpp; |
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4 | library lpp; | |
5 | use lpp.lpp_ad_conv.all; |
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5 | use lpp.lpp_ad_conv.all; | |
6 | use lpp.lpp_amba.all; |
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6 | use lpp.lpp_amba.all; | |
7 | use lpp.apb_devices_list.all; |
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7 | use lpp.apb_devices_list.all; | |
8 | use lpp.general_purpose.all; |
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8 | use lpp.general_purpose.all; | |
9 | use lpp.Rocket_PCM_Encoder.all; |
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9 | use lpp.Rocket_PCM_Encoder.all; | |
10 |
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10 | |||
11 | use work.config.all; |
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11 | use work.config.all; | |
12 |
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12 | |||
13 |
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13 | |||
14 | entity DC_ACQ_TOP is |
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14 | entity DC_ACQ_TOP is | |
15 | generic( |
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15 | generic( | |
16 | WordSize : integer := 8; |
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16 | WordSize : integer := 8; | |
17 | WordCnt : integer := 144; |
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17 | WordCnt : integer := 144; | |
18 | MinFCount : integer := 64; |
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18 | MinFCount : integer := 64; | |
19 | EnableSR : integer := 1; |
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19 | EnableSR : integer := 1; | |
20 | CstDATA : integer := 0; |
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20 | CstDATA : integer := 0; | |
21 | FakeADC : integer := 0; |
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21 | FakeADC : integer := 0; | |
22 | CDS : integer := 0 |
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22 | CDS : integer := 0 | |
23 | ); |
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23 | ); | |
24 | port( |
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24 | port( | |
25 |
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25 | |||
26 | reset : in std_logic; |
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26 | reset : in std_logic; | |
27 | clk : in std_logic; |
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27 | clk : in std_logic; | |
28 | SyncSig : in STD_LOGIC; |
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28 | SyncSig : in STD_LOGIC; | |
29 | minorF : in std_logic; |
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29 | minorF : in std_logic; | |
30 | majorF : in std_logic; |
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30 | majorF : in std_logic; | |
31 | sclk : in std_logic; |
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31 | sclk : in std_logic; | |
32 | WordClk : in std_logic; |
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32 | WordClk : in std_logic; | |
33 |
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33 | |||
34 | DC_ADC_Sclk : out std_logic; |
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34 | DC_ADC_Sclk : out std_logic; | |
35 | DC_ADC_IN : in std_logic_vector(1 downto 0); |
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35 | DC_ADC_IN : in std_logic_vector(1 downto 0); | |
36 | DC_ADC_ClkDiv : out std_logic; |
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36 | DC_ADC_ClkDiv : out std_logic; | |
37 | DC_ADC_FSynch : out std_logic; |
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37 | DC_ADC_FSynch : out std_logic; | |
38 | SET_RESET0 : out std_logic; |
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38 | SET_RESET0 : out std_logic; | |
39 | SET_RESET1 : out std_logic; |
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39 | SET_RESET1 : out std_logic; | |
40 |
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40 | |||
41 | AMR1X : out std_logic_vector(23 downto 0); |
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41 | AMR1X : out std_logic_vector(23 downto 0); | |
42 | AMR1Y : out std_logic_vector(23 downto 0); |
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42 | AMR1Y : out std_logic_vector(23 downto 0); | |
43 | AMR1Z : out std_logic_vector(23 downto 0); |
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43 | AMR1Z : out std_logic_vector(23 downto 0); | |
44 |
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44 | |||
45 | AMR2X : out std_logic_vector(23 downto 0); |
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45 | AMR2X : out std_logic_vector(23 downto 0); | |
46 | AMR2Y : out std_logic_vector(23 downto 0); |
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46 | AMR2Y : out std_logic_vector(23 downto 0); | |
47 | AMR2Z : out std_logic_vector(23 downto 0); |
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47 | AMR2Z : out std_logic_vector(23 downto 0); | |
48 |
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48 | |||
49 | AMR3X : out std_logic_vector(23 downto 0); |
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49 | AMR3X : out std_logic_vector(23 downto 0); | |
50 | AMR3Y : out std_logic_vector(23 downto 0); |
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50 | AMR3Y : out std_logic_vector(23 downto 0); | |
51 | AMR3Z : out std_logic_vector(23 downto 0); |
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51 | AMR3Z : out std_logic_vector(23 downto 0); | |
52 |
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52 | |||
53 | AMR4X : out std_logic_vector(23 downto 0); |
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53 | AMR4X : out std_logic_vector(23 downto 0); | |
54 | AMR4Y : out std_logic_vector(23 downto 0); |
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54 | AMR4Y : out std_logic_vector(23 downto 0); | |
55 | AMR4Z : out std_logic_vector(23 downto 0); |
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55 | AMR4Z : out std_logic_vector(23 downto 0); | |
56 |
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56 | |||
57 | Temp1 : out std_logic_vector(23 downto 0); |
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57 | Temp1 : out std_logic_vector(23 downto 0); | |
58 | Temp2 : out std_logic_vector(23 downto 0); |
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58 | Temp2 : out std_logic_vector(23 downto 0); | |
59 | Temp3 : out std_logic_vector(23 downto 0); |
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59 | Temp3 : out std_logic_vector(23 downto 0); | |
60 | Temp4 : out std_logic_vector(23 downto 0) |
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60 | Temp4 : out std_logic_vector(23 downto 0) | |
61 | ); |
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61 | ); | |
62 | end DC_ACQ_TOP; |
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62 | end DC_ACQ_TOP; | |
63 |
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63 | |||
64 | architecture Behavioral of DC_ACQ_TOP is |
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64 | architecture Behavioral of DC_ACQ_TOP is | |
65 |
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65 | |||
66 | signal DC_ADC_SmplClk : std_logic; |
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66 | signal DC_ADC_SmplClk : std_logic; | |
67 | signal LF_ADC_SmplClk : std_logic; |
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67 | signal LF_ADC_SmplClk : std_logic; | |
68 | signal SET_RESET0_sig : std_logic; |
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68 | signal SET_RESET0_sig : std_logic; | |
69 | signal SET_RESET1_sig : std_logic; |
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69 | signal SET_RESET1_sig : std_logic; | |
70 | signal SET_RESET_counter : integer range 0 to 31:=0; |
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70 | signal SET_RESET_counter : integer range 0 to 31:=0; | |
71 |
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71 | |||
72 | signal AMR1X_Sync : std_logic_vector(23 downto 0); |
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72 | signal AMR1X_Sync : std_logic_vector(23 downto 0); | |
73 | signal AMR1Y_Sync : std_logic_vector(23 downto 0); |
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73 | signal AMR1Y_Sync : std_logic_vector(23 downto 0); | |
74 | signal AMR1Z_Sync : std_logic_vector(23 downto 0); |
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74 | signal AMR1Z_Sync : std_logic_vector(23 downto 0); | |
75 |
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75 | |||
76 | signal AMR2X_Sync : std_logic_vector(23 downto 0); |
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76 | signal AMR2X_Sync : std_logic_vector(23 downto 0); | |
77 | signal AMR2Y_Sync : std_logic_vector(23 downto 0); |
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77 | signal AMR2Y_Sync : std_logic_vector(23 downto 0); | |
78 | signal AMR2Z_Sync : std_logic_vector(23 downto 0); |
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78 | signal AMR2Z_Sync : std_logic_vector(23 downto 0); | |
79 |
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79 | |||
80 | signal AMR3X_Sync : std_logic_vector(23 downto 0); |
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80 | signal AMR3X_Sync : std_logic_vector(23 downto 0); | |
81 | signal AMR3Y_Sync : std_logic_vector(23 downto 0); |
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81 | signal AMR3Y_Sync : std_logic_vector(23 downto 0); | |
82 | signal AMR3Z_Sync : std_logic_vector(23 downto 0); |
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82 | signal AMR3Z_Sync : std_logic_vector(23 downto 0); | |
83 |
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83 | |||
84 | signal AMR4X_Sync : std_logic_vector(23 downto 0); |
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84 | signal AMR4X_Sync : std_logic_vector(23 downto 0); | |
85 | signal AMR4Y_Sync : std_logic_vector(23 downto 0); |
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85 | signal AMR4Y_Sync : std_logic_vector(23 downto 0); | |
86 | signal AMR4Z_Sync : std_logic_vector(23 downto 0); |
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86 | signal AMR4Z_Sync : std_logic_vector(23 downto 0); | |
87 |
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87 | |||
88 | signal Temp1_Sync : std_logic_vector(23 downto 0); |
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88 | signal Temp1_Sync : std_logic_vector(23 downto 0); | |
89 | signal Temp2_Sync : std_logic_vector(23 downto 0); |
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89 | signal Temp2_Sync : std_logic_vector(23 downto 0); | |
90 | signal Temp3_Sync : std_logic_vector(23 downto 0); |
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90 | signal Temp3_Sync : std_logic_vector(23 downto 0); | |
91 | signal Temp4_Sync : std_logic_vector(23 downto 0); |
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91 | signal Temp4_Sync : std_logic_vector(23 downto 0); | |
92 |
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92 | |||
93 | begin |
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93 | begin | |
94 |
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94 | |||
95 | ------------------------------------------------------------------ |
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95 | ------------------------------------------------------------------ | |
96 | -- |
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96 | -- | |
97 | -- DC sampling clock generation |
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97 | -- DC sampling clock generation | |
98 | -- |
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98 | -- | |
99 | ------------------------------------------------------------------ |
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99 | ------------------------------------------------------------------ | |
100 |
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100 | |||
101 |
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101 | |||
102 | DC_SMPL_CLK0 : entity work.LF_SMPL_CLK |
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102 | DC_SMPL_CLK0 : entity work.LF_SMPL_CLK | |
103 | --generic map(36) |
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103 | --generic map(36) | |
104 | generic map(288) |
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104 | generic map(288) | |
105 | port map( |
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105 | port map( | |
106 | reset => reset, |
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106 | reset => reset, | |
107 | wclk => WordClk, |
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107 | wclk => WordClk, | |
108 | SMPL_CLK => DC_ADC_SmplClk |
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108 | SMPL_CLK => DC_ADC_SmplClk | |
109 | ); |
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109 | ); | |
110 | ------------------------------------------------------------------ |
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110 | ------------------------------------------------------------------ | |
111 |
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111 | |||
112 |
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112 | |||
113 |
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113 | |||
114 |
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114 | |||
115 | ------------------------------------------------------------------ |
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115 | ------------------------------------------------------------------ | |
116 | -- |
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116 | -- | |
117 | -- DC ADC |
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117 | -- DC ADC | |
118 | -- |
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118 | -- | |
119 | ------------------------------------------------------------------ |
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119 | ------------------------------------------------------------------ | |
120 | ADC1: IF CstDATA /= 1 GENERATE |
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120 | ADC1: IF CstDATA /= 1 GENERATE | |
121 | ADC : IF FakeADC /=1 GENERATE |
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121 | ADC : IF FakeADC /=1 GENERATE | |
122 |
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122 | |||
123 | DC_ADC0 : DUAL_ADS1278_DRIVER |
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123 | DC_ADC0 : DUAL_ADS1278_DRIVER | |
124 | port map( |
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124 | port map( | |
125 | Clk => clk, |
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125 | Clk => clk, | |
126 | reset => reset, |
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126 | reset => reset, | |
127 | SpiClk => DC_ADC_Sclk, |
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127 | SpiClk => DC_ADC_Sclk, | |
128 | DIN => DC_ADC_IN, |
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128 | DIN => DC_ADC_IN, | |
129 | SmplClk => DC_ADC_SmplClk, |
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129 | SmplClk => DC_ADC_SmplClk, | |
130 | OUT00 => AMR1X_Sync, |
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130 | OUT00 => AMR1X_Sync, | |
131 | OUT01 => AMR1Y_Sync, |
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131 | OUT01 => AMR1Y_Sync, | |
132 | OUT02 => AMR1Z_Sync, |
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132 | OUT02 => AMR1Z_Sync, | |
133 | OUT03 => AMR2X_Sync, |
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133 | OUT03 => AMR2X_Sync, | |
134 | OUT04 => AMR2Y_Sync, |
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134 | OUT04 => AMR2Y_Sync, | |
135 | OUT05 => AMR2Z_Sync, |
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135 | OUT05 => AMR2Z_Sync, | |
136 | OUT06 => Temp1_Sync, |
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136 | OUT06 => Temp1_Sync, | |
137 | OUT07 => Temp2_Sync, |
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137 | OUT07 => Temp2_Sync, | |
138 | OUT10 => AMR3X_Sync, |
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138 | OUT10 => AMR3X_Sync, | |
139 | OUT11 => AMR3Y_Sync, |
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139 | OUT11 => AMR3Y_Sync, | |
140 | OUT12 => AMR3Z_Sync, |
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140 | OUT12 => AMR3Z_Sync, | |
141 | OUT13 => AMR4X_Sync, |
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141 | OUT13 => AMR4X_Sync, | |
142 | OUT14 => AMR4Y_Sync, |
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142 | OUT14 => AMR4Y_Sync, | |
143 | OUT15 => AMR4Z_Sync, |
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143 | OUT15 => AMR4Z_Sync, | |
144 | OUT16 => Temp3_Sync, |
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144 | OUT16 => Temp3_Sync, | |
145 | OUT17 => Temp4_Sync, |
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145 | OUT17 => Temp4_Sync, | |
146 | FSynch => DC_ADC_FSynch |
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146 | FSynch => DC_ADC_FSynch | |
147 | ); |
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147 | ); | |
148 | END GENERATE; |
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148 | END GENERATE; | |
149 |
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149 | |||
150 | NOADC: IF FakeADC=1 GENERATE |
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150 | NOADC: IF FakeADC=1 GENERATE | |
151 |
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151 | |||
152 | DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER |
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152 | DC_ADC0 : entity work.FAKE_DUAL_ADS1278_DRIVER | |
153 | port map( |
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153 | port map( | |
154 | Clk => clk, |
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154 | Clk => clk, | |
155 | reset => reset, |
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155 | reset => reset, | |
156 | SpiClk => DC_ADC_Sclk, |
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156 | SpiClk => DC_ADC_Sclk, | |
157 | DIN => DC_ADC_IN, |
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157 | DIN => DC_ADC_IN, | |
158 | SmplClk => DC_ADC_SmplClk, |
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158 | SmplClk => DC_ADC_SmplClk, | |
159 | OUT00 => AMR1X_Sync, |
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159 | OUT00 => AMR1X_Sync, | |
160 | OUT01 => AMR1Y_Sync, |
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160 | OUT01 => AMR1Y_Sync, | |
161 | OUT02 => AMR1Z_Sync, |
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161 | OUT02 => AMR1Z_Sync, | |
162 | OUT03 => AMR2X_Sync, |
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162 | OUT03 => AMR2X_Sync, | |
163 | OUT04 => AMR2Y_Sync, |
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163 | OUT04 => AMR2Y_Sync, | |
164 | OUT05 => AMR2Z_Sync, |
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164 | OUT05 => AMR2Z_Sync, | |
165 | OUT06 => Temp1_Sync, |
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165 | OUT06 => Temp1_Sync, | |
166 | OUT07 => Temp2_Sync, |
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166 | OUT07 => Temp2_Sync, | |
167 | OUT10 => AMR3X_Sync, |
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167 | OUT10 => AMR3X_Sync, | |
168 | OUT11 => AMR3Y_Sync, |
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168 | OUT11 => AMR3Y_Sync, | |
169 | OUT12 => AMR3Z_Sync, |
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169 | OUT12 => AMR3Z_Sync, | |
170 | OUT13 => AMR4X_Sync, |
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170 | OUT13 => AMR4X_Sync, | |
171 | OUT14 => AMR4Y_Sync, |
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171 | OUT14 => AMR4Y_Sync, | |
172 | OUT15 => AMR4Z_Sync, |
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172 | OUT15 => AMR4Z_Sync, | |
173 | OUT16 => Temp3_Sync, |
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173 | OUT16 => Temp3_Sync, | |
174 | OUT17 => Temp4_Sync, |
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174 | OUT17 => Temp4_Sync, | |
175 | FSynch => DC_ADC_FSynch |
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175 | FSynch => DC_ADC_FSynch | |
176 | ); |
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176 | ); | |
177 | END GENERATE; |
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177 | END GENERATE; | |
178 |
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178 | |||
179 | END GENERATE; |
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179 | END GENERATE; | |
180 | ------------------------------------------------------------------ |
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180 | ------------------------------------------------------------------ | |
181 |
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181 | |||
182 | NOADC: IF CstDATA = 1 GENERATE |
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182 | NOADC: IF CstDATA = 1 GENERATE | |
183 |
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183 | |||
184 | AMR1X_Sync <= AMR1Xcst; |
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184 | AMR1X_Sync <= AMR1Xcst; | |
185 | AMR1Y_Sync <= AMR1Ycst; |
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185 | AMR1Y_Sync <= AMR1Ycst; | |
186 | AMR1Z_Sync <= AMR1Zcst; |
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186 | AMR1Z_Sync <= AMR1Zcst; | |
187 | AMR2X_Sync <= AMR2Xcst; |
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187 | AMR2X_Sync <= AMR2Xcst; | |
188 | AMR2Y_Sync <= AMR2Ycst; |
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188 | AMR2Y_Sync <= AMR2Ycst; | |
189 | AMR2Z_Sync <= AMR2Zcst; |
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189 | AMR2Z_Sync <= AMR2Zcst; | |
190 | Temp1_Sync <= Temp1cst; |
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190 | Temp1_Sync <= Temp1cst; | |
191 | Temp2_Sync <= Temp2cst; |
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191 | Temp2_Sync <= Temp2cst; | |
192 | AMR3X_Sync <= AMR3Xcst; |
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192 | AMR3X_Sync <= AMR3Xcst; | |
193 | AMR3Y_Sync <= AMR3Ycst; |
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193 | AMR3Y_Sync <= AMR3Ycst; | |
194 | AMR3Z_Sync <= AMR3Zcst; |
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194 | AMR3Z_Sync <= AMR3Zcst; | |
195 | AMR4X_Sync <= AMR4Xcst; |
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195 | AMR4X_Sync <= AMR4Xcst; | |
196 | AMR4Y_Sync <= AMR4Ycst; |
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196 | AMR4Y_Sync <= AMR4Ycst; | |
197 | AMR4Z_Sync <= AMR4Zcst; |
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197 | AMR4Z_Sync <= AMR4Zcst; | |
198 | Temp3_Sync <= Temp3cst; |
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198 | Temp3_Sync <= Temp3cst; | |
199 | Temp4_Sync <= Temp4cst; |
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199 | Temp4_Sync <= Temp4cst; | |
200 |
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200 | |||
201 |
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201 | |||
202 |
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202 | |||
203 |
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203 | |||
204 |
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204 | |||
205 | END GENERATE; |
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205 | END GENERATE; | |
206 |
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206 | |||
207 |
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207 | |||
208 |
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208 | |||
209 |
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209 | |||
210 | ------------------------------------------------------------------ |
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210 | ------------------------------------------------------------------ | |
211 | -- |
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211 | -- | |
212 | -- SET/RESET GEN |
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212 | -- SET/RESET GEN | |
213 | -- |
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213 | -- | |
214 | ------------------------------------------------------------------ |
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214 | ------------------------------------------------------------------ | |
215 |
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215 | |||
216 | SR: IF EnableSR /=0 GENERATE |
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216 | SR: IF EnableSR /=0 GENERATE | |
217 | process(reset,DC_ADC_SmplClk) |
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217 | process(reset,DC_ADC_SmplClk) | |
218 | begin |
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218 | begin | |
219 | if reset = '0' then |
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219 | if reset = '0' then | |
220 | SET_RESET0_sig <= '0'; |
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220 | SET_RESET0_sig <= '0'; | |
221 | elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then |
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221 | elsif DC_ADC_SmplClk'event and DC_ADC_SmplClk = '0' then | |
222 | if(SET_RESET_counter = 31) then |
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222 | if(SET_RESET_counter = 31) then | |
223 | SET_RESET0_sig <= not SET_RESET0_sig; |
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223 | SET_RESET0_sig <= not SET_RESET0_sig; | |
224 | SET_RESET_counter <= 0; |
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224 | SET_RESET_counter <= 0; | |
225 | else |
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225 | else | |
226 | SET_RESET_counter <= SET_RESET_counter +1; |
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226 | SET_RESET_counter <= SET_RESET_counter +1; | |
227 | end if; |
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227 | end if; | |
228 | end if; |
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228 | end if; | |
229 | end process; |
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229 | end process; | |
230 |
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230 | |||
231 | END GENERATE; |
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231 | END GENERATE; | |
232 | NOSR: IF EnableSR=0 GENERATE |
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232 | NOSR: IF EnableSR=0 GENERATE | |
233 | SET_RESET0_sig <= '0'; |
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233 | SET_RESET0_sig <= '0'; | |
234 | END GENERATE; |
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234 | END GENERATE; | |
235 |
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235 | |||
236 | SET_RESET1_sig <= SET_RESET0_sig; |
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236 | SET_RESET1_sig <= SET_RESET0_sig; | |
237 | SET_RESET0 <= SET_RESET0_sig; |
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237 | SET_RESET0 <= SET_RESET0_sig; | |
238 | SET_RESET1 <= SET_RESET1_sig; |
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238 | SET_RESET1 <= SET_RESET1_sig; | |
239 | ------------------------------------------------------------------ |
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239 | ------------------------------------------------------------------ | |
240 | ------------------------------------------------------------------ |
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240 | ------------------------------------------------------------------ | |
241 |
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241 | |||
242 |
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242 | |||
243 | ------------------------------------------------------------------ |
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243 | ------------------------------------------------------------------ | |
244 | -- |
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244 | -- | |
245 | -- Cross domain clock synchronisation |
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245 | -- Cross domain clock synchronisation | |
246 | -- |
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246 | -- | |
247 | ------------------------------------------------------------------ |
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247 | ------------------------------------------------------------------ | |
248 |
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248 | |||
249 | IF CDS =1 GENERATE |
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249 | CDS0: IF CDS =1 GENERATE | |
250 |
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250 | |||
251 | AMR1Xsync: entity work.Fast2SlowSync |
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251 | AMR1Xsync: entity work.Fast2SlowSync | |
252 | generic map(N => 24) |
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252 | generic map(N => 24) | |
253 | port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X); |
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253 | port map( AMR1X_Sync,clk,sclk,SyncSig,AMR1X); | |
254 | AMR1Ysync: entity work.Fast2SlowSync |
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254 | AMR1Ysync: entity work.Fast2SlowSync | |
255 | generic map(N => 24) |
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255 | generic map(N => 24) | |
256 | port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y); |
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256 | port map( AMR1Y_Sync,clk,sclk,SyncSig,AMR1Y); | |
257 | AMR1Zsync: entity work.Fast2SlowSync |
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257 | AMR1Zsync: entity work.Fast2SlowSync | |
258 | generic map(N => 24) |
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258 | generic map(N => 24) | |
259 | port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z); |
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259 | port map( AMR1Z_Sync,clk,sclk,SyncSig,AMR1Z); | |
260 |
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260 | |||
261 | AMR2Xsync: entity work.Fast2SlowSync |
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261 | AMR2Xsync: entity work.Fast2SlowSync | |
262 | generic map(N => 24) |
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262 | generic map(N => 24) | |
263 | port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X); |
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263 | port map( AMR2X_Sync,clk,sclk,SyncSig,AMR2X); | |
264 | AMR2Ysync: entity work.Fast2SlowSync |
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264 | AMR2Ysync: entity work.Fast2SlowSync | |
265 | generic map(N => 24) |
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265 | generic map(N => 24) | |
266 | port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y); |
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266 | port map( AMR2Y_Sync,clk,sclk,SyncSig,AMR2Y); | |
267 | AMR2Zsync: entity work.Fast2SlowSync |
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267 | AMR2Zsync: entity work.Fast2SlowSync | |
268 | generic map(N => 24) |
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268 | generic map(N => 24) | |
269 | port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z); |
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269 | port map( AMR2Z_Sync,clk,sclk,SyncSig,AMR2Z); | |
270 |
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270 | |||
271 | AMR3Xsync: entity work.Fast2SlowSync |
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271 | AMR3Xsync: entity work.Fast2SlowSync | |
272 | generic map(N => 24) |
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272 | generic map(N => 24) | |
273 | port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X); |
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273 | port map( AMR3X_Sync,clk,sclk,SyncSig,AMR3X); | |
274 | AMR3Ysync: entity work.Fast2SlowSync |
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274 | AMR3Ysync: entity work.Fast2SlowSync | |
275 | generic map(N => 24) |
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275 | generic map(N => 24) | |
276 | port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y); |
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276 | port map( AMR3Y_Sync,clk,sclk,SyncSig,AMR3Y); | |
277 | AMR3Zsync: entity work.Fast2SlowSync |
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277 | AMR3Zsync: entity work.Fast2SlowSync | |
278 | generic map(N => 24) |
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278 | generic map(N => 24) | |
279 | port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z); |
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279 | port map( AMR3Z_Sync,clk,sclk,SyncSig,AMR3Z); | |
280 |
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280 | |||
281 |
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281 | |||
282 | AMR4Xsync: entity work.Fast2SlowSync |
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282 | AMR4Xsync: entity work.Fast2SlowSync | |
283 | generic map(N => 24) |
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283 | generic map(N => 24) | |
284 | port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X); |
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284 | port map( AMR4X_Sync,clk,sclk,SyncSig,AMR4X); | |
285 | AMR4Ysync: entity work.Fast2SlowSync |
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285 | AMR4Ysync: entity work.Fast2SlowSync | |
286 | generic map(N => 24) |
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286 | generic map(N => 24) | |
287 | port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y); |
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287 | port map( AMR4Y_Sync,clk,sclk,SyncSig,AMR4Y); | |
288 | AMR4Zsync: entity work.Fast2SlowSync |
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288 | AMR4Zsync: entity work.Fast2SlowSync | |
289 | generic map(N => 24) |
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289 | generic map(N => 24) | |
290 | port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z); |
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290 | port map( AMR4Z_Sync,clk,sclk,SyncSig,AMR4Z); | |
291 |
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291 | |||
292 |
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292 | |||
293 | TEMP1sync: entity work.Fast2SlowSync |
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293 | TEMP1sync: entity work.Fast2SlowSync | |
294 | generic map(N => 24) |
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294 | generic map(N => 24) | |
295 | port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1); |
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295 | port map( TEMP1_Sync,clk,sclk,SyncSig,TEMP1); | |
296 | TEMP2sync: entity work.Fast2SlowSync |
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296 | TEMP2sync: entity work.Fast2SlowSync | |
297 | generic map(N => 24) |
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297 | generic map(N => 24) | |
298 | port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2); |
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298 | port map( TEMP2_Sync,clk,sclk,SyncSig,TEMP2); | |
299 | TEMP3sync: entity work.Fast2SlowSync |
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299 | TEMP3sync: entity work.Fast2SlowSync | |
300 | generic map(N => 24) |
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300 | generic map(N => 24) | |
301 | port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3); |
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301 | port map( TEMP3_Sync,clk,sclk,SyncSig,TEMP3); | |
302 | TEMP4sync: entity work.Fast2SlowSync |
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302 | TEMP4sync: entity work.Fast2SlowSync | |
303 | generic map(N => 24) |
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303 | generic map(N => 24) | |
304 | port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4); |
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304 | port map( TEMP4_Sync,clk,sclk,SyncSig,TEMP4); | |
305 |
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305 | |||
306 | END GENERATE; |
|
306 | END GENERATE; | |
307 |
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307 | |||
308 | IF CDS /= 1 GENERATE |
|
308 | IF CDS /= 1 GENERATE | |
309 |
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309 | |||
310 |
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310 | |||
311 | AMR1X_Sync <= AMR1X; |
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311 | AMR1X_Sync <= AMR1X; | |
312 | AMR1Y_Sync <= AMR1Y; |
|
312 | AMR1Y_Sync <= AMR1Y; | |
313 | AMR1Z_Sync <= AMR1Z; |
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313 | AMR1Z_Sync <= AMR1Z; | |
314 | AMR2X_Sync <= AMR2X; |
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314 | AMR2X_Sync <= AMR2X; | |
315 | AMR2Y_Sync <= AMR2Y; |
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315 | AMR2Y_Sync <= AMR2Y; | |
316 | AMR2Z_Sync <= AMR2Z; |
|
316 | AMR2Z_Sync <= AMR2Z; | |
317 | Temp1_Sync <= Temp1; |
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317 | Temp1_Sync <= Temp1; | |
318 | Temp2_Sync <= Temp2; |
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318 | Temp2_Sync <= Temp2; | |
319 | AMR3X_Sync <= AMR3X; |
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319 | AMR3X_Sync <= AMR3X; | |
320 | AMR3Y_Sync <= AMR3Y; |
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320 | AMR3Y_Sync <= AMR3Y; | |
321 | AMR3Z_Sync <= AMR3Z; |
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321 | AMR3Z_Sync <= AMR3Z; | |
322 | AMR4X_Sync <= AMR4X; |
|
322 | AMR4X_Sync <= AMR4X; | |
323 | AMR4Y_Sync <= AMR4Y; |
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323 | AMR4Y_Sync <= AMR4Y; | |
324 | AMR4Z_Sync <= AMR4Z; |
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324 | AMR4Z_Sync <= AMR4Z; | |
325 | Temp3_Sync <= Temp3; |
|
325 | Temp3_Sync <= Temp3; | |
326 | Temp4_Sync <= Temp4; |
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326 | Temp4_Sync <= Temp4; | |
327 |
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327 | |||
328 | END GENERATE; |
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328 | END GENERATE; | |
329 | ------------------------------------------------------------------ |
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329 | ------------------------------------------------------------------ | |
330 |
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330 | |||
331 |
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331 | |||
332 | end Behavioral; |
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332 | end Behavioral; | |
333 |
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333 | |||
334 |
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334 | |||
335 |
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335 | |||
336 |
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336 | |||
337 |
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338 |
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338 | |||
339 |
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339 | |||
340 |
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340 | |||
341 |
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341 | |||
342 |
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342 | |||
343 |
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343 |
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