@@ -425,7 +425,7 BEGIN -- beh | |||||
425 | pirq_ms => 6, |
|
425 | pirq_ms => 6, | |
426 | pirq_wfp => 14, |
|
426 | pirq_wfp => 14, | |
427 | hindex => 2, |
|
427 | hindex => 2, | |
428 |
top_lfr_version => X"00010 |
|
428 | top_lfr_version => X"000107") -- aa.bb.cc version | |
429 | PORT MAP ( |
|
429 | PORT MAP ( | |
430 | clk => clk_25, |
|
430 | clk => clk_25, | |
431 | rstn => reset, |
|
431 | rstn => reset, |
@@ -150,17 +150,55 BEGIN -- beh | |||||
150 | WAIT UNTIL clk25MHz = '1'; |
|
150 | WAIT UNTIL clk25MHz = '1'; | |
151 | grspw_tick <= '0'; |
|
151 | grspw_tick <= '0'; | |
152 |
|
152 | |||
|
153 | WAIT FOR 250 ms; | |||
|
154 | TB_string <= "READ 1 "; | |||
|
155 | apbi.psel(0) <= '1'; | |||
|
156 | apbi.pwrite <= '0'; | |||
|
157 | apbi.penable <= '1'; | |||
|
158 | apbi.paddr <= X"00000008"; | |||
|
159 | WAIT UNTIL clk25MHz = '1'; | |||
|
160 | apbi.psel(0) <= '0'; | |||
|
161 | apbi.pwrite <= '0'; | |||
|
162 | apbi.penable <= '0'; | |||
|
163 | apbi.paddr <= (OTHERS => '0'); | |||
|
164 | WAIT UNTIL clk25MHz = '1'; | |||
|
165 | WAIT FOR 250 ms; | |||
|
166 | TB_string <= "READ 2 "; | |||
|
167 | apbi.psel(0) <= '1'; | |||
|
168 | apbi.pwrite <= '0'; | |||
|
169 | apbi.penable <= '1'; | |||
|
170 | apbi.paddr <= X"00000008"; | |||
|
171 | WAIT UNTIL clk25MHz = '1'; | |||
|
172 | apbi.psel(0) <= '0'; | |||
|
173 | apbi.pwrite <= '0'; | |||
|
174 | apbi.penable <= '0'; | |||
|
175 | apbi.paddr <= (OTHERS => '0'); | |||
|
176 | WAIT UNTIL clk25MHz = '1'; | |||
|
177 | WAIT FOR 250 ms; | |||
|
178 | TB_string <= "READ 3 "; | |||
|
179 | apbi.psel(0) <= '1'; | |||
|
180 | apbi.pwrite <= '0'; | |||
|
181 | apbi.penable <= '1'; | |||
|
182 | apbi.paddr <= X"00000008"; | |||
|
183 | WAIT UNTIL clk25MHz = '1'; | |||
|
184 | apbi.psel(0) <= '0'; | |||
|
185 | apbi.pwrite <= '0'; | |||
|
186 | apbi.penable <= '0'; | |||
|
187 | apbi.paddr <= (OTHERS => '0'); | |||
|
188 | WAIT UNTIL clk25MHz = '1'; | |||
153 |
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189 | |||
154 |
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190 | |||
155 |
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191 | |||
156 | WAIT FOR 750 ms; |
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|||
157 |
|
||||
158 | REPORT "*** END simulation ***" SEVERITY failure; |
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192 | REPORT "*** END simulation ***" SEVERITY failure; | |
159 | WAIT; |
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193 | WAIT; | |
160 |
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194 | |||
161 | END PROCESS; |
|
195 | END PROCESS; | |
162 |
|
196 | |||
163 |
|
197 | |||
|
198 | ----------------------------------------------------------------------------- | |||
|
199 | -- | |||
|
200 | ----------------------------------------------------------------------------- | |||
|
201 | ||||
164 | global_time <= coarse_time & fine_time; |
|
202 | global_time <= coarse_time & fine_time; | |
165 |
|
203 | |||
166 | PROCESS (clk25MHz, resetn) |
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204 | PROCESS (clk25MHz, resetn) |
@@ -12,8 +12,11 add wave -noupdate /tb/apb_lfr_time_mana | |||||
12 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time |
|
12 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/fine_time | |
13 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time |
|
13 | add wave -noupdate -group OUTPUT /tb/apb_lfr_time_management_1/coarse_time | |
14 | add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new |
|
14 | add wave -noupdate /tb/apb_lfr_time_management_1/lfr_time_management_1/fine_time_new | |
|
15 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbi.psel {-radix hexadecimal} /tb/apbi.psel(0) {-radix hexadecimal} /tb/apbi.psel(1) {-radix hexadecimal} /tb/apbi.psel(2) {-radix hexadecimal} /tb/apbi.psel(3) {-radix hexadecimal} /tb/apbi.psel(4) {-radix hexadecimal} /tb/apbi.psel(5) {-radix hexadecimal} /tb/apbi.psel(6) {-radix hexadecimal} /tb/apbi.psel(7) {-radix hexadecimal} /tb/apbi.psel(8) {-radix hexadecimal} /tb/apbi.psel(9) {-radix hexadecimal} /tb/apbi.psel(10) {-radix hexadecimal} /tb/apbi.psel(11) {-radix hexadecimal} /tb/apbi.psel(12) {-radix hexadecimal} /tb/apbi.psel(13) {-radix hexadecimal} /tb/apbi.psel(14) {-radix hexadecimal} /tb/apbi.psel(15) {-radix hexadecimal} /tb/apbi.penable {-radix hexadecimal} /tb/apbi.paddr {-radix hexadecimal} /tb/apbi.pwrite {-radix hexadecimal} /tb/apbi.pwdata {-radix hexadecimal} /tb/apbi.pirq {-radix hexadecimal} /tb/apbi.testen {-radix hexadecimal} /tb/apbi.testrst {-radix hexadecimal} /tb/apbi.scanen {-radix hexadecimal} /tb/apbi.testoen {-radix hexadecimal} /tb/apbi.testin {-radix hexadecimal}} /tb/apbi | |||
|
16 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apbo.prdata {-radix hexadecimal} /tb/apbo.pirq {-radix hexadecimal} /tb/apbo.pconfig {-radix hexadecimal} /tb/apbo.pindex {-radix hexadecimal}} /tb/apbo | |||
|
17 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/apb_lfr_time_management_1/r.ctrl {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time_load {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.coarse_time {-radix hexadecimal} /tb/apb_lfr_time_management_1/r.fine_time {-radix hexadecimal}} /tb/apb_lfr_time_management_1/r | |||
15 | TreeUpdate [SetDefaultTree] |
|
18 | TreeUpdate [SetDefaultTree] | |
16 |
WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} { |
|
19 | WaveRestoreCursors {{FT 1} {15279095 ps} 1} {{FT 1 + 1s} {1000012719095 ps} 1} {{Cursor 3} {750199620000 ps} 0} {TRANSITION {169333245705 ps} 1} | |
17 | configure wave -namecolwidth 512 |
|
20 | configure wave -namecolwidth 512 | |
18 | configure wave -valuecolwidth 139 |
|
21 | configure wave -valuecolwidth 139 | |
19 | configure wave -justifyvalue left |
|
22 | configure wave -justifyvalue left | |
@@ -28,4 +31,4 configure wave -griddelta 40 | |||||
28 | configure wave -timeline 0 |
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31 | configure wave -timeline 0 | |
29 | configure wave -timelineunits ps |
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32 | configure wave -timelineunits ps | |
30 | update |
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33 | update | |
31 |
WaveRestoreZoom {0 ps} { |
|
34 | WaveRestoreZoom {0 ps} {1185800469 ns} |
@@ -131,6 +131,7 BEGIN | |||||
131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); |
|
131 | r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); | |
132 | coarsetime_reg_updated <= '1'; |
|
132 | coarsetime_reg_updated <= '1'; | |
133 | WHEN OTHERS => |
|
133 | WHEN OTHERS => | |
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134 | NULL; | |||
134 | END CASE; |
|
135 | END CASE; | |
135 | ELSIF r.ctrl = '1' THEN |
|
136 | ELSIF r.ctrl = '1' THEN | |
136 | r.ctrl <= '0'; |
|
137 | r.ctrl <= '0'; | |
@@ -141,6 +142,7 BEGIN | |||||
141 | CASE apbi.paddr(7 DOWNTO 2) IS |
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142 | CASE apbi.paddr(7 DOWNTO 2) IS | |
142 | WHEN "000000" => |
|
143 | WHEN "000000" => | |
143 | Rdata(0) <= r.ctrl; |
|
144 | Rdata(0) <= r.ctrl; | |
|
145 | Rdata(31 DOWNTO 1) <= (others => '0'); | |||
144 | WHEN "000001" => |
|
146 | WHEN "000001" => | |
145 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); |
|
147 | Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); | |
146 | WHEN "000010" => |
|
148 | WHEN "000010" => | |
@@ -149,7 +151,7 BEGIN | |||||
149 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
151 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
150 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
|
152 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); | |
151 | WHEN OTHERS => |
|
153 | WHEN OTHERS => | |
152 |
Rdata(31 DOWNTO 0) <= |
|
154 | Rdata(31 DOWNTO 0) <= (others => '0'); | |
153 | END CASE; |
|
155 | END CASE; | |
154 | END IF; |
|
156 | END IF; | |
155 |
|
157 | |||
@@ -271,4 +273,4 BEGIN | |||||
271 | coarse_time => coarse_time_49, |
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273 | coarse_time => coarse_time_49, | |
272 | coarse_time_new => coarse_time_new_49); |
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274 | coarse_time_new => coarse_time_new_49); | |
273 |
|
275 | |||
274 |
END Behavioral; |
|
276 | END Behavioral; No newline at end of file |
@@ -151,6 +151,11 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs | |||||
151 |
|
151 | |||
152 | ----------------------------------------------------------------------------- |
|
152 | ----------------------------------------------------------------------------- | |
153 | SIGNAL log_empty_fifo : STD_LOGIC; |
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153 | SIGNAL log_empty_fifo : STD_LOGIC; | |
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154 | ----------------------------------------------------------------------------- | |||
|
155 | SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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156 | SIGNAL header_reg_val : STD_LOGIC; | |||
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157 | SIGNAL header_reg_ack : STD_LOGIC; | |||
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158 | SIGNAL header_error : STD_LOGIC; | |||
154 |
|
159 | |||
155 | BEGIN |
|
160 | BEGIN | |
156 |
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161 | |||
@@ -183,7 +188,7 BEGIN | |||||
183 | matrix_type <= (OTHERS => '0'); |
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188 | matrix_type <= (OTHERS => '0'); | |
184 | component_type <= (OTHERS => '0'); |
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189 | component_type <= (OTHERS => '0'); | |
185 | state <= IDLE; |
|
190 | state <= IDLE; | |
186 | header_ack <= '0'; |
|
191 | -- header_ack <= '0'; | |
187 | ready_matrix_f0_0 <= '0'; |
|
192 | ready_matrix_f0_0 <= '0'; | |
188 | ready_matrix_f0_1 <= '0'; |
|
193 | ready_matrix_f0_1 <= '0'; | |
189 | ready_matrix_f1 <= '0'; |
|
194 | ready_matrix_f1 <= '0'; | |
@@ -199,12 +204,14 BEGIN | |||||
199 | header_data <= (OTHERS => '0'); |
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204 | header_data <= (OTHERS => '0'); | |
200 | fine_time_reg <= (OTHERS => '0'); |
|
205 | fine_time_reg <= (OTHERS => '0'); | |
201 |
|
206 | |||
202 |
debug_reg_s( |
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207 | debug_reg_s( 2 DOWNTO 0) <= (OTHERS => '0'); | |
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208 | debug_reg_s(31 DOWNTO 4) <= (OTHERS => '0'); | |||
203 |
|
209 | |||
204 | log_empty_fifo <= '0'; |
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210 | log_empty_fifo <= '0'; | |
205 |
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211 | |||
206 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
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212 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
207 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); |
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213 | debug_reg_s(31 DOWNTO 10) <= (OTHERS => '0'); | |
|
214 | header_reg_ack <= '0'; | |||
208 |
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215 | |||
209 | CASE state IS |
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216 | CASE state IS | |
210 | WHEN IDLE => |
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217 | WHEN IDLE => | |
@@ -219,15 +226,14 BEGIN | |||||
219 | ready_matrix_f2 <= '0'; |
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226 | ready_matrix_f2 <= '0'; | |
220 | error_bad_component_error <= '0'; |
|
227 | error_bad_component_error <= '0'; | |
221 | header_select <= '1'; |
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228 | header_select <= '1'; | |
222 | IF header_val = '1' THEN |
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|||
223 | header_ack <= '1'; |
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|||
224 | END IF; |
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|||
225 | IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN |
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|||
226 | debug_reg_s(5 DOWNTO 4) <= header(1 DOWNTO 0); |
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|||
227 | debug_reg_s(9 DOWNTO 6) <= header(5 DOWNTO 2); |
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|||
228 |
|
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229 | ||
229 | matrix_type <= header(1 DOWNTO 0); |
|
230 | IF header_reg_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN | |
230 | component_type <= header(5 DOWNTO 2); |
|
231 | header_reg_ack <= '1'; | |
|
232 | debug_reg_s(5 DOWNTO 4) <= header_reg(1 DOWNTO 0); | |||
|
233 | debug_reg_s(9 DOWNTO 6) <= header_reg(5 DOWNTO 2); | |||
|
234 | ||||
|
235 | matrix_type <= header_reg(1 DOWNTO 0); | |||
|
236 | component_type <= header_reg(5 DOWNTO 2); | |||
231 | component_type_pre <= component_type; |
|
237 | component_type_pre <= component_type; | |
232 | state <= CHECK_COMPONENT_TYPE; |
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238 | state <= CHECK_COMPONENT_TYPE; | |
233 | END IF; |
|
239 | END IF; | |
@@ -235,7 +241,7 BEGIN | |||||
235 |
|
241 | |||
236 | WHEN CHECK_COMPONENT_TYPE => |
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242 | WHEN CHECK_COMPONENT_TYPE => | |
237 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
243 | debug_reg_s(2 DOWNTO 0) <= "001"; | |
238 | header_ack <= '0'; |
|
244 | --header_ack <= '0'; | |
239 |
|
245 | |||
240 | IF header_check_ok = '1' THEN |
|
246 | IF header_check_ok = '1' THEN | |
241 | header_send <= '0'; |
|
247 | header_send <= '0'; | |
@@ -321,7 +327,7 BEGIN | |||||
321 | WHEN TRASH_FIFO => |
|
327 | WHEN TRASH_FIFO => | |
322 | debug_reg_s(2 DOWNTO 0) <= "100"; |
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328 | debug_reg_s(2 DOWNTO 0) <= "100"; | |
323 |
|
329 | |||
324 |
|
|
330 | -- header_ack <= '0'; | |
325 | error_bad_component_error <= '0'; |
|
331 | error_bad_component_error <= '0'; | |
326 | error_anticipating_empty_fifo <= '0'; |
|
332 | error_anticipating_empty_fifo <= '0'; | |
327 | IF fifo_empty = '1' THEN |
|
333 | IF fifo_empty = '1' THEN | |
@@ -332,7 +338,7 BEGIN | |||||
332 | END IF; |
|
338 | END IF; | |
333 |
|
339 | |||
334 | WHEN SEND_DATA => |
|
340 | WHEN SEND_DATA => | |
335 | header_ack <= '0'; |
|
341 | -- header_ack <= '0'; | |
336 | debug_reg_s(2 DOWNTO 0) <= "101"; |
|
342 | debug_reg_s(2 DOWNTO 0) <= "101"; | |
337 |
|
343 | |||
338 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
344 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN | |
@@ -391,4 +397,35 BEGIN | |||||
391 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; |
|
397 | header_send_ok <= '0' WHEN header_select = '0' ELSE dma_done; | |
392 | header_send_ko <= '0'; |
|
398 | header_send_ko <= '0'; | |
393 |
|
399 | |||
394 | END Behavioral; |
|
400 | ||
|
401 | ----------------------------------------------------------------------------- | |||
|
402 | -- FSM HEADER ACK | |||
|
403 | ----------------------------------------------------------------------------- | |||
|
404 | PROCESS (HCLK, HRESETn) | |||
|
405 | BEGIN -- PROCESS | |||
|
406 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
407 | header_ack <= '0'; | |||
|
408 | header_reg <= (OTHERS => '0'); | |||
|
409 | header_reg_val <= '0'; | |||
|
410 | ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge | |||
|
411 | header_ack <= '0'; | |||
|
412 | ||||
|
413 | IF header_val = '1' THEN | |||
|
414 | header_ack <= '1'; | |||
|
415 | header_reg <= header; | |||
|
416 | END IF; | |||
|
417 | ||||
|
418 | IF header_val = '1' THEN | |||
|
419 | header_reg_val <= '1'; | |||
|
420 | ELSIF header_reg_ack = '1' THEN | |||
|
421 | header_reg_val <= '0'; | |||
|
422 | END IF; | |||
|
423 | ||||
|
424 | header_error <= header_val AND header_reg_val AND (NOT Header_reg_ack); | |||
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425 | ||||
|
426 | END IF; | |||
|
427 | END PROCESS; | |||
|
428 | ||||
|
429 | debug_reg_s(3) <= header_error; | |||
|
430 | ||||
|
431 | END Behavioral; No newline at end of file |
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