##// END OF EJS Templates
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r294:cbd409d860be JC
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63
63
64 --debug
64 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
66 debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
68 debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
70 debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC;
72 debug_f3_data_valid : OUT STD_LOGIC;
73
73
74 -- debug FIFO_IN
74 -- debug FIFO_IN
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83
83
84 --debug FIFO OUT
84 --debug FIFO OUT
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93
93
94 --debug DMA IN
94 --debug DMA IN
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
103 );
103 );
104 END lpp_lfr;
104 END lpp_lfr;
105
105
106 ARCHITECTURE beh OF lpp_lfr IS
106 ARCHITECTURE beh OF lpp_lfr IS
107 SIGNAL sample : Samples14v(7 DOWNTO 0);
107 SIGNAL sample : Samples14v(7 DOWNTO 0);
108 SIGNAL sample_s : Samples(7 DOWNTO 0);
108 SIGNAL sample_s : Samples(7 DOWNTO 0);
109 --
109 --
110 SIGNAL data_shaping_SP0 : STD_LOGIC;
110 SIGNAL data_shaping_SP0 : STD_LOGIC;
111 SIGNAL data_shaping_SP1 : STD_LOGIC;
111 SIGNAL data_shaping_SP1 : STD_LOGIC;
112 SIGNAL data_shaping_R0 : STD_LOGIC;
112 SIGNAL data_shaping_R0 : STD_LOGIC;
113 SIGNAL data_shaping_R1 : STD_LOGIC;
113 SIGNAL data_shaping_R1 : STD_LOGIC;
114 --
114 --
115 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 --
118 --
119 SIGNAL sample_f0_val : STD_LOGIC;
119 SIGNAL sample_f0_val : STD_LOGIC;
120 SIGNAL sample_f1_val : STD_LOGIC;
120 SIGNAL sample_f1_val : STD_LOGIC;
121 SIGNAL sample_f2_val : STD_LOGIC;
121 SIGNAL sample_f2_val : STD_LOGIC;
122 SIGNAL sample_f3_val : STD_LOGIC;
122 SIGNAL sample_f3_val : STD_LOGIC;
123 --
123 --
124 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
124 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
125 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
125 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 --
128 --
129 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
130 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
130 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132
132
133 -- SM
133 -- SM
134 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
134 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
135 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
135 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
136 SIGNAL ready_matrix_f1 : STD_LOGIC;
136 SIGNAL ready_matrix_f1 : STD_LOGIC;
137 SIGNAL ready_matrix_f2 : STD_LOGIC;
137 SIGNAL ready_matrix_f2 : STD_LOGIC;
138 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
138 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
139 SIGNAL error_bad_component_error : STD_LOGIC;
139 SIGNAL error_bad_component_error : STD_LOGIC;
140 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
141 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
142 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
145 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
145 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
146 SIGNAL status_error_bad_component_error : STD_LOGIC;
146 SIGNAL status_error_bad_component_error : STD_LOGIC;
147 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
147 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
148 SIGNAL config_active_interruption_onError : STD_LOGIC;
148 SIGNAL config_active_interruption_onError : STD_LOGIC;
149 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153
153
154 -- WFP
154 -- WFP
155 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
159 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
161 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
162 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164
164
165 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
165 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
166 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
166 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
167 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 SIGNAL enable_f0 : STD_LOGIC;
168 SIGNAL enable_f0 : STD_LOGIC;
169 SIGNAL enable_f1 : STD_LOGIC;
169 SIGNAL enable_f1 : STD_LOGIC;
170 SIGNAL enable_f2 : STD_LOGIC;
170 SIGNAL enable_f2 : STD_LOGIC;
171 SIGNAL enable_f3 : STD_LOGIC;
171 SIGNAL enable_f3 : STD_LOGIC;
172 SIGNAL burst_f0 : STD_LOGIC;
172 SIGNAL burst_f0 : STD_LOGIC;
173 SIGNAL burst_f1 : STD_LOGIC;
173 SIGNAL burst_f1 : STD_LOGIC;
174 SIGNAL burst_f2 : STD_LOGIC;
174 SIGNAL burst_f2 : STD_LOGIC;
175 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179
179
180 SIGNAL run : STD_LOGIC;
180 SIGNAL run : STD_LOGIC;
181 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
181 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
182
182
183 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_data_out_valid : STD_LOGIC;
185 SIGNAL data_f0_data_out_valid : STD_LOGIC;
186 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
186 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
187 SIGNAL data_f0_data_out_ren : STD_LOGIC;
187 SIGNAL data_f0_data_out_ren : STD_LOGIC;
188 --f1
188 --f1
189 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_data_out_valid : STD_LOGIC;
191 SIGNAL data_f1_data_out_valid : STD_LOGIC;
192 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
192 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
193 SIGNAL data_f1_data_out_ren : STD_LOGIC;
193 SIGNAL data_f1_data_out_ren : STD_LOGIC;
194 --f2
194 --f2
195 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_data_out_valid : STD_LOGIC;
197 SIGNAL data_f2_data_out_valid : STD_LOGIC;
198 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
198 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
199 SIGNAL data_f2_data_out_ren : STD_LOGIC;
199 SIGNAL data_f2_data_out_ren : STD_LOGIC;
200 --f3
200 --f3
201 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_data_out_valid : STD_LOGIC;
203 SIGNAL data_f3_data_out_valid : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
205 SIGNAL data_f3_data_out_ren : STD_LOGIC;
205 SIGNAL data_f3_data_out_ren : STD_LOGIC;
206
206
207 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
208 --
208 --
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
211 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
212 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
212 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
213 --f1
213 --f1
214 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
215 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
216 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
216 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
217 --f2
217 --f2
218 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
219 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
220 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
220 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
221 --f3
221 --f3
222 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
223 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
224 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
224 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
225
225
226 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
227 -- DMA RR
227 -- DMA RR
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 SIGNAL dma_sel_valid : STD_LOGIC;
229 SIGNAL dma_sel_valid : STD_LOGIC;
230 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
230 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
231 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
231 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
233
233
234 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
235 -- DMA_REG
235 -- DMA_REG
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 SIGNAL ongoing_reg : STD_LOGIC;
237 SIGNAL ongoing_reg : STD_LOGIC;
238 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_send_reg : STD_LOGIC;
239 SIGNAL dma_send_reg : STD_LOGIC;
240 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
240 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
241 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
243
243
244
244
245 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
246 -- DMA
246 -- DMA
247 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
248 SIGNAL dma_send : STD_LOGIC;
248 SIGNAL dma_send : STD_LOGIC;
249 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
249 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
250 SIGNAL dma_done : STD_LOGIC;
250 SIGNAL dma_done : STD_LOGIC;
251 SIGNAL dma_ren : STD_LOGIC;
251 SIGNAL dma_ren : STD_LOGIC;
252 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255
255
256 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
257 -- DEBUG
257 -- DEBUG
258 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
259 --
259 --
260 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
260 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
261 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
261 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
262 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
262 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
263 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
263 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
264
264
265 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273
273
274 BEGIN
274 BEGIN
275
275
276 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
276 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
277 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
277 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
278
278
279 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
279 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
280 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
280 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
281 END GENERATE all_channel;
281 END GENERATE all_channel;
282
282
283 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
284 lpp_lfr_filter_1 : lpp_lfr_filter
284 lpp_lfr_filter_1 : lpp_lfr_filter
285 GENERIC MAP (
285 GENERIC MAP (
286 Mem_use => Mem_use)
286 Mem_use => Mem_use)
287 PORT MAP (
287 PORT MAP (
288 sample => sample_s,
288 sample => sample_s,
289 sample_val => sample_val,
289 sample_val => sample_val,
290 clk => clk,
290 clk => clk,
291 rstn => rstn,
291 rstn => rstn,
292 data_shaping_SP0 => data_shaping_SP0,
292 data_shaping_SP0 => data_shaping_SP0,
293 data_shaping_SP1 => data_shaping_SP1,
293 data_shaping_SP1 => data_shaping_SP1,
294 data_shaping_R0 => data_shaping_R0,
294 data_shaping_R0 => data_shaping_R0,
295 data_shaping_R1 => data_shaping_R1,
295 data_shaping_R1 => data_shaping_R1,
296 sample_f0_val => sample_f0_val,
296 sample_f0_val => sample_f0_val,
297 sample_f1_val => sample_f1_val,
297 sample_f1_val => sample_f1_val,
298 sample_f2_val => sample_f2_val,
298 sample_f2_val => sample_f2_val,
299 sample_f3_val => sample_f3_val,
299 sample_f3_val => sample_f3_val,
300 sample_f0_wdata => sample_f0_data,
300 sample_f0_wdata => sample_f0_data,
301 sample_f1_wdata => sample_f1_data,
301 sample_f1_wdata => sample_f1_data,
302 sample_f2_wdata => sample_f2_data,
302 sample_f2_wdata => sample_f2_data,
303 sample_f3_wdata => sample_f3_data);
303 sample_f3_wdata => sample_f3_data);
304
304
305 -----------------------------------------------------------------------------
305 -----------------------------------------------------------------------------
306 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
306 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
307 GENERIC MAP (
307 GENERIC MAP (
308 nb_data_by_buffer_size => nb_data_by_buffer_size,
308 nb_data_by_buffer_size => nb_data_by_buffer_size,
309 nb_word_by_buffer_size => nb_word_by_buffer_size,
309 nb_word_by_buffer_size => nb_word_by_buffer_size,
310 nb_snapshot_param_size => nb_snapshot_param_size,
310 nb_snapshot_param_size => nb_snapshot_param_size,
311 delta_vector_size => delta_vector_size,
311 delta_vector_size => delta_vector_size,
312 delta_vector_size_f0_2 => delta_vector_size_f0_2,
312 delta_vector_size_f0_2 => delta_vector_size_f0_2,
313 pindex => pindex,
313 pindex => pindex,
314 paddr => paddr,
314 paddr => paddr,
315 pmask => pmask,
315 pmask => pmask,
316 pirq_ms => pirq_ms,
316 pirq_ms => pirq_ms,
317 pirq_wfp => pirq_wfp,
317 pirq_wfp => pirq_wfp,
318 top_lfr_version => top_lfr_version)
318 top_lfr_version => top_lfr_version)
319 PORT MAP (
319 PORT MAP (
320 HCLK => clk,
320 HCLK => clk,
321 HRESETn => rstn,
321 HRESETn => rstn,
322 apbi => apbi,
322 apbi => apbi,
323 apbo => apbo,
323 apbo => apbo,
324 ready_matrix_f0_0 => ready_matrix_f0_0,
324 ready_matrix_f0_0 => ready_matrix_f0_0,
325 ready_matrix_f0_1 => ready_matrix_f0_1,
325 ready_matrix_f0_1 => ready_matrix_f0_1,
326 ready_matrix_f1 => ready_matrix_f1,
326 ready_matrix_f1 => ready_matrix_f1,
327 ready_matrix_f2 => ready_matrix_f2,
327 ready_matrix_f2 => ready_matrix_f2,
328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 error_bad_component_error => error_bad_component_error,
329 error_bad_component_error => error_bad_component_error,
330 debug_reg => debug_reg,
330 debug_reg => debug_reg,
331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 status_ready_matrix_f1 => status_ready_matrix_f1,
333 status_ready_matrix_f1 => status_ready_matrix_f1,
334 status_ready_matrix_f2 => status_ready_matrix_f2,
334 status_ready_matrix_f2 => status_ready_matrix_f2,
335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 status_error_bad_component_error => status_error_bad_component_error,
336 status_error_bad_component_error => status_error_bad_component_error,
337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 config_active_interruption_onError => config_active_interruption_onError,
338 config_active_interruption_onError => config_active_interruption_onError,
339 addr_matrix_f0_0 => addr_matrix_f0_0,
339 addr_matrix_f0_0 => addr_matrix_f0_0,
340 addr_matrix_f0_1 => addr_matrix_f0_1,
340 addr_matrix_f0_1 => addr_matrix_f0_1,
341 addr_matrix_f1 => addr_matrix_f1,
341 addr_matrix_f1 => addr_matrix_f1,
342 addr_matrix_f2 => addr_matrix_f2,
342 addr_matrix_f2 => addr_matrix_f2,
343 status_full => status_full,
343 status_full => status_full,
344 status_full_ack => status_full_ack,
344 status_full_ack => status_full_ack,
345 status_full_err => status_full_err,
345 status_full_err => status_full_err,
346 status_new_err => status_new_err,
346 status_new_err => status_new_err,
347 data_shaping_BW => data_shaping_BW,
347 data_shaping_BW => data_shaping_BW,
348 data_shaping_SP0 => data_shaping_SP0,
348 data_shaping_SP0 => data_shaping_SP0,
349 data_shaping_SP1 => data_shaping_SP1,
349 data_shaping_SP1 => data_shaping_SP1,
350 data_shaping_R0 => data_shaping_R0,
350 data_shaping_R0 => data_shaping_R0,
351 data_shaping_R1 => data_shaping_R1,
351 data_shaping_R1 => data_shaping_R1,
352 delta_snapshot => delta_snapshot,
352 delta_snapshot => delta_snapshot,
353 delta_f0 => delta_f0,
353 delta_f0 => delta_f0,
354 delta_f0_2 => delta_f0_2,
354 delta_f0_2 => delta_f0_2,
355 delta_f1 => delta_f1,
355 delta_f1 => delta_f1,
356 delta_f2 => delta_f2,
356 delta_f2 => delta_f2,
357 nb_data_by_buffer => nb_data_by_buffer,
357 nb_data_by_buffer => nb_data_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
359 nb_snapshot_param => nb_snapshot_param,
359 nb_snapshot_param => nb_snapshot_param,
360 enable_f0 => enable_f0,
360 enable_f0 => enable_f0,
361 enable_f1 => enable_f1,
361 enable_f1 => enable_f1,
362 enable_f2 => enable_f2,
362 enable_f2 => enable_f2,
363 enable_f3 => enable_f3,
363 enable_f3 => enable_f3,
364 burst_f0 => burst_f0,
364 burst_f0 => burst_f0,
365 burst_f1 => burst_f1,
365 burst_f1 => burst_f1,
366 burst_f2 => burst_f2,
366 burst_f2 => burst_f2,
367 run => run,
367 run => run,
368 addr_data_f0 => addr_data_f0,
368 addr_data_f0 => addr_data_f0,
369 addr_data_f1 => addr_data_f1,
369 addr_data_f1 => addr_data_f1,
370 addr_data_f2 => addr_data_f2,
370 addr_data_f2 => addr_data_f2,
371 addr_data_f3 => addr_data_f3,
371 addr_data_f3 => addr_data_f3,
372 start_date => start_date,
372 start_date => start_date,
373 ---------------------------------------------------------------------------
373 ---------------------------------------------------------------------------
374 debug_reg0 => debug_reg0,
374 debug_reg0 => debug_reg0,
375 debug_reg1 => debug_reg1,
375 debug_reg1 => debug_reg1,
376 debug_reg2 => debug_reg2,
376 debug_reg2 => debug_reg2,
377 debug_reg3 => debug_reg3,
377 debug_reg3 => debug_reg3,
378 debug_reg4 => debug_reg4,
378 debug_reg4 => debug_reg4,
379 debug_reg5 => debug_reg5,
379 debug_reg5 => debug_reg5,
380 debug_reg6 => debug_reg6,
380 debug_reg6 => debug_reg6,
381 debug_reg7 => debug_reg7);
381 debug_reg7 => debug_reg7);
382
382
383 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
383 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
384 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
384 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
385 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
385 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
386 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
387 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
387 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
388 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
388 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
389 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
389 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
390 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
390 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
391
391
392
392
393 -----------------------------------------------------------------------------
393 -----------------------------------------------------------------------------
394 lpp_waveform_1 : lpp_waveform
394 lpp_waveform_1 : lpp_waveform
395 GENERIC MAP (
395 GENERIC MAP (
396 tech => inferred,
396 tech => inferred,
397 data_size => 6*16,
397 data_size => 6*16,
398 nb_data_by_buffer_size => nb_data_by_buffer_size,
398 nb_data_by_buffer_size => nb_data_by_buffer_size,
399 nb_word_by_buffer_size => nb_word_by_buffer_size,
399 nb_word_by_buffer_size => nb_word_by_buffer_size,
400 nb_snapshot_param_size => nb_snapshot_param_size,
400 nb_snapshot_param_size => nb_snapshot_param_size,
401 delta_vector_size => delta_vector_size,
401 delta_vector_size => delta_vector_size,
402 delta_vector_size_f0_2 => delta_vector_size_f0_2
402 delta_vector_size_f0_2 => delta_vector_size_f0_2
403 )
403 )
404 PORT MAP (
404 PORT MAP (
405 clk => clk,
405 clk => clk,
406 rstn => rstn,
406 rstn => rstn,
407
407
408 reg_run => run,
408 reg_run => run,
409 reg_start_date => start_date,
409 reg_start_date => start_date,
410 reg_delta_snapshot => delta_snapshot,
410 reg_delta_snapshot => delta_snapshot,
411 reg_delta_f0 => delta_f0,
411 reg_delta_f0 => delta_f0,
412 reg_delta_f0_2 => delta_f0_2,
412 reg_delta_f0_2 => delta_f0_2,
413 reg_delta_f1 => delta_f1,
413 reg_delta_f1 => delta_f1,
414 reg_delta_f2 => delta_f2,
414 reg_delta_f2 => delta_f2,
415
415
416 enable_f0 => enable_f0,
416 enable_f0 => enable_f0,
417 enable_f1 => enable_f1,
417 enable_f1 => enable_f1,
418 enable_f2 => enable_f2,
418 enable_f2 => enable_f2,
419 enable_f3 => enable_f3,
419 enable_f3 => enable_f3,
420 burst_f0 => burst_f0,
420 burst_f0 => burst_f0,
421 burst_f1 => burst_f1,
421 burst_f1 => burst_f1,
422 burst_f2 => burst_f2,
422 burst_f2 => burst_f2,
423
423
424 nb_data_by_buffer => nb_data_by_buffer,
424 nb_data_by_buffer => nb_data_by_buffer,
425 nb_word_by_buffer => nb_word_by_buffer,
425 nb_word_by_buffer => nb_word_by_buffer,
426 nb_snapshot_param => nb_snapshot_param,
426 nb_snapshot_param => nb_snapshot_param,
427 status_full => status_full,
427 status_full => status_full,
428 status_full_ack => status_full_ack,
428 status_full_ack => status_full_ack,
429 status_full_err => status_full_err,
429 status_full_err => status_full_err,
430 status_new_err => status_new_err,
430 status_new_err => status_new_err,
431
431
432 coarse_time => coarse_time,
432 coarse_time => coarse_time,
433 fine_time => fine_time,
433 fine_time => fine_time,
434
434
435 --f0
435 --f0
436 addr_data_f0 => addr_data_f0,
436 addr_data_f0 => addr_data_f0,
437 data_f0_in_valid => sample_f0_val,
437 data_f0_in_valid => sample_f0_val,
438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
439 --f1
439 --f1
440 addr_data_f1 => addr_data_f1,
440 addr_data_f1 => addr_data_f1,
441 data_f1_in_valid => sample_f1_val,
441 data_f1_in_valid => sample_f1_val,
442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
443 --f2
443 --f2
444 addr_data_f2 => addr_data_f2,
444 addr_data_f2 => addr_data_f2,
445 data_f2_in_valid => sample_f2_val,
445 data_f2_in_valid => sample_f2_val,
446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
447 --f3
447 --f3
448 addr_data_f3 => addr_data_f3,
448 addr_data_f3 => addr_data_f3,
449 data_f3_in_valid => sample_f3_val,
449 data_f3_in_valid => sample_f3_val,
450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
451 -- OUTPUT -- DMA interface
451 -- OUTPUT -- DMA interface
452 --f0
452 --f0
453 data_f0_addr_out => data_f0_addr_out_s,
453 data_f0_addr_out => data_f0_addr_out_s,
454 data_f0_data_out => data_f0_data_out,
454 data_f0_data_out => data_f0_data_out,
455 data_f0_data_out_valid => data_f0_data_out_valid_s,
455 data_f0_data_out_valid => data_f0_data_out_valid_s,
456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
457 data_f0_data_out_ren => data_f0_data_out_ren,
457 data_f0_data_out_ren => data_f0_data_out_ren,
458 --f1
458 --f1
459 data_f1_addr_out => data_f1_addr_out_s,
459 data_f1_addr_out => data_f1_addr_out_s,
460 data_f1_data_out => data_f1_data_out,
460 data_f1_data_out => data_f1_data_out,
461 data_f1_data_out_valid => data_f1_data_out_valid_s,
461 data_f1_data_out_valid => data_f1_data_out_valid_s,
462 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
462 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
463 data_f1_data_out_ren => data_f1_data_out_ren,
463 data_f1_data_out_ren => data_f1_data_out_ren,
464 --f2
464 --f2
465 data_f2_addr_out => data_f2_addr_out_s,
465 data_f2_addr_out => data_f2_addr_out_s,
466 data_f2_data_out => data_f2_data_out,
466 data_f2_data_out => data_f2_data_out,
467 data_f2_data_out_valid => data_f2_data_out_valid_s,
467 data_f2_data_out_valid => data_f2_data_out_valid_s,
468 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
468 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
469 data_f2_data_out_ren => data_f2_data_out_ren,
469 data_f2_data_out_ren => data_f2_data_out_ren,
470 --f3
470 --f3
471 data_f3_addr_out => data_f3_addr_out_s,
471 data_f3_addr_out => data_f3_addr_out_s,
472 data_f3_data_out => data_f3_data_out,
472 data_f3_data_out => data_f3_data_out,
473 data_f3_data_out_valid => data_f3_data_out_valid_s,
473 data_f3_data_out_valid => data_f3_data_out_valid_s,
474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
475 data_f3_data_out_ren => data_f3_data_out_ren,
475 data_f3_data_out_ren => data_f3_data_out_ren,
476
476
477 -- debug SNAPSHOT_OUT
477 -- debug SNAPSHOT_OUT
478 debug_f0_data => debug_f0_data,
478 debug_f0_data => debug_f0_data,
479 debug_f0_data_valid => debug_f0_data_valid ,
479 debug_f0_data_valid => debug_f0_data_valid ,
480 debug_f1_data => debug_f1_data ,
480 debug_f1_data => debug_f1_data ,
481 debug_f1_data_valid => debug_f1_data_valid,
481 debug_f1_data_valid => debug_f1_data_valid,
482 debug_f2_data => debug_f2_data ,
482 debug_f2_data => debug_f2_data ,
483 debug_f2_data_valid => debug_f2_data_valid ,
483 debug_f2_data_valid => debug_f2_data_valid ,
484 debug_f3_data => debug_f3_data ,
484 debug_f3_data => debug_f3_data ,
485 debug_f3_data_valid => debug_f3_data_valid,
485 debug_f3_data_valid => debug_f3_data_valid,
486
486
487 -- debug FIFO_IN
487 -- debug FIFO_IN
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
496
496
497 );
497 );
498
498
499
499
500 -----------------------------------------------------------------------------
500 -----------------------------------------------------------------------------
501 -- DEBUG -- WFP OUT
501 -- DEBUG -- WFP OUT
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 debug_f0_data_fifo_out <= data_f0_data_out;
503 debug_f0_data_fifo_out <= data_f0_data_out;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 debug_f1_data_fifo_out <= data_f1_data_out;
505 debug_f1_data_fifo_out <= data_f1_data_out;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 debug_f2_data_fifo_out <= data_f2_data_out;
507 debug_f2_data_fifo_out <= data_f2_data_out;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 debug_f3_data_fifo_out <= data_f3_data_out;
509 debug_f3_data_fifo_out <= data_f3_data_out;
510 -----------------------------------------------------------------------------
510 -----------------------------------------------------------------------------
511
511
512
512
513 -----------------------------------------------------------------------------
513 -----------------------------------------------------------------------------
514 -- TEMP
514 -- TEMP
515 -----------------------------------------------------------------------------
515 -----------------------------------------------------------------------------
516
516
517 PROCESS (clk, rstn)
517 PROCESS (clk, rstn)
518 BEGIN -- PROCESS
518 BEGIN -- PROCESS
519 IF rstn = '0' THEN -- asynchronous reset (active low)
519 IF rstn = '0' THEN -- asynchronous reset (active low)
520 data_f0_data_out_valid <= '0';
520 data_f0_data_out_valid <= '0';
521 data_f0_data_out_valid_burst <= '0';
521 data_f0_data_out_valid_burst <= '0';
522 data_f1_data_out_valid <= '0';
522 data_f1_data_out_valid <= '0';
523 data_f1_data_out_valid_burst <= '0';
523 data_f1_data_out_valid_burst <= '0';
524 data_f2_data_out_valid <= '0';
524 data_f2_data_out_valid <= '0';
525 data_f2_data_out_valid_burst <= '0';
525 data_f2_data_out_valid_burst <= '0';
526 data_f3_data_out_valid <= '0';
526 data_f3_data_out_valid <= '0';
527 data_f3_data_out_valid_burst <= '0';
527 data_f3_data_out_valid_burst <= '0';
528 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
528 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
529 data_f0_data_out_valid <= data_f0_data_out_valid_s;
529 data_f0_data_out_valid <= data_f0_data_out_valid_s;
530 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
530 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
531 data_f1_data_out_valid <= data_f1_data_out_valid_s;
531 data_f1_data_out_valid <= data_f1_data_out_valid_s;
532 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
532 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
533 data_f2_data_out_valid <= data_f2_data_out_valid_s;
533 data_f2_data_out_valid <= data_f2_data_out_valid_s;
534 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
534 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
535 data_f3_data_out_valid <= data_f3_data_out_valid_s;
535 data_f3_data_out_valid <= data_f3_data_out_valid_s;
536 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
536 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
537 END IF;
537 END IF;
538 END PROCESS;
538 END PROCESS;
539
539
540 data_f0_addr_out <= data_f0_addr_out_s;
540 data_f0_addr_out <= data_f0_addr_out_s;
541 data_f1_addr_out <= data_f1_addr_out_s;
541 data_f1_addr_out <= data_f1_addr_out_s;
542 data_f2_addr_out <= data_f2_addr_out_s;
542 data_f2_addr_out <= data_f2_addr_out_s;
543 data_f3_addr_out <= data_f3_addr_out_s;
543 data_f3_addr_out <= data_f3_addr_out_s;
544
544
545 -----------------------------------------------------------------------------
545 -----------------------------------------------------------------------------
546 -- RoundRobin Selection For DMA
546 -- RoundRobin Selection For DMA
547 -----------------------------------------------------------------------------
547 -----------------------------------------------------------------------------
548
548
549 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
549 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
550 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
550 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
551 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
551 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
552 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
552 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
553
553
554 RR_Arbiter_4_1 : RR_Arbiter_4
554 RR_Arbiter_4_1 : RR_Arbiter_4
555 PORT MAP (
555 PORT MAP (
556 clk => clk,
556 clk => clk,
557 rstn => rstn,
557 rstn => rstn,
558 in_valid => dma_rr_valid,
558 in_valid => dma_rr_valid,
559 out_grant => dma_rr_grant);
559 out_grant => dma_rr_grant);
560
560
561
561
562 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
563 -- in : dma_rr_grant
563 -- in : dma_rr_grant
564 -- send
564 -- send
565 -- out : dma_sel
565 -- out : dma_sel
566 -- dma_valid_burst
566 -- dma_valid_burst
567 -- dma_sel_valid
567 -- dma_sel_valid
568 -----------------------------------------------------------------------------
568 -----------------------------------------------------------------------------
569 PROCESS (clk, rstn)
569 PROCESS (clk, rstn)
570 BEGIN -- PROCESS
570 BEGIN -- PROCESS
571 IF rstn = '0' THEN -- asynchronous reset (active low)
571 IF rstn = '0' THEN -- asynchronous reset (active low)
572 dma_sel <= (OTHERS => '0');
572 dma_sel <= (OTHERS => '0');
573 dma_send <= '0';
573 dma_send <= '0';
574 dma_valid_burst <= '0';
574 dma_valid_burst <= '0';
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 IF run = '1' THEN
576 IF run = '1' THEN
577 -- IF dma_sel = "0000" OR dma_send = '1' THEN
577 -- IF dma_sel = "0000" OR dma_send = '1' THEN
578 IF dma_sel = "0000" OR dma_done = '1' THEN
578 IF dma_sel = "0000" OR dma_done = '1' THEN
579 dma_sel <= dma_rr_grant;
579 dma_sel <= dma_rr_grant;
580 IF dma_rr_grant(0) = '1' THEN
580 IF dma_rr_grant(0) = '1' THEN
581 dma_send <= '1';
581 dma_send <= '1';
582 dma_valid_burst <= data_f0_data_out_valid_burst;
582 dma_valid_burst <= data_f0_data_out_valid_burst;
583 dma_sel_valid <= data_f0_data_out_valid;
583 dma_sel_valid <= data_f0_data_out_valid;
584 ELSIF dma_rr_grant(1) = '1' THEN
584 ELSIF dma_rr_grant(1) = '1' THEN
585 dma_send <= '1';
585 dma_send <= '1';
586 dma_valid_burst <= data_f1_data_out_valid_burst;
586 dma_valid_burst <= data_f1_data_out_valid_burst;
587 dma_sel_valid <= data_f1_data_out_valid;
587 dma_sel_valid <= data_f1_data_out_valid;
588 ELSIF dma_rr_grant(2) = '1' THEN
588 ELSIF dma_rr_grant(2) = '1' THEN
589 dma_send <= '1';
589 dma_send <= '1';
590 dma_valid_burst <= data_f2_data_out_valid_burst;
590 dma_valid_burst <= data_f2_data_out_valid_burst;
591 dma_sel_valid <= data_f2_data_out_valid;
591 dma_sel_valid <= data_f2_data_out_valid;
592 ELSIF dma_rr_grant(3) = '1' THEN
592 ELSIF dma_rr_grant(3) = '1' THEN
593 dma_send <= '1';
593 dma_send <= '1';
594 dma_valid_burst <= data_f3_data_out_valid_burst;
594 dma_valid_burst <= data_f3_data_out_valid_burst;
595 dma_sel_valid <= data_f3_data_out_valid;
595 dma_sel_valid <= data_f3_data_out_valid;
596 END IF;
596 END IF;
597 ELSE
597 ELSE
598 dma_sel <= dma_sel;
598 dma_sel <= dma_sel;
599 dma_send <= '0';
599 dma_send <= '0';
600 END IF;
600 END IF;
601 ELSE
601 ELSE
602 dma_sel <= (OTHERS => '0');
602 dma_sel <= (OTHERS => '0');
603 dma_send <= '0';
603 dma_send <= '0';
604 dma_valid_burst <= '0';
604 dma_valid_burst <= '0';
605 END IF;
605 END IF;
606 END IF;
606 END IF;
607 END PROCESS;
607 END PROCESS;
608
608
609
609
610 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
610 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
611 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
611 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
612 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
612 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
613 data_f3_addr_out;
613 data_f3_addr_out;
614
614
615 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
615 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
616 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
616 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
617 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
617 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
618 data_f3_data_out;
618 data_f3_data_out;
619
619
620 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
620 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
621 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
621 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
622 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
622 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
623 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
623 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
624
624
625 dma_data_2 <= dma_data;
625 dma_data_2 <= dma_data;
626
626
627
627
628
628
629
629
630
630
631 -----------------------------------------------------------------------------
631 -----------------------------------------------------------------------------
632 -- DEBUG -- DMA IN
632 -- DEBUG -- DMA IN
633 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
633 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
634 debug_f0_data_dma_in <= dma_data;
634 debug_f0_data_dma_in <= dma_data;
635 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
635 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
636 debug_f1_data_dma_in <= dma_data;
636 debug_f1_data_dma_in <= dma_data;
637 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
637 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
638 debug_f2_data_dma_in <= dma_data;
638 debug_f2_data_dma_in <= dma_data;
639 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
639 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
640 debug_f3_data_dma_in <= dma_data;
640 debug_f3_data_dma_in <= dma_data;
641 -----------------------------------------------------------------------------
641 -----------------------------------------------------------------------------
642
642
643 -----------------------------------------------------------------------------
643 -----------------------------------------------------------------------------
644 -- DMA
644 -- DMA
645 -----------------------------------------------------------------------------
645 -----------------------------------------------------------------------------
646 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
646 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
647 GENERIC MAP (
647 GENERIC MAP (
648 tech => inferred,
648 tech => inferred,
649 hindex => hindex)
649 hindex => hindex)
650 PORT MAP (
650 PORT MAP (
651 HCLK => clk,
651 HCLK => clk,
652 HRESETn => rstn,
652 HRESETn => rstn,
653 run => run,
653 run => run,
654 AHB_Master_In => ahbi,
654 AHB_Master_In => ahbi,
655 AHB_Master_Out => ahbo,
655 AHB_Master_Out => ahbo,
656
656
657 send => dma_send,
657 send => dma_send,
658 valid_burst => dma_valid_burst,
658 valid_burst => dma_valid_burst,
659 done => dma_done,
659 done => dma_done,
660 ren => dma_ren,
660 ren => dma_ren,
661 address => dma_address,
661 address => dma_address,
662 data => dma_data_2);
662 data => dma_data_2);
663
663
664 -----------------------------------------------------------------------------
664 -----------------------------------------------------------------------------
665 -- Matrix Spectral - TODO
665 -- Matrix Spectral - TODO
666 -----------------------------------------------------------------------------
666 -----------------------------------------------------------------------------
667 -----------------------------------------------------------------------------
667 -----------------------------------------------------------------------------
668 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
668 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
669 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
669 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
670 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
670 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
671 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
671 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
672 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
672 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
673 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
673 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
674
674
675 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
675 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
676 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
676 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
677 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
677 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
678 -------------------------------------------------------------------------------
678 -------------------------------------------------------------------------------
679 --lpp_lfr_ms_1: lpp_lfr_ms
679 --lpp_lfr_ms_1: lpp_lfr_ms
680 -- GENERIC MAP (
680 -- GENERIC MAP (
681 -- hindex => hindex_ms)
681 -- hindex => hindex_ms)
682 -- PORT MAP (
682 -- PORT MAP (
683 -- clk => clk,
683 -- clk => clk,
684 -- rstn => rstn,
684 -- rstn => rstn,
685 -- sample_f0_wen => sample_f0_wen,
685 -- sample_f0_wen => sample_f0_wen,
686 -- sample_f0_wdata => sample_f0_wdata,
686 -- sample_f0_wdata => sample_f0_wdata,
687 -- sample_f1_wen => sample_f1_wen,
687 -- sample_f1_wen => sample_f1_wen,
688 -- sample_f1_wdata => sample_f1_wdata,
688 -- sample_f1_wdata => sample_f1_wdata,
689 -- sample_f3_wen => sample_f3_wen,
689 -- sample_f3_wen => sample_f3_wen,
690 -- sample_f3_wdata => sample_f3_wdata,
690 -- sample_f3_wdata => sample_f3_wdata,
691 -- AHB_Master_In => ahbi_ms,
691 -- AHB_Master_In => ahbi_ms,
692 -- AHB_Master_Out => ahbo_ms,
692 -- AHB_Master_Out => ahbo_ms,
693
693
694 -- ready_matrix_f0_0 => ready_matrix_f0_0,
694 -- ready_matrix_f0_0 => ready_matrix_f0_0,
695 -- ready_matrix_f0_1 => ready_matrix_f0_1,
695 -- ready_matrix_f0_1 => ready_matrix_f0_1,
696 -- ready_matrix_f1 => ready_matrix_f1,
696 -- ready_matrix_f1 => ready_matrix_f1,
697 -- ready_matrix_f2 => ready_matrix_f2,
697 -- ready_matrix_f2 => ready_matrix_f2,
698 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
698 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
699 -- error_bad_component_error => error_bad_component_error,
699 -- error_bad_component_error => error_bad_component_error,
700 -- debug_reg => debug_reg,
700 -- debug_reg => debug_reg,
701 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
701 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
702 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
702 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
703 -- status_ready_matrix_f1 => status_ready_matrix_f1,
703 -- status_ready_matrix_f1 => status_ready_matrix_f1,
704 -- status_ready_matrix_f2 => status_ready_matrix_f2,
704 -- status_ready_matrix_f2 => status_ready_matrix_f2,
705 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
705 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
706 -- status_error_bad_component_error => status_error_bad_component_error,
706 -- status_error_bad_component_error => status_error_bad_component_error,
707 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
707 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
708 -- config_active_interruption_onError => config_active_interruption_onError,
708 -- config_active_interruption_onError => config_active_interruption_onError,
709 -- addr_matrix_f0_0 => addr_matrix_f0_0,
709 -- addr_matrix_f0_0 => addr_matrix_f0_0,
710 -- addr_matrix_f0_1 => addr_matrix_f0_1,
710 -- addr_matrix_f0_1 => addr_matrix_f0_1,
711 -- addr_matrix_f1 => addr_matrix_f1,
711 -- addr_matrix_f1 => addr_matrix_f1,
712 -- addr_matrix_f2 => addr_matrix_f2);
712 -- addr_matrix_f2 => addr_matrix_f2);
713
713
714 END beh;
714 END beh;
@@ -1,493 +1,493
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 -- IN
62 -- IN
63 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
70
71 -- OUT
71 -- OUT
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78
78
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
87 -- WaveForm picker Reg
87 -- WaveForm picker Reg
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92
92
93 -- OUT
93 -- OUT
94 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_BW : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
99
99
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108
108
109 enable_f0 : OUT STD_LOGIC;
109 enable_f0 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
113
113
114 burst_f0 : OUT STD_LOGIC;
114 burst_f0 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
117
117
118 run : OUT STD_LOGIC;
118 run : OUT STD_LOGIC;
119
119
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 ---------------------------------------------------------------------------
125 ---------------------------------------------------------------------------
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
134
134
135 ---------------------------------------------------------------------------
135 ---------------------------------------------------------------------------
136 );
136 );
137
137
138 END lpp_lfr_apbreg;
138 END lpp_lfr_apbreg;
139
139
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
141
141
142 CONSTANT REVISION : INTEGER := 1;
142 CONSTANT REVISION : INTEGER := 1;
143
143
144 CONSTANT pconfig : apb_config_type := (
144 CONSTANT pconfig : apb_config_type := (
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
146 1 => apb_iobar(paddr, pmask));
146 1 => apb_iobar(paddr, pmask));
147
147
148 TYPE lpp_SpectralMatrix_regs IS RECORD
148 TYPE lpp_SpectralMatrix_regs IS RECORD
149 config_active_interruption_onNewMatrix : STD_LOGIC;
149 config_active_interruption_onNewMatrix : STD_LOGIC;
150 config_active_interruption_onError : STD_LOGIC;
150 config_active_interruption_onError : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
152 status_ready_matrix_f0_1 : STD_LOGIC;
152 status_ready_matrix_f0_1 : STD_LOGIC;
153 status_ready_matrix_f1 : STD_LOGIC;
153 status_ready_matrix_f1 : STD_LOGIC;
154 status_ready_matrix_f2 : STD_LOGIC;
154 status_ready_matrix_f2 : STD_LOGIC;
155 status_error_anticipating_empty_fifo : STD_LOGIC;
155 status_error_anticipating_empty_fifo : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 END RECORD;
161 END RECORD;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
163
163
164 TYPE lpp_WaveformPicker_regs IS RECORD
164 TYPE lpp_WaveformPicker_regs IS RECORD
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_shaping_BW : STD_LOGIC;
168 data_shaping_BW : STD_LOGIC;
169 data_shaping_SP0 : STD_LOGIC;
169 data_shaping_SP0 : STD_LOGIC;
170 data_shaping_SP1 : STD_LOGIC;
170 data_shaping_SP1 : STD_LOGIC;
171 data_shaping_R0 : STD_LOGIC;
171 data_shaping_R0 : STD_LOGIC;
172 data_shaping_R1 : STD_LOGIC;
172 data_shaping_R1 : STD_LOGIC;
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
181 enable_f0 : STD_LOGIC;
181 enable_f0 : STD_LOGIC;
182 enable_f1 : STD_LOGIC;
182 enable_f1 : STD_LOGIC;
183 enable_f2 : STD_LOGIC;
183 enable_f2 : STD_LOGIC;
184 enable_f3 : STD_LOGIC;
184 enable_f3 : STD_LOGIC;
185 burst_f0 : STD_LOGIC;
185 burst_f0 : STD_LOGIC;
186 burst_f1 : STD_LOGIC;
186 burst_f1 : STD_LOGIC;
187 burst_f2 : STD_LOGIC;
187 burst_f2 : STD_LOGIC;
188 run : STD_LOGIC;
188 run : STD_LOGIC;
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
194 END RECORD;
194 END RECORD;
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
196
196
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
198
198
199 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
200 -- IRQ
200 -- IRQ
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
207 SIGNAL ored_irq_wfp : STD_LOGIC;
207 SIGNAL ored_irq_wfp : STD_LOGIC;
208
208
209 BEGIN -- beh
209 BEGIN -- beh
210
210
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
217
217
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
224
224
225
225
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
231
231
232 delta_snapshot <= reg_wp.delta_snapshot;
232 delta_snapshot <= reg_wp.delta_snapshot;
233 delta_f0 <= reg_wp.delta_f0;
233 delta_f0 <= reg_wp.delta_f0;
234 delta_f0_2 <= reg_wp.delta_f0_2;
234 delta_f0_2 <= reg_wp.delta_f0_2;
235 delta_f1 <= reg_wp.delta_f1;
235 delta_f1 <= reg_wp.delta_f1;
236 delta_f2 <= reg_wp.delta_f2;
236 delta_f2 <= reg_wp.delta_f2;
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
240
240
241 enable_f0 <= reg_wp.enable_f0;
241 enable_f0 <= reg_wp.enable_f0;
242 enable_f1 <= reg_wp.enable_f1;
242 enable_f1 <= reg_wp.enable_f1;
243 enable_f2 <= reg_wp.enable_f2;
243 enable_f2 <= reg_wp.enable_f2;
244 enable_f3 <= reg_wp.enable_f3;
244 enable_f3 <= reg_wp.enable_f3;
245
245
246 burst_f0 <= reg_wp.burst_f0;
246 burst_f0 <= reg_wp.burst_f0;
247 burst_f1 <= reg_wp.burst_f1;
247 burst_f1 <= reg_wp.burst_f1;
248 burst_f2 <= reg_wp.burst_f2;
248 burst_f2 <= reg_wp.burst_f2;
249
249
250 run <= reg_wp.run;
250 run <= reg_wp.run;
251
251
252 addr_data_f0 <= reg_wp.addr_data_f0;
252 addr_data_f0 <= reg_wp.addr_data_f0;
253 addr_data_f1 <= reg_wp.addr_data_f1;
253 addr_data_f1 <= reg_wp.addr_data_f1;
254 addr_data_f2 <= reg_wp.addr_data_f2;
254 addr_data_f2 <= reg_wp.addr_data_f2;
255 addr_data_f3 <= reg_wp.addr_data_f3;
255 addr_data_f3 <= reg_wp.addr_data_f3;
256
256
257 start_date <= reg_wp.start_date;
257 start_date <= reg_wp.start_date;
258
258
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
261 BEGIN -- PROCESS lpp_dma_top
261 BEGIN -- PROCESS lpp_dma_top
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
264 reg_sp.config_active_interruption_onError <= '0';
264 reg_sp.config_active_interruption_onError <= '0';
265 reg_sp.status_ready_matrix_f0_0 <= '0';
265 reg_sp.status_ready_matrix_f0_0 <= '0';
266 reg_sp.status_ready_matrix_f0_1 <= '0';
266 reg_sp.status_ready_matrix_f0_1 <= '0';
267 reg_sp.status_ready_matrix_f1 <= '0';
267 reg_sp.status_ready_matrix_f1 <= '0';
268 reg_sp.status_ready_matrix_f2 <= '0';
268 reg_sp.status_ready_matrix_f2 <= '0';
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
270 reg_sp.status_error_bad_component_error <= '0';
270 reg_sp.status_error_bad_component_error <= '0';
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
275 prdata <= (OTHERS => '0');
275 prdata <= (OTHERS => '0');
276
276
277 apbo.pirq <= (OTHERS => '0');
277 apbo.pirq <= (OTHERS => '0');
278
278
279 status_full_ack <= (OTHERS => '0');
279 status_full_ack <= (OTHERS => '0');
280
280
281 reg_wp.data_shaping_BW <= '0';
281 reg_wp.data_shaping_BW <= '0';
282 reg_wp.data_shaping_SP0 <= '0';
282 reg_wp.data_shaping_SP0 <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
284 reg_wp.data_shaping_R0 <= '0';
284 reg_wp.data_shaping_R0 <= '0';
285 reg_wp.data_shaping_R1 <= '0';
285 reg_wp.data_shaping_R1 <= '0';
286 reg_wp.enable_f0 <= '0';
286 reg_wp.enable_f0 <= '0';
287 reg_wp.enable_f1 <= '0';
287 reg_wp.enable_f1 <= '0';
288 reg_wp.enable_f2 <= '0';
288 reg_wp.enable_f2 <= '0';
289 reg_wp.enable_f3 <= '0';
289 reg_wp.enable_f3 <= '0';
290 reg_wp.burst_f0 <= '0';
290 reg_wp.burst_f0 <= '0';
291 reg_wp.burst_f1 <= '0';
291 reg_wp.burst_f1 <= '0';
292 reg_wp.burst_f2 <= '0';
292 reg_wp.burst_f2 <= '0';
293 reg_wp.run <= '0';
293 reg_wp.run <= '0';
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
305 reg_wp.delta_f2 <= (OTHERS => '0');
305 reg_wp.delta_f2 <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
309
309
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
311 status_full_ack <= (OTHERS => '0');
311 status_full_ack <= (OTHERS => '0');
312
312
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
317
317
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
327 END LOOP all_status;
327 END LOOP all_status;
328
328
329 paddr := "000000";
329 paddr := "000000";
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
331 prdata <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
332 IF apbi.psel(pindex) = '1' THEN
332 IF apbi.psel(pindex) = '1' THEN
333 -- APB DMA READ --
333 -- APB DMA READ --
334 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
335 --
335 --
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
337 prdata(1) <= reg_sp.config_active_interruption_onError;
337 prdata(1) <= reg_sp.config_active_interruption_onError;
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
343 prdata(5) <= reg_sp.status_error_bad_component_error;
343 prdata(5) <= reg_sp.status_error_bad_component_error;
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
348 WHEN "000110" => prdata <= debug_reg;
348 WHEN "000110" => prdata <= debug_reg;
349 --
349 --
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
351 prdata(1) <= reg_wp.data_shaping_SP0;
351 prdata(1) <= reg_wp.data_shaping_SP0;
352 prdata(2) <= reg_wp.data_shaping_SP1;
352 prdata(2) <= reg_wp.data_shaping_SP1;
353 prdata(3) <= reg_wp.data_shaping_R0;
353 prdata(3) <= reg_wp.data_shaping_R0;
354 prdata(4) <= reg_wp.data_shaping_R1;
354 prdata(4) <= reg_wp.data_shaping_R1;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
356 prdata(1) <= reg_wp.enable_f1;
356 prdata(1) <= reg_wp.enable_f1;
357 prdata(2) <= reg_wp.enable_f2;
357 prdata(2) <= reg_wp.enable_f2;
358 prdata(3) <= reg_wp.enable_f3;
358 prdata(3) <= reg_wp.enable_f3;
359 prdata(4) <= reg_wp.burst_f0;
359 prdata(4) <= reg_wp.burst_f0;
360 prdata(5) <= reg_wp.burst_f1;
360 prdata(5) <= reg_wp.burst_f1;
361 prdata(6) <= reg_wp.burst_f2;
361 prdata(6) <= reg_wp.burst_f2;
362 prdata(7) <= reg_wp.run;
362 prdata(7) <= reg_wp.run;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
379 ----------------------------------------------------
379 ----------------------------------------------------
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 ----------------------------------------------------
388 ----------------------------------------------------
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
389 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
390 WHEN OTHERS => NULL;
390 WHEN OTHERS => NULL;
391 END CASE;
391 END CASE;
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
393 -- APB DMA WRITE --
393 -- APB DMA WRITE --
394 CASE paddr(7 DOWNTO 2) IS
394 CASE paddr(7 DOWNTO 2) IS
395 --
395 --
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
408 --
408 --
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
415 reg_wp.enable_f1 <= apbi.pwdata(1);
415 reg_wp.enable_f1 <= apbi.pwdata(1);
416 reg_wp.enable_f2 <= apbi.pwdata(2);
416 reg_wp.enable_f2 <= apbi.pwdata(2);
417 reg_wp.enable_f3 <= apbi.pwdata(3);
417 reg_wp.enable_f3 <= apbi.pwdata(3);
418 reg_wp.burst_f0 <= apbi.pwdata(4);
418 reg_wp.burst_f0 <= apbi.pwdata(4);
419 reg_wp.burst_f1 <= apbi.pwdata(5);
419 reg_wp.burst_f1 <= apbi.pwdata(5);
420 reg_wp.burst_f2 <= apbi.pwdata(6);
420 reg_wp.burst_f2 <= apbi.pwdata(6);
421 reg_wp.run <= apbi.pwdata(7);
421 reg_wp.run <= apbi.pwdata(7);
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
442 --
442 --
443 WHEN OTHERS => NULL;
443 WHEN OTHERS => NULL;
444 END CASE;
444 END CASE;
445 END IF;
445 END IF;
446 END IF;
446 END IF;
447
447
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
449 ready_matrix_f0_1 OR
449 ready_matrix_f0_1 OR
450 ready_matrix_f1 OR
450 ready_matrix_f1 OR
451 ready_matrix_f2)
451 ready_matrix_f2)
452 )
452 )
453 OR
453 OR
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
455 error_bad_component_error)
455 error_bad_component_error)
456 ));
456 ));
457
457
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
462 -- );
462 -- );
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
464
464
465 END IF;
465 END IF;
466 END PROCESS lpp_lfr_apbreg;
466 END PROCESS lpp_lfr_apbreg;
467
467
468 apbo.pindex <= pindex;
468 apbo.pindex <= pindex;
469 apbo.pconfig <= pconfig;
469 apbo.pconfig <= pconfig;
470 apbo.prdata <= prdata;
470 apbo.prdata <= prdata;
471
471
472 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
473 -- IRQ
473 -- IRQ
474 -----------------------------------------------------------------------------
474 -----------------------------------------------------------------------------
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
476
476
477 PROCESS (HCLK, HRESETn)
477 PROCESS (HCLK, HRESETn)
478 BEGIN -- PROCESS
478 BEGIN -- PROCESS
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
480 irq_wfp_reg <= (OTHERS => '0');
480 irq_wfp_reg <= (OTHERS => '0');
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
482 irq_wfp_reg <= irq_wfp_reg_s;
482 irq_wfp_reg <= irq_wfp_reg_s;
483 END IF;
483 END IF;
484 END PROCESS;
484 END PROCESS;
485
485
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
488 END GENERATE all_irq_wfp;
488 END GENERATE all_irq_wfp;
489
489
490 irq_wfp_ZERO <= (OTHERS => '0');
490 irq_wfp_ZERO <= (OTHERS => '0');
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
492
492
493 END beh;
493 END beh;
@@ -1,252 +1,252
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
80 delta_vector_size : INTEGER;
80 delta_vector_size : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex : INTEGER;
87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
88 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
89 );
89 );
90 PORT (
90 PORT (
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
93 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_B : IN Samples14v(2 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
95 sample_val : IN STD_LOGIC;
95 sample_val : IN STD_LOGIC;
96 apbi : IN apb_slv_in_type;
96 apbi : IN apb_slv_in_type;
97 apbo : OUT apb_slv_out_type;
97 apbo : OUT apb_slv_out_type;
98 ahbi : IN AHB_Mst_In_Type;
98 ahbi : IN AHB_Mst_In_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
103
103
104 --debug
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC;
112 debug_f3_data_valid : OUT STD_LOGIC;
113
113
114 -- debug FIFO_IN
114 -- debug FIFO_IN
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123
123
124 --debug FIFO OUT
124 --debug FIFO OUT
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133
133
134 --debug DMA IN
134 --debug DMA IN
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 );
143 );
144 END COMPONENT;
144 END COMPONENT;
145
145
146 COMPONENT lpp_lfr_apbreg
146 COMPONENT lpp_lfr_apbreg
147 GENERIC (
147 GENERIC (
148 nb_data_by_buffer_size : INTEGER;
148 nb_data_by_buffer_size : INTEGER;
149 nb_word_by_buffer_size : INTEGER;
149 nb_word_by_buffer_size : INTEGER;
150 nb_snapshot_param_size : INTEGER;
150 nb_snapshot_param_size : INTEGER;
151 delta_vector_size : INTEGER;
151 delta_vector_size : INTEGER;
152 delta_vector_size_f0_2 : INTEGER;
152 delta_vector_size_f0_2 : INTEGER;
153 pindex : INTEGER;
153 pindex : INTEGER;
154 paddr : INTEGER;
154 paddr : INTEGER;
155 pmask : INTEGER;
155 pmask : INTEGER;
156 pirq_ms : INTEGER;
156 pirq_ms : INTEGER;
157 pirq_wfp : INTEGER;
157 pirq_wfp : INTEGER;
158 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
158 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
159 PORT (
159 PORT (
160 HCLK : IN STD_ULOGIC;
160 HCLK : IN STD_ULOGIC;
161 HRESETn : IN STD_ULOGIC;
161 HRESETn : IN STD_ULOGIC;
162 apbi : IN apb_slv_in_type;
162 apbi : IN apb_slv_in_type;
163 apbo : OUT apb_slv_out_type;
163 apbo : OUT apb_slv_out_type;
164 ready_matrix_f0_0 : IN STD_LOGIC;
164 ready_matrix_f0_0 : IN STD_LOGIC;
165 ready_matrix_f0_1 : IN STD_LOGIC;
165 ready_matrix_f0_1 : IN STD_LOGIC;
166 ready_matrix_f1 : IN STD_LOGIC;
166 ready_matrix_f1 : IN STD_LOGIC;
167 ready_matrix_f2 : IN STD_LOGIC;
167 ready_matrix_f2 : IN STD_LOGIC;
168 error_anticipating_empty_fifo : IN STD_LOGIC;
168 error_anticipating_empty_fifo : IN STD_LOGIC;
169 error_bad_component_error : IN STD_LOGIC;
169 error_bad_component_error : IN STD_LOGIC;
170 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 status_ready_matrix_f0_0 : OUT STD_LOGIC;
171 status_ready_matrix_f0_0 : OUT STD_LOGIC;
172 status_ready_matrix_f0_1 : OUT STD_LOGIC;
172 status_ready_matrix_f0_1 : OUT STD_LOGIC;
173 status_ready_matrix_f1 : OUT STD_LOGIC;
173 status_ready_matrix_f1 : OUT STD_LOGIC;
174 status_ready_matrix_f2 : OUT STD_LOGIC;
174 status_ready_matrix_f2 : OUT STD_LOGIC;
175 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
175 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
176 status_error_bad_component_error : OUT STD_LOGIC;
176 status_error_bad_component_error : OUT STD_LOGIC;
177 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
177 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
178 config_active_interruption_onError : OUT STD_LOGIC;
178 config_active_interruption_onError : OUT STD_LOGIC;
179 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
183 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
184 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
184 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
187 data_shaping_BW : OUT STD_LOGIC;
187 data_shaping_BW : OUT STD_LOGIC;
188 data_shaping_SP0 : OUT STD_LOGIC;
188 data_shaping_SP0 : OUT STD_LOGIC;
189 data_shaping_SP1 : OUT STD_LOGIC;
189 data_shaping_SP1 : OUT STD_LOGIC;
190 data_shaping_R0 : OUT STD_LOGIC;
190 data_shaping_R0 : OUT STD_LOGIC;
191 data_shaping_R1 : OUT STD_LOGIC;
191 data_shaping_R1 : OUT STD_LOGIC;
192 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
192 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
194 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
195 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
197 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
198 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
198 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
199 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
199 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
200 enable_f0 : OUT STD_LOGIC;
200 enable_f0 : OUT STD_LOGIC;
201 enable_f1 : OUT STD_LOGIC;
201 enable_f1 : OUT STD_LOGIC;
202 enable_f2 : OUT STD_LOGIC;
202 enable_f2 : OUT STD_LOGIC;
203 enable_f3 : OUT STD_LOGIC;
203 enable_f3 : OUT STD_LOGIC;
204 burst_f0 : OUT STD_LOGIC;
204 burst_f0 : OUT STD_LOGIC;
205 burst_f1 : OUT STD_LOGIC;
205 burst_f1 : OUT STD_LOGIC;
206 burst_f2 : OUT STD_LOGIC;
206 burst_f2 : OUT STD_LOGIC;
207 run : OUT STD_LOGIC;
207 run : OUT STD_LOGIC;
208 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
208 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
213 ---------------------------------------------------------------------------
213 ---------------------------------------------------------------------------
214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
222 END COMPONENT;
222 END COMPONENT;
223
223
224 COMPONENT lpp_top_ms
224 COMPONENT lpp_top_ms
225 GENERIC (
225 GENERIC (
226 Mem_use : INTEGER;
226 Mem_use : INTEGER;
227 nb_burst_available_size : INTEGER;
227 nb_burst_available_size : INTEGER;
228 nb_snapshot_param_size : INTEGER;
228 nb_snapshot_param_size : INTEGER;
229 delta_snapshot_size : INTEGER;
229 delta_snapshot_size : INTEGER;
230 delta_f2_f0_size : INTEGER;
230 delta_f2_f0_size : INTEGER;
231 delta_f2_f1_size : INTEGER;
231 delta_f2_f1_size : INTEGER;
232 pindex : INTEGER;
232 pindex : INTEGER;
233 paddr : INTEGER;
233 paddr : INTEGER;
234 pmask : INTEGER;
234 pmask : INTEGER;
235 pirq_ms : INTEGER;
235 pirq_ms : INTEGER;
236 pirq_wfp : INTEGER;
236 pirq_wfp : INTEGER;
237 hindex_wfp : INTEGER;
237 hindex_wfp : INTEGER;
238 hindex_ms : INTEGER);
238 hindex_ms : INTEGER);
239 PORT (
239 PORT (
240 clk : IN STD_LOGIC;
240 clk : IN STD_LOGIC;
241 rstn : IN STD_LOGIC;
241 rstn : IN STD_LOGIC;
242 sample_B : IN Samples14v(2 DOWNTO 0);
242 sample_B : IN Samples14v(2 DOWNTO 0);
243 sample_E : IN Samples14v(4 DOWNTO 0);
243 sample_E : IN Samples14v(4 DOWNTO 0);
244 sample_val : IN STD_LOGIC;
244 sample_val : IN STD_LOGIC;
245 apbi : IN apb_slv_in_type;
245 apbi : IN apb_slv_in_type;
246 apbo : OUT apb_slv_out_type;
246 apbo : OUT apb_slv_out_type;
247 ahbi_ms : IN AHB_Mst_In_Type;
247 ahbi_ms : IN AHB_Mst_In_Type;
248 ahbo_ms : OUT AHB_Mst_Out_Type;
248 ahbo_ms : OUT AHB_Mst_Out_Type;
249 data_shaping_BW : OUT STD_LOGIC);
249 data_shaping_BW : OUT STD_LOGIC);
250 END COMPONENT;
250 END COMPONENT;
251
251
252 END lpp_lfr_pkg;
252 END lpp_lfr_pkg;
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