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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_dma_pkg.ALL;
12 12 USE lpp.lpp_top_lfr_pkg.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.general_purpose.ALL;
15 15
16 16 LIBRARY techmap;
17 17 USE techmap.gencomp.ALL;
18 18
19 19 LIBRARY grlib;
20 20 USE grlib.amba.ALL;
21 21 USE grlib.stdlib.ALL;
22 22 USE grlib.devices.ALL;
23 23 USE GRLIB.DMA2AHB_Package.ALL;
24 24
25 25 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 29 nb_word_by_buffer_size : INTEGER := 11;
30 30 nb_snapshot_param_size : INTEGER := 11;
31 31 delta_vector_size : INTEGER := 20;
32 32 delta_vector_size_f0_2 : INTEGER := 7;
33 33
34 34 pindex : INTEGER := 4;
35 35 paddr : INTEGER := 4;
36 36 pmask : INTEGER := 16#fff#;
37 37 pirq_ms : INTEGER := 0;
38 38 pirq_wfp : INTEGER := 1;
39 39
40 40 hindex : INTEGER := 2;
41 41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43 43
44 44 );
45 45 PORT (
46 46 clk : IN STD_LOGIC;
47 47 rstn : IN STD_LOGIC;
48 48 -- SAMPLE
49 49 sample_B : IN Samples14v(2 DOWNTO 0);
50 50 sample_E : IN Samples14v(4 DOWNTO 0);
51 51 sample_val : IN STD_LOGIC;
52 52 -- APB
53 53 apbi : IN apb_slv_in_type;
54 54 apbo : OUT apb_slv_out_type;
55 55 -- AHB
56 56 ahbi : IN AHB_Mst_In_Type;
57 57 ahbo : OUT AHB_Mst_Out_Type;
58 58 -- TIME
59 59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 61 --
62 62 data_shaping_BW : OUT STD_LOGIC;
63 63
64 64 --debug
65 65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 66 debug_f0_data_valid : OUT STD_LOGIC;
67 67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 68 debug_f1_data_valid : OUT STD_LOGIC;
69 69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 debug_f2_data_valid : OUT STD_LOGIC;
71 71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 72 debug_f3_data_valid : OUT STD_LOGIC;
73 73
74 74 -- debug FIFO_IN
75 75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83 83
84 84 --debug FIFO OUT
85 85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93 93
94 94 --debug DMA IN
95 95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
103 103 );
104 104 END lpp_lfr;
105 105
106 106 ARCHITECTURE beh OF lpp_lfr IS
107 107 SIGNAL sample : Samples14v(7 DOWNTO 0);
108 108 SIGNAL sample_s : Samples(7 DOWNTO 0);
109 109 --
110 110 SIGNAL data_shaping_SP0 : STD_LOGIC;
111 111 SIGNAL data_shaping_SP1 : STD_LOGIC;
112 112 SIGNAL data_shaping_R0 : STD_LOGIC;
113 113 SIGNAL data_shaping_R1 : STD_LOGIC;
114 114 --
115 115 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 118 --
119 119 SIGNAL sample_f0_val : STD_LOGIC;
120 120 SIGNAL sample_f1_val : STD_LOGIC;
121 121 SIGNAL sample_f2_val : STD_LOGIC;
122 122 SIGNAL sample_f3_val : STD_LOGIC;
123 123 --
124 124 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
125 125 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 126 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 127 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 128 --
129 129 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
130 130 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 131 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 132
133 133 -- SM
134 134 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
135 135 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
136 136 SIGNAL ready_matrix_f1 : STD_LOGIC;
137 137 SIGNAL ready_matrix_f2 : STD_LOGIC;
138 138 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
139 139 SIGNAL error_bad_component_error : STD_LOGIC;
140 140 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 141 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
142 142 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
143 143 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
144 144 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
145 145 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
146 146 SIGNAL status_error_bad_component_error : STD_LOGIC;
147 147 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
148 148 SIGNAL config_active_interruption_onError : STD_LOGIC;
149 149 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 150 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 151 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153
154 154 -- WFP
155 155 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 156 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 157 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 158 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 160 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 161 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
162 162 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 163 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 164
165 165 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
166 166 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
167 167 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 168 SIGNAL enable_f0 : STD_LOGIC;
169 169 SIGNAL enable_f1 : STD_LOGIC;
170 170 SIGNAL enable_f2 : STD_LOGIC;
171 171 SIGNAL enable_f3 : STD_LOGIC;
172 172 SIGNAL burst_f0 : STD_LOGIC;
173 173 SIGNAL burst_f1 : STD_LOGIC;
174 174 SIGNAL burst_f2 : STD_LOGIC;
175 175 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 176 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 177 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 178 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 179
180 180 SIGNAL run : STD_LOGIC;
181 181 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
182 182
183 183 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 184 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 185 SIGNAL data_f0_data_out_valid : STD_LOGIC;
186 186 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
187 187 SIGNAL data_f0_data_out_ren : STD_LOGIC;
188 188 --f1
189 189 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 191 SIGNAL data_f1_data_out_valid : STD_LOGIC;
192 192 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
193 193 SIGNAL data_f1_data_out_ren : STD_LOGIC;
194 194 --f2
195 195 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 196 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 197 SIGNAL data_f2_data_out_valid : STD_LOGIC;
198 198 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
199 199 SIGNAL data_f2_data_out_ren : STD_LOGIC;
200 200 --f3
201 201 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 202 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 203 SIGNAL data_f3_data_out_valid : STD_LOGIC;
204 204 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
205 205 SIGNAL data_f3_data_out_ren : STD_LOGIC;
206 206
207 207 -----------------------------------------------------------------------------
208 208 --
209 209 -----------------------------------------------------------------------------
210 210 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
211 211 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
212 212 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
213 213 --f1
214 214 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
215 215 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
216 216 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
217 217 --f2
218 218 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 219 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
220 220 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
221 221 --f3
222 222 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 223 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
224 224 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
225 225
226 226 -----------------------------------------------------------------------------
227 227 -- DMA RR
228 228 -----------------------------------------------------------------------------
229 229 SIGNAL dma_sel_valid : STD_LOGIC;
230 230 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
231 231 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 232 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 233
234 234 -----------------------------------------------------------------------------
235 235 -- DMA_REG
236 236 -----------------------------------------------------------------------------
237 237 SIGNAL ongoing_reg : STD_LOGIC;
238 238 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 239 SIGNAL dma_send_reg : STD_LOGIC;
240 240 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
241 241 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 242 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
243 243
244 244
245 245 -----------------------------------------------------------------------------
246 246 -- DMA
247 247 -----------------------------------------------------------------------------
248 248 SIGNAL dma_send : STD_LOGIC;
249 249 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
250 250 SIGNAL dma_done : STD_LOGIC;
251 251 SIGNAL dma_ren : STD_LOGIC;
252 252 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 253 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 254 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
255 255
256 256 -----------------------------------------------------------------------------
257 257 -- DEBUG
258 258 -----------------------------------------------------------------------------
259 259 --
260 260 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
261 261 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
262 262 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
263 263 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
264 264
265 265 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 266 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 267 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 268 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 269 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 270 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 271 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 272 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 273
274 274 BEGIN
275 275
276 276 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
277 277 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
278 278
279 279 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
280 280 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
281 281 END GENERATE all_channel;
282 282
283 283 -----------------------------------------------------------------------------
284 284 lpp_lfr_filter_1 : lpp_lfr_filter
285 285 GENERIC MAP (
286 286 Mem_use => Mem_use)
287 287 PORT MAP (
288 288 sample => sample_s,
289 289 sample_val => sample_val,
290 290 clk => clk,
291 291 rstn => rstn,
292 292 data_shaping_SP0 => data_shaping_SP0,
293 293 data_shaping_SP1 => data_shaping_SP1,
294 294 data_shaping_R0 => data_shaping_R0,
295 295 data_shaping_R1 => data_shaping_R1,
296 296 sample_f0_val => sample_f0_val,
297 297 sample_f1_val => sample_f1_val,
298 298 sample_f2_val => sample_f2_val,
299 299 sample_f3_val => sample_f3_val,
300 300 sample_f0_wdata => sample_f0_data,
301 301 sample_f1_wdata => sample_f1_data,
302 302 sample_f2_wdata => sample_f2_data,
303 303 sample_f3_wdata => sample_f3_data);
304 304
305 305 -----------------------------------------------------------------------------
306 306 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
307 307 GENERIC MAP (
308 308 nb_data_by_buffer_size => nb_data_by_buffer_size,
309 309 nb_word_by_buffer_size => nb_word_by_buffer_size,
310 310 nb_snapshot_param_size => nb_snapshot_param_size,
311 311 delta_vector_size => delta_vector_size,
312 312 delta_vector_size_f0_2 => delta_vector_size_f0_2,
313 313 pindex => pindex,
314 314 paddr => paddr,
315 315 pmask => pmask,
316 316 pirq_ms => pirq_ms,
317 317 pirq_wfp => pirq_wfp,
318 318 top_lfr_version => top_lfr_version)
319 319 PORT MAP (
320 320 HCLK => clk,
321 321 HRESETn => rstn,
322 322 apbi => apbi,
323 323 apbo => apbo,
324 324 ready_matrix_f0_0 => ready_matrix_f0_0,
325 325 ready_matrix_f0_1 => ready_matrix_f0_1,
326 326 ready_matrix_f1 => ready_matrix_f1,
327 327 ready_matrix_f2 => ready_matrix_f2,
328 328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 329 error_bad_component_error => error_bad_component_error,
330 330 debug_reg => debug_reg,
331 331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 333 status_ready_matrix_f1 => status_ready_matrix_f1,
334 334 status_ready_matrix_f2 => status_ready_matrix_f2,
335 335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 336 status_error_bad_component_error => status_error_bad_component_error,
337 337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 338 config_active_interruption_onError => config_active_interruption_onError,
339 339 addr_matrix_f0_0 => addr_matrix_f0_0,
340 340 addr_matrix_f0_1 => addr_matrix_f0_1,
341 341 addr_matrix_f1 => addr_matrix_f1,
342 342 addr_matrix_f2 => addr_matrix_f2,
343 343 status_full => status_full,
344 344 status_full_ack => status_full_ack,
345 345 status_full_err => status_full_err,
346 346 status_new_err => status_new_err,
347 347 data_shaping_BW => data_shaping_BW,
348 348 data_shaping_SP0 => data_shaping_SP0,
349 349 data_shaping_SP1 => data_shaping_SP1,
350 350 data_shaping_R0 => data_shaping_R0,
351 351 data_shaping_R1 => data_shaping_R1,
352 352 delta_snapshot => delta_snapshot,
353 353 delta_f0 => delta_f0,
354 354 delta_f0_2 => delta_f0_2,
355 355 delta_f1 => delta_f1,
356 356 delta_f2 => delta_f2,
357 357 nb_data_by_buffer => nb_data_by_buffer,
358 358 nb_word_by_buffer => nb_word_by_buffer,
359 359 nb_snapshot_param => nb_snapshot_param,
360 360 enable_f0 => enable_f0,
361 361 enable_f1 => enable_f1,
362 362 enable_f2 => enable_f2,
363 363 enable_f3 => enable_f3,
364 364 burst_f0 => burst_f0,
365 365 burst_f1 => burst_f1,
366 366 burst_f2 => burst_f2,
367 367 run => run,
368 368 addr_data_f0 => addr_data_f0,
369 369 addr_data_f1 => addr_data_f1,
370 370 addr_data_f2 => addr_data_f2,
371 371 addr_data_f3 => addr_data_f3,
372 372 start_date => start_date,
373 373 ---------------------------------------------------------------------------
374 374 debug_reg0 => debug_reg0,
375 375 debug_reg1 => debug_reg1,
376 376 debug_reg2 => debug_reg2,
377 377 debug_reg3 => debug_reg3,
378 378 debug_reg4 => debug_reg4,
379 379 debug_reg5 => debug_reg5,
380 380 debug_reg6 => debug_reg6,
381 381 debug_reg7 => debug_reg7);
382 382
383 383 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
384 384 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
385 385 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
386 386 -----------------------------------------------------------------------------
387 387 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
388 388 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
389 389 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
390 390 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
391 391
392 392
393 393 -----------------------------------------------------------------------------
394 394 lpp_waveform_1 : lpp_waveform
395 395 GENERIC MAP (
396 396 tech => inferred,
397 397 data_size => 6*16,
398 398 nb_data_by_buffer_size => nb_data_by_buffer_size,
399 399 nb_word_by_buffer_size => nb_word_by_buffer_size,
400 400 nb_snapshot_param_size => nb_snapshot_param_size,
401 401 delta_vector_size => delta_vector_size,
402 402 delta_vector_size_f0_2 => delta_vector_size_f0_2
403 403 )
404 404 PORT MAP (
405 405 clk => clk,
406 406 rstn => rstn,
407 407
408 408 reg_run => run,
409 409 reg_start_date => start_date,
410 410 reg_delta_snapshot => delta_snapshot,
411 411 reg_delta_f0 => delta_f0,
412 412 reg_delta_f0_2 => delta_f0_2,
413 413 reg_delta_f1 => delta_f1,
414 414 reg_delta_f2 => delta_f2,
415 415
416 416 enable_f0 => enable_f0,
417 417 enable_f1 => enable_f1,
418 418 enable_f2 => enable_f2,
419 419 enable_f3 => enable_f3,
420 420 burst_f0 => burst_f0,
421 421 burst_f1 => burst_f1,
422 422 burst_f2 => burst_f2,
423 423
424 424 nb_data_by_buffer => nb_data_by_buffer,
425 425 nb_word_by_buffer => nb_word_by_buffer,
426 426 nb_snapshot_param => nb_snapshot_param,
427 427 status_full => status_full,
428 428 status_full_ack => status_full_ack,
429 429 status_full_err => status_full_err,
430 430 status_new_err => status_new_err,
431 431
432 432 coarse_time => coarse_time,
433 433 fine_time => fine_time,
434 434
435 435 --f0
436 436 addr_data_f0 => addr_data_f0,
437 437 data_f0_in_valid => sample_f0_val,
438 438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
439 439 --f1
440 440 addr_data_f1 => addr_data_f1,
441 441 data_f1_in_valid => sample_f1_val,
442 442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
443 443 --f2
444 444 addr_data_f2 => addr_data_f2,
445 445 data_f2_in_valid => sample_f2_val,
446 446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
447 447 --f3
448 448 addr_data_f3 => addr_data_f3,
449 449 data_f3_in_valid => sample_f3_val,
450 450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
451 451 -- OUTPUT -- DMA interface
452 452 --f0
453 453 data_f0_addr_out => data_f0_addr_out_s,
454 454 data_f0_data_out => data_f0_data_out,
455 455 data_f0_data_out_valid => data_f0_data_out_valid_s,
456 456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
457 457 data_f0_data_out_ren => data_f0_data_out_ren,
458 458 --f1
459 459 data_f1_addr_out => data_f1_addr_out_s,
460 460 data_f1_data_out => data_f1_data_out,
461 461 data_f1_data_out_valid => data_f1_data_out_valid_s,
462 462 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
463 463 data_f1_data_out_ren => data_f1_data_out_ren,
464 464 --f2
465 465 data_f2_addr_out => data_f2_addr_out_s,
466 466 data_f2_data_out => data_f2_data_out,
467 467 data_f2_data_out_valid => data_f2_data_out_valid_s,
468 468 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
469 469 data_f2_data_out_ren => data_f2_data_out_ren,
470 470 --f3
471 471 data_f3_addr_out => data_f3_addr_out_s,
472 472 data_f3_data_out => data_f3_data_out,
473 473 data_f3_data_out_valid => data_f3_data_out_valid_s,
474 474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
475 475 data_f3_data_out_ren => data_f3_data_out_ren,
476 476
477 477 -- debug SNAPSHOT_OUT
478 478 debug_f0_data => debug_f0_data,
479 479 debug_f0_data_valid => debug_f0_data_valid ,
480 480 debug_f1_data => debug_f1_data ,
481 481 debug_f1_data_valid => debug_f1_data_valid,
482 482 debug_f2_data => debug_f2_data ,
483 483 debug_f2_data_valid => debug_f2_data_valid ,
484 484 debug_f3_data => debug_f3_data ,
485 485 debug_f3_data_valid => debug_f3_data_valid,
486 486
487 487 -- debug FIFO_IN
488 488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
496 496
497 497 );
498 498
499 499
500 500 -----------------------------------------------------------------------------
501 501 -- DEBUG -- WFP OUT
502 502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 503 debug_f0_data_fifo_out <= data_f0_data_out;
504 504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 505 debug_f1_data_fifo_out <= data_f1_data_out;
506 506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 507 debug_f2_data_fifo_out <= data_f2_data_out;
508 508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 509 debug_f3_data_fifo_out <= data_f3_data_out;
510 510 -----------------------------------------------------------------------------
511 511
512 512
513 513 -----------------------------------------------------------------------------
514 514 -- TEMP
515 515 -----------------------------------------------------------------------------
516 516
517 517 PROCESS (clk, rstn)
518 518 BEGIN -- PROCESS
519 519 IF rstn = '0' THEN -- asynchronous reset (active low)
520 520 data_f0_data_out_valid <= '0';
521 521 data_f0_data_out_valid_burst <= '0';
522 522 data_f1_data_out_valid <= '0';
523 523 data_f1_data_out_valid_burst <= '0';
524 524 data_f2_data_out_valid <= '0';
525 525 data_f2_data_out_valid_burst <= '0';
526 526 data_f3_data_out_valid <= '0';
527 527 data_f3_data_out_valid_burst <= '0';
528 528 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
529 529 data_f0_data_out_valid <= data_f0_data_out_valid_s;
530 530 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
531 531 data_f1_data_out_valid <= data_f1_data_out_valid_s;
532 532 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
533 533 data_f2_data_out_valid <= data_f2_data_out_valid_s;
534 534 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
535 535 data_f3_data_out_valid <= data_f3_data_out_valid_s;
536 536 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
537 537 END IF;
538 538 END PROCESS;
539 539
540 540 data_f0_addr_out <= data_f0_addr_out_s;
541 541 data_f1_addr_out <= data_f1_addr_out_s;
542 542 data_f2_addr_out <= data_f2_addr_out_s;
543 543 data_f3_addr_out <= data_f3_addr_out_s;
544 544
545 545 -----------------------------------------------------------------------------
546 546 -- RoundRobin Selection For DMA
547 547 -----------------------------------------------------------------------------
548 548
549 549 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
550 550 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
551 551 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
552 552 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
553 553
554 554 RR_Arbiter_4_1 : RR_Arbiter_4
555 555 PORT MAP (
556 556 clk => clk,
557 557 rstn => rstn,
558 558 in_valid => dma_rr_valid,
559 559 out_grant => dma_rr_grant);
560 560
561 561
562 562 -----------------------------------------------------------------------------
563 563 -- in : dma_rr_grant
564 564 -- send
565 565 -- out : dma_sel
566 566 -- dma_valid_burst
567 567 -- dma_sel_valid
568 568 -----------------------------------------------------------------------------
569 569 PROCESS (clk, rstn)
570 570 BEGIN -- PROCESS
571 571 IF rstn = '0' THEN -- asynchronous reset (active low)
572 572 dma_sel <= (OTHERS => '0');
573 573 dma_send <= '0';
574 574 dma_valid_burst <= '0';
575 575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 576 IF run = '1' THEN
577 577 -- IF dma_sel = "0000" OR dma_send = '1' THEN
578 578 IF dma_sel = "0000" OR dma_done = '1' THEN
579 579 dma_sel <= dma_rr_grant;
580 580 IF dma_rr_grant(0) = '1' THEN
581 581 dma_send <= '1';
582 582 dma_valid_burst <= data_f0_data_out_valid_burst;
583 583 dma_sel_valid <= data_f0_data_out_valid;
584 584 ELSIF dma_rr_grant(1) = '1' THEN
585 585 dma_send <= '1';
586 586 dma_valid_burst <= data_f1_data_out_valid_burst;
587 587 dma_sel_valid <= data_f1_data_out_valid;
588 588 ELSIF dma_rr_grant(2) = '1' THEN
589 589 dma_send <= '1';
590 590 dma_valid_burst <= data_f2_data_out_valid_burst;
591 591 dma_sel_valid <= data_f2_data_out_valid;
592 592 ELSIF dma_rr_grant(3) = '1' THEN
593 593 dma_send <= '1';
594 594 dma_valid_burst <= data_f3_data_out_valid_burst;
595 595 dma_sel_valid <= data_f3_data_out_valid;
596 596 END IF;
597 597 ELSE
598 598 dma_sel <= dma_sel;
599 599 dma_send <= '0';
600 600 END IF;
601 601 ELSE
602 602 dma_sel <= (OTHERS => '0');
603 603 dma_send <= '0';
604 604 dma_valid_burst <= '0';
605 605 END IF;
606 606 END IF;
607 607 END PROCESS;
608 608
609 609
610 610 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
611 611 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
612 612 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
613 613 data_f3_addr_out;
614 614
615 615 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
616 616 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
617 617 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
618 618 data_f3_data_out;
619 619
620 620 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
621 621 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
622 622 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
623 623 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
624 624
625 625 dma_data_2 <= dma_data;
626 626
627 627
628 628
629 629
630 630
631 631 -----------------------------------------------------------------------------
632 632 -- DEBUG -- DMA IN
633 633 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
634 634 debug_f0_data_dma_in <= dma_data;
635 635 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
636 636 debug_f1_data_dma_in <= dma_data;
637 637 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
638 638 debug_f2_data_dma_in <= dma_data;
639 639 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
640 640 debug_f3_data_dma_in <= dma_data;
641 641 -----------------------------------------------------------------------------
642 642
643 643 -----------------------------------------------------------------------------
644 644 -- DMA
645 645 -----------------------------------------------------------------------------
646 646 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
647 647 GENERIC MAP (
648 648 tech => inferred,
649 649 hindex => hindex)
650 650 PORT MAP (
651 651 HCLK => clk,
652 652 HRESETn => rstn,
653 653 run => run,
654 654 AHB_Master_In => ahbi,
655 655 AHB_Master_Out => ahbo,
656 656
657 657 send => dma_send,
658 658 valid_burst => dma_valid_burst,
659 659 done => dma_done,
660 660 ren => dma_ren,
661 661 address => dma_address,
662 662 data => dma_data_2);
663 663
664 664 -----------------------------------------------------------------------------
665 665 -- Matrix Spectral - TODO
666 666 -----------------------------------------------------------------------------
667 667 -----------------------------------------------------------------------------
668 668 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
669 669 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
670 670 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
671 671 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
672 672 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
673 673 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
674 674
675 675 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
676 676 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
677 677 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
678 678 -------------------------------------------------------------------------------
679 679 --lpp_lfr_ms_1: lpp_lfr_ms
680 680 -- GENERIC MAP (
681 681 -- hindex => hindex_ms)
682 682 -- PORT MAP (
683 683 -- clk => clk,
684 684 -- rstn => rstn,
685 685 -- sample_f0_wen => sample_f0_wen,
686 686 -- sample_f0_wdata => sample_f0_wdata,
687 687 -- sample_f1_wen => sample_f1_wen,
688 688 -- sample_f1_wdata => sample_f1_wdata,
689 689 -- sample_f3_wen => sample_f3_wen,
690 690 -- sample_f3_wdata => sample_f3_wdata,
691 691 -- AHB_Master_In => ahbi_ms,
692 692 -- AHB_Master_Out => ahbo_ms,
693 693
694 694 -- ready_matrix_f0_0 => ready_matrix_f0_0,
695 695 -- ready_matrix_f0_1 => ready_matrix_f0_1,
696 696 -- ready_matrix_f1 => ready_matrix_f1,
697 697 -- ready_matrix_f2 => ready_matrix_f2,
698 698 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
699 699 -- error_bad_component_error => error_bad_component_error,
700 700 -- debug_reg => debug_reg,
701 701 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
702 702 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
703 703 -- status_ready_matrix_f1 => status_ready_matrix_f1,
704 704 -- status_ready_matrix_f2 => status_ready_matrix_f2,
705 705 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
706 706 -- status_error_bad_component_error => status_error_bad_component_error,
707 707 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
708 708 -- config_active_interruption_onError => config_active_interruption_onError,
709 709 -- addr_matrix_f0_0 => addr_matrix_f0_0,
710 710 -- addr_matrix_f0_1 => addr_matrix_f0_1,
711 711 -- addr_matrix_f1 => addr_matrix_f1,
712 712 -- addr_matrix_f2 => addr_matrix_f2);
713 713
714 714 END beh;
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@@ -1,493 +1,493
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_amba.ALL;
32 32 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36 36
37 37 ENTITY lpp_lfr_apbreg IS
38 38 GENERIC (
39 39 nb_data_by_buffer_size : INTEGER := 11;
40 40 nb_word_by_buffer_size : INTEGER := 11;
41 41 nb_snapshot_param_size : INTEGER := 11;
42 42 delta_vector_size : INTEGER := 20;
43 43 delta_vector_size_f0_2 : INTEGER := 3;
44 44
45 45 pindex : INTEGER := 4;
46 46 paddr : INTEGER := 4;
47 47 pmask : INTEGER := 16#fff#;
48 48 pirq_ms : INTEGER := 0;
49 49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
51 51 PORT (
52 52 -- AMBA AHB system signals
53 53 HCLK : IN STD_ULOGIC;
54 54 HRESETn : IN STD_ULOGIC;
55 55
56 56 -- AMBA APB Slave Interface
57 57 apbi : IN apb_slv_in_type;
58 58 apbo : OUT apb_slv_out_type;
59 59
60 60 ---------------------------------------------------------------------------
61 61 -- Spectral Matrix Reg
62 62 -- IN
63 63 ready_matrix_f0_0 : IN STD_LOGIC;
64 64 ready_matrix_f0_1 : IN STD_LOGIC;
65 65 ready_matrix_f1 : IN STD_LOGIC;
66 66 ready_matrix_f2 : IN STD_LOGIC;
67 67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 68 error_bad_component_error : IN STD_LOGIC;
69 69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70
71 71 -- OUT
72 72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 77 status_error_bad_component_error : OUT STD_LOGIC;
78 78
79 79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 80 config_active_interruption_onError : OUT STD_LOGIC;
81 81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 ---------------------------------------------------------------------------
86 86 ---------------------------------------------------------------------------
87 87 -- WaveForm picker Reg
88 88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 92
93 93 -- OUT
94 94 data_shaping_BW : OUT STD_LOGIC;
95 95 data_shaping_SP0 : OUT STD_LOGIC;
96 96 data_shaping_SP1 : OUT STD_LOGIC;
97 97 data_shaping_R0 : OUT STD_LOGIC;
98 98 data_shaping_R1 : OUT STD_LOGIC;
99 99
100 100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108 108
109 109 enable_f0 : OUT STD_LOGIC;
110 110 enable_f1 : OUT STD_LOGIC;
111 111 enable_f2 : OUT STD_LOGIC;
112 112 enable_f3 : OUT STD_LOGIC;
113 113
114 114 burst_f0 : OUT STD_LOGIC;
115 115 burst_f1 : OUT STD_LOGIC;
116 116 burst_f2 : OUT STD_LOGIC;
117 117
118 118 run : OUT STD_LOGIC;
119 119
120 120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 125 ---------------------------------------------------------------------------
126 126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
134 134
135 135 ---------------------------------------------------------------------------
136 136 );
137 137
138 138 END lpp_lfr_apbreg;
139 139
140 140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
141 141
142 142 CONSTANT REVISION : INTEGER := 1;
143 143
144 144 CONSTANT pconfig : apb_config_type := (
145 145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
146 146 1 => apb_iobar(paddr, pmask));
147 147
148 148 TYPE lpp_SpectralMatrix_regs IS RECORD
149 149 config_active_interruption_onNewMatrix : STD_LOGIC;
150 150 config_active_interruption_onError : STD_LOGIC;
151 151 status_ready_matrix_f0_0 : STD_LOGIC;
152 152 status_ready_matrix_f0_1 : STD_LOGIC;
153 153 status_ready_matrix_f1 : STD_LOGIC;
154 154 status_ready_matrix_f2 : STD_LOGIC;
155 155 status_error_anticipating_empty_fifo : STD_LOGIC;
156 156 status_error_bad_component_error : STD_LOGIC;
157 157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 161 END RECORD;
162 162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
163 163
164 164 TYPE lpp_WaveformPicker_regs IS RECORD
165 165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 168 data_shaping_BW : STD_LOGIC;
169 169 data_shaping_SP0 : STD_LOGIC;
170 170 data_shaping_SP1 : STD_LOGIC;
171 171 data_shaping_R0 : STD_LOGIC;
172 172 data_shaping_R1 : STD_LOGIC;
173 173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
175 175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
176 176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
178 178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
179 179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
180 180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
181 181 enable_f0 : STD_LOGIC;
182 182 enable_f1 : STD_LOGIC;
183 183 enable_f2 : STD_LOGIC;
184 184 enable_f3 : STD_LOGIC;
185 185 burst_f0 : STD_LOGIC;
186 186 burst_f1 : STD_LOGIC;
187 187 burst_f2 : STD_LOGIC;
188 188 run : STD_LOGIC;
189 189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
194 194 END RECORD;
195 195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
196 196
197 197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 198
199 199 -----------------------------------------------------------------------------
200 200 -- IRQ
201 201 -----------------------------------------------------------------------------
202 202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
203 203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
207 207 SIGNAL ored_irq_wfp : STD_LOGIC;
208 208
209 209 BEGIN -- beh
210 210
211 211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
212 212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
213 213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
214 214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
215 215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
216 216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
217 217
218 218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
219 219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
220 220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
221 221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
222 222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
223 223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
224 224
225 225
226 226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
227 227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
228 228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
229 229 data_shaping_R0 <= reg_wp.data_shaping_R0;
230 230 data_shaping_R1 <= reg_wp.data_shaping_R1;
231 231
232 232 delta_snapshot <= reg_wp.delta_snapshot;
233 233 delta_f0 <= reg_wp.delta_f0;
234 234 delta_f0_2 <= reg_wp.delta_f0_2;
235 235 delta_f1 <= reg_wp.delta_f1;
236 236 delta_f2 <= reg_wp.delta_f2;
237 237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
238 238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
239 239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
240 240
241 241 enable_f0 <= reg_wp.enable_f0;
242 242 enable_f1 <= reg_wp.enable_f1;
243 243 enable_f2 <= reg_wp.enable_f2;
244 244 enable_f3 <= reg_wp.enable_f3;
245 245
246 246 burst_f0 <= reg_wp.burst_f0;
247 247 burst_f1 <= reg_wp.burst_f1;
248 248 burst_f2 <= reg_wp.burst_f2;
249 249
250 250 run <= reg_wp.run;
251 251
252 252 addr_data_f0 <= reg_wp.addr_data_f0;
253 253 addr_data_f1 <= reg_wp.addr_data_f1;
254 254 addr_data_f2 <= reg_wp.addr_data_f2;
255 255 addr_data_f3 <= reg_wp.addr_data_f3;
256 256
257 257 start_date <= reg_wp.start_date;
258 258
259 259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
260 260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
261 261 BEGIN -- PROCESS lpp_dma_top
262 262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
263 263 reg_sp.config_active_interruption_onNewMatrix <= '0';
264 264 reg_sp.config_active_interruption_onError <= '0';
265 265 reg_sp.status_ready_matrix_f0_0 <= '0';
266 266 reg_sp.status_ready_matrix_f0_1 <= '0';
267 267 reg_sp.status_ready_matrix_f1 <= '0';
268 268 reg_sp.status_ready_matrix_f2 <= '0';
269 269 reg_sp.status_error_anticipating_empty_fifo <= '0';
270 270 reg_sp.status_error_bad_component_error <= '0';
271 271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
272 272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
273 273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
274 274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
275 275 prdata <= (OTHERS => '0');
276 276
277 277 apbo.pirq <= (OTHERS => '0');
278 278
279 279 status_full_ack <= (OTHERS => '0');
280 280
281 281 reg_wp.data_shaping_BW <= '0';
282 282 reg_wp.data_shaping_SP0 <= '0';
283 283 reg_wp.data_shaping_SP1 <= '0';
284 284 reg_wp.data_shaping_R0 <= '0';
285 285 reg_wp.data_shaping_R1 <= '0';
286 286 reg_wp.enable_f0 <= '0';
287 287 reg_wp.enable_f1 <= '0';
288 288 reg_wp.enable_f2 <= '0';
289 289 reg_wp.enable_f3 <= '0';
290 290 reg_wp.burst_f0 <= '0';
291 291 reg_wp.burst_f1 <= '0';
292 292 reg_wp.burst_f2 <= '0';
293 293 reg_wp.run <= '0';
294 294 reg_wp.addr_data_f0 <= (OTHERS => '0');
295 295 reg_wp.addr_data_f1 <= (OTHERS => '0');
296 296 reg_wp.addr_data_f2 <= (OTHERS => '0');
297 297 reg_wp.addr_data_f3 <= (OTHERS => '0');
298 298 reg_wp.status_full <= (OTHERS => '0');
299 299 reg_wp.status_full_err <= (OTHERS => '0');
300 300 reg_wp.status_new_err <= (OTHERS => '0');
301 301 reg_wp.delta_snapshot <= (OTHERS => '0');
302 302 reg_wp.delta_f0 <= (OTHERS => '0');
303 303 reg_wp.delta_f0_2 <= (OTHERS => '0');
304 304 reg_wp.delta_f1 <= (OTHERS => '0');
305 305 reg_wp.delta_f2 <= (OTHERS => '0');
306 306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
307 307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
308 308 reg_wp.start_date <= (OTHERS => '0');
309 309
310 310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
311 311 status_full_ack <= (OTHERS => '0');
312 312
313 313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
314 314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
315 315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
316 316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
317 317
318 318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
319 319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
320 320 all_status: FOR I IN 3 DOWNTO 0 LOOP
321 321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
322 322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
323 323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
324 324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
325 325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
326 326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
327 327 END LOOP all_status;
328 328
329 329 paddr := "000000";
330 330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
331 331 prdata <= (OTHERS => '0');
332 332 IF apbi.psel(pindex) = '1' THEN
333 333 -- APB DMA READ --
334 334 CASE paddr(7 DOWNTO 2) IS
335 335 --
336 336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
337 337 prdata(1) <= reg_sp.config_active_interruption_onError;
338 338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
339 339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
340 340 prdata(2) <= reg_sp.status_ready_matrix_f1;
341 341 prdata(3) <= reg_sp.status_ready_matrix_f2;
342 342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
343 343 prdata(5) <= reg_sp.status_error_bad_component_error;
344 344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
345 345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
346 346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
347 347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
348 348 WHEN "000110" => prdata <= debug_reg;
349 349 --
350 350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
351 351 prdata(1) <= reg_wp.data_shaping_SP0;
352 352 prdata(2) <= reg_wp.data_shaping_SP1;
353 353 prdata(3) <= reg_wp.data_shaping_R0;
354 354 prdata(4) <= reg_wp.data_shaping_R1;
355 355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
356 356 prdata(1) <= reg_wp.enable_f1;
357 357 prdata(2) <= reg_wp.enable_f2;
358 358 prdata(3) <= reg_wp.enable_f3;
359 359 prdata(4) <= reg_wp.burst_f0;
360 360 prdata(5) <= reg_wp.burst_f1;
361 361 prdata(6) <= reg_wp.burst_f2;
362 362 prdata(7) <= reg_wp.run;
363 363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
364 364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
365 365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
366 366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
367 367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
368 368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
369 369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
370 370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
371 371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
372 372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
373 373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
374 374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
375 375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
376 376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
377 377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
378 378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
379 379 ----------------------------------------------------
380 380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 388 ----------------------------------------------------
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
389 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
390 390 WHEN OTHERS => NULL;
391 391 END CASE;
392 392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
393 393 -- APB DMA WRITE --
394 394 CASE paddr(7 DOWNTO 2) IS
395 395 --
396 396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
397 397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
398 398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
399 399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
400 400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
401 401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
402 402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
403 403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
404 404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
405 405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
406 406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
407 407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
408 408 --
409 409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
410 410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
411 411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
412 412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
413 413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
414 414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
415 415 reg_wp.enable_f1 <= apbi.pwdata(1);
416 416 reg_wp.enable_f2 <= apbi.pwdata(2);
417 417 reg_wp.enable_f3 <= apbi.pwdata(3);
418 418 reg_wp.burst_f0 <= apbi.pwdata(4);
419 419 reg_wp.burst_f1 <= apbi.pwdata(5);
420 420 reg_wp.burst_f2 <= apbi.pwdata(6);
421 421 reg_wp.run <= apbi.pwdata(7);
422 422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
423 423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
424 424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
425 425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
426 426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
427 427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
428 428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
429 429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
430 430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
431 431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
432 432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
433 433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
436 436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
438 438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
439 439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
440 440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
441 441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
442 442 --
443 443 WHEN OTHERS => NULL;
444 444 END CASE;
445 445 END IF;
446 446 END IF;
447 447
448 448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
449 449 ready_matrix_f0_1 OR
450 450 ready_matrix_f1 OR
451 451 ready_matrix_f2)
452 452 )
453 453 OR
454 454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
455 455 error_bad_component_error)
456 456 ));
457 457
458 458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
459 459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
460 460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
461 461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
462 462 -- );
463 463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
464 464
465 465 END IF;
466 466 END PROCESS lpp_lfr_apbreg;
467 467
468 468 apbo.pindex <= pindex;
469 469 apbo.pconfig <= pconfig;
470 470 apbo.prdata <= prdata;
471 471
472 472 -----------------------------------------------------------------------------
473 473 -- IRQ
474 474 -----------------------------------------------------------------------------
475 475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
476 476
477 477 PROCESS (HCLK, HRESETn)
478 478 BEGIN -- PROCESS
479 479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
480 480 irq_wfp_reg <= (OTHERS => '0');
481 481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
482 482 irq_wfp_reg <= irq_wfp_reg_s;
483 483 END IF;
484 484 END PROCESS;
485 485
486 486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
487 487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
488 488 END GENERATE all_irq_wfp;
489 489
490 490 irq_wfp_ZERO <= (OTHERS => '0');
491 491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
492 492
493 493 END beh;
Show file before | Show file after | Hide comments
@@ -1,252 +1,252
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_lfr_pkg IS
16 16
17 17 COMPONENT lpp_lfr_ms
18 18 GENERIC (
19 19 hindex : INTEGER);
20 20 PORT (
21 21 clk : IN STD_LOGIC;
22 22 rstn : IN STD_LOGIC;
23 23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 29 AHB_Master_In : IN AHB_Mst_In_Type;
30 30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 33 ready_matrix_f1 : OUT STD_LOGIC;
34 34 ready_matrix_f2 : OUT STD_LOGIC;
35 35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 36 error_bad_component_error : OUT STD_LOGIC;
37 37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 40 status_ready_matrix_f1 : IN STD_LOGIC;
41 41 status_ready_matrix_f2 : IN STD_LOGIC;
42 42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 43 status_error_bad_component_error : IN STD_LOGIC;
44 44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 45 config_active_interruption_onError : IN STD_LOGIC;
46 46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 50 END COMPONENT;
51 51
52 52 COMPONENT lpp_lfr_filter
53 53 GENERIC (
54 54 Mem_use : INTEGER);
55 55 PORT (
56 56 sample : IN Samples(7 DOWNTO 0);
57 57 sample_val : IN STD_LOGIC;
58 58 clk : IN STD_LOGIC;
59 59 rstn : IN STD_LOGIC;
60 60 data_shaping_SP0 : IN STD_LOGIC;
61 61 data_shaping_SP1 : IN STD_LOGIC;
62 62 data_shaping_R0 : IN STD_LOGIC;
63 63 data_shaping_R1 : IN STD_LOGIC;
64 64 sample_f0_val : OUT STD_LOGIC;
65 65 sample_f1_val : OUT STD_LOGIC;
66 66 sample_f2_val : OUT STD_LOGIC;
67 67 sample_f3_val : OUT STD_LOGIC;
68 68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 72 END COMPONENT;
73 73
74 74 COMPONENT lpp_lfr
75 75 GENERIC (
76 76 Mem_use : INTEGER;
77 77 nb_data_by_buffer_size : INTEGER;
78 78 nb_word_by_buffer_size : INTEGER;
79 79 nb_snapshot_param_size : INTEGER;
80 80 delta_vector_size : INTEGER;
81 81 delta_vector_size_f0_2 : INTEGER;
82 82 pindex : INTEGER;
83 83 paddr : INTEGER;
84 84 pmask : INTEGER;
85 85 pirq_ms : INTEGER;
86 86 pirq_wfp : INTEGER;
87 87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
88 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
89 89 );
90 90 PORT (
91 91 clk : IN STD_LOGIC;
92 92 rstn : IN STD_LOGIC;
93 93 sample_B : IN Samples14v(2 DOWNTO 0);
94 94 sample_E : IN Samples14v(4 DOWNTO 0);
95 95 sample_val : IN STD_LOGIC;
96 96 apbi : IN apb_slv_in_type;
97 97 apbo : OUT apb_slv_out_type;
98 98 ahbi : IN AHB_Mst_In_Type;
99 99 ahbo : OUT AHB_Mst_Out_Type;
100 100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 102 data_shaping_BW : OUT STD_LOGIC;
103 103
104 104 --debug
105 105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 106 debug_f0_data_valid : OUT STD_LOGIC;
107 107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 108 debug_f1_data_valid : OUT STD_LOGIC;
109 109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 110 debug_f2_data_valid : OUT STD_LOGIC;
111 111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 112 debug_f3_data_valid : OUT STD_LOGIC;
113 113
114 114 -- debug FIFO_IN
115 115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123 123
124 124 --debug FIFO OUT
125 125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133 133
134 134 --debug DMA IN
135 135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 143 );
144 144 END COMPONENT;
145 145
146 146 COMPONENT lpp_lfr_apbreg
147 147 GENERIC (
148 148 nb_data_by_buffer_size : INTEGER;
149 149 nb_word_by_buffer_size : INTEGER;
150 150 nb_snapshot_param_size : INTEGER;
151 151 delta_vector_size : INTEGER;
152 152 delta_vector_size_f0_2 : INTEGER;
153 153 pindex : INTEGER;
154 154 paddr : INTEGER;
155 155 pmask : INTEGER;
156 156 pirq_ms : INTEGER;
157 157 pirq_wfp : INTEGER;
158 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
158 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
159 159 PORT (
160 160 HCLK : IN STD_ULOGIC;
161 161 HRESETn : IN STD_ULOGIC;
162 162 apbi : IN apb_slv_in_type;
163 163 apbo : OUT apb_slv_out_type;
164 164 ready_matrix_f0_0 : IN STD_LOGIC;
165 165 ready_matrix_f0_1 : IN STD_LOGIC;
166 166 ready_matrix_f1 : IN STD_LOGIC;
167 167 ready_matrix_f2 : IN STD_LOGIC;
168 168 error_anticipating_empty_fifo : IN STD_LOGIC;
169 169 error_bad_component_error : IN STD_LOGIC;
170 170 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 171 status_ready_matrix_f0_0 : OUT STD_LOGIC;
172 172 status_ready_matrix_f0_1 : OUT STD_LOGIC;
173 173 status_ready_matrix_f1 : OUT STD_LOGIC;
174 174 status_ready_matrix_f2 : OUT STD_LOGIC;
175 175 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
176 176 status_error_bad_component_error : OUT STD_LOGIC;
177 177 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
178 178 config_active_interruption_onError : OUT STD_LOGIC;
179 179 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 181 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
182 182 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
184 184 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
185 185 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
186 186 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
187 187 data_shaping_BW : OUT STD_LOGIC;
188 188 data_shaping_SP0 : OUT STD_LOGIC;
189 189 data_shaping_SP1 : OUT STD_LOGIC;
190 190 data_shaping_R0 : OUT STD_LOGIC;
191 191 data_shaping_R1 : OUT STD_LOGIC;
192 192 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 193 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
194 194 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
195 195 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 196 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
197 197 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
198 198 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
199 199 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
200 200 enable_f0 : OUT STD_LOGIC;
201 201 enable_f1 : OUT STD_LOGIC;
202 202 enable_f2 : OUT STD_LOGIC;
203 203 enable_f3 : OUT STD_LOGIC;
204 204 burst_f0 : OUT STD_LOGIC;
205 205 burst_f1 : OUT STD_LOGIC;
206 206 burst_f2 : OUT STD_LOGIC;
207 207 run : OUT STD_LOGIC;
208 208 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
209 209 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
210 210 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
211 211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
212 212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
213 213 ---------------------------------------------------------------------------
214 214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
222 222 END COMPONENT;
223 223
224 224 COMPONENT lpp_top_ms
225 225 GENERIC (
226 226 Mem_use : INTEGER;
227 227 nb_burst_available_size : INTEGER;
228 228 nb_snapshot_param_size : INTEGER;
229 229 delta_snapshot_size : INTEGER;
230 230 delta_f2_f0_size : INTEGER;
231 231 delta_f2_f1_size : INTEGER;
232 232 pindex : INTEGER;
233 233 paddr : INTEGER;
234 234 pmask : INTEGER;
235 235 pirq_ms : INTEGER;
236 236 pirq_wfp : INTEGER;
237 237 hindex_wfp : INTEGER;
238 238 hindex_ms : INTEGER);
239 239 PORT (
240 240 clk : IN STD_LOGIC;
241 241 rstn : IN STD_LOGIC;
242 242 sample_B : IN Samples14v(2 DOWNTO 0);
243 243 sample_E : IN Samples14v(4 DOWNTO 0);
244 244 sample_val : IN STD_LOGIC;
245 245 apbi : IN apb_slv_in_type;
246 246 apbo : OUT apb_slv_out_type;
247 247 ahbi_ms : IN AHB_Mst_In_Type;
248 248 ahbo_ms : OUT AHB_Mst_Out_Type;
249 249 data_shaping_BW : OUT STD_LOGIC);
250 250 END COMPONENT;
251 251
252 252 END lpp_lfr_pkg;
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