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Removed reference to ssram_plugin2.
jeandet@PC-DE-JEANDET.lpp.polytechnique.fr -
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1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 library ieee;
22 22 use ieee.std_logic_1164.all;
23 23 library grlib;
24 24 use grlib.amba.all;
25 25 use grlib.stdlib.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library gaisler;
29 29 use gaisler.memctrl.all;
30 30 use gaisler.leon3.all;
31 31 use gaisler.uart.all;
32 32 use gaisler.misc.all;
33 33 library esa;
34 34 use esa.memoryctrl.all;
35 35 use work.config.all;
36 36 library lpp;
37 37 use lpp.lpp_amba.all;
38 38 use lpp.lpp_memory.all;
39 39 --use lpp.lpp_uart.all;
40 40 --use lpp.lpp_matrix.all;
41 41 --use lpp.lpp_usb.all;
42 42
43 43 entity leon3mp is
44 44 generic (
45 45 fabtech : integer := CFG_FABTECH;
46 46 memtech : integer := CFG_MEMTECH;
47 47 padtech : integer := CFG_PADTECH;
48 48 clktech : integer := CFG_CLKTECH;
49 49 disas : integer := CFG_DISAS; -- Enable disassembly to console
50 50 dbguart : integer := CFG_DUART; -- Print UART on console
51 51 pclow : integer := CFG_PCLOW
52 52 );
53 53 port (
54 54 clk50MHz : in std_ulogic;
55 55 reset : in std_ulogic;
56 56 ramclk : out std_logic;
57 57
58 58 ahbrxd : in std_ulogic; -- DSU rx data
59 59 ahbtxd : out std_ulogic; -- DSU tx data
60 60 dsubre : in std_ulogic;
61 61 dsuact : out std_ulogic;
62 62 urxd1 : in std_ulogic; -- UART1 rx data
63 63 utxd1 : out std_ulogic; -- UART1 tx data
64 64 errorn : out std_ulogic;
65 65
66 66 address : out std_logic_vector(18 downto 0);
67 67 data : inout std_logic_vector(31 downto 0);
68 68
69 69 nBWa : out std_logic;
70 70 nBWb : out std_logic;
71 71 nBWc : out std_logic;
72 72 nBWd : out std_logic;
73 73 nBWE : out std_logic;
74 74 nADSC : out std_logic;
75 75 nADSP : out std_logic;
76 76 nADV : out std_logic;
77 77 nGW : out std_logic;
78 78 nCE1 : out std_logic;
79 79 CE2 : out std_logic;
80 80 nCE3 : out std_logic;
81 81 nOE : out std_logic;
82 82 MODE : out std_logic;
83 83 SSRAM_CLK : out std_logic;
84 84 ZZ : out std_logic;
85 85 led : out std_logic_vector(1 downto 0)
86 86 );
87 87 end;
88 88
89 89 architecture Behavioral of leon3mp is
90 90
91 91 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
92 92 CFG_GRETH+CFG_AHB_JTAG;
93 93 constant maxahbm : integer := maxahbmsp;
94 94
95 95 --Clk & Rst gοΏ½nοΏ½
96 96 signal vcc : std_logic_vector(4 downto 0);
97 97 signal gnd : std_logic_vector(4 downto 0);
98 98 signal resetnl : std_ulogic;
99 99 signal clk2x : std_ulogic;
100 100 signal lclk : std_ulogic;
101 101 signal lclk2x : std_ulogic;
102 102 signal clkm : std_ulogic;
103 103 signal rstn : std_ulogic;
104 104 signal rstraw : std_ulogic;
105 105 signal pciclk : std_ulogic;
106 106 signal sdclkl : std_ulogic;
107 107 signal cgi : clkgen_in_type;
108 108 signal cgo : clkgen_out_type;
109 109 --- AHB / APB
110 110 signal apbi : apb_slv_in_type;
111 111 signal apbo : apb_slv_out_vector := (others => apb_none);
112 112 signal ahbsi : ahb_slv_in_type;
113 113 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
114 114 signal ahbmi : ahb_mst_in_type;
115 115 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
116 116 --UART
117 117 signal ahbuarti : uart_in_type;
118 118 signal ahbuarto : uart_out_type;
119 119 signal apbuarti : uart_in_type;
120 120 signal apbuarto : uart_out_type;
121 121 --MEM CTRLR
122 122 signal memi : memory_in_type;
123 123 signal memo : memory_out_type;
124 124 signal wpo : wprot_out_type;
125 125 signal sdo : sdram_out_type;
126 126 --IRQ
127 127 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
128 128 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
129 129 --Timer
130 130 signal gpti : gptimer_in_type;
131 131 signal gpto : gptimer_out_type;
132 132 --GPIO
133 133 signal gpioi : gpio_in_type;
134 134 signal gpioo : gpio_out_type;
135 135 --DSU
136 136 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
137 137 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
138 138 signal dsui : dsu_in_type;
139 139 signal dsuo : dsu_out_type;
140 140 ----------------------------------------------------------------------
141 141 --- AJOUT TEST ------------------------Signaux----------------------
142 142 ----------------------------------------------------------------------
143 143 -- TEST USB
144 144 --signal USB_Read : std_logic;
145 145 --signal USB_Write : std_logic;
146 146
147 147 -- MATRICE SPECTRALE
148 148 --signal Matrix_Write : std_logic;
149 149 --signal Matrix_Read : std_logic_vector(1 downto 0);
150 150 --signal Matrix_Full : std_logic_vector(1 downto 0);
151 151 --signal Matrix_Empty : std_logic_vector(1 downto 0);
152 152 --signal Matrix_Data1 : std_logic_vector(15 downto 0);
153 153 --signal Matrix_Data2 : std_logic_vector(15 downto 0);
154 154 --signal Matrix_Result : std_logic_vector(31 downto 0);
155 155
156 156 ---------------------------------------------------------------------
157 157 constant IOAEN : integer := CFG_CAN;
158 158 constant boardfreq : integer := 50000;
159 159
160 160 begin
161 161
162 162 ----------------------------------------------------------------------
163 163 --- Reset and Clock generation -------------------------------------
164 164 ----------------------------------------------------------------------
165 165
166 166 vcc <= (others => '1'); gnd <= (others => '0');
167 167 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
168 168
169 169 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
170 170
171 171
172 172 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
173 173
174 174 clkgen0 : clkgen -- clock generator
175 175 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
176 176 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
177 177 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
178 178
179 179 ramclk <= clkm;
180 180 process(lclk2x)
181 181 begin
182 182 if lclk2x'event and lclk2x = '1' then
183 183 lclk <= not lclk;
184 184 end if;
185 185 end process;
186 186
187 187 ----------------------------------------------------------------------
188 188 --- LEON3 processor / DSU / IRQ ------------------------------------
189 189 ----------------------------------------------------------------------
190 190
191 191 l3 : if CFG_LEON3 = 1 generate
192 192 cpu : for i in 0 to CFG_NCPU-1 generate
193 193 u0 : leon3s -- LEON3 processor
194 194 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
195 195 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
196 196 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
197 197 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
198 198 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
199 199 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
200 200 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
201 201 irqi(i), irqo(i), dbgi(i), dbgo(i));
202 202 end generate;
203 203 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
204 204
205 205 dsugen : if CFG_DSU = 1 generate
206 206 dsu0 : dsu3 -- LEON3 Debug Support Unit
207 207 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
208 208 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
209 209 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
210 210 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
211 211 dsui.enable <= '1';
212 212 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
213 213 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
214 214 end generate;
215 215 end generate;
216 216
217 217 nodsu : if CFG_DSU = 0 generate
218 218 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
219 219 end generate;
220 220
221 221 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
222 222 irqctrl0 : irqmp -- interrupt controller
223 223 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
224 224 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
225 225 end generate;
226 226 irq3 : if CFG_IRQ3_ENABLE = 0 generate
227 227 x : for i in 0 to CFG_NCPU-1 generate
228 228 irqi(i).irl <= "0000";
229 229 end generate;
230 230 apbo(2) <= apb_none;
231 231 end generate;
232 232
233 233 ----------------------------------------------------------------------
234 234 --- Memory controllers ---------------------------------------------
235 235 ----------------------------------------------------------------------
236 236
237 237 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
238 238 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
239 239
240 240 memi.brdyn <= '1'; memi.bexcn <= '1';
241 241 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
242 242
243 243 bdr : for i in 0 to 3 generate
244 244 data_pad : iopadv generic map (tech => padtech, width => 8)
245 245 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
246 246 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
247 247 end generate;
248 248
249 249
250 250 addr_pad : outpadv generic map (width => 19, tech => padtech)
251 251 port map (address, memo.address(20 downto 2));
252 252
253 253
254 254 --SSRAM_0:entity ssram_plugin
255 255 --generic map (tech => padtech)
256 256 --port map
257 257 --(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
258 258
259 SSRAM_0:entity work.ssram_plugin2
259 SSRAM_0:entity ssram_plugin
260 260 generic map (tech => padtech)
261 261 port map
262 262 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
263 263
264 264 ----------------------------------------------------------------------
265 265 --- AHB CONTROLLER -------------------------------------------------
266 266 ----------------------------------------------------------------------
267 267
268 268 ahb0 : ahbctrl -- AHB arbiter/multiplexer
269 269 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
270 270 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
271 271 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
272 272 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
273 273
274 274 ----------------------------------------------------------------------
275 275 --- AHB UART -------------------------------------------------------
276 276 ----------------------------------------------------------------------
277 277 dcomgen : if CFG_AHB_UART = 1 generate
278 278 dcom0: ahbuart -- Debug UART
279 279 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
280 280 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
281 281 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
282 282 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
283 283 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
284 284 end generate;
285 285 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
286 286
287 287 ----------------------------------------------------------------------
288 288 --- APB Bridge -----------------------------------------------------
289 289 ----------------------------------------------------------------------
290 290
291 291 apb0 : apbctrl -- AHB/APB bridge
292 292 generic map (hindex => 1, haddr => CFG_APBADDR)
293 293 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
294 294
295 295 ----------------------------------------------------------------------
296 296 --- GPT Timer ------------------------------------------------------
297 297 ----------------------------------------------------------------------
298 298
299 299 gpt : if CFG_GPT_ENABLE /= 0 generate
300 300 timer0 : gptimer -- timer unit
301 301 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
302 302 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
303 303 nbits => CFG_GPT_TW)
304 304 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
305 305 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
306 306 -- led(4) <= gpto.wdog;
307 307 end generate;
308 308 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
309 309
310 310
311 311 ----------------------------------------------------------------------
312 312 --- APB UART -------------------------------------------------------
313 313 ----------------------------------------------------------------------
314 314
315 315 ua1 : if CFG_UART1_ENABLE /= 0 generate
316 316 uart1 : apbuart -- UART 1
317 317 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
318 318 fifosize => CFG_UART1_FIFO)
319 319 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
320 320 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
321 321 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
322 322 led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
323 323 end generate;
324 324 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
325 325
326 326 ---------------------------------------------------------------------
327 327 --- AJOUT TEST -------------------------------------IPs------------
328 328 ---------------------------------------------------------------------
329 329
330 330
331 331 end Behavioral; No newline at end of file
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