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Removed reference to ssram_plugin2.
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1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 library ieee;
21 library ieee;
22 use ieee.std_logic_1164.all;
22 use ieee.std_logic_1164.all;
23 library grlib;
23 library grlib;
24 use grlib.amba.all;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
25 use grlib.stdlib.all;
26 library techmap;
26 library techmap;
27 use techmap.gencomp.all;
27 use techmap.gencomp.all;
28 library gaisler;
28 library gaisler;
29 use gaisler.memctrl.all;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
32 use gaisler.misc.all;
33 library esa;
33 library esa;
34 use esa.memoryctrl.all;
34 use esa.memoryctrl.all;
35 use work.config.all;
35 use work.config.all;
36 library lpp;
36 library lpp;
37 use lpp.lpp_amba.all;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
38 use lpp.lpp_memory.all;
39 --use lpp.lpp_uart.all;
39 --use lpp.lpp_uart.all;
40 --use lpp.lpp_matrix.all;
40 --use lpp.lpp_matrix.all;
41 --use lpp.lpp_usb.all;
41 --use lpp.lpp_usb.all;
42
42
43 entity leon3mp is
43 entity leon3mp is
44 generic (
44 generic (
45 fabtech : integer := CFG_FABTECH;
45 fabtech : integer := CFG_FABTECH;
46 memtech : integer := CFG_MEMTECH;
46 memtech : integer := CFG_MEMTECH;
47 padtech : integer := CFG_PADTECH;
47 padtech : integer := CFG_PADTECH;
48 clktech : integer := CFG_CLKTECH;
48 clktech : integer := CFG_CLKTECH;
49 disas : integer := CFG_DISAS; -- Enable disassembly to console
49 disas : integer := CFG_DISAS; -- Enable disassembly to console
50 dbguart : integer := CFG_DUART; -- Print UART on console
50 dbguart : integer := CFG_DUART; -- Print UART on console
51 pclow : integer := CFG_PCLOW
51 pclow : integer := CFG_PCLOW
52 );
52 );
53 port (
53 port (
54 clk50MHz : in std_ulogic;
54 clk50MHz : in std_ulogic;
55 reset : in std_ulogic;
55 reset : in std_ulogic;
56 ramclk : out std_logic;
56 ramclk : out std_logic;
57
57
58 ahbrxd : in std_ulogic; -- DSU rx data
58 ahbrxd : in std_ulogic; -- DSU rx data
59 ahbtxd : out std_ulogic; -- DSU tx data
59 ahbtxd : out std_ulogic; -- DSU tx data
60 dsubre : in std_ulogic;
60 dsubre : in std_ulogic;
61 dsuact : out std_ulogic;
61 dsuact : out std_ulogic;
62 urxd1 : in std_ulogic; -- UART1 rx data
62 urxd1 : in std_ulogic; -- UART1 rx data
63 utxd1 : out std_ulogic; -- UART1 tx data
63 utxd1 : out std_ulogic; -- UART1 tx data
64 errorn : out std_ulogic;
64 errorn : out std_ulogic;
65
65
66 address : out std_logic_vector(18 downto 0);
66 address : out std_logic_vector(18 downto 0);
67 data : inout std_logic_vector(31 downto 0);
67 data : inout std_logic_vector(31 downto 0);
68
68
69 nBWa : out std_logic;
69 nBWa : out std_logic;
70 nBWb : out std_logic;
70 nBWb : out std_logic;
71 nBWc : out std_logic;
71 nBWc : out std_logic;
72 nBWd : out std_logic;
72 nBWd : out std_logic;
73 nBWE : out std_logic;
73 nBWE : out std_logic;
74 nADSC : out std_logic;
74 nADSC : out std_logic;
75 nADSP : out std_logic;
75 nADSP : out std_logic;
76 nADV : out std_logic;
76 nADV : out std_logic;
77 nGW : out std_logic;
77 nGW : out std_logic;
78 nCE1 : out std_logic;
78 nCE1 : out std_logic;
79 CE2 : out std_logic;
79 CE2 : out std_logic;
80 nCE3 : out std_logic;
80 nCE3 : out std_logic;
81 nOE : out std_logic;
81 nOE : out std_logic;
82 MODE : out std_logic;
82 MODE : out std_logic;
83 SSRAM_CLK : out std_logic;
83 SSRAM_CLK : out std_logic;
84 ZZ : out std_logic;
84 ZZ : out std_logic;
85 led : out std_logic_vector(1 downto 0)
85 led : out std_logic_vector(1 downto 0)
86 );
86 );
87 end;
87 end;
88
88
89 architecture Behavioral of leon3mp is
89 architecture Behavioral of leon3mp is
90
90
91 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
91 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
92 CFG_GRETH+CFG_AHB_JTAG;
92 CFG_GRETH+CFG_AHB_JTAG;
93 constant maxahbm : integer := maxahbmsp;
93 constant maxahbm : integer := maxahbmsp;
94
94
95 --Clk & Rst gοΏ½nοΏ½
95 --Clk & Rst gοΏ½nοΏ½
96 signal vcc : std_logic_vector(4 downto 0);
96 signal vcc : std_logic_vector(4 downto 0);
97 signal gnd : std_logic_vector(4 downto 0);
97 signal gnd : std_logic_vector(4 downto 0);
98 signal resetnl : std_ulogic;
98 signal resetnl : std_ulogic;
99 signal clk2x : std_ulogic;
99 signal clk2x : std_ulogic;
100 signal lclk : std_ulogic;
100 signal lclk : std_ulogic;
101 signal lclk2x : std_ulogic;
101 signal lclk2x : std_ulogic;
102 signal clkm : std_ulogic;
102 signal clkm : std_ulogic;
103 signal rstn : std_ulogic;
103 signal rstn : std_ulogic;
104 signal rstraw : std_ulogic;
104 signal rstraw : std_ulogic;
105 signal pciclk : std_ulogic;
105 signal pciclk : std_ulogic;
106 signal sdclkl : std_ulogic;
106 signal sdclkl : std_ulogic;
107 signal cgi : clkgen_in_type;
107 signal cgi : clkgen_in_type;
108 signal cgo : clkgen_out_type;
108 signal cgo : clkgen_out_type;
109 --- AHB / APB
109 --- AHB / APB
110 signal apbi : apb_slv_in_type;
110 signal apbi : apb_slv_in_type;
111 signal apbo : apb_slv_out_vector := (others => apb_none);
111 signal apbo : apb_slv_out_vector := (others => apb_none);
112 signal ahbsi : ahb_slv_in_type;
112 signal ahbsi : ahb_slv_in_type;
113 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
113 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
114 signal ahbmi : ahb_mst_in_type;
114 signal ahbmi : ahb_mst_in_type;
115 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
115 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
116 --UART
116 --UART
117 signal ahbuarti : uart_in_type;
117 signal ahbuarti : uart_in_type;
118 signal ahbuarto : uart_out_type;
118 signal ahbuarto : uart_out_type;
119 signal apbuarti : uart_in_type;
119 signal apbuarti : uart_in_type;
120 signal apbuarto : uart_out_type;
120 signal apbuarto : uart_out_type;
121 --MEM CTRLR
121 --MEM CTRLR
122 signal memi : memory_in_type;
122 signal memi : memory_in_type;
123 signal memo : memory_out_type;
123 signal memo : memory_out_type;
124 signal wpo : wprot_out_type;
124 signal wpo : wprot_out_type;
125 signal sdo : sdram_out_type;
125 signal sdo : sdram_out_type;
126 --IRQ
126 --IRQ
127 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
127 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
128 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
128 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
129 --Timer
129 --Timer
130 signal gpti : gptimer_in_type;
130 signal gpti : gptimer_in_type;
131 signal gpto : gptimer_out_type;
131 signal gpto : gptimer_out_type;
132 --GPIO
132 --GPIO
133 signal gpioi : gpio_in_type;
133 signal gpioi : gpio_in_type;
134 signal gpioo : gpio_out_type;
134 signal gpioo : gpio_out_type;
135 --DSU
135 --DSU
136 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
136 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
137 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
137 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
138 signal dsui : dsu_in_type;
138 signal dsui : dsu_in_type;
139 signal dsuo : dsu_out_type;
139 signal dsuo : dsu_out_type;
140 ----------------------------------------------------------------------
140 ----------------------------------------------------------------------
141 --- AJOUT TEST ------------------------Signaux----------------------
141 --- AJOUT TEST ------------------------Signaux----------------------
142 ----------------------------------------------------------------------
142 ----------------------------------------------------------------------
143 -- TEST USB
143 -- TEST USB
144 --signal USB_Read : std_logic;
144 --signal USB_Read : std_logic;
145 --signal USB_Write : std_logic;
145 --signal USB_Write : std_logic;
146
146
147 -- MATRICE SPECTRALE
147 -- MATRICE SPECTRALE
148 --signal Matrix_Write : std_logic;
148 --signal Matrix_Write : std_logic;
149 --signal Matrix_Read : std_logic_vector(1 downto 0);
149 --signal Matrix_Read : std_logic_vector(1 downto 0);
150 --signal Matrix_Full : std_logic_vector(1 downto 0);
150 --signal Matrix_Full : std_logic_vector(1 downto 0);
151 --signal Matrix_Empty : std_logic_vector(1 downto 0);
151 --signal Matrix_Empty : std_logic_vector(1 downto 0);
152 --signal Matrix_Data1 : std_logic_vector(15 downto 0);
152 --signal Matrix_Data1 : std_logic_vector(15 downto 0);
153 --signal Matrix_Data2 : std_logic_vector(15 downto 0);
153 --signal Matrix_Data2 : std_logic_vector(15 downto 0);
154 --signal Matrix_Result : std_logic_vector(31 downto 0);
154 --signal Matrix_Result : std_logic_vector(31 downto 0);
155
155
156 ---------------------------------------------------------------------
156 ---------------------------------------------------------------------
157 constant IOAEN : integer := CFG_CAN;
157 constant IOAEN : integer := CFG_CAN;
158 constant boardfreq : integer := 50000;
158 constant boardfreq : integer := 50000;
159
159
160 begin
160 begin
161
161
162 ----------------------------------------------------------------------
162 ----------------------------------------------------------------------
163 --- Reset and Clock generation -------------------------------------
163 --- Reset and Clock generation -------------------------------------
164 ----------------------------------------------------------------------
164 ----------------------------------------------------------------------
165
165
166 vcc <= (others => '1'); gnd <= (others => '0');
166 vcc <= (others => '1'); gnd <= (others => '0');
167 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
167 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
168
168
169 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
169 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
170
170
171
171
172 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
172 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
173
173
174 clkgen0 : clkgen -- clock generator
174 clkgen0 : clkgen -- clock generator
175 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
175 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
176 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
176 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
177 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
177 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
178
178
179 ramclk <= clkm;
179 ramclk <= clkm;
180 process(lclk2x)
180 process(lclk2x)
181 begin
181 begin
182 if lclk2x'event and lclk2x = '1' then
182 if lclk2x'event and lclk2x = '1' then
183 lclk <= not lclk;
183 lclk <= not lclk;
184 end if;
184 end if;
185 end process;
185 end process;
186
186
187 ----------------------------------------------------------------------
187 ----------------------------------------------------------------------
188 --- LEON3 processor / DSU / IRQ ------------------------------------
188 --- LEON3 processor / DSU / IRQ ------------------------------------
189 ----------------------------------------------------------------------
189 ----------------------------------------------------------------------
190
190
191 l3 : if CFG_LEON3 = 1 generate
191 l3 : if CFG_LEON3 = 1 generate
192 cpu : for i in 0 to CFG_NCPU-1 generate
192 cpu : for i in 0 to CFG_NCPU-1 generate
193 u0 : leon3s -- LEON3 processor
193 u0 : leon3s -- LEON3 processor
194 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
194 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
195 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
195 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
196 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
196 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
197 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
197 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
198 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
198 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
199 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
199 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
200 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
200 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
201 irqi(i), irqo(i), dbgi(i), dbgo(i));
201 irqi(i), irqo(i), dbgi(i), dbgo(i));
202 end generate;
202 end generate;
203 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
203 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
204
204
205 dsugen : if CFG_DSU = 1 generate
205 dsugen : if CFG_DSU = 1 generate
206 dsu0 : dsu3 -- LEON3 Debug Support Unit
206 dsu0 : dsu3 -- LEON3 Debug Support Unit
207 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
207 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
208 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
208 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
209 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
209 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
210 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
210 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
211 dsui.enable <= '1';
211 dsui.enable <= '1';
212 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
212 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
213 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
213 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
214 end generate;
214 end generate;
215 end generate;
215 end generate;
216
216
217 nodsu : if CFG_DSU = 0 generate
217 nodsu : if CFG_DSU = 0 generate
218 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
218 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
219 end generate;
219 end generate;
220
220
221 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
221 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
222 irqctrl0 : irqmp -- interrupt controller
222 irqctrl0 : irqmp -- interrupt controller
223 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
223 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
224 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
224 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
225 end generate;
225 end generate;
226 irq3 : if CFG_IRQ3_ENABLE = 0 generate
226 irq3 : if CFG_IRQ3_ENABLE = 0 generate
227 x : for i in 0 to CFG_NCPU-1 generate
227 x : for i in 0 to CFG_NCPU-1 generate
228 irqi(i).irl <= "0000";
228 irqi(i).irl <= "0000";
229 end generate;
229 end generate;
230 apbo(2) <= apb_none;
230 apbo(2) <= apb_none;
231 end generate;
231 end generate;
232
232
233 ----------------------------------------------------------------------
233 ----------------------------------------------------------------------
234 --- Memory controllers ---------------------------------------------
234 --- Memory controllers ---------------------------------------------
235 ----------------------------------------------------------------------
235 ----------------------------------------------------------------------
236
236
237 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
237 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
238 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
238 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
239
239
240 memi.brdyn <= '1'; memi.bexcn <= '1';
240 memi.brdyn <= '1'; memi.bexcn <= '1';
241 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
241 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
242
242
243 bdr : for i in 0 to 3 generate
243 bdr : for i in 0 to 3 generate
244 data_pad : iopadv generic map (tech => padtech, width => 8)
244 data_pad : iopadv generic map (tech => padtech, width => 8)
245 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
245 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
246 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
246 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
247 end generate;
247 end generate;
248
248
249
249
250 addr_pad : outpadv generic map (width => 19, tech => padtech)
250 addr_pad : outpadv generic map (width => 19, tech => padtech)
251 port map (address, memo.address(20 downto 2));
251 port map (address, memo.address(20 downto 2));
252
252
253
253
254 --SSRAM_0:entity ssram_plugin
254 --SSRAM_0:entity ssram_plugin
255 --generic map (tech => padtech)
255 --generic map (tech => padtech)
256 --port map
256 --port map
257 --(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
257 --(lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
258
258
259 SSRAM_0:entity work.ssram_plugin2
259 SSRAM_0:entity ssram_plugin
260 generic map (tech => padtech)
260 generic map (tech => padtech)
261 port map
261 port map
262 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
262 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
263
263
264 ----------------------------------------------------------------------
264 ----------------------------------------------------------------------
265 --- AHB CONTROLLER -------------------------------------------------
265 --- AHB CONTROLLER -------------------------------------------------
266 ----------------------------------------------------------------------
266 ----------------------------------------------------------------------
267
267
268 ahb0 : ahbctrl -- AHB arbiter/multiplexer
268 ahb0 : ahbctrl -- AHB arbiter/multiplexer
269 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
269 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
270 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
270 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
271 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
271 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
272 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
272 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
273
273
274 ----------------------------------------------------------------------
274 ----------------------------------------------------------------------
275 --- AHB UART -------------------------------------------------------
275 --- AHB UART -------------------------------------------------------
276 ----------------------------------------------------------------------
276 ----------------------------------------------------------------------
277 dcomgen : if CFG_AHB_UART = 1 generate
277 dcomgen : if CFG_AHB_UART = 1 generate
278 dcom0: ahbuart -- Debug UART
278 dcom0: ahbuart -- Debug UART
279 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
279 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
280 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
280 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
281 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
281 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
282 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
282 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
283 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
283 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
284 end generate;
284 end generate;
285 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
285 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
286
286
287 ----------------------------------------------------------------------
287 ----------------------------------------------------------------------
288 --- APB Bridge -----------------------------------------------------
288 --- APB Bridge -----------------------------------------------------
289 ----------------------------------------------------------------------
289 ----------------------------------------------------------------------
290
290
291 apb0 : apbctrl -- AHB/APB bridge
291 apb0 : apbctrl -- AHB/APB bridge
292 generic map (hindex => 1, haddr => CFG_APBADDR)
292 generic map (hindex => 1, haddr => CFG_APBADDR)
293 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
293 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
294
294
295 ----------------------------------------------------------------------
295 ----------------------------------------------------------------------
296 --- GPT Timer ------------------------------------------------------
296 --- GPT Timer ------------------------------------------------------
297 ----------------------------------------------------------------------
297 ----------------------------------------------------------------------
298
298
299 gpt : if CFG_GPT_ENABLE /= 0 generate
299 gpt : if CFG_GPT_ENABLE /= 0 generate
300 timer0 : gptimer -- timer unit
300 timer0 : gptimer -- timer unit
301 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
301 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
302 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
302 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
303 nbits => CFG_GPT_TW)
303 nbits => CFG_GPT_TW)
304 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
304 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
305 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
305 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
306 -- led(4) <= gpto.wdog;
306 -- led(4) <= gpto.wdog;
307 end generate;
307 end generate;
308 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
308 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
309
309
310
310
311 ----------------------------------------------------------------------
311 ----------------------------------------------------------------------
312 --- APB UART -------------------------------------------------------
312 --- APB UART -------------------------------------------------------
313 ----------------------------------------------------------------------
313 ----------------------------------------------------------------------
314
314
315 ua1 : if CFG_UART1_ENABLE /= 0 generate
315 ua1 : if CFG_UART1_ENABLE /= 0 generate
316 uart1 : apbuart -- UART 1
316 uart1 : apbuart -- UART 1
317 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
317 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
318 fifosize => CFG_UART1_FIFO)
318 fifosize => CFG_UART1_FIFO)
319 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
319 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
320 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
320 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
321 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
321 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
322 led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
322 led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
323 end generate;
323 end generate;
324 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
324 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
325
325
326 ---------------------------------------------------------------------
326 ---------------------------------------------------------------------
327 --- AJOUT TEST -------------------------------------IPs------------
327 --- AJOUT TEST -------------------------------------IPs------------
328 ---------------------------------------------------------------------
328 ---------------------------------------------------------------------
329
329
330
330
331 end Behavioral; No newline at end of file
331 end Behavioral;
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