@@ -0,0 +1,192 | |||||
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1 | ||||
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2 | ------------------------------------------------------------------------------ | |||
|
3 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
5 | -- | |||
|
6 | -- This program is free software; you can redistribute it and/or modify | |||
|
7 | -- it under the terms of the GNU General Public License as published by | |||
|
8 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
9 | -- (at your option) any later version. | |||
|
10 | -- | |||
|
11 | -- This program is distributed in the hope that it will be useful, | |||
|
12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
14 | -- GNU General Public License for more details. | |||
|
15 | -- | |||
|
16 | -- You should have received a copy of the GNU General Public License | |||
|
17 | -- along with this program; if not, write to the Free Software | |||
|
18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
19 | ------------------------------------------------------------------------------- | |||
|
20 | -- Author : Jean-christophe Pellion | |||
|
21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
22 | -- jean-christophe.pellion@easii-ic.com | |||
|
23 | ------------------------------------------------------------------------------- | |||
|
24 | -- 1.0 - initial version | |||
|
25 | -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) | |||
|
26 | ------------------------------------------------------------------------------- | |||
|
27 | LIBRARY ieee; | |||
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28 | USE ieee.std_logic_1164.ALL; | |||
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29 | USE ieee.numeric_std.ALL; | |||
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30 | LIBRARY grlib; | |||
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31 | USE grlib.amba.ALL; | |||
|
32 | USE grlib.stdlib.ALL; | |||
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33 | USE grlib.devices.ALL; | |||
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34 | USE GRLIB.DMA2AHB_Package.ALL; | |||
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35 | LIBRARY lpp; | |||
|
36 | USE lpp.lpp_amba.ALL; | |||
|
37 | USE lpp.apb_devices_list.ALL; | |||
|
38 | USE lpp.lpp_memory.ALL; | |||
|
39 | USE lpp.lpp_dma_pkg.ALL; | |||
|
40 | USE lpp.lpp_waveform_pkg.ALL; | |||
|
41 | LIBRARY techmap; | |||
|
42 | USE techmap.gencomp.ALL; | |||
|
43 | ||||
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44 | ||||
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45 | ENTITY lpp_debug_dma_singleOrBurst IS | |||
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46 | GENERIC ( | |||
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47 | tech : INTEGER := inferred; | |||
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48 | hindex : INTEGER := 2; | |||
|
49 | pindex : INTEGER := 4; | |||
|
50 | paddr : INTEGER := 4; | |||
|
51 | pmask : INTEGER := 16#fff# | |||
|
52 | ); | |||
|
53 | PORT ( | |||
|
54 | -- AMBA AHB system signals | |||
|
55 | HCLK : IN STD_ULOGIC; | |||
|
56 | HRESETn : IN STD_ULOGIC; | |||
|
57 | -- AMBA AHB Master Interface | |||
|
58 | ahbmi : IN AHB_Mst_In_Type; | |||
|
59 | ahbmo : OUT AHB_Mst_Out_Type; | |||
|
60 | -- AMBA AHB Master Interface | |||
|
61 | apbi : IN apb_slv_in_type; | |||
|
62 | apbo : OUT apb_slv_out_type | |||
|
63 | ); | |||
|
64 | END; | |||
|
65 | ||||
|
66 | ARCHITECTURE Behavioral OF lpp_debug_dma_singleOrBurst IS | |||
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67 | SIGNAL run : STD_LOGIC; | |||
|
68 | SIGNAL send : STD_LOGIC; | |||
|
69 | SIGNAL valid_burst : STD_LOGIC; | |||
|
70 | SIGNAL done : STD_LOGIC; | |||
|
71 | SIGNAL ren : STD_LOGIC; | |||
|
72 | SIGNAL address : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
73 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
74 | -- | |||
|
75 | ||||
|
76 | CONSTANT REVISION : INTEGER := 1; | |||
|
77 | ||||
|
78 | CONSTANT pconfig : apb_config_type := ( | |||
|
79 | 0 => ahb_device_reg (VENDOR_LPP, LPP_DEBUG_DMA, 2, REVISION, 0), | |||
|
80 | 1 => apb_iobar(paddr, pmask)); | |||
|
81 | ||||
|
82 | TYPE lpp_debug_dma_regs IS RECORD | |||
|
83 | run : STD_LOGIC; | |||
|
84 | send : STD_LOGIC; | |||
|
85 | valid_burst : STD_LOGIC; | |||
|
86 | done : STD_LOGIC; | |||
|
87 | ren : STD_LOGIC; | |||
|
88 | addr : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
89 | data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
90 | nb_ren : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
|
91 | END RECORD; | |||
|
92 | SIGNAL reg : lpp_debug_dma_regs; | |||
|
93 | ||||
|
94 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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95 | ||||
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96 | BEGIN | |||
|
97 | ||||
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98 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst | |||
|
99 | GENERIC MAP ( | |||
|
100 | tech => tech, | |||
|
101 | hindex => hindex) | |||
|
102 | PORT MAP ( | |||
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103 | HCLK => HCLK, | |||
|
104 | HRESETn => HRESETn, | |||
|
105 | run => run, -- | |||
|
106 | AHB_Master_In => ahbmi, | |||
|
107 | AHB_Master_Out => ahbmo, | |||
|
108 | send => send, -- | |||
|
109 | valid_burst => valid_burst, -- | |||
|
110 | done => done, -- out | |||
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111 | ren => ren, -- out | |||
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112 | address => address, | |||
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113 | data => data); | |||
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114 | ||||
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115 | ||||
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116 | run <= reg.run; | |||
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117 | valid_burst <= reg.valid_burst; | |||
|
118 | send <= reg.send; | |||
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119 | address <= reg.addr; | |||
|
120 | data <= reg.data; | |||
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121 | ||||
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122 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |||
|
123 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |||
|
124 | BEGIN -- PROCESS lpp_dma_top | |||
|
125 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |||
|
126 | reg.run <= '0'; | |||
|
127 | reg.send <= '0'; | |||
|
128 | reg.valid_burst <= '0'; | |||
|
129 | reg.done <= '0'; | |||
|
130 | reg.ren <= '0'; | |||
|
131 | reg.addr <= (OTHERS => '0'); | |||
|
132 | reg.data <= (OTHERS => '0'); | |||
|
133 | reg.nb_ren <= (OTHERS => '0'); | |||
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134 | ||||
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135 | apbo.pirq <= (OTHERS => '0'); | |||
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136 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |||
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137 | paddr := "000000"; | |||
|
138 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); | |||
|
139 | prdata <= (OTHERS => '0'); | |||
|
140 | ------------------------------------ | |||
|
141 | reg.send <= '0'; | |||
|
142 | IF done = '1' THEN | |||
|
143 | reg.done <= '1'; | |||
|
144 | END IF; | |||
|
145 | IF ren = '0' THEN | |||
|
146 | reg.ren <= '1'; | |||
|
147 | reg.nb_ren <= STD_LOGIC_VECTOR(UNSIGNED(reg.nb_ren) + 1); | |||
|
148 | END IF; | |||
|
149 | ------------------------------------ | |||
|
150 | ||||
|
151 | IF apbi.psel(pindex) = '1' THEN | |||
|
152 | -- APB DMA READ -- | |||
|
153 | CASE paddr(7 DOWNTO 2) IS | |||
|
154 | -- | |||
|
155 | WHEN "000000" => prdata(0) <= reg.run; | |||
|
156 | prdata(1) <= reg.send; | |||
|
157 | prdata(2) <= reg.valid_burst; | |||
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158 | prdata(3) <= reg.done; | |||
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159 | prdata(4) <= reg.ren; | |||
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160 | WHEN "000001" => prdata <= reg.addr; | |||
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161 | WHEN "000010" => prdata <= reg.data; | |||
|
162 | WHEN "000011" => prdata <= reg.nb_ren; | |||
|
163 | ||||
|
164 | WHEN OTHERS => NULL; | |||
|
165 | END CASE; | |||
|
166 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |||
|
167 | -- APB DMA WRITE -- | |||
|
168 | CASE paddr(7 DOWNTO 2) IS | |||
|
169 | -- | |||
|
170 | WHEN "000000" => reg.run <= apbi.pwdata(0); | |||
|
171 | reg.send <= apbi.pwdata(1); | |||
|
172 | reg.valid_burst <= apbi.pwdata(2); | |||
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173 | reg.done <= apbi.pwdata(3); | |||
|
174 | reg.ren <= apbi.pwdata(4); | |||
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175 | WHEN "000001" => reg.addr <= apbi.pwdata; | |||
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176 | WHEN "000010" => reg.data <= apbi.pwdata; | |||
|
177 | WHEN "000011" => reg.nb_ren <= apbi.pwdata; | |||
|
178 | WHEN OTHERS => NULL; | |||
|
179 | END CASE; | |||
|
180 | END IF; | |||
|
181 | END IF; | |||
|
182 | ||||
|
183 | END IF; | |||
|
184 | END PROCESS lpp_lfr_apbreg; | |||
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185 | ||||
|
186 | apbo.pindex <= pindex; | |||
|
187 | apbo.pconfig <= pconfig; | |||
|
188 | apbo.prdata <= prdata; | |||
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189 | ||||
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190 | ||||
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191 | ||||
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192 | END Behavioral; No newline at end of file |
@@ -0,0 +1,46 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ---------------------------------------------------------------------------- | |||
|
23 | LIBRARY ieee; | |||
|
24 | USE ieee.std_logic_1164.ALL; | |||
|
25 | LIBRARY grlib; | |||
|
26 | USE grlib.amba.ALL; | |||
|
27 | ||||
|
28 | PACKAGE lpp_debug_lfr_pkg IS | |||
|
29 | ||||
|
30 | COMPONENT lpp_debug_dma_singleOrBurst | |||
|
31 | GENERIC ( | |||
|
32 | tech : INTEGER; | |||
|
33 | hindex : INTEGER; | |||
|
34 | pindex : INTEGER; | |||
|
35 | paddr : INTEGER; | |||
|
36 | pmask : INTEGER); | |||
|
37 | PORT ( | |||
|
38 | HCLK : IN STD_ULOGIC; | |||
|
39 | HRESETn : IN STD_ULOGIC; | |||
|
40 | ahbmi : IN AHB_Mst_In_Type; | |||
|
41 | ahbmo : OUT AHB_Mst_Out_Type; | |||
|
42 | apbi : IN apb_slv_in_type; | |||
|
43 | apbo : OUT apb_slv_out_type); | |||
|
44 | END COMPONENT; | |||
|
45 | ||||
|
46 | END; |
@@ -1,275 +1,292 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
|
31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
|
32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
|
33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
|
34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; -- PLE |
|
35 | USE gaisler.spacewire.ALL; -- PLE | |
36 | LIBRARY esa; |
|
36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
|
37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
|
38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
|
39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; |
|
41 | USE lpp.lpp_lfr_pkg.ALL; | |
42 | USE lpp.iir_filter.ALL; |
|
42 | USE lpp.iir_filter.ALL; | |
43 | USE lpp.general_purpose.ALL; |
|
43 | USE lpp.general_purpose.ALL; | |
44 | USE lpp.lpp_lfr_time_management.ALL; |
|
44 | USE lpp.lpp_lfr_time_management.ALL; | |
45 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
45 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
|
46 | USE lpp.lpp_debug_lfr_pkg.ALL; | |||
46 |
|
47 | |||
47 | ENTITY MINI_LFR_top IS |
|
48 | ENTITY MINI_LFR_top IS | |
48 |
|
49 | |||
49 | PORT ( |
|
50 | PORT ( | |
50 | clk_50 : IN STD_LOGIC; |
|
51 | clk_50 : IN STD_LOGIC; | |
51 | clk_49 : IN STD_LOGIC; |
|
52 | clk_49 : IN STD_LOGIC; | |
52 | reset : IN STD_LOGIC; |
|
53 | reset : IN STD_LOGIC; | |
53 | --BPs |
|
54 | --BPs | |
54 | BP0 : IN STD_LOGIC; |
|
55 | BP0 : IN STD_LOGIC; | |
55 | BP1 : IN STD_LOGIC; |
|
56 | BP1 : IN STD_LOGIC; | |
56 | --LEDs |
|
57 | --LEDs | |
57 | LED0 : OUT STD_LOGIC; |
|
58 | LED0 : OUT STD_LOGIC; | |
58 | LED1 : OUT STD_LOGIC; |
|
59 | LED1 : OUT STD_LOGIC; | |
59 | LED2 : OUT STD_LOGIC; |
|
60 | LED2 : OUT STD_LOGIC; | |
60 | --UARTs |
|
61 | --UARTs | |
61 | TXD1 : IN STD_LOGIC; |
|
62 | TXD1 : IN STD_LOGIC; | |
62 | RXD1 : OUT STD_LOGIC; |
|
63 | RXD1 : OUT STD_LOGIC; | |
63 | nCTS1 : OUT STD_LOGIC; |
|
64 | nCTS1 : OUT STD_LOGIC; | |
64 | nRTS1 : IN STD_LOGIC; |
|
65 | nRTS1 : IN STD_LOGIC; | |
65 |
|
66 | |||
66 | TXD2 : IN STD_LOGIC; |
|
67 | TXD2 : IN STD_LOGIC; | |
67 | RXD2 : OUT STD_LOGIC; |
|
68 | RXD2 : OUT STD_LOGIC; | |
68 | nCTS2 : OUT STD_LOGIC; |
|
69 | nCTS2 : OUT STD_LOGIC; | |
69 | nDTR2 : IN STD_LOGIC; |
|
70 | nDTR2 : IN STD_LOGIC; | |
70 | nRTS2 : IN STD_LOGIC; |
|
71 | nRTS2 : IN STD_LOGIC; | |
71 | nDCD2 : OUT STD_LOGIC; |
|
72 | nDCD2 : OUT STD_LOGIC; | |
72 |
|
73 | |||
73 | --EXT CONNECTOR |
|
74 | --EXT CONNECTOR | |
74 | IO0 : INOUT STD_LOGIC; |
|
75 | IO0 : INOUT STD_LOGIC; | |
75 | IO1 : INOUT STD_LOGIC; |
|
76 | IO1 : INOUT STD_LOGIC; | |
76 | IO2 : INOUT STD_LOGIC; |
|
77 | IO2 : INOUT STD_LOGIC; | |
77 | IO3 : INOUT STD_LOGIC; |
|
78 | IO3 : INOUT STD_LOGIC; | |
78 | IO4 : INOUT STD_LOGIC; |
|
79 | IO4 : INOUT STD_LOGIC; | |
79 | IO5 : INOUT STD_LOGIC; |
|
80 | IO5 : INOUT STD_LOGIC; | |
80 | IO6 : INOUT STD_LOGIC; |
|
81 | IO6 : INOUT STD_LOGIC; | |
81 | IO7 : INOUT STD_LOGIC; |
|
82 | IO7 : INOUT STD_LOGIC; | |
82 | IO8 : INOUT STD_LOGIC; |
|
83 | IO8 : INOUT STD_LOGIC; | |
83 | IO9 : INOUT STD_LOGIC; |
|
84 | IO9 : INOUT STD_LOGIC; | |
84 | IO10 : INOUT STD_LOGIC; |
|
85 | IO10 : INOUT STD_LOGIC; | |
85 | IO11 : INOUT STD_LOGIC; |
|
86 | IO11 : INOUT STD_LOGIC; | |
86 |
|
87 | |||
87 | --SPACE WIRE |
|
88 | --SPACE WIRE | |
88 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
89 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
90 | SPW_NOM_SIN : IN STD_LOGIC; |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
91 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
92 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
93 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
94 | SPW_RED_SIN : IN STD_LOGIC; |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
95 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
96 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
97 | -- MINI LFR ADC INPUTS |
|
98 | -- MINI LFR ADC INPUTS | |
98 | ADC_nCS : OUT STD_LOGIC; |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
99 | ADC_CLK : OUT STD_LOGIC; |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
100 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
101 |
|
102 | |||
102 | -- SRAM |
|
103 | -- SRAM | |
103 | SRAM_nWE : OUT STD_LOGIC; |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
104 | SRAM_CE : OUT STD_LOGIC; |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
105 | SRAM_nOE : OUT STD_LOGIC; |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
106 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
107 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
108 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
109 | ); |
|
110 | ); | |
110 |
|
111 | |||
111 | END MINI_LFR_top; |
|
112 | END MINI_LFR_top; | |
112 |
|
113 | |||
113 |
|
114 | |||
114 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
115 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
116 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
117 | ----------------------------------------------------------------------------- |
|
118 | ----------------------------------------------------------------------------- | |
118 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
119 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
120 | -- |
|
121 | -- | |
121 | SIGNAL errorn : STD_LOGIC; |
|
122 | SIGNAL errorn : STD_LOGIC; | |
122 | -- UART AHB --------------------------------------------------------------- |
|
123 | -- UART AHB --------------------------------------------------------------- | |
123 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
124 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
125 |
|
126 | |||
126 | -- UART APB --------------------------------------------------------------- |
|
127 | -- UART APB --------------------------------------------------------------- | |
127 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
128 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
129 | -- |
|
130 | -- | |
130 | SIGNAL I00_s : STD_LOGIC; |
|
131 | SIGNAL I00_s : STD_LOGIC; | |
131 | -- |
|
132 | -- | |
132 | CONSTANT NB_APB_SLAVE : INTEGER := 1; |
|
133 | CONSTANT NB_APB_SLAVE : INTEGER := 1; | |
133 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
134 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
134 | CONSTANT NB_AHB_MASTER : INTEGER := 1; |
|
135 | CONSTANT NB_AHB_MASTER : INTEGER := 1; | |
135 |
|
136 | |||
136 | SIGNAL apbi_ext : apb_slv_in_type; |
|
137 | SIGNAL apbi_ext : apb_slv_in_type; | |
137 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); |
|
138 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none); | |
138 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
139 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
139 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); |
|
140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); | |
140 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
141 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); |
|
142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); | |
142 |
|
143 | |||
143 | BEGIN -- beh |
|
144 | BEGIN -- beh | |
144 |
|
145 | |||
145 | ----------------------------------------------------------------------------- |
|
146 | ----------------------------------------------------------------------------- | |
146 | -- CLK |
|
147 | -- CLK | |
147 | ----------------------------------------------------------------------------- |
|
148 | ----------------------------------------------------------------------------- | |
148 |
|
149 | |||
149 | PROCESS(clk_50) |
|
150 | PROCESS(clk_50) | |
150 | BEGIN |
|
151 | BEGIN | |
151 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
152 | IF clk_50'EVENT AND clk_50 = '1' THEN | |
152 | clk_50_s <= NOT clk_50_s; |
|
153 | clk_50_s <= NOT clk_50_s; | |
153 | END IF; |
|
154 | END IF; | |
154 | END PROCESS; |
|
155 | END PROCESS; | |
155 |
|
156 | |||
156 | PROCESS(clk_50_s) |
|
157 | PROCESS(clk_50_s) | |
157 | BEGIN |
|
158 | BEGIN | |
158 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
159 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
159 | clk_25 <= NOT clk_25; |
|
160 | clk_25 <= NOT clk_25; | |
160 | END IF; |
|
161 | END IF; | |
161 | END PROCESS; |
|
162 | END PROCESS; | |
162 |
|
163 | |||
163 | ----------------------------------------------------------------------------- |
|
164 | ----------------------------------------------------------------------------- | |
164 |
|
165 | |||
165 | PROCESS (clk_25, reset) |
|
166 | PROCESS (clk_25, reset) | |
166 | BEGIN -- PROCESS |
|
167 | BEGIN -- PROCESS | |
167 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
168 | IF reset = '0' THEN -- asynchronous reset (active low) | |
168 | LED0 <= '0'; |
|
169 | LED0 <= '0'; | |
169 | LED1 <= '0'; |
|
170 | LED1 <= '0'; | |
170 | LED2 <= '0'; |
|
171 | LED2 <= '0'; | |
171 | IO1 <= '0'; |
|
172 | IO1 <= '0'; | |
172 | IO2 <= '1'; |
|
173 | IO2 <= '1'; | |
173 | IO3 <= '0'; |
|
174 | IO3 <= '0'; | |
174 | IO4 <= '0'; |
|
175 | IO4 <= '0'; | |
175 | IO5 <= '0'; |
|
176 | IO5 <= '0'; | |
176 | IO6 <= '0'; |
|
177 | IO6 <= '0'; | |
177 | IO7 <= '0'; |
|
178 | IO7 <= '0'; | |
178 | IO8 <= '0'; |
|
179 | IO8 <= '0'; | |
179 | IO9 <= '0'; |
|
180 | IO9 <= '0'; | |
180 | IO10 <= '0'; |
|
181 | IO10 <= '0'; | |
181 | IO11 <= '0'; |
|
182 | IO11 <= '0'; | |
182 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
183 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
183 | LED0 <= '0'; |
|
184 | LED0 <= '0'; | |
184 | LED1 <= '1'; |
|
185 | LED1 <= '1'; | |
185 | LED2 <= BP0; |
|
186 | LED2 <= BP0; | |
186 | IO1 <= '1'; |
|
187 | IO1 <= '1'; | |
187 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
188 | IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
188 | IO3 <= ADC_SDO(0); |
|
189 | IO3 <= ADC_SDO(0); | |
189 | IO4 <= ADC_SDO(1); |
|
190 | IO4 <= ADC_SDO(1); | |
190 | IO5 <= ADC_SDO(2); |
|
191 | IO5 <= ADC_SDO(2); | |
191 | IO6 <= ADC_SDO(3); |
|
192 | IO6 <= ADC_SDO(3); | |
192 | IO7 <= ADC_SDO(4); |
|
193 | IO7 <= ADC_SDO(4); | |
193 | IO8 <= ADC_SDO(5); |
|
194 | IO8 <= ADC_SDO(5); | |
194 | IO9 <= ADC_SDO(6); |
|
195 | IO9 <= ADC_SDO(6); | |
195 | IO10 <= ADC_SDO(7); |
|
196 | IO10 <= ADC_SDO(7); | |
196 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
197 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
197 | END IF; |
|
198 | END IF; | |
198 | END PROCESS; |
|
199 | END PROCESS; | |
199 |
|
200 | |||
200 | PROCESS (clk_49, reset) |
|
201 | PROCESS (clk_49, reset) | |
201 | BEGIN -- PROCESS |
|
202 | BEGIN -- PROCESS | |
202 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
203 | IF reset = '0' THEN -- asynchronous reset (active low) | |
203 | I00_s <= '0'; |
|
204 | I00_s <= '0'; | |
204 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge |
|
205 | ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge | |
205 | I00_s <= NOT I00_s; |
|
206 | I00_s <= NOT I00_s; | |
206 | END IF; |
|
207 | END IF; | |
207 | END PROCESS; |
|
208 | END PROCESS; | |
208 | IO0 <= I00_s; |
|
209 | IO0 <= I00_s; | |
209 |
|
210 | |||
210 | --UARTs |
|
211 | --UARTs | |
211 | nCTS1 <= '1'; |
|
212 | nCTS1 <= '1'; | |
212 | nCTS2 <= '1'; |
|
213 | nCTS2 <= '1'; | |
213 | nDCD2 <= '1'; |
|
214 | nDCD2 <= '1'; | |
214 |
|
215 | |||
215 | --EXT CONNECTOR |
|
|||
216 |
|
||||
217 |
|
|
216 | --SPACE WIRE | |
218 | SPW_EN <= '0'; -- 0 => off |
|
217 | SPW_EN <= '0'; -- 0 => off | |
219 |
|
218 | |||
220 | SPW_NOM_DOUT <= '0'; |
|
219 | SPW_NOM_DOUT <= '0'; | |
221 | SPW_NOM_SOUT <= '0'; |
|
220 | SPW_NOM_SOUT <= '0'; | |
222 | SPW_RED_DOUT <= '0'; |
|
221 | SPW_RED_DOUT <= '0'; | |
223 | SPW_RED_SOUT <= '0'; |
|
222 | SPW_RED_SOUT <= '0'; | |
224 |
|
223 | |||
225 | ADC_nCS <= '0'; |
|
224 | ADC_nCS <= '0'; | |
226 | ADC_CLK <= '0'; |
|
225 | ADC_CLK <= '0'; | |
227 |
|
226 | |||
228 |
|
227 | |||
|
228 | ----------------------------------------------------------------------------- | |||
|
229 | lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst | |||
|
230 | GENERIC MAP ( | |||
|
231 | tech => apa3e, | |||
|
232 | hindex => 1, | |||
|
233 | pindex => 5, | |||
|
234 | paddr => 5, | |||
|
235 | pmask => 16#fff#) | |||
|
236 | PORT MAP ( | |||
|
237 | HCLK => clk_25, | |||
|
238 | HRESETn => reset , | |||
|
239 | ahbmi => ahbi_m_ext , | |||
|
240 | ahbmo => ahbo_m_ext(1), | |||
|
241 | apbi => apbi_ext, | |||
|
242 | apbo => apbo_ext(5)); | |||
|
243 | ||||
|
244 | ----------------------------------------------------------------------------- | |||
|
245 | ||||
229 | leon3_soc_1: leon3_soc |
|
246 | leon3_soc_1: leon3_soc | |
230 | GENERIC MAP ( |
|
247 | GENERIC MAP ( | |
231 | fabtech => apa3e, |
|
248 | fabtech => apa3e, | |
232 | memtech => apa3e, |
|
249 | memtech => apa3e, | |
233 | padtech => inferred, |
|
250 | padtech => inferred, | |
234 | clktech => inferred, |
|
251 | clktech => inferred, | |
235 | disas => 0, |
|
252 | disas => 0, | |
236 | dbguart => 0, |
|
253 | dbguart => 0, | |
237 | pclow => 2, |
|
254 | pclow => 2, | |
238 | clk_freq => 25000, |
|
255 | clk_freq => 25000, | |
239 | NB_CPU => 1, |
|
256 | NB_CPU => 1, | |
240 | ENABLE_FPU => 0, |
|
257 | ENABLE_FPU => 0, | |
241 | FPU_NETLIST => 0, |
|
258 | FPU_NETLIST => 0, | |
242 | ENABLE_DSU => 1, |
|
259 | ENABLE_DSU => 1, | |
243 | ENABLE_AHB_UART => 1, |
|
260 | ENABLE_AHB_UART => 1, | |
244 | ENABLE_APB_UART => 1, |
|
261 | ENABLE_APB_UART => 1, | |
245 | ENABLE_IRQMP => 1, |
|
262 | ENABLE_IRQMP => 1, | |
246 | ENABLE_GPT => 1, |
|
263 | ENABLE_GPT => 1, | |
247 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
264 | NB_AHB_MASTER => NB_AHB_MASTER, | |
248 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
265 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
249 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
266 | NB_APB_SLAVE => NB_APB_SLAVE) | |
250 | PORT MAP ( |
|
267 | PORT MAP ( | |
251 | clk => clk_25, |
|
268 | clk => clk_25, | |
252 | reset => reset, |
|
269 | reset => reset, | |
253 | errorn => errorn, |
|
270 | errorn => errorn, | |
254 | ahbrxd => TXD1, |
|
271 | ahbrxd => TXD1, | |
255 | ahbtxd => RXD1, |
|
272 | ahbtxd => RXD1, | |
256 | urxd1 => TXD2, |
|
273 | urxd1 => TXD2, | |
257 | utxd1 => RXD2, |
|
274 | utxd1 => RXD2, | |
258 | address => SRAM_A, |
|
275 | address => SRAM_A, | |
259 | data => SRAM_DQ, |
|
276 | data => SRAM_DQ, | |
260 | nSRAM_BE0 => SRAM_nBE(0), |
|
277 | nSRAM_BE0 => SRAM_nBE(0), | |
261 | nSRAM_BE1 => SRAM_nBE(1), |
|
278 | nSRAM_BE1 => SRAM_nBE(1), | |
262 | nSRAM_BE2 => SRAM_nBE(2), |
|
279 | nSRAM_BE2 => SRAM_nBE(2), | |
263 | nSRAM_BE3 => SRAM_nBE(3), |
|
280 | nSRAM_BE3 => SRAM_nBE(3), | |
264 | nSRAM_WE => SRAM_nWE, |
|
281 | nSRAM_WE => SRAM_nWE, | |
265 | nSRAM_CE => SRAM_CE, |
|
282 | nSRAM_CE => SRAM_CE, | |
266 | nSRAM_OE => SRAM_nOE, |
|
283 | nSRAM_OE => SRAM_nOE, | |
267 |
|
284 | |||
268 | apbi_ext => apbi_ext, |
|
285 | apbi_ext => apbi_ext, | |
269 | apbo_ext => apbo_ext, |
|
286 | apbo_ext => apbo_ext, | |
270 | ahbi_s_ext => ahbi_s_ext, |
|
287 | ahbi_s_ext => ahbi_s_ext, | |
271 | ahbo_s_ext => ahbo_s_ext, |
|
288 | ahbo_s_ext => ahbo_s_ext, | |
272 | ahbi_m_ext => ahbi_m_ext, |
|
289 | ahbi_m_ext => ahbi_m_ext, | |
273 | ahbo_m_ext => ahbo_m_ext); |
|
290 | ahbo_m_ext => ahbo_m_ext); | |
274 |
|
291 | |||
275 |
END beh; |
|
292 | END beh; No newline at end of file |
@@ -1,24 +1,25 | |||||
1 | ./amba_lcd_16x2_ctrlr |
|
1 | ./amba_lcd_16x2_ctrlr | |
2 | ./general_purpose |
|
2 | ./general_purpose | |
3 | ./general_purpose/lpp_AMR |
|
3 | ./general_purpose/lpp_AMR | |
4 | ./general_purpose/lpp_balise |
|
4 | ./general_purpose/lpp_balise | |
5 | ./general_purpose/lpp_delay |
|
5 | ./general_purpose/lpp_delay | |
6 | ./lpp_amba |
|
6 | ./lpp_amba | |
7 | ./dsp/iir_filter |
|
7 | ./dsp/iir_filter | |
8 | ./dsp/lpp_downsampling |
|
8 | ./dsp/lpp_downsampling | |
9 | ./dsp/lpp_fft |
|
9 | ./dsp/lpp_fft | |
10 | ./lfr_time_management |
|
10 | ./lfr_time_management | |
11 | ./lpp_ad_Conv |
|
11 | ./lpp_ad_Conv | |
12 | ./lpp_bootloader |
|
12 | ./lpp_bootloader | |
13 | ./lpp_cna |
|
13 | ./lpp_cna | |
14 | ./lpp_demux |
|
14 | ./lpp_demux | |
15 | ./lpp_Header |
|
15 | ./lpp_Header | |
16 | ./lpp_matrix |
|
16 | ./lpp_matrix | |
17 | ./lpp_memory |
|
17 | ./lpp_memory | |
18 | ./lpp_dma |
|
18 | ./lpp_dma | |
19 | ./lpp_uart |
|
19 | ./lpp_uart | |
20 | ./lpp_usb |
|
20 | ./lpp_usb | |
21 | ./lpp_waveform |
|
21 | ./lpp_waveform | |
22 | ./lpp_top_lfr |
|
22 | ./lpp_top_lfr | |
23 | ./lpp_Header |
|
23 | ./lpp_Header | |
24 | ./lpp_leon3_soc |
|
24 | ./lpp_leon3_soc | |
|
25 | ./lpp_debug_lfr |
@@ -1,41 +1,43 | |||||
1 |
|
1 | |||
2 | --================================================================================= |
|
2 | --================================================================================= | |
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT |
|
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT | |
4 | -- |
|
4 | -- | |
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID |
|
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID | |
6 | --================================================================================= |
|
6 | --================================================================================= | |
7 |
|
7 | |||
8 |
|
8 | |||
9 | LIBRARY ieee; |
|
9 | LIBRARY ieee; | |
10 | USE ieee.std_logic_1164.ALL; |
|
10 | USE ieee.std_logic_1164.ALL; | |
11 | LIBRARY grlib; |
|
11 | LIBRARY grlib; | |
12 | USE grlib.amba.ALL; |
|
12 | USE grlib.amba.ALL; | |
13 | USE std.textio.ALL; |
|
13 | USE std.textio.ALL; | |
14 |
|
14 | |||
15 |
|
15 | |||
16 | PACKAGE apb_devices_list IS |
|
16 | PACKAGE apb_devices_list IS | |
17 |
|
17 | |||
18 |
|
18 | |||
19 | CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#; |
|
19 | CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#; | |
20 |
|
20 | |||
21 | CONSTANT ROCKET_TM : amba_device_type := 16#1#; |
|
21 | CONSTANT ROCKET_TM : amba_device_type := 16#1#; | |
22 | CONSTANT otherCore : amba_device_type := 16#2#; |
|
22 | CONSTANT otherCore : amba_device_type := 16#2#; | |
23 | CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#; |
|
23 | CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#; | |
24 | CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#; |
|
24 | CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#; | |
25 | CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#; |
|
25 | CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#; | |
26 | CONSTANT LPP_UART : amba_device_type := 16#6#; |
|
26 | CONSTANT LPP_UART : amba_device_type := 16#6#; | |
27 | CONSTANT LPP_CNA : amba_device_type := 16#7#; |
|
27 | CONSTANT LPP_CNA : amba_device_type := 16#7#; | |
28 | CONSTANT LPP_APB_ADC : amba_device_type := 16#8#; |
|
28 | CONSTANT LPP_APB_ADC : amba_device_type := 16#8#; | |
29 | CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#; |
|
29 | CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#; | |
30 | CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; |
|
30 | CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; | |
31 | CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#; |
|
31 | CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#; | |
32 | CONSTANT LPP_FFT : amba_device_type := 16#12#; |
|
32 | CONSTANT LPP_FFT : amba_device_type := 16#12#; | |
33 | CONSTANT LPP_MATRIX : amba_device_type := 16#13#; |
|
33 | CONSTANT LPP_MATRIX : amba_device_type := 16#13#; | |
34 | CONSTANT LPP_DELAY : amba_device_type := 16#14#; |
|
34 | CONSTANT LPP_DELAY : amba_device_type := 16#14#; | |
35 | CONSTANT LPP_USB : amba_device_type := 16#15#; |
|
35 | CONSTANT LPP_USB : amba_device_type := 16#15#; | |
36 | CONSTANT LPP_BALISE : amba_device_type := 16#16#; |
|
36 | CONSTANT LPP_BALISE : amba_device_type := 16#16#; | |
37 | CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#; |
|
37 | CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#; | |
38 | CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; |
|
38 | CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; | |
39 | CONSTANT LPP_LFR : amba_device_type := 16#19#; |
|
39 | CONSTANT LPP_LFR : amba_device_type := 16#19#; | |
40 |
|
40 | |||
|
41 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |||
|
42 | ||||
41 | END; |
|
43 | END; |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
1 | NO CONTENT: file was removed |
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NO CONTENT: file was removed |
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