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(MINI-LFR) 0.1.44...
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r502:c71ce0e554fc (MINI-LFR) WFP_MS-0-1-46 (LFR-EM) WFP_MS_1-1-47 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 -- HK ---------------------------------------------------------------------
86 86 HK_smpclk : OUT STD_LOGIC;
87 87 ADC_OEB_bar_HK : OUT STD_LOGIC;
88 88 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
89 89 ---------------------------------------------------------------------------
90 90 TAG8 : OUT STD_LOGIC;
91 91 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
92 92 );
93 93
94 94 END LFR_em;
95 95
96 96
97 97 ARCHITECTURE beh OF LFR_em IS
98 98 SIGNAL clk_50_s : STD_LOGIC := '0';
99 99 SIGNAL clk_25 : STD_LOGIC := '0';
100 100 SIGNAL clk_24 : STD_LOGIC := '0';
101 101 -----------------------------------------------------------------------------
102 102 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 103 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
104 104
105 105 -- CONSTANTS
106 106 CONSTANT CFG_PADTECH : INTEGER := inferred;
107 107 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
108 108 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
109 109 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
110 110
111 111 SIGNAL apbi_ext : apb_slv_in_type;
112 112 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
113 113 SIGNAL ahbi_s_ext : ahb_slv_in_type;
114 114 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
115 115 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
116 116 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
117 117
118 118 -- Spacewire signals
119 119 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 120 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 121 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 122 SIGNAL spw_rxtxclk : STD_ULOGIC;
123 123 SIGNAL spw_rxclkn : STD_ULOGIC;
124 124 SIGNAL spw_clk : STD_LOGIC;
125 125 SIGNAL swni : grspw_in_type;
126 126 SIGNAL swno : grspw_out_type;
127 127
128 128 --GPIO
129 129 SIGNAL gpioi : gpio_in_type;
130 130 SIGNAL gpioo : gpio_out_type;
131 131
132 132 -- AD Converter ADS7886
133 133 SIGNAL sample : Samples14v(8 DOWNTO 0);
134 134 SIGNAL sample_s : Samples(8 DOWNTO 0);
135 135 SIGNAL sample_val : STD_LOGIC;
136 136 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
137 137
138 138 -----------------------------------------------------------------------------
139 139 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 140
141 141 -----------------------------------------------------------------------------
142 142 SIGNAL rstn : STD_LOGIC;
143 143
144 144 SIGNAL LFR_soft_rstn : STD_LOGIC;
145 145 SIGNAL LFR_rstn : STD_LOGIC;
146 146
147 147 SIGNAL ADC_smpclk_s : STD_LOGIC;
148 148 -----------------------------------------------------------------------------
149 149 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150
151 151 BEGIN -- beh
152 152
153 153 -----------------------------------------------------------------------------
154 154 -- CLK
155 155 -----------------------------------------------------------------------------
156 156 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
157 157
158 158 PROCESS(clk100MHz)
159 159 BEGIN
160 160 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
161 161 clk_50_s <= NOT clk_50_s;
162 162 END IF;
163 163 END PROCESS;
164 164
165 165 PROCESS(clk_50_s)
166 166 BEGIN
167 167 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
168 168 clk_25 <= NOT clk_25;
169 169 END IF;
170 170 END PROCESS;
171 171
172 172 PROCESS(clk49_152MHz)
173 173 BEGIN
174 174 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
175 175 clk_24 <= NOT clk_24;
176 176 END IF;
177 177 END PROCESS;
178 178
179 179 -----------------------------------------------------------------------------
180 180
181 181 PROCESS (clk_25, rstn)
182 182 BEGIN -- PROCESS
183 183 IF rstn = '0' THEN -- asynchronous reset (active low)
184 184 led(0) <= '0';
185 185 led(1) <= '0';
186 186 led(2) <= '0';
187 187 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
188 188 led(0) <= '0';
189 189 led(1) <= '1';
190 190 led(2) <= '1';
191 191 END IF;
192 192 END PROCESS;
193 193
194 194 --
195 195 leon3_soc_1 : leon3_soc
196 196 GENERIC MAP (
197 197 fabtech => apa3e,
198 198 memtech => apa3e,
199 199 padtech => inferred,
200 200 clktech => inferred,
201 201 disas => 0,
202 202 dbguart => 0,
203 203 pclow => 2,
204 204 clk_freq => 25000,
205 205 NB_CPU => 1,
206 206 ENABLE_FPU => 1,
207 207 FPU_NETLIST => 0,
208 208 ENABLE_DSU => 1,
209 209 ENABLE_AHB_UART => 1,
210 210 ENABLE_APB_UART => 1,
211 211 ENABLE_IRQMP => 1,
212 212 ENABLE_GPT => 1,
213 213 NB_AHB_MASTER => NB_AHB_MASTER,
214 214 NB_AHB_SLAVE => NB_AHB_SLAVE,
215 215 NB_APB_SLAVE => NB_APB_SLAVE,
216 216 ADDRESS_SIZE => 20,
217 217 USES_IAP_MEMCTRLR => 0)
218 218 PORT MAP (
219 219 clk => clk_25,
220 220 reset => rstn,
221 221 errorn => OPEN,
222 222
223 223 ahbrxd => TAG1,
224 224 ahbtxd => TAG3,
225 225 urxd1 => TAG2,
226 226 utxd1 => TAG4,
227 227
228 228 address => address,
229 229 data => data,
230 230 nSRAM_BE0 => nSRAM_BE0,
231 231 nSRAM_BE1 => nSRAM_BE1,
232 232 nSRAM_BE2 => nSRAM_BE2,
233 233 nSRAM_BE3 => nSRAM_BE3,
234 234 nSRAM_WE => nSRAM_WE,
235 235 nSRAM_CE => nSRAM_CE_s,
236 236 nSRAM_OE => nSRAM_OE,
237 237 nSRAM_READY => '0',
238 238 SRAM_MBE => OPEN,
239 239
240 240 apbi_ext => apbi_ext,
241 241 apbo_ext => apbo_ext,
242 242 ahbi_s_ext => ahbi_s_ext,
243 243 ahbo_s_ext => ahbo_s_ext,
244 244 ahbi_m_ext => ahbi_m_ext,
245 245 ahbo_m_ext => ahbo_m_ext);
246 246
247 247
248 248 nSRAM_CE <= nSRAM_CE_s(0);
249 249
250 250 -------------------------------------------------------------------------------
251 251 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
252 252 -------------------------------------------------------------------------------
253 253 apb_lfr_time_management_1 : apb_lfr_time_management
254 254 GENERIC MAP (
255 255 pindex => 6,
256 256 paddr => 6,
257 257 pmask => 16#fff#,
258 258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
259 259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
260 260 PORT MAP (
261 261 clk25MHz => clk_25,
262 262 clk24_576MHz => clk_24, -- 49.152MHz/2
263 263 resetn => rstn,
264 264 grspw_tick => swno.tickout,
265 265 apbi => apbi_ext,
266 266 apbo => apbo_ext(6),
267 267 coarse_time => coarse_time,
268 268 fine_time => fine_time,
269 269 LFR_soft_rstn => LFR_soft_rstn
270 270 );
271 271
272 272 -----------------------------------------------------------------------
273 273 --- SpaceWire --------------------------------------------------------
274 274 -----------------------------------------------------------------------
275 275
276 276 -- SPW_EN <= '1';
277 277
278 278 spw_clk <= clk_50_s;
279 279 spw_rxtxclk <= spw_clk;
280 280 spw_rxclkn <= NOT spw_rxtxclk;
281 281
282 282 -- PADS for SPW1
283 283 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
284 284 PORT MAP (spw1_din, dtmp(0));
285 285 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
286 286 PORT MAP (spw1_sin, stmp(0));
287 287 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
288 288 PORT MAP (spw1_dout, swno.d(0));
289 289 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
290 290 PORT MAP (spw1_sout, swno.s(0));
291 291 -- PADS FOR SPW2
292 292 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
293 293 PORT MAP (spw2_din, dtmp(1));
294 294 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
295 295 PORT MAP (spw2_sin, stmp(1));
296 296 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
297 297 PORT MAP (spw2_dout, swno.d(1));
298 298 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
299 299 PORT MAP (spw2_sout, swno.s(1));
300 300
301 301 -- GRSPW PHY
302 302 --spw1_input: if CFG_SPW_GRSPW = 1 generate
303 303 spw_inputloop : FOR j IN 0 TO 1 GENERATE
304 304 spw_phy0 : grspw_phy
305 305 GENERIC MAP(
306 306 tech => apa3e,
307 307 rxclkbuftype => 1,
308 308 scantest => 0)
309 309 PORT MAP(
310 310 rxrst => swno.rxrst,
311 311 di => dtmp(j),
312 312 si => stmp(j),
313 313 rxclko => spw_rxclk(j),
314 314 do => swni.d(j),
315 315 ndo => swni.nd(j*5+4 DOWNTO j*5),
316 316 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
317 317 END GENERATE spw_inputloop;
318 318
319 319 -- SPW core
320 320 sw0 : grspwm GENERIC MAP(
321 321 tech => apa3e,
322 322 hindex => 1,
323 323 pindex => 5,
324 324 paddr => 5,
325 325 pirq => 11,
326 326 sysfreq => 25000, -- CPU_FREQ
327 327 rmap => 1,
328 328 rmapcrc => 1,
329 329 fifosize1 => 16,
330 330 fifosize2 => 16,
331 331 rxclkbuftype => 1,
332 332 rxunaligned => 0,
333 333 rmapbufs => 4,
334 334 ft => 0,
335 335 netlist => 0,
336 336 ports => 2,
337 337 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
338 338 memtech => apa3e,
339 339 destkey => 2,
340 340 spwcore => 1
341 341 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
342 342 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
343 343 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
344 344 )
345 345 PORT MAP(rstn, clk_25, spw_rxclk(0),
346 346 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
347 347 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
348 348 swni, swno);
349 349
350 350 swni.tickin <= '0';
351 351 swni.rmapen <= '1';
352 352 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
353 353 swni.tickinraw <= '0';
354 354 swni.timein <= (OTHERS => '0');
355 355 swni.dcrstval <= (OTHERS => '0');
356 356 swni.timerrstval <= (OTHERS => '0');
357 357
358 358 -------------------------------------------------------------------------------
359 359 -- LFR ------------------------------------------------------------------------
360 360 -------------------------------------------------------------------------------
361 361 LFR_rstn <= LFR_soft_rstn AND rstn;
362 362
363 363 lpp_lfr_1 : lpp_lfr
364 364 GENERIC MAP (
365 365 Mem_use => use_RAM,
366 366 nb_data_by_buffer_size => 32,
367 367 --nb_word_by_buffer_size => 30,
368 368 nb_snapshot_param_size => 32,
369 369 delta_vector_size => 32,
370 370 delta_vector_size_f0_2 => 7, -- log2(96)
371 371 pindex => 15,
372 372 paddr => 15,
373 373 pmask => 16#fff#,
374 374 pirq_ms => 6,
375 375 pirq_wfp => 14,
376 376 hindex => 2,
377 top_lfr_version => X"01012D") -- aa.bb.cc version
377 top_lfr_version => X"01012F") -- aa.bb.cc version
378 378 -- AA : BOARD NUMBER
379 379 -- 0 => MINI_LFR
380 380 -- 1 => EM
381 381 PORT MAP (
382 382 clk => clk_25,
383 383 rstn => LFR_rstn,
384 384 sample_B => sample_s(2 DOWNTO 0),
385 385 sample_E => sample_s(7 DOWNTO 3),
386 386 sample_val => sample_val,
387 387 apbi => apbi_ext,
388 388 apbo => apbo_ext(15),
389 389 ahbi => ahbi_m_ext,
390 390 ahbo => ahbo_m_ext(2),
391 391 coarse_time => coarse_time,
392 392 fine_time => fine_time,
393 393 data_shaping_BW => bias_fail_sw,
394 394 debug_vector => OPEN,
395 395 debug_vector_ms => OPEN); --,
396 396 --observation_vector_0 => OPEN,
397 397 --observation_vector_1 => OPEN,
398 398 --observation_reg => observation_reg);
399 399
400 400
401 401 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
402 402 sample_s(I) <= sample(I) & '0' & '0';
403 403 END GENERATE all_sample;
404 404 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
405 405
406 406 -----------------------------------------------------------------------------
407 407 --
408 408 -----------------------------------------------------------------------------
409 409 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
410 410 GENERIC MAP (
411 411 ChanelCount => 9,
412 412 ncycle_cnv_high => 13,
413 413 ncycle_cnv => 25,
414 414 FILTER_ENABLED => 16#FF#)
415 415 PORT MAP (
416 416 cnv_clk => clk_24,
417 417 cnv_rstn => rstn,
418 418 cnv => ADC_smpclk_s,
419 419 clk => clk_25,
420 420 rstn => rstn,
421 421 ADC_data => ADC_data,
422 422 ADC_nOE => ADC_OEB_bar_CH_s,
423 423 sample => sample,
424 424 sample_val => sample_val);
425 425
426 426 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
427 427
428 428 ADC_smpclk <= ADC_smpclk_s;
429 429 HK_smpclk <= ADC_smpclk_s;
430 430
431 431 TAG8 <= ADC_smpclk_s;
432 432
433 433 -----------------------------------------------------------------------------
434 434 -- HK
435 435 -----------------------------------------------------------------------------
436 436 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
437 437
438 438 lpp_lfr_hk_1: lpp_lfr_hk
439 439 GENERIC MAP (
440 440 pindex => 7,
441 441 paddr => 7,
442 442 pmask => 16#fff#)
443 443 PORT MAP (
444 444 clk => clk_25,
445 445 rstn => rstn,
446 446
447 447 apbi => apbi_ext,
448 448 apbo => apbo_ext(7),
449 449
450 450 sample_val => sample_val,
451 451 sample => sample_s(8),
452 452 HK_SEL => HK_SEL);
453 453
454 454 END beh;
Show file before | Show file after | Hide comments
@@ -1,720 +1,746
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
199 --
200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
198 202
199 203 BEGIN -- beh
200 204
201 205 -----------------------------------------------------------------------------
202 206 -- CLK
203 207 -----------------------------------------------------------------------------
204 208
205 209 --PROCESS(clk_50)
206 210 --BEGIN
207 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
208 212 -- clk_50_s <= NOT clk_50_s;
209 213 -- END IF;
210 214 --END PROCESS;
211 215
212 216 --PROCESS(clk_50_s)
213 217 --BEGIN
214 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
215 219 -- clk_25 <= NOT clk_25;
216 220 -- END IF;
217 221 --END PROCESS;
218 222
219 223 --PROCESS(clk_49)
220 224 --BEGIN
221 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
222 226 -- clk_24 <= NOT clk_24;
223 227 -- END IF;
224 228 --END PROCESS;
225 229
226 230 --PROCESS(clk_25)
227 231 --BEGIN
228 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
229 233 -- rstn_25 <= reset;
230 234 -- END IF;
231 235 --END PROCESS;
232 236
233 237 PROCESS (clk_50, reset)
234 238 BEGIN -- PROCESS
235 239 IF reset = '0' THEN -- asynchronous reset (active low)
236 240 clk_50_s <= '0';
237 241 rstn_50 <= '0';
238 242 rstn_50_d1 <= '0';
239 243 rstn_50_d2 <= '0';
240 244 rstn_50_d3 <= '0';
241 245
242 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
243 247 clk_50_s <= NOT clk_50_s;
244 248 rstn_50_d1 <= '1';
245 249 rstn_50_d2 <= rstn_50_d1;
246 250 rstn_50_d3 <= rstn_50_d2;
247 251 rstn_50 <= rstn_50_d3;
248 252 END IF;
249 253 END PROCESS;
250 254
251 255 PROCESS (clk_50_s, rstn_50)
252 256 BEGIN -- PROCESS
253 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
254 258 clk_25 <= '0';
255 259 rstn_25 <= '0';
256 260 rstn_25_d1 <= '0';
257 261 rstn_25_d2 <= '0';
258 262 rstn_25_d3 <= '0';
259 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
260 264 clk_25 <= NOT clk_25;
261 265 rstn_25_d1 <= '1';
262 266 rstn_25_d2 <= rstn_25_d1;
263 267 rstn_25_d3 <= rstn_25_d2;
264 268 rstn_25 <= rstn_25_d3;
265 269 END IF;
266 270 END PROCESS;
267 271
268 272 PROCESS (clk_49, reset)
269 273 BEGIN -- PROCESS
270 274 IF reset = '0' THEN -- asynchronous reset (active low)
271 275 clk_24 <= '0';
272 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
273 277 clk_24 <= NOT clk_24;
274 278 END IF;
275 279 END PROCESS;
276 280
277 281 -----------------------------------------------------------------------------
278 282
279 283 PROCESS (clk_25, rstn_25)
280 284 BEGIN -- PROCESS
281 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
282 286 LED0 <= '0';
283 287 LED1 <= '0';
284 288 LED2 <= '0';
285 289 --IO1 <= '0';
286 290 --IO2 <= '1';
287 291 --IO3 <= '0';
288 292 --IO4 <= '0';
289 293 --IO5 <= '0';
290 294 --IO6 <= '0';
291 295 --IO7 <= '0';
292 296 --IO8 <= '0';
293 297 --IO9 <= '0';
294 298 --IO10 <= '0';
295 299 --IO11 <= '0';
296 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
297 301 LED0 <= '0';
298 302 LED1 <= '1';
299 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
300 304 --IO1 <= '1';
301 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
302 306 --IO3 <= ADC_SDO(0);
303 307 --IO4 <= ADC_SDO(1);
304 308 --IO5 <= ADC_SDO(2);
305 309 --IO6 <= ADC_SDO(3);
306 310 --IO7 <= ADC_SDO(4);
307 311 --IO8 <= ADC_SDO(5);
308 312 --IO9 <= ADC_SDO(6);
309 313 --IO10 <= ADC_SDO(7);
310 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
311 315 END IF;
312 316 END PROCESS;
313 317
314 318 PROCESS (clk_24, rstn_25)
315 319 BEGIN -- PROCESS
316 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
317 321 I00_s <= '0';
318 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
319 323 I00_s <= NOT I00_s;
320 324 END IF;
321 325 END PROCESS;
322 326 -- IO0 <= I00_s;
323 327
324 328 --UARTs
325 329 nCTS1 <= '1';
326 330 nCTS2 <= '1';
327 331 nDCD2 <= '1';
328 332
329 333 --EXT CONNECTOR
330 334
331 335 --SPACE WIRE
332 336
333 337 leon3_soc_1 : leon3_soc
334 338 GENERIC MAP (
335 339 fabtech => apa3e,
336 340 memtech => apa3e,
337 341 padtech => inferred,
338 342 clktech => inferred,
339 343 disas => 0,
340 344 dbguart => 0,
341 345 pclow => 2,
342 346 clk_freq => 25000,
343 347 NB_CPU => 1,
344 348 ENABLE_FPU => 1,
345 349 FPU_NETLIST => 0,
346 350 ENABLE_DSU => 1,
347 351 ENABLE_AHB_UART => 1,
348 352 ENABLE_APB_UART => 1,
349 353 ENABLE_IRQMP => 1,
350 354 ENABLE_GPT => 1,
351 355 NB_AHB_MASTER => NB_AHB_MASTER,
352 356 NB_AHB_SLAVE => NB_AHB_SLAVE,
353 357 NB_APB_SLAVE => NB_APB_SLAVE,
354 358 ADDRESS_SIZE => 20,
355 359 USES_IAP_MEMCTRLR => 0)
356 360 PORT MAP (
357 361 clk => clk_25,
358 362 reset => rstn_25,
359 363 errorn => errorn,
360 364 ahbrxd => TXD1,
361 365 ahbtxd => RXD1,
362 366 urxd1 => TXD2,
363 367 utxd1 => RXD2,
364 368 address => SRAM_A,
365 369 data => SRAM_DQ,
366 370 nSRAM_BE0 => SRAM_nBE(0),
367 371 nSRAM_BE1 => SRAM_nBE(1),
368 372 nSRAM_BE2 => SRAM_nBE(2),
369 373 nSRAM_BE3 => SRAM_nBE(3),
370 374 nSRAM_WE => SRAM_nWE,
371 375 nSRAM_CE => SRAM_CE_s,
372 376 nSRAM_OE => SRAM_nOE,
373 377 nSRAM_READY => '0',
374 378 SRAM_MBE => OPEN,
375 379 apbi_ext => apbi_ext,
376 380 apbo_ext => apbo_ext,
377 381 ahbi_s_ext => ahbi_s_ext,
378 382 ahbo_s_ext => ahbo_s_ext,
379 383 ahbi_m_ext => ahbi_m_ext,
380 384 ahbo_m_ext => ahbo_m_ext);
381 385
382 386 SRAM_CE <= SRAM_CE_s(0);
383 387 -------------------------------------------------------------------------------
384 388 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
385 389 -------------------------------------------------------------------------------
386 390 apb_lfr_time_management_1 : apb_lfr_time_management
387 391 GENERIC MAP (
388 392 pindex => 6,
389 393 paddr => 6,
390 394 pmask => 16#fff#,
391 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
392 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
393 397 PORT MAP (
394 398 clk25MHz => clk_25,
395 399 clk24_576MHz => clk_24, -- 49.152MHz/2
396 400 resetn => rstn_25,
397 401 grspw_tick => swno.tickout,
398 402 apbi => apbi_ext,
399 403 apbo => apbo_ext(6),
400 404 coarse_time => coarse_time,
401 405 fine_time => fine_time,
402 406 LFR_soft_rstn => LFR_soft_rstn
403 407 );
404 408
405 409 -----------------------------------------------------------------------
406 410 --- SpaceWire --------------------------------------------------------
407 411 -----------------------------------------------------------------------
408 412
409 413 SPW_EN <= '1';
410 414
411 415 spw_clk <= clk_50_s;
412 416 spw_rxtxclk <= spw_clk;
413 417 spw_rxclkn <= NOT spw_rxtxclk;
414 418
415 419 -- PADS for SPW1
416 420 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
417 421 PORT MAP (SPW_NOM_DIN, dtmp(0));
418 422 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
419 423 PORT MAP (SPW_NOM_SIN, stmp(0));
420 424 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
421 425 PORT MAP (SPW_NOM_DOUT, swno.d(0));
422 426 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
423 427 PORT MAP (SPW_NOM_SOUT, swno.s(0));
424 428 -- PADS FOR SPW2
425 429 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
426 430 PORT MAP (SPW_RED_SIN, dtmp(1));
427 431 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
428 432 PORT MAP (SPW_RED_DIN, stmp(1));
429 433 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
430 434 PORT MAP (SPW_RED_DOUT, swno.d(1));
431 435 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
432 436 PORT MAP (SPW_RED_SOUT, swno.s(1));
433 437
434 438 -- GRSPW PHY
435 439 --spw1_input: if CFG_SPW_GRSPW = 1 generate
436 440 spw_inputloop : FOR j IN 0 TO 1 GENERATE
437 441 spw_phy0 : grspw_phy
438 442 GENERIC MAP(
439 443 tech => apa3e,
440 444 rxclkbuftype => 1,
441 445 scantest => 0)
442 446 PORT MAP(
443 447 rxrst => swno.rxrst,
444 448 di => dtmp(j),
445 449 si => stmp(j),
446 450 rxclko => spw_rxclk(j),
447 451 do => swni.d(j),
448 452 ndo => swni.nd(j*5+4 DOWNTO j*5),
449 453 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
450 454 END GENERATE spw_inputloop;
451 455
452 456 swni.rmapnodeaddr <= (OTHERS => '0');
453 457
454 458 -- SPW core
455 459 sw0 : grspwm GENERIC MAP(
456 460 tech => apa3e,
457 461 hindex => 1,
458 462 pindex => 5,
459 463 paddr => 5,
460 464 pirq => 11,
461 465 sysfreq => 25000, -- CPU_FREQ
462 466 rmap => 1,
463 467 rmapcrc => 1,
464 468 fifosize1 => 16,
465 469 fifosize2 => 16,
466 470 rxclkbuftype => 1,
467 471 rxunaligned => 0,
468 472 rmapbufs => 4,
469 473 ft => 0,
470 474 netlist => 0,
471 475 ports => 2,
472 476 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
473 477 memtech => apa3e,
474 478 destkey => 2,
475 479 spwcore => 1
476 480 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
477 481 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
478 482 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
479 483 )
480 484 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
481 485 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
482 486 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
483 487 swni, swno);
484 488
485 489 swni.tickin <= '0';
486 490 swni.rmapen <= '1';
487 491 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
488 492 swni.tickinraw <= '0';
489 493 swni.timein <= (OTHERS => '0');
490 494 swni.dcrstval <= (OTHERS => '0');
491 495 swni.timerrstval <= (OTHERS => '0');
492 496
493 497 -------------------------------------------------------------------------------
494 498 -- LFR ------------------------------------------------------------------------
495 499 -------------------------------------------------------------------------------
496 500
497 501
498 502 LFR_rstn <= LFR_soft_rstn AND rstn_25;
499 503 --LFR_rstn <= rstn_25;
500 504
501 505 lpp_lfr_1 : lpp_lfr
502 506 GENERIC MAP (
503 507 Mem_use => use_RAM,
504 508 nb_data_by_buffer_size => 32,
505 509 nb_snapshot_param_size => 32,
506 510 delta_vector_size => 32,
507 511 delta_vector_size_f0_2 => 7, -- log2(96)
508 512 pindex => 15,
509 513 paddr => 15,
510 514 pmask => 16#fff#,
511 515 pirq_ms => 6,
512 516 pirq_wfp => 14,
513 517 hindex => 2,
514 top_lfr_version => X"00012C") -- aa.bb.cc version
518 top_lfr_version => X"00012E") -- aa.bb.cc version
515 519 PORT MAP (
516 520 clk => clk_25,
517 521 rstn => LFR_rstn,
518 522 sample_B => sample_s(2 DOWNTO 0),
519 523 sample_E => sample_s(7 DOWNTO 3),
520 524 sample_val => sample_val,
521 525 apbi => apbi_ext,
522 526 apbo => apbo_ext(15),
523 527 ahbi => ahbi_m_ext,
524 528 ahbo => ahbo_m_ext(2),
525 529 coarse_time => coarse_time,
526 530 fine_time => fine_time,
527 531 data_shaping_BW => bias_fail_sw_sig,
528 532 debug_vector => lfr_debug_vector,
529 533 debug_vector_ms => lfr_debug_vector_ms
530 534 );
531 535
532 536 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
533 537 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
534 538 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
535 539 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
536 540 IO0 <= rstn_25;
537 541 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
538 542 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
539 543 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
540 544 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
541 545 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
542 546 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
543 547 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
544 548
545 549 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
546 550 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
547 551 END GENERATE all_sample;
548 552
549 553 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
550 554 GENERIC MAP(
551 555 ChannelCount => 8,
552 556 SampleNbBits => 14,
553 557 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
554 558 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
555 559 PORT MAP (
556 560 -- CONV
557 561 cnv_clk => clk_24,
558 562 cnv_rstn => rstn_25,
559 563 cnv => ADC_nCS_sig,
560 564 -- DATA
561 565 clk => clk_25,
562 566 rstn => rstn_25,
563 567 sck => ADC_CLK_sig,
564 568 sdo => ADC_SDO_sig,
565 569 -- SAMPLE
566 570 sample => sample,
567 571 sample_val => sample_val);
568 572
569 573 --IO10 <= ADC_SDO_sig(5);
570 574 --IO9 <= ADC_SDO_sig(4);
571 575 --IO8 <= ADC_SDO_sig(3);
572 576
573 577 ADC_nCS <= ADC_nCS_sig;
574 578 ADC_CLK <= ADC_CLK_sig;
575 579 ADC_SDO_sig <= ADC_SDO;
576 580
581 lpp_lfr_hk_1: lpp_lfr_hk
582 GENERIC MAP (
583 pindex => 7,
584 paddr => 7,
585 pmask => 16#fff#)
586 PORT MAP (
587 clk => clk_25,
588 rstn => rstn_25,
589
590 apbi => apbi_ext,
591 apbo => apbo_ext(7),
592
593 sample_val => sample_val,
594 sample => sample_hk,
595 HK_SEL => HK_SEL);
596
597 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
598 "0010001000100010" WHEN HK_SEL = "10" ELSE
599 "0100010001000100" WHEN HK_SEL = "10" ELSE
600 (OTHERS => '0');
601
602
577 603 ----------------------------------------------------------------------
578 604 --- GPIO -----------------------------------------------------------
579 605 ----------------------------------------------------------------------
580 606
581 607 grgpio0 : grgpio
582 608 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
583 609 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
584 610
585 611 gpioi.sig_en <= (OTHERS => '0');
586 612 gpioi.sig_in <= (OTHERS => '0');
587 613 gpioi.din <= (OTHERS => '0');
588 614 --pio_pad_0 : iopad
589 615 -- GENERIC MAP (tech => CFG_PADTECH)
590 616 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
591 617 --pio_pad_1 : iopad
592 618 -- GENERIC MAP (tech => CFG_PADTECH)
593 619 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
594 620 --pio_pad_2 : iopad
595 621 -- GENERIC MAP (tech => CFG_PADTECH)
596 622 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
597 623 --pio_pad_3 : iopad
598 624 -- GENERIC MAP (tech => CFG_PADTECH)
599 625 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
600 626 --pio_pad_4 : iopad
601 627 -- GENERIC MAP (tech => CFG_PADTECH)
602 628 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
603 629 --pio_pad_5 : iopad
604 630 -- GENERIC MAP (tech => CFG_PADTECH)
605 631 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
606 632 --pio_pad_6 : iopad
607 633 -- GENERIC MAP (tech => CFG_PADTECH)
608 634 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
609 635 --pio_pad_7 : iopad
610 636 -- GENERIC MAP (tech => CFG_PADTECH)
611 637 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
612 638
613 639 PROCESS (clk_25, rstn_25)
614 640 BEGIN -- PROCESS
615 641 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
616 642 -- --IO0 <= '0';
617 643 -- IO1 <= '0';
618 644 -- IO2 <= '0';
619 645 -- IO3 <= '0';
620 646 -- IO4 <= '0';
621 647 -- IO5 <= '0';
622 648 -- IO6 <= '0';
623 649 -- IO7 <= '0';
624 650 IO8 <= '0';
625 651 IO9 <= '0';
626 652 IO10 <= '0';
627 653 IO11 <= '0';
628 654 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
629 655 CASE gpioo.dout(2 DOWNTO 0) IS
630 656 WHEN "011" =>
631 657 -- --IO0 <= observation_reg(0 );
632 658 -- IO1 <= observation_reg(1 );
633 659 -- IO2 <= observation_reg(2 );
634 660 -- IO3 <= observation_reg(3 );
635 661 -- IO4 <= observation_reg(4 );
636 662 -- IO5 <= observation_reg(5 );
637 663 -- IO6 <= observation_reg(6 );
638 664 -- IO7 <= observation_reg(7 );
639 665 IO8 <= observation_reg(8);
640 666 IO9 <= observation_reg(9);
641 667 IO10 <= observation_reg(10);
642 668 IO11 <= observation_reg(11);
643 669 WHEN "001" =>
644 670 -- --IO0 <= observation_reg(0 + 12);
645 671 -- IO1 <= observation_reg(1 + 12);
646 672 -- IO2 <= observation_reg(2 + 12);
647 673 -- IO3 <= observation_reg(3 + 12);
648 674 -- IO4 <= observation_reg(4 + 12);
649 675 -- IO5 <= observation_reg(5 + 12);
650 676 -- IO6 <= observation_reg(6 + 12);
651 677 -- IO7 <= observation_reg(7 + 12);
652 678 IO8 <= observation_reg(8 + 12);
653 679 IO9 <= observation_reg(9 + 12);
654 680 IO10 <= observation_reg(10 + 12);
655 681 IO11 <= observation_reg(11 + 12);
656 682 WHEN "010" =>
657 683 -- --IO0 <= observation_reg(0 + 12 + 12);
658 684 -- IO1 <= observation_reg(1 + 12 + 12);
659 685 -- IO2 <= observation_reg(2 + 12 + 12);
660 686 -- IO3 <= observation_reg(3 + 12 + 12);
661 687 -- IO4 <= observation_reg(4 + 12 + 12);
662 688 -- IO5 <= observation_reg(5 + 12 + 12);
663 689 -- IO6 <= observation_reg(6 + 12 + 12);
664 690 -- IO7 <= observation_reg(7 + 12 + 12);
665 691 IO8 <= '0';
666 692 IO9 <= '0';
667 693 IO10 <= '0';
668 694 IO11 <= '0';
669 695 WHEN "000" =>
670 696 -- --IO0 <= observation_vector_0(0 );
671 697 -- IO1 <= observation_vector_0(1 );
672 698 -- IO2 <= observation_vector_0(2 );
673 699 -- IO3 <= observation_vector_0(3 );
674 700 -- IO4 <= observation_vector_0(4 );
675 701 -- IO5 <= observation_vector_0(5 );
676 702 -- IO6 <= observation_vector_0(6 );
677 703 -- IO7 <= observation_vector_0(7 );
678 704 IO8 <= observation_vector_0(8);
679 705 IO9 <= observation_vector_0(9);
680 706 IO10 <= observation_vector_0(10);
681 707 IO11 <= observation_vector_0(11);
682 708 WHEN "100" =>
683 709 -- --IO0 <= observation_vector_1(0 );
684 710 -- IO1 <= observation_vector_1(1 );
685 711 -- IO2 <= observation_vector_1(2 );
686 712 -- IO3 <= observation_vector_1(3 );
687 713 -- IO4 <= observation_vector_1(4 );
688 714 -- IO5 <= observation_vector_1(5 );
689 715 -- IO6 <= observation_vector_1(6 );
690 716 -- IO7 <= observation_vector_1(7 );
691 717 IO8 <= observation_vector_1(8);
692 718 IO9 <= observation_vector_1(9);
693 719 IO10 <= observation_vector_1(10);
694 720 IO11 <= observation_vector_1(11);
695 721 WHEN OTHERS => NULL;
696 722 END CASE;
697 723
698 724 END IF;
699 725 END PROCESS;
700 726 -----------------------------------------------------------------------------
701 727 --
702 728 -----------------------------------------------------------------------------
703 729 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
730 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 7 AND I /= 11 AND I /= 15 GENERATE
705 731 apbo_ext(I) <= apb_none;
706 732 END GENERATE apbo_ext_not_used;
707 733 END GENERATE all_apbo_ext;
708 734
709 735
710 736 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
711 737 ahbo_s_ext(I) <= ahbs_none;
712 738 END GENERATE all_ahbo_ext;
713 739
714 740 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
715 741 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
716 742 ahbo_m_ext(I) <= ahbm_none;
717 743 END GENERATE ahbo_m_ext_not_used;
718 744 END GENERATE all_ahbo_m_ext;
719 745
720 746 END beh;
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