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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 library lpp;
25 use work.fft_components.all;
26 26 use lpp.lpp_fft.all;
27 use work.fft_components.all;
27
28 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
28 29
29 30 entity FFT is
30 31 generic(
31 32 Data_sz : integer := 16;
32 33 NbData : integer := 256);
33 34 port(
34 35 clkm : in std_logic;
35 36 rstn : in std_logic;
36 37 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 38 FifoIN_Data : in std_logic_vector(79 downto 0);
38 39 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 Load : out std_logic;
39 41 Read : out std_logic_vector(4 downto 0);
40 42 Write : out std_logic_vector(4 downto 0);
41 43 ReUse : out std_logic_vector(4 downto 0);
42 44 Data : out std_logic_vector(79 downto 0)
43 45 );
44 46 end entity;
45 47
46 48
47 49 architecture ar_FFT of FFT is
48 50
49 51 signal Drive_Write : std_logic;
50 52 signal Drive_DataRE : std_logic_vector(15 downto 0);
51 53 signal Drive_DataIM : std_logic_vector(15 downto 0);
52 54
53 55 signal Start : std_logic;
54 56 signal FFT_Load : std_logic;
55 57 signal FFT_Ready : std_logic;
56 58 signal FFT_Valid : std_logic;
57 59 signal FFT_DataRE : std_logic_vector(15 downto 0);
58 60 signal FFT_DataIM : std_logic_vector(15 downto 0);
59 61
60 62 signal Link_Read : std_logic;
61 63
62 64 begin
63 65
64 66 Start <= '0';
67 Load <= FFT_Load;
65 68
66 69 DRIVE : Driver_FFT
67 70 generic map(Data_sz,NbData)
68 71 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Read,Drive_DataRE,Drive_DataIM);
69 72
70 73 FFT0 : CoreFFT
71 74 generic map(
72 75 LOGPTS => gLOGPTS,
73 76 LOGLOGPTS => gLOGLOGPTS,
74 77 WSIZE => gWSIZE,
75 78 TWIDTH => gTWIDTH,
76 79 DWIDTH => gDWIDTH,
77 80 TDWIDTH => gTDWIDTH,
78 81 RND_MODE => gRND_MODE,
79 82 SCALE_MODE => gSCALE_MODE,
80 83 PTS => gPTS,
81 84 HALFPTS => gHALFPTS,
82 85 inBuf_RWDLY => gInBuf_RWDLY)
83 86 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
84 87
85 88
86 89 LINK : Linker_FFT
87 90 generic map(Data_sz,NbData)
88 91 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoOUT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Write,ReUse,Data);
89 92
90 93
91 94 end architecture; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 use work.fft_components.all;
30 30
31 31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 32
33 33 package lpp_fft is
34 34
35 35 component APB_FFT is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16
43 43 );
44 44 port (
45 45 clk : in std_logic;
46 46 rst : in std_logic; --! Reset general du composant
47 47 apbi : in apb_slv_in_type;
48 48 apbo : out apb_slv_out_type
49 49 );
50 50 end component;
51 51
52 52
53 53 component APB_FFT_half is
54 54 generic (
55 55 pindex : integer := 0;
56 56 paddr : integer := 0;
57 57 pmask : integer := 16#fff#;
58 58 pirq : integer := 0;
59 59 abits : integer := 8;
60 60 Data_sz : integer := 16
61 61 );
62 62 port (
63 63 clk : in std_logic; --! Horloge du composant
64 64 rst : in std_logic; --! Reset general du composant
65 65 Ren : in std_logic;
66 66 ready : out std_logic;
67 67 valid : out std_logic;
68 68 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
69 69 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
70 70 OUTfill : out std_logic;
71 71 OUTwrite : out std_logic;
72 72 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
73 73 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
74 74 );
75 75 end component;
76 76
77 77 component FFT is
78 78 generic(
79 79 Data_sz : integer := 16;
80 80 NbData : integer := 256);
81 81 port(
82 82 clkm : in std_logic;
83 83 rstn : in std_logic;
84 84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Load : out std_logic;
87 88 Read : out std_logic_vector(4 downto 0);
88 89 Write : out std_logic_vector(4 downto 0);
89 90 ReUse : out std_logic_vector(4 downto 0);
90 91 Data : out std_logic_vector(79 downto 0)
91 92 );
92 93 end component;
93 94
94 95 component Flag_Extremum is
95 96 port(
96 97 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
97 98 load : in std_logic; --! Signal en provenance de CoreFFT
98 99 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
99 100 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
100 101 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
101 102 );
102 103 end component;
103 104
104 105
105 106 component Linker_FFT is
106 107 generic(
107 108 Data_sz : integer range 1 to 32 := 16;
108 109 NbData : integer range 1 to 512 := 256
109 110 );
110 111 port(
111 112 clk : in std_logic;
112 113 rstn : in std_logic;
113 114 Ready : in std_logic;
114 115 Valid : in std_logic;
115 116 Full : in std_logic_vector(4 downto 0);
116 117 Data_re : in std_logic_vector(Data_sz-1 downto 0);
117 118 Data_im : in std_logic_vector(Data_sz-1 downto 0);
118 119 Read : out std_logic;
119 120 Write : out std_logic_vector(4 downto 0);
120 121 ReUse : out std_logic_vector(4 downto 0);
121 122 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
122 123 );
123 124 end component;
124 125
125 126
126 127 component Driver_FFT is
127 128 generic(
128 129 Data_sz : integer range 1 to 32 := 16;
129 130 NbData : integer range 1 to 512 := 256
130 131 );
131 132 port(
132 133 clk : in std_logic;
133 134 rstn : in std_logic;
134 135 Load : in std_logic;
135 136 Empty : in std_logic_vector(4 downto 0);
136 137 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
137 138 Valid : out std_logic;
138 139 Read : out std_logic_vector(4 downto 0);
139 140 Data_re : out std_logic_vector(Data_sz-1 downto 0);
140 141 Data_im : out std_logic_vector(Data_sz-1 downto 0)
141 142 );
142 143 end component;
143 144
144 145 component FFTamont is
145 146 generic(
146 147 Data_sz : integer range 1 to 32 := 16;
147 148 NbData : integer range 1 to 512 := 256
148 149 );
149 150 port(
150 151 clk : in std_logic;
151 152 rstn : in std_logic;
152 153 Load : in std_logic;
153 154 Empty : in std_logic;
154 155 DATA : in std_logic_vector(Data_sz-1 downto 0);
155 156 Valid : out std_logic;
156 157 Read : out std_logic;
157 158 Data_re : out std_logic_vector(Data_sz-1 downto 0);
158 159 Data_im : out std_logic_vector(Data_sz-1 downto 0)
159 160 );
160 161 end component;
161 162
162 163 component FFTaval is
163 164 generic(
164 165 Data_sz : integer range 1 to 32 := 8;
165 166 NbData : integer range 1 to 512 := 256
166 167 );
167 168 port(
168 169 clk : in std_logic;
169 170 rstn : in std_logic;
170 171 Ready : in std_logic;
171 172 Valid : in std_logic;
172 173 Full : in std_logic;
173 174 Data_re : in std_logic_vector(Data_sz-1 downto 0);
174 175 Data_im : in std_logic_vector(Data_sz-1 downto 0);
175 176 Read : out std_logic;
176 177 Write : out std_logic;
177 178 ReUse : out std_logic;
178 179 DATA : out std_logic_vector(Data_sz-1 downto 0)
179 180 );
180 181 end component;
181 182 --==============================================================|
182 183 --================== IP VHDL de la FFT actel ===================|
183 184 --================ non partag� dans la VHD_Lib =================|
184 185 --==============================================================|
185 186
186 187 component CoreFFT IS
187 188 GENERIC (
188 189 LOGPTS : integer := gLOGPTS;
189 190 LOGLOGPTS : integer := gLOGLOGPTS;
190 191 WSIZE : integer := gWSIZE;
191 192 TWIDTH : integer := gTWIDTH;
192 193 DWIDTH : integer := gDWIDTH;
193 194 TDWIDTH : integer := gTDWIDTH;
194 195 RND_MODE : integer := gRND_MODE;
195 196 SCALE_MODE : integer := gSCALE_MODE;
196 197 PTS : integer := gPTS;
197 198 HALFPTS : integer := gHALFPTS;
198 199 inBuf_RWDLY : integer := gInBuf_RWDLY );
199 200 PORT (
200 201 clk,ifiStart,ifiNreset : IN std_logic;
201 202 ifiD_valid, ifiRead_y : IN std_logic;
202 203 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
203 204 ifoLoad, ifoPong : OUT std_logic;
204 205 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
205 206 ifoY_valid, ifoY_rdy : OUT std_logic);
206 207 END component;
207 208
208 209
209 210 component actar is
210 211 port( DataA : in std_logic_vector(15 downto 0); DataB : in
211 212 std_logic_vector(15 downto 0); Mult : out
212 213 std_logic_vector(31 downto 0);Clock : in std_logic) ;
213 214 end component;
214 215
215 216 component actram is
216 217 port( DI : in std_logic_vector(31 downto 0); DO : out
217 218 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
218 219 WADDR : in std_logic_vector(6 downto 0); RADDR : in
219 220 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
220 221 std_logic) ;
221 222 end component;
222 223
223 224 component switch IS
224 225 GENERIC ( DWIDTH : integer := 32 );
225 226 PORT (
226 227 clk, sel, validIn : IN std_logic;
227 228 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
228 229 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
229 230 validOut : OUT std_logic);
230 231 END component;
231 232
232 233 component twid_rA IS
233 234 GENERIC (LOGPTS : integer := 8;
234 235 LOGLOGPTS : integer := 3 );
235 236 PORT (clk : IN std_logic;
236 237 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
237 238 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
238 239 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
239 240 END component;
240 241
241 242 component counter IS
242 243 GENERIC (
243 244 WIDTH : integer := 7;
244 245 TERMCOUNT : integer := 127 );
245 246 PORT (
246 247 clk, nGrst, rst, cntEn : IN std_logic;
247 248 tc : OUT std_logic;
248 249 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
249 250 END component;
250 251
251 252
252 253 component twiddle IS
253 254 PORT (
254 255 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
255 256 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
256 257 END component;
257 258
258 259
259 260 end; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30
31 31
32 32
33 33 PACKAGE general_purpose IS
34 34
35 35
36 36
37 37 COMPONENT Clk_divider IS
38 38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 39 TargetFreq_Hz : INTEGER := 50000);
40 40 PORT (clk : IN STD_LOGIC;
41 41 reset : IN STD_LOGIC;
42 42 clk_divided : OUT STD_LOGIC);
43 43 END COMPONENT;
44 44
45 45
46 46 COMPONENT Clk_divider2 IS
47 47 generic(N : integer := 16);
48 48 port(
49 49 clk_in : in std_logic;
50 50 clk_out : out std_logic);
51 51 END COMPONENT;
52 52
53 53 COMPONENT Adder IS
54 54 GENERIC(
55 55 Input_SZ_A : INTEGER := 16;
56 56 Input_SZ_B : INTEGER := 16
57 57
58 58 );
59 59 PORT(
60 60 clk : IN STD_LOGIC;
61 61 reset : IN STD_LOGIC;
62 62 clr : IN STD_LOGIC;
63 63 load : IN STD_LOGIC;
64 64 add : IN STD_LOGIC;
65 65 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
66 66 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
67 67 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
68 68 );
69 69 END COMPONENT;
70 70
71 71 COMPONENT ADDRcntr IS
72 72 PORT(
73 73 clk : IN STD_LOGIC;
74 74 reset : IN STD_LOGIC;
75 75 count : IN STD_LOGIC;
76 76 clr : IN STD_LOGIC;
77 77 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
78 78 );
79 79 END COMPONENT;
80 80
81 81 COMPONENT ALU IS
82 82 GENERIC(
83 83 Arith_en : INTEGER := 1;
84 84 Logic_en : INTEGER := 1;
85 85 Input_SZ_1 : INTEGER := 16;
86 86 Input_SZ_2 : INTEGER := 9
87 87
88 88 );
89 89 PORT(
90 90 clk : IN STD_LOGIC;
91 91 reset : IN STD_LOGIC;
92 92 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
93 93 comp : IN STD_LOGIC_VECTOR(1 downto 0);
94 94 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
95 95 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
96 96 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
97 97 );
98 98 END COMPONENT;
99 99
100 100 ---------------------------------------------------------
101 101 -------- // S�lection grace a l'entr�e "ctrl" \\ --------
102 102 ---------------------------------------------------------
103 103 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
104 104 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
105 105 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
106 106 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
107 107 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
108 108 ---------------------------------------------------------
109 109
110 110 COMPONENT MAC IS
111 111 GENERIC(
112 112 Input_SZ_A : INTEGER := 8;
113 113 Input_SZ_B : INTEGER := 8
114
115 114 );
116 115 PORT(
117 116 clk : IN STD_LOGIC;
118 117 reset : IN STD_LOGIC;
119 118 clr_MAC : IN STD_LOGIC;
120 119 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 120 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 121 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
123 122 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
124 123 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
125 124 );
126 125 END COMPONENT;
127 126
128 127 COMPONENT TwoComplementer is
129 128 generic(
130 129 Input_SZ : integer := 16);
131 130 port(
132 131 clk : in std_logic; --! Horloge du composant
133 132 reset : in std_logic; --! Reset general du composant
134 133 clr : in std_logic; --! Un reset sp�cifique au programme
135 134 TwoComp : in std_logic; --! Autorise l'utilisation du compl�ment
136 135 OP : in std_logic_vector(Input_SZ-1 downto 0); --! Op�rande d'entr�e
137 136 RES : out std_logic_vector(Input_SZ-1 downto 0) --! R�sultat, op�rande compl�ment� ou non
138 137 );
139 138 end COMPONENT;
140 139
141 140 COMPONENT MAC_CONTROLER IS
142 141 PORT(
143 142 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
144 143 MULT : OUT STD_LOGIC;
145 144 ADD : OUT STD_LOGIC;
146 145 LOAD_ADDER : out std_logic;
147 146 MACMUX_sel : OUT STD_LOGIC;
148 147 MACMUX2_sel : OUT STD_LOGIC
149 148 );
150 149 END COMPONENT;
151 150
152 151 COMPONENT MAC_MUX IS
153 152 GENERIC(
154 153 Input_SZ_A : INTEGER := 16;
155 154 Input_SZ_B : INTEGER := 16
156 155
157 156 );
158 157 PORT(
159 158 sel : IN STD_LOGIC;
160 159 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
161 160 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
162 161 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
163 162 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
164 163 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
165 164 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
166 165 );
167 166 END COMPONENT;
168 167
169 168
170 169 COMPONENT MAC_MUX2 IS
171 170 GENERIC(Input_SZ : INTEGER := 16);
172 171 PORT(
173 172 sel : IN STD_LOGIC;
174 173 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
175 174 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
176 175 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
177 176 );
178 177 END COMPONENT;
179 178
180 179
181 180 COMPONENT MAC_REG IS
182 181 GENERIC(size : INTEGER := 16);
183 182 PORT(
184 183 reset : IN STD_LOGIC;
185 184 clk : IN STD_LOGIC;
186 185 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
187 186 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
188 187 );
189 188 END COMPONENT;
190 189
191 190
192 191 COMPONENT MUX2 IS
193 192 GENERIC(Input_SZ : INTEGER := 16);
194 193 PORT(
195 194 sel : IN STD_LOGIC;
196 195 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
197 196 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
198 197 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
199 198 );
200 199 END COMPONENT;
201 200
202 201 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
203 202 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
204 203
205 204 COMPONENT MUXN
206 205 GENERIC (
207 206 Input_SZ : INTEGER;
208 207 NbStage : INTEGER);
209 208 PORT (
210 209 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
211 210 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
212 211 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
213 212 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
214 213 END COMPONENT;
215 214
216 215
217 216
218 217 COMPONENT Multiplier IS
219 218 GENERIC(
220 219 Input_SZ_A : INTEGER := 16;
221 220 Input_SZ_B : INTEGER := 16
222 221
223 222 );
224 223 PORT(
225 224 clk : IN STD_LOGIC;
226 225 reset : IN STD_LOGIC;
227 226 mult : IN STD_LOGIC;
228 227 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
229 228 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
230 229 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
231 230 );
232 231 END COMPONENT;
233 232
234 233 COMPONENT REG IS
235 234 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
236 235 PORT(
237 236 reset : IN STD_LOGIC;
238 237 clk : IN STD_LOGIC;
239 238 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
240 239 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
241 240 );
242 241 END COMPONENT;
243 242
244 243
245 244
246 245 COMPONENT RShifter IS
247 246 GENERIC(
248 247 Input_SZ : INTEGER := 16;
249 248 shift_SZ : INTEGER := 4
250 249 );
251 250 PORT(
252 251 clk : IN STD_LOGIC;
253 252 reset : IN STD_LOGIC;
254 253 shift : IN STD_LOGIC;
255 254 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
256 255 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
257 256 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
258 257 );
259 258 END COMPONENT;
260 259
261 260 COMPONENT SYNC_FF
262 261 GENERIC (
263 262 NB_FF_OF_SYNC : INTEGER);
264 263 PORT (
265 264 clk : IN STD_LOGIC;
266 265 rstn : IN STD_LOGIC;
267 266 A : IN STD_LOGIC;
268 267 A_sync : OUT STD_LOGIC);
269 268 END COMPONENT;
270 269
271 270 END;
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@@ -1,17 +1,18
1 1 ADDRcntr.vhd
2 2 ALU.vhd
3 3 Adder.vhd
4 4 Clk_Divider2.vhd
5 5 Clk_divider.vhd
6 6 MAC.vhd
7 7 MAC_CONTROLER.vhd
8 8 MAC_MUX.vhd
9 9 MAC_MUX2.vhd
10 10 MAC_REG.vhd
11 11 MUX2.vhd
12 12 MUXN.vhd
13 13 Multiplier.vhd
14 14 REG.vhd
15 15 SYNC_FF.vhd
16 16 Shifter.vhd
17 17 general_purpose.vhd
18 TwoComplementer.vhd
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@@ -1,619 +1,651
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 library ieee;
22 22 use ieee.std_logic_1164.all;
23 23 library grlib;
24 24 use grlib.amba.all;
25 25 use grlib.stdlib.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library gaisler;
29 29 use gaisler.memctrl.all;
30 30 use gaisler.leon3.all;
31 31 use gaisler.uart.all;
32 32 use gaisler.misc.all;
33 33 library esa;
34 34 use esa.memoryctrl.all;
35 35 use work.config.all;
36 36 library lpp;
37 37 use lpp.lpp_amba.all;
38 38 use lpp.lpp_memory.all;
39 39 use lpp.lpp_uart.all;
40 40 use lpp.lpp_matrix.all;
41 41 use lpp.lpp_delay.all;
42 42 use lpp.lpp_fft.all;
43 43 use lpp.fft_components.all;
44 44 use lpp.lpp_ad_conv.all;
45 45 use lpp.iir_filter.all;
46 46 use lpp.general_purpose.all;
47 47 use lpp.Filtercfg.all;
48 48 use lpp.lpp_demux.all;
49 49 use lpp.lpp_top_lfr_pkg.all;
50 50
51 51 entity leon3mp is
52 52 generic (
53 53 fabtech : integer := CFG_FABTECH;
54 54 memtech : integer := CFG_MEMTECH;
55 55 padtech : integer := CFG_PADTECH;
56 56 clktech : integer := CFG_CLKTECH;
57 57 disas : integer := CFG_DISAS; -- Enable disassembly to console
58 58 dbguart : integer := CFG_DUART; -- Print UART on console
59 59 pclow : integer := CFG_PCLOW
60 60 );
61 61 port (
62 62 clk50MHz : in std_ulogic;
63 63 reset : in std_ulogic;
64 64 ramclk : out std_logic;
65 65
66 66 ahbrxd : in std_ulogic; -- DSU rx data
67 67 ahbtxd : out std_ulogic; -- DSU tx data
68 68 dsubre : in std_ulogic;
69 69 dsuact : out std_ulogic;
70 70 urxd1 : in std_ulogic; -- UART1 rx data
71 71 utxd1 : out std_ulogic; -- UART1 tx data
72 72 errorn : out std_ulogic;
73 73
74 74 address : out std_logic_vector(18 downto 0);
75 75 data : inout std_logic_vector(31 downto 0);
76 76 gpio : inout std_logic_vector(6 downto 0); -- I/O port
77 77
78 78 nBWa : out std_logic;
79 79 nBWb : out std_logic;
80 80 nBWc : out std_logic;
81 81 nBWd : out std_logic;
82 82 nBWE : out std_logic;
83 83 nADSC : out std_logic;
84 84 nADSP : out std_logic;
85 85 nADV : out std_logic;
86 86 nGW : out std_logic;
87 87 nCE1 : out std_logic;
88 88 CE2 : out std_logic;
89 89 nCE3 : out std_logic;
90 90 nOE : out std_logic;
91 91 MODE : out std_logic;
92 92 SSRAM_CLK : out std_logic;
93 93 ZZ : out std_logic;
94 94 ---------------------------------------------------------------------
95 95 --- AJOUT TEST ------------------------In/Out-----------------------
96 96 ---------------------------------------------------------------------
97 97 -- UART
98 98 UART_RXD : in std_logic;
99 99 UART_TXD : out std_logic;
100 100 -- ACQ
101 Clk_49Mhz : IN STD_LOGIC;
102 101 CNV_CH1 : OUT STD_LOGIC;
103 102 SCK_CH1 : OUT STD_LOGIC;
104 103 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
104 Bias_Fails : out std_logic;
105 105 -- ADC
106 106 -- ADC_in : in AD7688_in(4 downto 0);
107 107 -- ADC_out : out AD7688_out;
108 -- Bias_Fails : out std_logic;
108
109 109 -- CNA
110 110 -- DAC_SYNC : out std_logic;
111 111 -- DAC_SCLK : out std_logic;
112 112 -- DAC_DATA : out std_logic;
113 113 -- Diver
114 114 SPW1_EN : out std_logic;
115 115 SPW2_EN : out std_logic;
116 116 TEST : out std_logic_vector(3 downto 0);
117 117
118 118 BP : in std_logic;
119 119 ---------------------------------------------------------------------
120 120 led : out std_logic_vector(1 downto 0)
121 121 );
122 122 end;
123 123
124 124 architecture Behavioral of leon3mp is
125 125
126 126 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
127 127 CFG_GRETH+CFG_AHB_JTAG;
128 128 constant maxahbm : integer := maxahbmsp;
129 129
130 130 --Clk & Rst g�n�
131 131 signal vcc : std_logic_vector(4 downto 0);
132 132 signal gnd : std_logic_vector(4 downto 0);
133 133 signal resetnl : std_ulogic;
134 134 signal clk2x : std_ulogic;
135 135 signal lclk : std_ulogic;
136 136 signal lclk2x : std_ulogic;
137 137 signal clkm : std_ulogic;
138 138 signal rstn : std_ulogic;
139 139 signal rstraw : std_ulogic;
140 140 signal pciclk : std_ulogic;
141 141 signal sdclkl : std_ulogic;
142 142 signal cgi : clkgen_in_type;
143 143 signal cgo : clkgen_out_type;
144 144 --- AHB / APB
145 145 signal apbi : apb_slv_in_type;
146 146 signal apbo : apb_slv_out_vector := (others => apb_none);
147 147 signal ahbsi : ahb_slv_in_type;
148 148 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
149 149 signal ahbmi : ahb_mst_in_type;
150 150 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
151 151 --UART
152 152 signal ahbuarti : uart_in_type;
153 153 signal ahbuarto : uart_out_type;
154 154 signal apbuarti : uart_in_type;
155 155 signal apbuarto : uart_out_type;
156 156 --MEM CTRLR
157 157 signal memi : memory_in_type;
158 158 signal memo : memory_out_type;
159 159 signal wpo : wprot_out_type;
160 160 signal sdo : sdram_out_type;
161 161 --IRQ
162 162 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
163 163 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
164 164 --Timer
165 165 signal gpti : gptimer_in_type;
166 166 signal gpto : gptimer_out_type;
167 167 --GPIO
168 168 signal gpioi : gpio_in_type;
169 169 signal gpioo : gpio_out_type;
170 170 --DSU
171 171 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
172 172 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
173 173 signal dsui : dsu_in_type;
174 174 signal dsuo : dsu_out_type;
175 175
176 176 ---------------------------------------------------------------------
177 177 --- AJOUT TEST ------------------------Signaux----------------------
178 178 ---------------------------------------------------------------------
179 179 -- FIFOs
180 signal FifoF0a_Full : std_logic_vector(4 downto 0);
181 signal FifoF0a_Empty : std_logic_vector(4 downto 0);
182 signal FifoF0a_Data : std_logic_vector(79 downto 0);
183 signal FifoF0b_Full : std_logic_vector(4 downto 0);
184 signal FifoF0b_Empty : std_logic_vector(4 downto 0);
185 signal FifoF0b_Data : std_logic_vector(79 downto 0);
186 signal FifoF1_Full : std_logic_vector(4 downto 0);
180 signal FifoF0_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0_Data : std_logic_vector(79 downto 0);
187 182 signal FifoF1_Empty : std_logic_vector(4 downto 0);
188 183 signal FifoF1_Data : std_logic_vector(79 downto 0);
189 signal FifoF3_Full : std_logic_vector(4 downto 0);
190 184 signal FifoF3_Empty : std_logic_vector(4 downto 0);
191 185 signal FifoF3_Data : std_logic_vector(79 downto 0);
192 186
193 187 signal FifoINT_Full : std_logic_vector(4 downto 0);
194 188 signal FifoINT_Data : std_logic_vector(79 downto 0);
195 189
196 --signal FifoOUT_FullV : std_logic;
197 190 signal FifoOUT_Full : std_logic_vector(1 downto 0);
198 --signal Matrix_WriteV : std_logic_vector(0 downto 0);
199 191
200 192 -- MATRICE SPECTRALE
201 193 signal SM_FlagError : std_logic;
202 194 signal SM_Pong : std_logic;
203 195 signal SM_Read : std_logic_vector(4 downto 0);
204 196 signal SM_Write : std_logic_vector(1 downto 0);
205 197 signal SM_Data : std_logic_vector(63 downto 0);
206 198
207 199 signal Dma_acq : std_logic;
208 200
209 201 -- FFT
202 signal FFT_Load : std_logic;
210 203 signal FFT_Read : std_logic_vector(4 downto 0);
211 204 signal FFT_Write : std_logic_vector(4 downto 0);
212 205 signal FFT_ReUse : std_logic_vector(4 downto 0);
213 206 signal FFT_Data : std_logic_vector(79 downto 0);
214 207
215 208 -- DEMUX
216 signal DEMU_Read : std_logic_vector(19 downto 0);
209 signal DEMU_Read : std_logic_vector(14 downto 0);
217 210 signal DEMU_Empty : std_logic_vector(4 downto 0);
218 211 signal DEMU_Data : std_logic_vector(79 downto 0);
219 212
220 213 -- ACQ
221 signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
222 signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
214
215 signal sample_val : STD_LOGIC;
216 signal sample : Samples(8-1 DOWNTO 0);
217
218 signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 219 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 220 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 221 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 222 signal TopACQ_WenF3 : STD_LOGIC_VECTOR(4 DOWNTO 0);
227 223 signal TopACQ_DataF3 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
228 224
229 225 -- ADC
230 226 --signal SmplClk : std_logic;
231 227 --signal ADC_DataReady : std_logic;
232 228 --signal ADC_SmplOut : Samples_out(4 downto 0);
233 229 --signal enableADC : std_logic;
234 230 --
235 231 --signal WG_Write : std_logic_vector(4 downto 0);
236 232 --signal WG_ReUse : std_logic_vector(4 downto 0);
237 233 --signal WG_DATA : std_logic_vector(79 downto 0);
238 234 --signal s_out : std_logic_vector(79 downto 0);
239 235 --
240 236 --signal fuller : std_logic_vector(4 downto 0);
241 237 --signal reader : std_logic_vector(4 downto 0);
242 238 --signal try : std_logic_vector(1 downto 0);
243 239 --signal TXDint : std_logic;
244 240 --
245 241 ---- IIR Filter
246 242 --signal sample_clk_out : std_logic;
247 243 --
248 244 --signal Rd : std_logic_vector(0 downto 0);
249 245 --signal Ept : std_logic_vector(4 downto 0);
250 246 --
251 247 --signal Bwr : std_logic_vector(0 downto 0);
252 248 --signal Bre : std_logic_vector(0 downto 0);
253 249 --signal DataTMP : std_logic_vector(15 downto 0);
254 250 --signal FullUp : std_logic_vector(0 downto 0);
255 251 --signal EmptyUp : std_logic_vector(0 downto 0);
256 252 --signal FullDown : std_logic_vector(0 downto 0);
257 253 --signal EmptyDown : std_logic_vector(0 downto 0);
258 254 ---------------------------------------------------------------------
259 255 constant IOAEN : integer := CFG_CAN;
260 256 constant boardfreq : integer := 50000;
261 257
262 258 begin
263 259
264 260 ---------------------------------------------------------------------
265 261 --- AJOUT TEST -------------------------------------IPs-------------
266 262 ---------------------------------------------------------------------
267 263 led(1 downto 0) <= gpio(1 downto 0);
268 264
269 265 --- COM USB ---------------------------------------------------------
270 266 -- MemIn0 : APB_FifoWrite
271 267 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
272 268 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
273 269 --
274 270 -- BUF0 : APB_USB
275 271 -- generic map (6,6,DataMax => 1024)
276 272 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
277 273 --
278 274 -- MemOut0 : APB_FifoRead
279 275 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
280 276 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
281 277 --
282 278 --slrd <= usb_Read;
283 279 --slwr <= usb_Write;
284 280
285 281 --- CNA -------------------------------------------------------------
286 282
287 283 -- CONV : APB_CNA
288 284 -- generic map (5,5)
289 285 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
290 286
291 287 --TEST(0) <= SmplClk;
292 288 --TEST(1) <= WG_Write(0);
293 289 --TEST(2) <= Fuller(0);
294 290 --TEST(3) <= s_out(s_out'length-1);
295 291
296 292
297 293 --SPW1_EN <= '1';
298 294 --SPW2_EN <= '0';
299 295
300 296 --- CAN -------------------------------------------------------------
301 297
302 298 -- Divider : Clk_divider
303 299 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
304 300 -- Port map(clkm,rstn,SmplClk);
305 301 --
306 302 -- ADC : AD7688_drvr
307 303 -- generic map (ChanelCount => 5, clkkHz => 24_576)
308 304 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
309 305 --
310 306 -- WG : WriteGen_ADC
311 307 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
312 308 --
313 309 --enableADC <= gpio(0);
314 --Bias_Fails <= '0';
310
315 311 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
316 312 --
317 313 --
318 314 -- MemIn1 : APB_FIFO
319 315 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
320 316 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
321 317
322 TopACQ : lpp_top_acq
323 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
318 DIGITAL_acquisition : ADS7886_drvr
319 GENERIC MAP (
320 ChanelCount => 8,
321 ncycle_cnv_high => 79,
322 ncycle_cnv => 500)
323 PORT MAP (
324 cnv_clk => clk50MHz, --
325 cnv_rstn => rstn, --
326 cnv_run => '1', --
327 cnv => CNV_CH1, --
328 clk => clkm, --
329 rstn => rstn, --
330 sck => SCK_CH1, --
331 sdo => SDO_CH1, --
332 sample => sample,
333 sample_val => sample_val);
334 --
335 TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
336 TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0);
337 --
338 TEST(0) <= TopACQ_WenF0(1);
339 TEST(1) <= SDO_CH1(1);
340 --
341 --
342 --
343 --process(clkm,rstn)
344 --begin
345 -- if(rstn='0')then
346 -- TopACQ_WenF0a <= (others => '1');
347 --
348 -- elsif(clkm'event and clkm='1')then
349 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
350 --
351 -- end if;
352 --end process;
324 353
354 -- TopACQ : lpp_top_acq
355 -- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
356
357 Bias_Fails <= '0';
325 358 --- FIFO IN -------------------------------------------------------------
326 359
327 Memf0a : lppFIFOxN
328 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
329 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
360 MemOut : APB_FIFO
361 generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
362 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 -- Memf0 : lppFIFOxN
364 -- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 -- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
330 366
331 Memf0b : lppFIFOxN
332 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
333 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
334
335 367 Memf1 : lppFIFOxN
336 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
337 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
369 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
338 370
339 371 Memf3 : lppFIFOxN
340 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
341 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
372 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
373 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
342 374
343 375 --- DEMUX -------------------------------------------------------------
344 376
345 DEMUX0 : Demultiplex
377 DEMU0 : DEMUX
346 378 generic map(Data_sz => 16)
347 port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
379 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
348 380
349 381 --- FFT -------------------------------------------------------------
350 382
351 383 -- MemIn : APB_FIFO
352 384 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
353 385 -- port map (clkm,rstn,clkm,clkm,(others => '0'),FFT_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
354 386
355 387 FFT0 : FFT
356 388 generic map(Data_sz => 16,NbData => 256)
357 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
389 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
358 390
359 391 ----- LINK MEMORY -------------------------------------------------------
360 392
361 393 -- MemOut : APB_FIFO
362 394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
363 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
395 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
364 396
365 397 MemInt : lppFIFOxN
366 398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
367 399 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
368
400 --
369 401 -- MemIn : APB_FIFO
370 402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
371 403 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
372 404
373 405 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
374 406
375 407 SM0 : MatriceSpectrale
376 408 generic map(Input_SZ => 16,Result_SZ => 32)
377 409 port map(clkm,rstn,FifoINT_Full,FifoOUT_Full,FifoINT_Data,Dma_acq,SM_FlagError,SM_Pong,SM_Write,SM_Read,SM_Data);
378 410
379 411 Dma_acq <= '1';
380 412
381 MemOut : APB_FIFO
382 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
383 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
413 -- MemOut : APB_FIFO
414 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
415 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
384 416
385 417 ----- FIFO -------------------------------------------------------------
386 418
387 419 Memtest : APB_FIFO
388 420 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
389 421 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
390 422
391 423 --***************************************TEST DEMI-FIFO********************************************************************************
392 424 -- MemIn : APB_FIFO
393 425 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
394 426 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
395 427 --
396 428 -- Pont : Bridge
397 429 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
398 430 --
399 431 -- MemOut : APB_FIFO
400 432 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
401 433 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
402 434 --*************************************************************************************************************************************
403 435
404 436 --- UART -------------------------------------------------------------
405 437
406 438 COM0 : APB_UART
407 439 generic map (pindex => 4, paddr => 4)
408 440 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
409 441
410 442 --- DELAY ------------------------------------------------------------
411 443
412 444 -- Delay0 : APB_Delay
413 445 -- generic map (pindex => 4, paddr => 4)
414 446 -- port map (clkm,rstn,apbi,apbo(4));
415 447
416 448 --- IIR Filter -------------------------------------------------------
417 449 --Test(0) <= sample_clk_out;
418 450 --
419 451 --
420 452 -- IIR1: APB_IIR_Filter
421 453 -- generic map(
422 454 -- tech => CFG_MEMTECH,
423 455 -- pindex => 8,
424 456 -- paddr => 8,
425 457 -- Sample_SZ => Sample_SZ,
426 458 -- ChanelsCount => ChanelsCount,
427 459 -- Coef_SZ => Coef_SZ,
428 460 -- CoefCntPerCel => CoefCntPerCel,
429 461 -- Cels_count => Cels_count,
430 462 -- virgPos => virgPos
431 463 -- )
432 464 -- port map(
433 465 -- rst => rstn,
434 466 -- clk => clkm,
435 467 -- apbi => apbi,
436 468 -- apbo => apbo(8),
437 469 -- sample_clk_out => sample_clk_out,
438 470 -- GOtest => Test(1),
439 471 -- CoefsInitVal => (others => '1')
440 472 -- );
441 473 ----------------------------------------------------------------------
442 474
443 475 ----------------------------------------------------------------------
444 476 --- Reset and Clock generation -------------------------------------
445 477 ----------------------------------------------------------------------
446 478
447 479 vcc <= (others => '1'); gnd <= (others => '0');
448 480 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
449 481
450 482 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
451 483
452 484
453 485 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
454 486
455 487 clkgen0 : clkgen -- clock generator
456 488 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
457 489 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
458 490 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
459 491
460 492 ramclk <= clkm;
461 493 process(lclk2x)
462 494 begin
463 495 if lclk2x'event and lclk2x = '1' then
464 496 lclk <= not lclk;
465 497 end if;
466 498 end process;
467 499
468 500 ----------------------------------------------------------------------
469 501 --- LEON3 processor / DSU / IRQ ------------------------------------
470 502 ----------------------------------------------------------------------
471 503
472 504 l3 : if CFG_LEON3 = 1 generate
473 505 cpu : for i in 0 to CFG_NCPU-1 generate
474 506 u0 : leon3s -- LEON3 processor
475 507 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
476 508 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
477 509 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
478 510 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
479 511 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
480 512 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
481 513 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
482 514 irqi(i), irqo(i), dbgi(i), dbgo(i));
483 515 end generate;
484 516 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
485 517
486 518 dsugen : if CFG_DSU = 1 generate
487 519 dsu0 : dsu3 -- LEON3 Debug Support Unit
488 520 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
489 521 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
490 522 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
491 523 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
492 524 dsui.enable <= '1';
493 525 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
494 526 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
495 527 end generate;
496 528 end generate;
497 529
498 530 nodsu : if CFG_DSU = 0 generate
499 531 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
500 532 end generate;
501 533
502 534 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
503 535 irqctrl0 : irqmp -- interrupt controller
504 536 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
505 537 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
506 538 end generate;
507 539 irq3 : if CFG_IRQ3_ENABLE = 0 generate
508 540 x : for i in 0 to CFG_NCPU-1 generate
509 541 irqi(i).irl <= "0000";
510 542 end generate;
511 543 apbo(2) <= apb_none;
512 544 end generate;
513 545
514 546 ----------------------------------------------------------------------
515 547 --- Memory controllers ---------------------------------------------
516 548 ----------------------------------------------------------------------
517 549
518 550 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
519 551 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
520 552
521 553 memi.brdyn <= '1'; memi.bexcn <= '1';
522 554 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
523 555
524 556 bdr : for i in 0 to 3 generate
525 557 data_pad : iopadv generic map (tech => padtech, width => 8)
526 558 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
527 559 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
528 560 end generate;
529 561
530 562
531 563 addr_pad : outpadv generic map (width => 19, tech => padtech)
532 564 port map (address, memo.address(20 downto 2));
533 565
534 566
535 567 SSRAM_0:entity ssram_plugin
536 568 generic map (tech => padtech)
537 569 port map
538 570 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
539 571
540 572 ----------------------------------------------------------------------
541 573 --- AHB CONTROLLER -------------------------------------------------
542 574 ----------------------------------------------------------------------
543 575
544 576 ahb0 : ahbctrl -- AHB arbiter/multiplexer
545 577 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
546 578 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
547 579 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
548 580 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
549 581
550 582 ----------------------------------------------------------------------
551 583 --- AHB UART -------------------------------------------------------
552 584 ----------------------------------------------------------------------
553 585
554 586 dcomgen : if CFG_AHB_UART = 1 generate
555 587 dcom0: ahbuart -- Debug UART
556 588 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
557 589 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
558 590 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
559 591 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
560 592 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
561 593 end generate;
562 594 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
563 595
564 596 ----------------------------------------------------------------------
565 597 --- APB Bridge -----------------------------------------------------
566 598 ----------------------------------------------------------------------
567 599
568 600 apb0 : apbctrl -- AHB/APB bridge
569 601 generic map (hindex => 1, haddr => CFG_APBADDR)
570 602 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
571 603
572 604 ----------------------------------------------------------------------
573 605 --- GPT Timer ------------------------------------------------------
574 606 ----------------------------------------------------------------------
575 607
576 608 gpt : if CFG_GPT_ENABLE /= 0 generate
577 609 timer0 : gptimer -- timer unit
578 610 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
579 611 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
580 612 nbits => CFG_GPT_TW)
581 613 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
582 614 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
583 615 -- led(4) <= gpto.wdog;
584 616 end generate;
585 617 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
586 618
587 619
588 620 ----------------------------------------------------------------------
589 621 --- APB UART -------------------------------------------------------
590 622 ----------------------------------------------------------------------
591 623
592 624 ua1 : if CFG_UART1_ENABLE /= 0 generate
593 625 uart1 : apbuart -- UART 1
594 626 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
595 627 fifosize => CFG_UART1_FIFO)
596 628 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
597 629 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
598 630 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
599 631 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
600 632 end generate;
601 633 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
602 634
603 635 ----------------------------------------------------------------------
604 636 --- GPIO -----------------------------------------------------------
605 637 ----------------------------------------------------------------------
606 638
607 639 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
608 640 grgpio0: grgpio
609 641 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
610 642 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
611 643
612 644 pio_pads : for i in 0 to 6 generate
613 645 pio_pad : iopad generic map (tech => padtech)
614 646 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
615 647 end generate;
616 648 end generate;
617 649
618 650
619 651 end Behavioral; No newline at end of file
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@@ -1,179 +1,149
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity DEMUX is
27 27 generic(
28 28 Data_sz : integer range 1 to 32 := 16);
29 29 port(
30 30 clk : in std_logic;
31 31 rstn : in std_logic;
32 32
33 33 Read : in std_logic_vector(4 downto 0);
34 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
34 Load : in std_logic;
35 35
36 EmptyF0a : in std_logic_vector(4 downto 0);
37 EmptyF0b : in std_logic_vector(4 downto 0);
36 EmptyF0 : in std_logic_vector(4 downto 0);
38 37 EmptyF1 : in std_logic_vector(4 downto 0);
39 38 EmptyF2 : in std_logic_vector(4 downto 0);
40 39
41 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
43 41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
44 42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
45 43
46 Read_DEMUX : out std_logic_vector(19 downto 0);
44 Read_DEMUX : out std_logic_vector(14 downto 0);
47 45 Empty : out std_logic_vector(4 downto 0);
48 46 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
49 47 );
50 48 end entity;
51 49
52 50
53 51 architecture ar_DEMUX of DEMUX is
54 52
55 53 type etat is (eX,e0,e1,e2,e3);
56 54 signal ect : etat;
57 55
58 signal pong : std_logic;
59 56
60 signal DataCpt_reg : std_logic_vector(3 downto 0);
57 signal load_reg : std_logic;
61 58 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
62 59
63 60 signal Countf0 : integer;
64 61 signal Countf1 : integer;
65 62
66 63 begin
67 64 process(clk,rstn)
68 65 begin
69 66 if(rstn='0')then
70 67 ect <= e0;
71 pong <= '0';
72 Countf0 <= 1;
68 load_reg <= '0';
69 Countf0 <= 5;
73 70 Countf1 <= 0;
74 71
75 72 elsif(clk'event and clk='1')then
76 DataCpt_reg <= DataCpt;
73 load_reg <= Load;
77 74
78 75 case ect is
79 76
80 77 when e0 =>
81 if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then
82 pong <= not pong;
83 if(Countf0 = 5)then
78 if(load_reg = '1' and Load = '0')then
79 if(Countf0 = 24)then
84 80 Countf0 <= 0;
85 ect <= e2;
81 ect <= e1;
86 82 else
87 83 Countf0 <= Countf0 + 1;
88 ect <= e1;
84 ect <= e0;
89 85 end if;
90 86 end if;
91 87
92 88 when e1 =>
93 if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then
94 pong <= not pong;
95 if(Countf0 = 5)then
96 Countf0 <= 0;
89 if(load_reg = '1' and Load = '0')then
90 if(Countf1 = 74)then
91 Countf1 <= 0;
97 92 ect <= e2;
98 93 else
99 Countf0 <= Countf0 + 1;
94 Countf1 <= Countf1 + 1;
100 95 ect <= e0;
101 96 end if;
102 97 end if;
103 98
104 99 when e2 =>
105 if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then
106 if(Countf1 = 15)then
107 Countf1 <= 0;
108 ect <= e3;
109 else
110 Countf1 <= Countf1 + 1;
111 if(pong = '0')then
112 ect <= e0;
113 else
114 ect <= e1;
115 end if;
116 end if;
117 end if;
118
119 when e3 =>
120 if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then
121 if(pong = '0')then
122 ect <= e0;
123 else
124 ect <= e1;
125 end if;
100 if(load_reg = '1' and Load = '0')then
101 ect <= e0;
126 102 end if;
127 103
128 104 when others =>
129 105 null;
130 106
131 107 end case;
132 108 end if;
133 109 end process;
134 110
135 111 with ect select
136 Empty <= EmptyF0a when e0,
137 EmptyF0b when e1,
138 EmptyF1 when e2,
139 EmptyF2 when e3,
112 Empty <= EmptyF0 when e0,
113 EmptyF1 when e1,
114 EmptyF2 when e2,
140 115 (others => '1') when others;
141 116
142 117 with ect select
143 Data <= DataF0a when e0,
144 DataF0b when e1,
145 DataF1 when e2,
146 DataF2 when e3,
118 Data <= DataF0 when e0,
119 DataF1 when e1,
120 DataF2 when e2,
147 121 (others => '0') when others;
148 122
149 123 with ect select
150 Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0,
151 Dummy_Read & Dummy_Read & Read & Dummy_Read when e1,
152 Dummy_Read & Read & Dummy_Read & Dummy_Read when e2,
153 Read & Dummy_Read & Dummy_Read & Dummy_Read when e3,
124 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
125 Dummy_Read & Read & Dummy_Read when e1,
126 Read & Dummy_Read & Dummy_Read when e2,
154 127 (others => '1') when others;
155 128
156
157
158
159 129 end architecture;
160 130
161 131
162 132
163 133
164 134
165 135
166 136
167 137
168 138
169 139
170 140
171 141
172 142
173 143
174 144
175 145
176 146
177 147
178 148
179 149
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@@ -1,103 +1,58
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 31
32 package lpp_demux is
33
34
35 component Demultiplex is
36 generic(
37 Data_sz : integer range 1 to 32 := 16);
38 port(
39 clk : in std_logic;
40 rstn : in std_logic;
41
42 Read : in std_logic_vector(4 downto 0);
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
32 package lpp_demux is
60 33
61 34 component DEMUX is
62 35 generic(
63 36 Data_sz : integer range 1 to 32 := 16);
64 37 port(
65 38 clk : in std_logic;
66 39 rstn : in std_logic;
67 40
68 41 Read : in std_logic_vector(4 downto 0);
69 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
42 Load : in std_logic;
70 43
71 EmptyF0a : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
44 EmptyF0 : in std_logic_vector(4 downto 0);
73 45 EmptyF1 : in std_logic_vector(4 downto 0);
74 46 EmptyF2 : in std_logic_vector(4 downto 0);
75 47
76 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
77 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
48 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
78 49 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
79 50 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
80 51
81 Read_DEMUX : out std_logic_vector(19 downto 0);
52 Read_DEMUX : out std_logic_vector(14 downto 0);
82 53 Empty : out std_logic_vector(4 downto 0);
83 54 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
84 55 );
85 56 end component;
86 57
87
88 component WatchFlag is
89 port(
90 clk : in std_logic;
91 rstn : in std_logic;
92
93 EmptyF0a : in std_logic_vector(4 downto 0);
94 EmptyF0b : in std_logic_vector(4 downto 0);
95 EmptyF1 : in std_logic_vector(4 downto 0);
96 EmptyF2 : in std_logic_vector(4 downto 0);
97
98 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
99 );
100 end component;
101
102
103 58 end; No newline at end of file
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@@ -1,86 +1,64
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 27 library techmap;
28 28 use techmap.gencomp.all;
29 29
30 30 entity lppFIFOxN is
31 31 generic(
32 32 tech : integer := 0;
33 33 Data_sz : integer range 1 to 32 := 8;
34 Addr_sz : integer range 1 to 32 := 8;
34 35 FifoCnt : integer := 1;
35 36 Enable_ReUse : std_logic := '0'
36 37 );
37 38 port(
38 39 rst : in std_logic;
39 40 wclk : in std_logic;
40 41 rclk : in std_logic;
41 42 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
42 43 wen : in std_logic_vector(FifoCnt-1 downto 0);
43 44 ren : in std_logic_vector(FifoCnt-1 downto 0);
44 45 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
45 46 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
46 47 full : out std_logic_vector(FifoCnt-1 downto 0);
47 48 empty : out std_logic_vector(FifoCnt-1 downto 0)
48 49 );
49 50 end entity;
50 51
51 52
52 53 architecture ar_lppFIFOxN of lppFIFOxN is
53 54
54 55 begin
55 56
56 57 fifos: for i in 0 to FifoCnt-1 generate
57 58 FIFO0 : lpp_fifo
58 generic map (tech,Enable_ReUse,Data_sz,8)
59 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
59 60 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
60 61 end generate;
61 62
62
63
64 -- fifoB1 : entity work.lpp_fifo
65 -- generic map (tech,Enable_ReUse,Data_sz,8)
66 -- port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
67 --
68 -- fifoB2 : entity work.lpp_fifo
69 -- generic map (tech,Enable_ReUse,Data_sz,8)
70 -- port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
71 --
72 -- fifoB3 : entity work.lpp_fifo
73 -- generic map (tech,Enable_ReUse,Data_sz,8)
74 -- port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
75 --
76 -- fifoE1 : entity work.lpp_fifo
77 -- generic map (tech,Enable_ReUse,Data_sz,8)
78 -- port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
79 --
80 -- fifoE2 : entity work.lpp_fifo
81 -- generic map (tech,Enable_ReUse,Data_sz,8)
82 -- port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
83
84
85 63 end architecture;
86 64
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@@ -1,176 +1,177
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 library gaisler;
30 30 use gaisler.misc.all;
31 31 use gaisler.memctrl.all;
32 32 library techmap;
33 33 use techmap.gencomp.all;
34 34
35 35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36 36
37 37 package lpp_memory is
38 38
39 39 component APB_FIFO is
40 40 generic (
41 41 tech : integer := apa3;
42 42 pindex : integer := 0;
43 43 paddr : integer := 0;
44 44 pmask : integer := 16#fff#;
45 45 pirq : integer := 0;
46 46 abits : integer := 8;
47 47 FifoCnt : integer := 2;
48 48 Data_sz : integer := 16;
49 49 Addr_sz : integer := 9;
50 50 Enable_ReUse : std_logic := '0';
51 51 R : integer := 1;
52 52 W : integer := 1
53 53 );
54 54 port (
55 55 clk : in std_logic; --! Horloge du composant
56 56 rst : in std_logic; --! Reset general du composant
57 57 rclk : in std_logic;
58 58 wclk : in std_logic;
59 59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 70 );
71 71 end component;
72 72
73 73
74 74 component lpp_fifo is
75 75 generic(
76 76 tech : integer := 0;
77 77 Enable_ReUse : std_logic := '0';
78 78 DataSz : integer range 1 to 32 := 8;
79 79 abits : integer range 2 to 12 := 8
80 80 );
81 81 port(
82 82 rstn : in std_logic;
83 83 ReUse : in std_logic; --27/01/12
84 84 rclk : in std_logic;
85 85 ren : in std_logic;
86 86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 87 empty : out std_logic;
88 88 raddr : out std_logic_vector(abits-1 downto 0);
89 89 wclk : in std_logic;
90 90 wen : in std_logic;
91 91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 92 full : out std_logic;
93 93 waddr : out std_logic_vector(abits-1 downto 0)
94 94 );
95 95 end component;
96 96
97 97
98 98 component lppFIFOxN is
99 99 generic(
100 100 tech : integer := 0;
101 101 Data_sz : integer range 1 to 32 := 8;
102 Addr_sz : integer range 1 to 32 := 8;
102 103 FifoCnt : integer := 1;
103 104 Enable_ReUse : std_logic := '0'
104 105 );
105 106 port(
106 107 rst : in std_logic;
107 108 wclk : in std_logic;
108 109 rclk : in std_logic;
109 110 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
110 111 wen : in std_logic_vector(FifoCnt-1 downto 0);
111 112 ren : in std_logic_vector(FifoCnt-1 downto 0);
112 113 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 114 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 115 full : out std_logic_vector(FifoCnt-1 downto 0);
115 116 empty : out std_logic_vector(FifoCnt-1 downto 0)
116 117 );
117 118 end component;
118 119
119 120 component lppFIFOx5 is
120 121 generic(
121 122 tech : integer := 0;
122 123 Data_sz : integer range 1 to 32 := 16;
123 124 Addr_sz : integer range 2 to 12 := 8;
124 125 Enable_ReUse : std_logic := '0'
125 126 );
126 127 port(
127 128 rst : in std_logic;
128 129 wclk : in std_logic;
129 130 rclk : in std_logic;
130 131 ReUse : in std_logic_vector(4 downto 0);
131 132 wen : in std_logic_vector(4 downto 0);
132 133 ren : in std_logic_vector(4 downto 0);
133 134 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 135 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 136 full : out std_logic_vector(4 downto 0);
136 137 empty : out std_logic_vector(4 downto 0)
137 138 );
138 139 end component;
139 140
140 141 component Bridge is
141 142 port(
142 143 clk : in std_logic;
143 144 raz : in std_logic;
144 145 EmptyUp : in std_logic;
145 146 FullDwn : in std_logic;
146 147 WriteDwn : out std_logic;
147 148 ReadUp : out std_logic
148 149 );
149 150 end component;
150 151
151 152 component ssram_plugin is
152 153 generic (tech : integer := 0);
153 154 port
154 155 (
155 156 clk : in std_logic;
156 157 mem_ctrlr_o : in memory_out_type;
157 158 SSRAM_CLK : out std_logic;
158 159 nBWa : out std_logic;
159 160 nBWb : out std_logic;
160 161 nBWc : out std_logic;
161 162 nBWd : out std_logic;
162 163 nBWE : out std_logic;
163 164 nADSC : out std_logic;
164 165 nADSP : out std_logic;
165 166 nADV : out std_logic;
166 167 nGW : out std_logic;
167 168 nCE1 : out std_logic;
168 169 CE2 : out std_logic;
169 170 nCE3 : out std_logic;
170 171 nOE : out std_logic;
171 172 MODE : out std_logic;
172 173 ZZ : out std_logic
173 174 );
174 175 end component;
175 176
176 177 end;
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@@ -1,332 +1,303
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 LIBRARY lpp;
4 4 USE lpp.lpp_ad_conv.ALL;
5 5 USE lpp.iir_filter.ALL;
6 6 USE lpp.FILTERcfg.ALL;
7 7 USE lpp.lpp_memory.ALL;
8 8 USE lpp.lpp_top_lfr_pkg.ALL;
9 9 LIBRARY techmap;
10 10 USE techmap.gencomp.ALL;
11 11
12 12 ENTITY lpp_top_acq IS
13 13 GENERIC(
14 14 tech : INTEGER := 0
15 15 );
16 16 PORT (
17 17 -- ADS7886
18 18 cnv_run : IN STD_LOGIC;
19 19 cnv : OUT STD_LOGIC;
20 20 sck : OUT STD_LOGIC;
21 21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 22 --
23 23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 24 cnv_rstn : IN STD_LOGIC;
25 25 --
26 26 clk : IN STD_LOGIC; -- 25 MHz
27 27 rstn : IN STD_LOGIC;
28 28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 31 --
33 32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 34 --
36 35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38 37 --
39 38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
40 39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
41 40 );
42 41 END lpp_top_acq;
43 42
44 43 ARCHITECTURE tb OF lpp_top_acq IS
45 44
46 45 COMPONENT Downsampling
47 46 GENERIC (
48 47 ChanelCount : INTEGER;
49 48 SampleSize : INTEGER;
50 49 DivideParam : INTEGER);
51 50 PORT (
52 51 clk : IN STD_LOGIC;
53 52 rstn : IN STD_LOGIC;
54 53 sample_in_val : IN STD_LOGIC;
55 54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
56 55 sample_out_val : OUT STD_LOGIC;
57 56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
58 57 END COMPONENT;
59 58
60 59 -----------------------------------------------------------------------------
61 60 CONSTANT ChanelCount : INTEGER := 8;
62 61 CONSTANT ncycle_cnv_high : INTEGER := 79;
63 62 CONSTANT ncycle_cnv : INTEGER := 500;
64 63
65 64 -----------------------------------------------------------------------------
66 65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
67 66 SIGNAL sample_val : STD_LOGIC;
68 67 SIGNAL sample_val_delay : STD_LOGIC;
69 68 -----------------------------------------------------------------------------
70 69 CONSTANT Coef_SZ : INTEGER := 9;
71 70 CONSTANT CoefCntPerCel : INTEGER := 6;
72 71 CONSTANT CoefPerCel : INTEGER := 5;
73 72 CONSTANT Cels_count : INTEGER := 5;
74 73
75 74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
76 75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
77 76 --
78 77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
79 78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 79 --
81 80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
82 81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
83 82 -----------------------------------------------------------------------------
84 83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
85 84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
86 85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
87 86 --
88 87 SIGNAL sample_f0_val : STD_LOGIC;
89 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
90 --
91 SIGNAL sample_f0_0_val : STD_LOGIC;
92 SIGNAL sample_f0_1_val : STD_LOGIC;
93 SIGNAL counter_f0 : INTEGER;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
94 89 -----------------------------------------------------------------------------
95 90 SIGNAL sample_f1_val : STD_LOGIC;
96 91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
97 92 --
98 93 SIGNAL sample_f2_val : STD_LOGIC;
99 94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
100 95 --
101 96 SIGNAL sample_f3_val : STD_LOGIC;
102 97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
103 98
104 99 BEGIN
105 100
106 101 -- component instantiation
107 102 -----------------------------------------------------------------------------
108 103 DIGITAL_acquisition : ADS7886_drvr
109 104 GENERIC MAP (
110 105 ChanelCount => ChanelCount,
111 106 ncycle_cnv_high => ncycle_cnv_high,
112 107 ncycle_cnv => ncycle_cnv)
113 108 PORT MAP (
114 109 cnv_clk => cnv_clk, --
115 110 cnv_rstn => cnv_rstn, --
116 111 cnv_run => cnv_run, --
117 112 cnv => cnv, --
118 113 clk => clk, --
119 114 rstn => rstn, --
120 115 sck => sck, --
121 116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
122 117 sample => sample,
123 118 sample_val => sample_val);
124 119
125 120 -----------------------------------------------------------------------------
126 121
127 122 PROCESS (clk, rstn)
128 123 BEGIN -- PROCESS
129 124 IF rstn = '0' THEN -- asynchronous reset (active low)
130 125 sample_val_delay <= '0';
131 126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
132 127 sample_val_delay <= sample_val;
133 128 END IF;
134 129 END PROCESS;
135 130
136 131 -----------------------------------------------------------------------------
137 132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
138 133 SampleLoop : FOR j IN 0 TO 15 GENERATE
139 134 sample_filter_in(i, j) <= sample(i)(j);
140 135 END GENERATE;
141 136
142 137 sample_filter_in(i, 16) <= sample(i)(15);
143 138 sample_filter_in(i, 17) <= sample(i)(15);
144 139 END GENERATE;
145 140
146 141 coefs_v2 <= CoefsInitValCst_v2;
147 142
148 143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
149 144 GENERIC MAP (
150 145 tech => 0,
151 146 Mem_use => use_RAM,
152 147 Sample_SZ => 18,
153 148 Coef_SZ => Coef_SZ,
154 149 Coef_Nb => 25, -- TODO
155 150 Coef_sel_SZ => 5, -- TODO
156 151 Cels_count => Cels_count,
157 152 ChanelsCount => ChanelCount)
158 153 PORT MAP (
159 154 rstn => rstn,
160 155 clk => clk,
161 156 virg_pos => 7,
162 157 coefs => coefs_v2,
163 158 sample_in_val => sample_val_delay,
164 159 sample_in => sample_filter_in,
165 160 sample_out_val => sample_filter_v2_out_val,
166 161 sample_out => sample_filter_v2_out);
167 162
168 163 -----------------------------------------------------------------------------
169 164 PROCESS (clk, rstn)
170 165 BEGIN -- PROCESS
171 166 IF rstn = '0' THEN -- asynchronous reset (active low)
172 167 sample_filter_v2_out_r_val <= '0';
173 168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
174 169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
175 170 sample_filter_v2_out_r(I, J) <= '0';
176 171 END LOOP rst_all_bits;
177 172 END LOOP rst_all_chanel;
178 173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
179 174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
180 175 IF sample_filter_v2_out_val = '1' THEN
181 176 sample_filter_v2_out_r <= sample_filter_v2_out;
182 177 END IF;
183 178 END IF;
184 179 END PROCESS;
185 180
186 181 -----------------------------------------------------------------------------
187 182 -- F0 -- @24.576 kHz
188 183 -----------------------------------------------------------------------------
189 184 Downsampling_f0 : Downsampling
190 185 GENERIC MAP (
191 186 ChanelCount => ChanelCount,
192 187 SampleSize => 18,
193 188 DivideParam => 4)
194 189 PORT MAP (
195 190 clk => clk,
196 191 rstn => rstn,
197 192 sample_in_val => sample_filter_v2_out_val ,
198 193 sample_in => sample_filter_v2_out,
199 194 sample_out_val => sample_f0_val,
200 195 sample_out => sample_f0);
201 196
202 197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
203 198 sample_f0_wdata(I) <= sample_f0(0, I);
204 199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
205 200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
206 201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
207 202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
208 203 END GENERATE all_bit_sample_f0;
209 204
210 PROCESS (clk, rstn)
211 BEGIN -- PROCESS
212 IF rstn = '0' THEN -- asynchronous reset (active low)
213 counter_f0 <= 0;
214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
215 IF sample_f0_val = '1' THEN
216 IF counter_f0 = 511 THEN
217 counter_f0 <= 0;
218 ELSE
219 counter_f0 <= counter_f0 + 1;
220 END IF;
221 END IF;
222 END IF;
223 END PROCESS;
224
225 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
226 sample_f0_0_wen <= NOT(sample_f0_0_val) &
227 NOT(sample_f0_0_val) &
228 NOT(sample_f0_0_val) &
229 NOT(sample_f0_0_val) &
230 NOT(sample_f0_0_val);
231
232 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
233 sample_f0_1_wen <= NOT(sample_f0_1_val) &
234 NOT(sample_f0_1_val) &
235 NOT(sample_f0_1_val) &
236 NOT(sample_f0_1_val) &
237 NOT(sample_f0_1_val);
238
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
239 210
240 211 -----------------------------------------------------------------------------
241 212 -- F1 -- @4096 Hz
242 213 -----------------------------------------------------------------------------
243 214 Downsampling_f1 : Downsampling
244 215 GENERIC MAP (
245 216 ChanelCount => ChanelCount,
246 217 SampleSize => 18,
247 218 DivideParam => 6)
248 219 PORT MAP (
249 220 clk => clk,
250 221 rstn => rstn,
251 222 sample_in_val => sample_f0_val ,
252 223 sample_in => sample_f0,
253 224 sample_out_val => sample_f1_val,
254 225 sample_out => sample_f1);
255 226
256 227 sample_f1_wen <= NOT(sample_f1_val) &
257 228 NOT(sample_f1_val) &
258 229 NOT(sample_f1_val) &
259 230 NOT(sample_f1_val) &
260 231 NOT(sample_f1_val);
261 232
262 233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
263 234 sample_f1_wdata(I) <= sample_f1(0, I);
264 235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
265 236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
266 237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
267 238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
268 239 END GENERATE all_bit_sample_f1;
269 240
270 241 -----------------------------------------------------------------------------
271 242 -- F2 -- @16 Hz
272 243 -----------------------------------------------------------------------------
273 244 Downsampling_f2 : Downsampling
274 245 GENERIC MAP (
275 246 ChanelCount => ChanelCount,
276 247 SampleSize => 18,
277 248 DivideParam => 256)
278 249 PORT MAP (
279 250 clk => clk,
280 251 rstn => rstn,
281 252 sample_in_val => sample_f1_val ,
282 253 sample_in => sample_f1,
283 254 sample_out_val => sample_f2_val,
284 255 sample_out => sample_f2);
285 256
286 257 sample_f2_wen <= NOT(sample_f2_val) &
287 258 NOT(sample_f2_val) &
288 259 NOT(sample_f2_val) &
289 260 NOT(sample_f2_val) &
290 261 NOT(sample_f2_val);
291 262
292 263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
293 264 sample_f2_wdata(I) <= sample_f2(0, I);
294 265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
295 266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
296 267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
297 268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
298 269 END GENERATE all_bit_sample_f2;
299 270
300 271 -----------------------------------------------------------------------------
301 272 -- F3 -- @256 Hz
302 273 -----------------------------------------------------------------------------
303 274 Downsampling_f3 : Downsampling
304 275 GENERIC MAP (
305 276 ChanelCount => ChanelCount,
306 277 SampleSize => 18,
307 278 DivideParam => 96)
308 279 PORT MAP (
309 280 clk => clk,
310 281 rstn => rstn,
311 282 sample_in_val => sample_f0_val ,
312 283 sample_in => sample_f0,
313 284 sample_out_val => sample_f3_val,
314 285 sample_out => sample_f3);
315 286
316 287 sample_f3_wen <= (NOT sample_f3_val) &
317 288 (NOT sample_f3_val) &
318 289 (NOT sample_f3_val) &
319 290 (NOT sample_f3_val) &
320 291 (NOT sample_f3_val);
321 292
322 293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
323 294 sample_f3_wdata(I) <= sample_f3(0, I);
324 295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
325 296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
326 297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
327 298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
328 299 END GENERATE all_bit_sample_f3;
329 300
330 301
331 302
332 303 END tb;
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@@ -1,72 +1,80
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4 LIBRARY grlib;
5 5 USE grlib.amba.ALL;
6 6
7 7 LIBRARY lpp;
8 8 USE lpp.lpp_ad_conv.ALL;
9 9 USE lpp.iir_filter.ALL;
10 10 USE lpp.FILTERcfg.ALL;
11 11 USE lpp.lpp_memory.ALL;
12 12 LIBRARY techmap;
13 13 USE techmap.gencomp.ALL;
14 14
15 15 PACKAGE lpp_top_lfr_pkg IS
16 16
17 17 COMPONENT lpp_top_acq
18 GENERIC (
19 tech : integer);
20 PORT (
21 cnv_run : IN STD_LOGIC;
22 cnv : OUT STD_LOGIC;
23 sck : OUT STD_LOGIC;
24 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
25 cnv_clk : IN STD_LOGIC;
26 cnv_rstn : IN STD_LOGIC;
27 clk : IN STD_LOGIC;
28 rstn : IN STD_LOGIC;
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
18 GENERIC(
19 tech : INTEGER := 0
20 );
21 PORT (
22 -- ADS7886
23 cnv_run : IN STD_LOGIC;
24 cnv : OUT STD_LOGIC;
25 sck : OUT STD_LOGIC;
26 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 --
28 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 cnv_rstn : IN STD_LOGIC;
30 --
31 clk : IN STD_LOGIC; -- 25 MHz
32 rstn : IN STD_LOGIC;
33 --
34 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 --
37 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 --
40 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
43 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 );
38 46 END COMPONENT;
39 47
40 48 COMPONENT lpp_top_apbreg
41 49 GENERIC (
42 50 pindex : INTEGER;
43 51 paddr : INTEGER;
44 52 pmask : INTEGER;
45 53 pirq : INTEGER);
46 54 PORT (
47 55 HCLK : IN STD_ULOGIC;
48 56 HRESETn : IN STD_ULOGIC;
49 57 apbi : IN apb_slv_in_type;
50 58 apbo : OUT apb_slv_out_type;
51 59 ready_matrix_f0_0 : IN STD_LOGIC;
52 60 ready_matrix_f0_1 : IN STD_LOGIC;
53 61 ready_matrix_f1 : IN STD_LOGIC;
54 62 ready_matrix_f2 : IN STD_LOGIC;
55 63 error_anticipating_empty_fifo : IN STD_LOGIC;
56 64 error_bad_component_error : IN STD_LOGIC;
57 65 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 66 status_ready_matrix_f0_0 : OUT STD_LOGIC;
59 67 status_ready_matrix_f0_1 : OUT STD_LOGIC;
60 68 status_ready_matrix_f1 : OUT STD_LOGIC;
61 69 status_ready_matrix_f2 : OUT STD_LOGIC;
62 70 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
63 71 status_error_bad_component_error : OUT STD_LOGIC;
64 72 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
65 73 config_active_interruption_onError : OUT STD_LOGIC;
66 74 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 75 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 76 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 77 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
70 78 END COMPONENT;
71 79
72 80 END lpp_top_lfr_pkg; No newline at end of file
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