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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@member.fsf.org
20 -- Mail : alexis.jeandet@member.fsf.org
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22
22
23
23
24 LIBRARY IEEE;
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
27
28 ENTITY SPI_DAC_DRIVER IS
28 ENTITY SPI_DAC_DRIVER IS
29 GENERIC(
29 GENERIC(
30 datawidth : INTEGER := 16;
30 datawidth : INTEGER := 16;
31 MSBFIRST : INTEGER := 1
31 MSBFIRST : INTEGER := 1
32 );
32 );
33 PORT (
33 PORT (
34 clk : IN STD_LOGIC;
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
37 SMP_CLK : IN STD_LOGIC;
37 SMP_CLK : IN STD_LOGIC;
38 SYNC : OUT STD_LOGIC;
38 SYNC : OUT STD_LOGIC;
39 DOUT : OUT STD_LOGIC;
39 DOUT : OUT STD_LOGIC;
40 SCLK : OUT STD_LOGIC
40 SCLK : OUT STD_LOGIC
41 );
41 );
42 END ENTITY SPI_DAC_DRIVER;
42 END ENTITY SPI_DAC_DRIVER;
43
43
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 SIGNAL DATA_s : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
45 SIGNAL DATA_s : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
46 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
47 SIGNAL SMP_CLK_RisingEdge : STD_LOGIC := '0';
47 SIGNAL SMP_CLK_RisingEdge : STD_LOGIC := '0';
48 SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
48 SIGNAL SMP_CLK_RisingEdge_1 : STD_LOGIC := '0';
49 SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
49 SIGNAL SMP_CLK_RisingEdge_2 : STD_LOGIC := '0';
50
50
51 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
51 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth DOWNTO 0) := (OTHERS => '0');
52 SIGNAL shiftcnt : INTEGER := 0;
52 SIGNAL shiftcnt : INTEGER := 0;
53 SIGNAL shifting : STD_LOGIC := '0';
53 SIGNAL shifting : STD_LOGIC := '0';
54
54
55 SIGNAL SCLK_s : STD_LOGIC;
55 SIGNAL SCLK_s : STD_LOGIC;
56 BEGIN
56 BEGIN
57
57
58 -----------------------------------------------------------------------------
58 -----------------------------------------------------------------------------
59 -- Data Re-Orderng
59 -- Data Re-Orderng
60 -----------------------------------------------------------------------------
60 -----------------------------------------------------------------------------
61
61
62 MSB : IF MSBFIRST = 1 GENERATE
62 MSB : IF MSBFIRST = 1 GENERATE
63 DATA_s <= DATA;
63 DATA_s <= DATA;
64 END GENERATE;
64 END GENERATE;
65
65
66 LSB : IF MSBFIRST = 0 GENERATE
66 LSB : IF MSBFIRST = 0 GENERATE
67 DATA_s(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
67 all_bits: FOR I IN 0 TO datawidth-1 GENERATE
68 DATA_s(datawidth-1 - I) <= DATA(I);
69 END GENERATE all_bits;
68 END GENERATE;
70 END GENERATE;
69
71
70 -----------------------------------------------------------------------------
72 -----------------------------------------------------------------------------
71 --
73 --
72 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
73 PROCESS(clk, rstn)
75 PROCESS(clk, rstn)
74 BEGIN
76 BEGIN
75 IF rstn = '0' THEN
77 IF rstn = '0' THEN
76 SMP_CLK_R <= '0';
78 SMP_CLK_R <= '0';
77 SMP_CLK_RisingEdge_2 <= '0';
79 SMP_CLK_RisingEdge_2 <= '0';
78 ELSIF clk'EVENT AND clk = '1' THEN
80 ELSIF clk'EVENT AND clk = '1' THEN
79 SMP_CLK_R <= SMP_CLK;
81 SMP_CLK_R <= SMP_CLK;
80 SMP_CLK_RisingEdge_2 <= SMP_CLK_RisingEdge_1;
82 SMP_CLK_RisingEdge_2 <= SMP_CLK_RisingEdge_1;
81 END IF;
83 END IF;
82 END PROCESS;
84 END PROCESS;
83
85
84 SMP_CLK_RisingEdge_1 <= '1' WHEN SMP_CLK = '1' AND SMP_CLK_R = '0' ELSE '0';
86 SMP_CLK_RisingEdge_1 <= '1' WHEN SMP_CLK = '1' AND SMP_CLK_R = '0' ELSE '0';
85 SMP_CLK_RisingEdge <= '1' WHEN SMP_CLK_RisingEdge_1 = '1' OR SMP_CLK_RisingEdge_2 = '1' ELSE '0';
87 SMP_CLK_RisingEdge <= '1' WHEN SMP_CLK_RisingEdge_1 = '1' OR SMP_CLK_RisingEdge_2 = '1' ELSE '0';
86
88
87
89
88 -----------------------------------------------------------------------------
90 -----------------------------------------------------------------------------
89 --
91 --
90 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
91 SCLK <= SCLK_s;
93 SCLK <= SCLK_s;
92 DOUT <= SHIFTREG(datawidth-1);
94 DOUT <= SHIFTREG(datawidth);
93
95
94 PROCESS (clk, rstn)
96 PROCESS (clk, rstn)
95 BEGIN -- PROCESS
97 BEGIN -- PROCESS
96 IF rstn = '0' THEN -- asynchronous reset (active low)
98 IF rstn = '0' THEN -- asynchronous reset (active low)
97 SCLK_s <= '0';
99 SCLK_s <= '0';
98 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
100 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
99 SCLK_s <= NOT SCLK_s;
101 SCLK_s <= NOT SCLK_s;
100 END IF;
102 END IF;
101 END PROCESS;
103 END PROCESS;
102
104
103 PROCESS(clk, rstn)
105 PROCESS(clk, rstn)
104 BEGIN
106 BEGIN
105 IF rstn = '0' THEN
107 IF rstn = '0' THEN
106 shifting <= '0';
108 shifting <= '0';
107 SHIFTREG <= (OTHERS => '0');
109 SHIFTREG <= (OTHERS => '0');
108 SYNC <= '0';
110 SYNC <= '0';
109 shiftcnt <= 0;
111 shiftcnt <= 0;
110 ELSIF clk'EVENT AND clk = '1' THEN
112 ELSIF clk'EVENT AND clk = '1' THEN
111
113
112 IF SCLK_s = '0' THEN
114 IF SCLK_s = '0' THEN
113
115
114 IF SMP_CLK_RisingEdge = '1' THEN
116 IF SMP_CLK_RisingEdge = '1' THEN
115 SYNC <= '1';
117 SYNC <= '1';
116 shifting <= '1';
118 shifting <= '1';
117 ELSE
119 ELSE
118 SYNC <= '0';
120 SYNC <= '0';
119 IF shiftcnt = datawidth-1 THEN
121 IF shiftcnt = datawidth-1 THEN
120 shifting <= '0';
122 shifting <= '0';
121 END IF;
123 END IF;
122 END IF;
124 END IF;
123
125
124 IF shifting = '1' THEN
126 IF shifting = '1' THEN
125 shiftcnt <= shiftcnt + 1;
127 shiftcnt <= shiftcnt + 1;
126 SHIFTREG(datawidth-1 DOWNTO 1) <= SHIFTREG (datawidth-2 DOWNTO 0);
128 SHIFTREG(datawidth DOWNTO 1) <= SHIFTREG (datawidth-1 DOWNTO 0);
127 ELSE
129 ELSE
128 SHIFTREG <= DATA_s;
130 SHIFTREG(datawidth-1 DOWNTO 0) <= DATA_s;
129 shiftcnt <= 0;
131 shiftcnt <= 0;
130 END IF;
132 END IF;
131
133
132 END IF;
134 END IF;
133 END IF;
135 END IF;
134 END PROCESS;
136 END PROCESS;
135
137
136 END ARCHITECTURE behav;
138 END ARCHITECTURE behav;
Show file before | Show file after | Hide comments
@@ -1,835 +1,836
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_lfr_pkg.ALL;
33 USE lpp.lpp_lfr_pkg.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37
37
38 LIBRARY techmap;
38 LIBRARY techmap;
39 USE techmap.gencomp.ALL;
39 USE techmap.gencomp.ALL;
40
40
41 ENTITY lpp_lfr_apbreg IS
41 ENTITY lpp_lfr_apbreg IS
42 GENERIC (
42 GENERIC (
43 nb_data_by_buffer_size : INTEGER := 32;
43 nb_data_by_buffer_size : INTEGER := 32;
44 nb_snapshot_param_size : INTEGER := 32;
44 nb_snapshot_param_size : INTEGER := 32;
45 delta_vector_size : INTEGER := 32;
45 delta_vector_size : INTEGER := 32;
46 delta_vector_size_f0_2 : INTEGER := 7;
46 delta_vector_size_f0_2 : INTEGER := 7;
47
47
48 pindex : INTEGER := 4;
48 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
49 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
50 pmask : INTEGER := 16#fff#;
51 pirq_ms : INTEGER := 0;
51 pirq_ms : INTEGER := 0;
52 pirq_wfp : INTEGER := 1;
52 pirq_wfp : INTEGER := 1;
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
53 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
54 PORT (
54 PORT (
55 -- AMBA AHB system signals
55 -- AMBA AHB system signals
56 HCLK : IN STD_ULOGIC;
56 HCLK : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
58
58
59 -- AMBA APB Slave Interface
59 -- AMBA APB Slave Interface
60 apbi : IN apb_slv_in_type;
60 apbi : IN apb_slv_in_type;
61 apbo : OUT apb_slv_out_type;
61 apbo : OUT apb_slv_out_type;
62
62
63 ---------------------------------------------------------------------------
63 ---------------------------------------------------------------------------
64 -- Spectral Matrix Reg
64 -- Spectral Matrix Reg
65 -- run_ms : OUT STD_LOGIC;
65 -- run_ms : OUT STD_LOGIC;
66 -- IN
66 -- IN
67 ready_matrix_f0 : IN STD_LOGIC;
67 ready_matrix_f0 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f1 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
69 ready_matrix_f2 : IN STD_LOGIC;
70
70
71 -- error_bad_component_error : IN STD_LOGIC;
71 -- error_bad_component_error : IN STD_LOGIC;
72 error_buffer_full : IN STD_LOGIC; -- TODO
72 error_buffer_full : IN STD_LOGIC; -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
73 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
74
74
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76
76
77 -- OUT
77 -- OUT
78 status_ready_matrix_f0 : OUT STD_LOGIC;
78 status_ready_matrix_f0 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
79 status_ready_matrix_f1 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
80 status_ready_matrix_f2 : OUT STD_LOGIC;
81
81
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
82 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
83 --config_active_interruption_onError : OUT STD_LOGIC;
84
84
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88
88
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
89 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
90 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
91 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
92
92
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
93 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
96
96
97 ---------------------------------------------------------------------------
97 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
98 ---------------------------------------------------------------------------
99 -- WaveForm picker Reg
99 -- WaveForm picker Reg
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
103 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
104
104
105 -- OUT
105 -- OUT
106 data_shaping_BW : OUT STD_LOGIC;
106 data_shaping_BW : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
107 data_shaping_SP0 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
108 data_shaping_SP1 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
109 data_shaping_R0 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
110 data_shaping_R1 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
111 data_shaping_R2 : OUT STD_LOGIC;
112
112
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
113 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
114 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
115 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
116 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
118 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
119 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
120 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
121
121
122 enable_f0 : OUT STD_LOGIC;
122 enable_f0 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
123 enable_f1 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
124 enable_f2 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
125 enable_f3 : OUT STD_LOGIC;
126
126
127 burst_f0 : OUT STD_LOGIC;
127 burst_f0 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
128 burst_f1 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
129 burst_f2 : OUT STD_LOGIC;
130
130
131 run : OUT STD_LOGIC;
131 run : OUT STD_LOGIC;
132
132
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
133 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
134
134
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
136 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
137 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
138 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
139 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
140 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
141 ---------------------------------------------------------------------------
141 ---------------------------------------------------------------------------
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
142 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
143 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
144 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
145 sample_f3_valid : IN STD_LOGIC;
145 sample_f3_valid : IN STD_LOGIC;
146 ---------------------------------------------------------------------------
146 ---------------------------------------------------------------------------
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
147 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
148
148
149 );
149 );
150
150
151 END lpp_lfr_apbreg;
151 END lpp_lfr_apbreg;
152
152
153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
153 ARCHITECTURE beh OF lpp_lfr_apbreg IS
154
154
155 CONSTANT REVISION : INTEGER := 1;
155 CONSTANT REVISION : INTEGER := 1;
156
156
157 CONSTANT pconfig : apb_config_type := (
157 CONSTANT pconfig : apb_config_type := (
158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
158 0 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
159 1 => apb_iobar(paddr, pmask));
159 1 => apb_iobar(paddr, pmask));
160
160
161 --CONSTANT pconfig : apb_config_type := (
161 --CONSTANT pconfig : apb_config_type := (
162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
162 -- 0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
163 -- 1 => apb_iobar(paddr, pmask));
163 -- 1 => apb_iobar(paddr, pmask));
164
164
165 TYPE lpp_SpectralMatrix_regs IS RECORD
165 TYPE lpp_SpectralMatrix_regs IS RECORD
166 config_active_interruption_onNewMatrix : STD_LOGIC;
166 config_active_interruption_onNewMatrix : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
167 config_active_interruption_onError : STD_LOGIC;
168 -- config_ms_run : STD_LOGIC;
168 config_ms_run : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
169 status_ready_matrix_f0_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
170 status_ready_matrix_f1_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
171 status_ready_matrix_f2_0 : STD_LOGIC;
172 status_ready_matrix_f0_1 : STD_LOGIC;
172 status_ready_matrix_f0_1 : STD_LOGIC;
173 status_ready_matrix_f1_1 : STD_LOGIC;
173 status_ready_matrix_f1_1 : STD_LOGIC;
174 status_ready_matrix_f2_1 : STD_LOGIC;
174 status_ready_matrix_f2_1 : STD_LOGIC;
175 -- status_error_bad_component_error : STD_LOGIC;
175 -- status_error_bad_component_error : STD_LOGIC;
176 status_error_buffer_full : STD_LOGIC;
176 status_error_buffer_full : STD_LOGIC;
177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
177 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
178
178
179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185
185
186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
186 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
187
187
188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
190 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
191 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
192 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
193 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
194 END RECORD;
194 END RECORD;
195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
195 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
196
196
197 TYPE lpp_WaveformPicker_regs IS RECORD
197 TYPE lpp_WaveformPicker_regs IS RECORD
198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
198 -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
199 -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
200 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 data_shaping_BW : STD_LOGIC;
201 data_shaping_BW : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
202 data_shaping_SP0 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
203 data_shaping_SP1 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
204 data_shaping_R0 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
205 data_shaping_R1 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
206 data_shaping_R2 : STD_LOGIC;
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
207 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
208 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
209 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
210 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
211 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
212 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
213 -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
214 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
215 enable_f0 : STD_LOGIC;
215 enable_f0 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
216 enable_f1 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
217 enable_f2 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
218 enable_f3 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
219 burst_f0 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
220 burst_f1 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
221 burst_f2 : STD_LOGIC;
222 run : STD_LOGIC;
222 run : STD_LOGIC;
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
223 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
224 addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
225 time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
226 length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
227 error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
228 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
229 END RECORD;
229 END RECORD;
230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
230 SIGNAL reg_wp : lpp_WaveformPicker_regs;
231
231
232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
233
233
234 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
235 -- IRQ
235 -- IRQ
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
237 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
238 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
239 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
240 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
241 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
242 SIGNAL ored_irq_wfp : STD_LOGIC;
242 SIGNAL ored_irq_wfp : STD_LOGIC;
243
243
244 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
245 --
245 --
246 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
247 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 -- SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
249 -- SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
250
250
251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
251 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 -- SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
253 -- SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
254
254
255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
255 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
256 -- SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
257 -- SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
258
258
259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
259 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 -- SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
261 -- SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
262
262
263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
263 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 -- SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
265 -- SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
266
266
267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
267 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
269 -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
270 SIGNAL apbo_irq_ms : STD_LOGIC;
270 SIGNAL apbo_irq_ms : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
271 SIGNAL apbo_irq_wfp : STD_LOGIC;
272 -----------------------------------------------------------------------------
272 -----------------------------------------------------------------------------
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0);
273 SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0);
274
274
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0);
276
276
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
277 SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
278 SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
279 SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
280
280
281 BEGIN -- beh
281 BEGIN -- beh
282
282
283 debug_vector(0) <= error_buffer_full;
283 debug_vector(0) <= error_buffer_full;
284 debug_vector(1) <= reg_sp.status_error_buffer_full;
284 debug_vector(1) <= reg_sp.status_error_buffer_full;
285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
285 debug_vector(4 DOWNTO 2) <= error_input_fifo_write;
286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
286 debug_vector(7 DOWNTO 5) <= reg_sp.status_error_input_fifo_write;
287 debug_vector(8) <= ready_matrix_f2;
287 debug_vector(8) <= ready_matrix_f2;
288 debug_vector(9) <= reg0_ready_matrix_f2;
288 debug_vector(9) <= reg0_ready_matrix_f2;
289 debug_vector(10) <= reg1_ready_matrix_f2;
289 debug_vector(10) <= reg1_ready_matrix_f2;
290 debug_vector(11) <= HRESETn;
290 debug_vector(11) <= HRESETn;
291
291
292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
292 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
293 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
294 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
295
295
296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
296 -- config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
297 -- config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
298
298
299
299
300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
300 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
301 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
302 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
303
303
304
304
305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
305 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
306 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
307 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
308 data_shaping_R0 <= reg_wp.data_shaping_R0;
308 data_shaping_R0 <= reg_wp.data_shaping_R0;
309 data_shaping_R1 <= reg_wp.data_shaping_R1;
309 data_shaping_R1 <= reg_wp.data_shaping_R1;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
310 data_shaping_R2 <= reg_wp.data_shaping_R2;
311
311
312 delta_snapshot <= reg_wp.delta_snapshot;
312 delta_snapshot <= reg_wp.delta_snapshot;
313 delta_f0 <= reg_wp.delta_f0;
313 delta_f0 <= reg_wp.delta_f0; --<= X"0001280A";
314 delta_f0_2 <= reg_wp.delta_f0_2;
314 delta_f0_2 <= reg_wp.delta_f0_2; --<= "0110000";
315 delta_f1 <= reg_wp.delta_f1;
315 delta_f1 <= reg_wp.delta_f1; --<= X"0001283F";
316 delta_f2 <= reg_wp.delta_f2;
316 delta_f2 <= reg_wp.delta_f2; --<= X"000127FF";
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
317 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;--<= X"00000A7F";
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;
318 nb_snapshot_param <= reg_wp.nb_snapshot_param;--<= X"00000A80";
319
319
320 enable_f0 <= reg_wp.enable_f0;
320 enable_f0 <= reg_wp.enable_f0;
321 enable_f1 <= reg_wp.enable_f1;
321 enable_f1 <= reg_wp.enable_f1;
322 enable_f2 <= reg_wp.enable_f2;
322 enable_f2 <= reg_wp.enable_f2;
323 enable_f3 <= reg_wp.enable_f3;
323 enable_f3 <= reg_wp.enable_f3;
324
324
325 burst_f0 <= reg_wp.burst_f0;
325 burst_f0 <= reg_wp.burst_f0;
326 burst_f1 <= reg_wp.burst_f1;
326 burst_f1 <= reg_wp.burst_f1;
327 burst_f2 <= reg_wp.burst_f2;
327 burst_f2 <= reg_wp.burst_f2;
328
328
329 run <= reg_wp.run;
329 run <= reg_wp.run;
330
330
331 --addr_data_f0 <= reg_wp.addr_data_f0;
331 --addr_data_f0 <= reg_wp.addr_data_f0;
332 --addr_data_f1 <= reg_wp.addr_data_f1;
332 --addr_data_f1 <= reg_wp.addr_data_f1;
333 --addr_data_f2 <= reg_wp.addr_data_f2;
333 --addr_data_f2 <= reg_wp.addr_data_f2;
334 --addr_data_f3 <= reg_wp.addr_data_f3;
334 --addr_data_f3 <= reg_wp.addr_data_f3;
335
335
336 start_date <= reg_wp.start_date;
336 start_date <= reg_wp.start_date;
337
337
338 length_matrix_f0 <= reg_sp.length_matrix;
338 length_matrix_f0 <= "00" & X"0000C8";--reg_sp.length_matrix;
339 length_matrix_f1 <= reg_sp.length_matrix;
339 length_matrix_f1 <= "00" & X"0000C8";--reg_sp.length_matrix;
340 length_matrix_f2 <= reg_sp.length_matrix;
340 length_matrix_f2 <= "00" & X"0000C8";--reg_sp.length_matrix;
341 wfp_length_buffer <= reg_wp.length_buffer;
341 wfp_length_buffer <= "00" & X"0001F8"; --<= reg_wp.length_buffer;
342
342
343
343
344
344
345 PROCESS (HCLK, HRESETn)
345 PROCESS (HCLK, HRESETn)
346 BEGIN -- PROCESS
346 BEGIN -- PROCESS
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
347 IF HRESETn = '0' THEN -- asynchronous reset (active low)
348 sample_f3_v_reg <= (OTHERS => '0');
348 sample_f3_v_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
349 sample_f3_e1_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
350 sample_f3_e2_reg <= (OTHERS => '0');
351 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
351 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
352 IF sample_f3_valid = '1' THEN
352 IF sample_f3_valid = '1' THEN
353 sample_f3_v_reg <= sample_f3_v;
353 sample_f3_v_reg <= sample_f3_v;
354 sample_f3_e1_reg <= sample_f3_e1;
354 sample_f3_e1_reg <= sample_f3_e1;
355 sample_f3_e2_reg <= sample_f3_e2;
355 sample_f3_e2_reg <= sample_f3_e2;
356 END IF;
356 END IF;
357 END IF;
357 END IF;
358 END PROCESS;
358 END PROCESS;
359
359
360
360
361 reg_sp.length_matrix <= "00" & X"0000C8";
361 -- reg_sp.length_matrix <= "00" & X"0000C8";
362 reg_sp.config_active_interruption_onError <= '0';
362 -- reg_sp.config_active_interruption_onError <= '0';
363 reg_wp.delta_f0 <= X"0001280A";
363 --reg_wp.delta_f0 <= X"0001280A";
364 reg_wp.delta_f0_2 <= "0110000";
364 --reg_wp.delta_f0_2 <= "0110000";
365 reg_wp.delta_f1 <= X"0001283F";
365 --reg_wp.delta_f1 <= X"0001283F";
366 reg_wp.delta_f2 <= X"000127FF";
366 --reg_wp.delta_f2 <= X"000127FF";
367 reg_wp.nb_data_by_buffer <= X"00000A7F";
367 --reg_wp.nb_data_by_buffer <= X"00000A7F";
368 reg_wp.nb_snapshot_param <= X"00000A80";
368 --reg_wp.nb_snapshot_param <= X"00000A80";
369 reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0
369 --reg_wp.length_buffer <= "00" & X"0001F8"; --25 .. 0
370
370
371 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
371 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
372 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
372 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
373 BEGIN -- PROCESS lpp_dma_top
373 BEGIN -- PROCESS lpp_dma_top
374 IF HRESETn = '0' THEN -- asynchronous reset (active low)
374 IF HRESETn = '0' THEN -- asynchronous reset (active low)
375 reg_sp.config_active_interruption_onNewMatrix <= '0';
375 reg_sp.config_active_interruption_onNewMatrix <= '0';
376 -- reg_sp.config_ms_run <= '0';
376 reg_sp.config_active_interruption_onError <= '0';
377 reg_sp.config_ms_run <= '0';
377 reg_sp.status_ready_matrix_f0_0 <= '0';
378 reg_sp.status_ready_matrix_f0_0 <= '0';
378 reg_sp.status_ready_matrix_f1_0 <= '0';
379 reg_sp.status_ready_matrix_f1_0 <= '0';
379 reg_sp.status_ready_matrix_f2_0 <= '0';
380 reg_sp.status_ready_matrix_f2_0 <= '0';
380 reg_sp.status_ready_matrix_f0_1 <= '0';
381 reg_sp.status_ready_matrix_f0_1 <= '0';
381 reg_sp.status_ready_matrix_f1_1 <= '0';
382 reg_sp.status_ready_matrix_f1_1 <= '0';
382 reg_sp.status_ready_matrix_f2_1 <= '0';
383 reg_sp.status_ready_matrix_f2_1 <= '0';
383 reg_sp.status_error_buffer_full <= '0';
384 reg_sp.status_error_buffer_full <= '0';
384 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
385 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
385
386
386 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
387 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
387 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
388 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
388 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
389 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
389
390
390 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
391 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
391 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
392 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
392 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
393 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
393
394
394 -- reg_sp.length_matrix <= (OTHERS => '0');
395 reg_sp.length_matrix <= (OTHERS => '0');
395
396
396 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
397 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
397 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
398 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
398 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
399 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
399
400
400 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
401 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
401 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
402 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
402 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
403 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
403
404
404 prdata <= (OTHERS => '0');
405 prdata <= (OTHERS => '0');
405
406
406
407
407 apbo_irq_ms <= '0';
408 apbo_irq_ms <= '0';
408 apbo_irq_wfp <= '0';
409 apbo_irq_wfp <= '0';
409
410
410
411
411 -- status_full_ack <= (OTHERS => '0');
412 -- status_full_ack <= (OTHERS => '0');
412
413
413 reg_wp.data_shaping_BW <= '0';
414 reg_wp.data_shaping_BW <= '0';
414 reg_wp.data_shaping_SP0 <= '0';
415 reg_wp.data_shaping_SP0 <= '0';
415 reg_wp.data_shaping_SP1 <= '0';
416 reg_wp.data_shaping_SP1 <= '0';
416 reg_wp.data_shaping_R0 <= '0';
417 reg_wp.data_shaping_R0 <= '0';
417 reg_wp.data_shaping_R1 <= '0';
418 reg_wp.data_shaping_R1 <= '0';
418 reg_wp.data_shaping_R2 <= '0';
419 reg_wp.data_shaping_R2 <= '0';
419 reg_wp.enable_f0 <= '0';
420 reg_wp.enable_f0 <= '0';
420 reg_wp.enable_f1 <= '0';
421 reg_wp.enable_f1 <= '0';
421 reg_wp.enable_f2 <= '0';
422 reg_wp.enable_f2 <= '0';
422 reg_wp.enable_f3 <= '0';
423 reg_wp.enable_f3 <= '0';
423 reg_wp.burst_f0 <= '0';
424 reg_wp.burst_f0 <= '0';
424 reg_wp.burst_f1 <= '0';
425 reg_wp.burst_f1 <= '0';
425 reg_wp.burst_f2 <= '0';
426 reg_wp.burst_f2 <= '0';
426 reg_wp.run <= '0';
427 reg_wp.run <= '0';
427 -- reg_wp.status_full <= (OTHERS => '0');
428 -- reg_wp.status_full <= (OTHERS => '0');
428 -- reg_wp.status_full_err <= (OTHERS => '0');
429 -- reg_wp.status_full_err <= (OTHERS => '0');
429 reg_wp.status_new_err <= (OTHERS => '0');
430 reg_wp.status_new_err <= (OTHERS => '0');
430 reg_wp.error_buffer_full <= (OTHERS => '0');
431 reg_wp.error_buffer_full <= (OTHERS => '0');
431 reg_wp.delta_snapshot <= (OTHERS => '0');
432 reg_wp.delta_snapshot <= (OTHERS => '0');
432 --reg_wp.delta_f0 <= (OTHERS => '0');
433 reg_wp.delta_f0 <= (OTHERS => '0');
433 --reg_wp.delta_f0_2 <= (OTHERS => '0');
434 reg_wp.delta_f0_2 <= (OTHERS => '0');
434 --reg_wp.delta_f1 <= (OTHERS => '0');
435 reg_wp.delta_f1 <= (OTHERS => '0');
435 --reg_wp.delta_f2 <= (OTHERS => '0');
436 reg_wp.delta_f2 <= (OTHERS => '0');
436 --reg_wp.nb_data_by_buffer <= (OTHERS => '0');
437 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
437 --reg_wp.nb_snapshot_param <= (OTHERS => '0');
438 reg_wp.nb_snapshot_param <= (OTHERS => '0');
438 reg_wp.start_date <= (OTHERS => '1');
439 reg_wp.start_date <= (OTHERS => '1');
439
440
440 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
441 reg_wp.status_ready_buffer_f <= (OTHERS => '0');
441 --reg_wp.length_buffer <= (OTHERS => '0');
442 reg_wp.length_buffer <= (OTHERS => '0');
442
443
443 pirq_temp <= (OTHERS => '0');
444 pirq_temp <= (OTHERS => '0');
444
445
445 reg_wp.addr_buffer_f <= (OTHERS => '0');
446 reg_wp.addr_buffer_f <= (OTHERS => '0');
446
447
447 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
448 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
448
449
449 -- status_full_ack <= (OTHERS => '0');
450 -- status_full_ack <= (OTHERS => '0');
450
451
451 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
452 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
452 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
453 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
453 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
454 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
454
455
455 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
456 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
456 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
457 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
457 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
458 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
458
459
459 all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP
460 all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP
460 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
461 reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
461 END LOOP all_status_ready_buffer_bit;
462 END LOOP all_status_ready_buffer_bit;
462
463
463
464
464 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
465 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
465 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
466 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
466 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
467 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
467 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
468 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
468
469
469
470
470
471
471 all_status : FOR I IN 3 DOWNTO 0 LOOP
472 all_status : FOR I IN 3 DOWNTO 0 LOOP
472 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
473 reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
473 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
474 reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I);
474 END LOOP all_status;
475 END LOOP all_status;
475
476
476 paddr := "000000";
477 paddr := "000000";
477 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
478 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
478 prdata <= (OTHERS => '0');
479 prdata <= (OTHERS => '0');
479 IF apbi.psel(pindex) = '1' THEN
480 IF apbi.psel(pindex) = '1' THEN
480 -- APB DMA READ --
481 -- APB DMA READ --
481 CASE paddr(7 DOWNTO 2) IS
482 CASE paddr(7 DOWNTO 2) IS
482
483
483 WHEN ADDR_LFR_SM_CONFIG =>
484 WHEN ADDR_LFR_SM_CONFIG =>
484 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
485 prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
485 -- prdata(1) <= reg_sp.config_active_interruption_onError;
486 prdata(1) <= reg_sp.config_active_interruption_onError;
486 -- prdata(2) <= reg_sp.config_ms_run;
487 prdata(2) <= reg_sp.config_ms_run;
487
488
488 WHEN ADDR_LFR_SM_STATUS =>
489 WHEN ADDR_LFR_SM_STATUS =>
489 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
490 prdata(0) <= reg_sp.status_ready_matrix_f0_0;
490 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
491 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
491 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
492 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
492 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
493 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
493 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
494 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
494 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
495 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
495 -- prdata(6) <= reg_sp.status_error_bad_component_error;
496 -- prdata(6) <= reg_sp.status_error_bad_component_error;
496 prdata(7) <= reg_sp.status_error_buffer_full;
497 prdata(7) <= reg_sp.status_error_buffer_full;
497 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
498 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
498 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
499 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
499 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
500 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
500
501
501 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
502 WHEN ADDR_LFR_SM_F0_0_ADDR => prdata <= reg_sp.addr_matrix_f0_0;
502 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
503 WHEN ADDR_LFR_SM_F0_1_ADDR => prdata <= reg_sp.addr_matrix_f0_1;
503 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
504 WHEN ADDR_LFR_SM_F1_0_ADDR => prdata <= reg_sp.addr_matrix_f1_0;
504 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
505 WHEN ADDR_LFR_SM_F1_1_ADDR => prdata <= reg_sp.addr_matrix_f1_1;
505 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
506 WHEN ADDR_LFR_SM_F2_0_ADDR => prdata <= reg_sp.addr_matrix_f2_0;
506 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
507 WHEN ADDR_LFR_SM_F2_1_ADDR => prdata <= reg_sp.addr_matrix_f2_1;
507 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
508 WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
508 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
509 WHEN ADDR_LFR_SM_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
509 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
510 WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
510 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
511 WHEN ADDR_LFR_SM_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
511 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
512 WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
512 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
513 WHEN ADDR_LFR_SM_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
513 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
514 WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
514 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
515 WHEN ADDR_LFR_SM_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
515 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
516 WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
516 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
517 WHEN ADDR_LFR_SM_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
517 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
518 WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
518 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
519 WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
519 -- WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
520 WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
520 ---------------------------------------------------------------------
521 ---------------------------------------------------------------------
521 WHEN ADDR_LFR_WP_DATASHAPING =>
522 WHEN ADDR_LFR_WP_DATASHAPING =>
522 prdata(0) <= reg_wp.data_shaping_BW;
523 prdata(0) <= reg_wp.data_shaping_BW;
523 prdata(1) <= reg_wp.data_shaping_SP0;
524 prdata(1) <= reg_wp.data_shaping_SP0;
524 prdata(2) <= reg_wp.data_shaping_SP1;
525 prdata(2) <= reg_wp.data_shaping_SP1;
525 prdata(3) <= reg_wp.data_shaping_R0;
526 prdata(3) <= reg_wp.data_shaping_R0;
526 prdata(4) <= reg_wp.data_shaping_R1;
527 prdata(4) <= reg_wp.data_shaping_R1;
527 prdata(5) <= reg_wp.data_shaping_R2;
528 prdata(5) <= reg_wp.data_shaping_R2;
528 WHEN ADDR_LFR_WP_CONTROL =>
529 WHEN ADDR_LFR_WP_CONTROL =>
529 prdata(0) <= reg_wp.enable_f0;
530 prdata(0) <= reg_wp.enable_f0;
530 prdata(1) <= reg_wp.enable_f1;
531 prdata(1) <= reg_wp.enable_f1;
531 prdata(2) <= reg_wp.enable_f2;
532 prdata(2) <= reg_wp.enable_f2;
532 prdata(3) <= reg_wp.enable_f3;
533 prdata(3) <= reg_wp.enable_f3;
533 prdata(4) <= reg_wp.burst_f0;
534 prdata(4) <= reg_wp.burst_f0;
534 prdata(5) <= reg_wp.burst_f1;
535 prdata(5) <= reg_wp.burst_f1;
535 prdata(6) <= reg_wp.burst_f2;
536 prdata(6) <= reg_wp.burst_f2;
536 prdata(7) <= reg_wp.run;
537 prdata(7) <= reg_wp.run;
537 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0
538 WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0
538 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
539 WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
539 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1
540 WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1
540 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
541 WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
541 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2
542 WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2
542 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
543 WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
543 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3
544 WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3
544 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
545 WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
545
546
546 WHEN ADDR_LFR_WP_STATUS =>
547 WHEN ADDR_LFR_WP_STATUS =>
547 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
548 prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f;
548 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
549 prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full;
549 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
550 prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
550
551
551 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
552 WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
552 -- WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
553 WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
553 -- WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
554 WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
554 -- WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
555 WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
555 -- WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
556 WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
556 -- WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
557 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
557 -- WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
558 WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
558 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
559 WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date;
559
560
560 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
561 WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
561 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
562 WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
562 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
563 WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
563 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
564 WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
564
565
565 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
566 WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
566 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
567 WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
567 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
568 WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
568 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
569 WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
569
570
570 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
571 WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
571 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
572 WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
572 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
573 WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
573 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
574 WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
574
575
575 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
576 WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
576 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
577 WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
577 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
578 WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
578 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
579 WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
579
580
580 -- WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
581 WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
581
582
582 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
583 WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg;
583 prdata(31 DOWNTO 16) <= (OTHERS => '0');
584 prdata(31 DOWNTO 16) <= (OTHERS => '0');
584 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
585 WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg;
585 prdata(31 DOWNTO 16) <= (OTHERS => '0');
586 prdata(31 DOWNTO 16) <= (OTHERS => '0');
586 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
587 WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg;
587 prdata(31 DOWNTO 16) <= (OTHERS => '0');
588 prdata(31 DOWNTO 16) <= (OTHERS => '0');
588 ---------------------------------------------------------------------
589 ---------------------------------------------------------------------
589 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
590 WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
590 WHEN OTHERS => NULL;
591 WHEN OTHERS => NULL;
591
592
592 END CASE;
593 END CASE;
593 IF (apbi.pwrite AND apbi.penable) = '1' THEN
594 IF (apbi.pwrite AND apbi.penable) = '1' THEN
594 -- APB DMA WRITE --
595 -- APB DMA WRITE --
595 CASE paddr(7 DOWNTO 2) IS
596 CASE paddr(7 DOWNTO 2) IS
596 --
597 --
597 WHEN ADDR_LFR_SM_CONFIG =>
598 WHEN ADDR_LFR_SM_CONFIG =>
598 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
599 reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
599 -- reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
600 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
600 -- reg_sp.config_ms_run <= apbi.pwdata(2);
601 reg_sp.config_ms_run <= apbi.pwdata(2);
601
602
602 WHEN ADDR_LFR_SM_STATUS =>
603 WHEN ADDR_LFR_SM_STATUS =>
603 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
604 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0;
604 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0;
605 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0;
605 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1;
606 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1;
606 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1;
607 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1;
607 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2;
608 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2;
608 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2;
609 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2;
609 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full;
610 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full;
610 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
611 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
611 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
612 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
612 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
613 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
613 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
614 WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
614 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
615 WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
615 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
616 WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
616 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
617 WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
617 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
618 WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
618 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
619 WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
619
620
620 -- WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
621 WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0);
621 ---------------------------------------------------------------------
622 ---------------------------------------------------------------------
622 WHEN ADDR_LFR_WP_DATASHAPING =>
623 WHEN ADDR_LFR_WP_DATASHAPING =>
623 reg_wp.data_shaping_BW <= apbi.pwdata(0);
624 reg_wp.data_shaping_BW <= apbi.pwdata(0);
624 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
625 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
625 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
626 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
626 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
627 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
627 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
628 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
628 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
629 reg_wp.data_shaping_R2 <= apbi.pwdata(5);
629 WHEN ADDR_LFR_WP_CONTROL =>
630 WHEN ADDR_LFR_WP_CONTROL =>
630 reg_wp.enable_f0 <= apbi.pwdata(0);
631 reg_wp.enable_f0 <= apbi.pwdata(0);
631 reg_wp.enable_f1 <= apbi.pwdata(1);
632 reg_wp.enable_f1 <= apbi.pwdata(1);
632 reg_wp.enable_f2 <= apbi.pwdata(2);
633 reg_wp.enable_f2 <= apbi.pwdata(2);
633 reg_wp.enable_f3 <= apbi.pwdata(3);
634 reg_wp.enable_f3 <= apbi.pwdata(3);
634 reg_wp.burst_f0 <= apbi.pwdata(4);
635 reg_wp.burst_f0 <= apbi.pwdata(4);
635 reg_wp.burst_f1 <= apbi.pwdata(5);
636 reg_wp.burst_f1 <= apbi.pwdata(5);
636 reg_wp.burst_f2 <= apbi.pwdata(6);
637 reg_wp.burst_f2 <= apbi.pwdata(6);
637 reg_wp.run <= apbi.pwdata(7);
638 reg_wp.run <= apbi.pwdata(7);
638 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
639 WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
639 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
640 WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
640 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
641 WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
641 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
642 WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
642 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
643 WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
643 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
644 WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
644 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
645 WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
645 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
646 WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
646 WHEN ADDR_LFR_WP_STATUS =>
647 WHEN ADDR_LFR_WP_STATUS =>
647 all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP
648 all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP
648 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2);
649 reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2);
649 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
650 reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
650 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I);
651 reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I);
651 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
652 reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I);
652 END LOOP all_reg_wp_status_bit;
653 END LOOP all_reg_wp_status_bit;
653
654
654 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
655 WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
655 --WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
656 WHEN ADDR_LFR_WP_DELTA_F0 => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
656 --WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
657 WHEN ADDR_LFR_WP_DELTA_F0_2 => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
657 --WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
658 WHEN ADDR_LFR_WP_DELTA_F1 => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
658 --WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
659 WHEN ADDR_LFR_WP_DELTA_F2 => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
659 --WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
660 WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
660 --WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
661 WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
661 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
662 WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
662
663
663 --WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
664 WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0);
664
665
665 WHEN OTHERS => NULL;
666 WHEN OTHERS => NULL;
666 END CASE;
667 END CASE;
667 END IF;
668 END IF;
668 END IF;
669 END IF;
669 --apbo.pirq(pirq_ms) <=
670 --apbo.pirq(pirq_ms) <=
670 pirq_temp(pirq_ms) <= apbo_irq_ms;
671 pirq_temp(pirq_ms) <= apbo_irq_ms;
671 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
672 pirq_temp(pirq_wfp) <= apbo_irq_wfp;
672 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
673 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
673 ready_matrix_f1 OR
674 ready_matrix_f1 OR
674 ready_matrix_f2)
675 ready_matrix_f2)
675 )
676 )
676 --OR
677 --OR
677 --(reg_sp.config_active_interruption_onError AND
678 --(reg_sp.config_active_interruption_onError AND
678 -- (
679 -- (
679 -- error_buffer_full
680 -- error_buffer_full
680 -- OR error_input_fifo_write(0)
681 -- OR error_input_fifo_write(0)
681 -- OR error_input_fifo_write(1)
682 -- OR error_input_fifo_write(1)
682 -- OR error_input_fifo_write(2))
683 -- OR error_input_fifo_write(2))
683 -- )
684 -- )
684 );
685 );
685 -- apbo.pirq(pirq_wfp)
686 -- apbo.pirq(pirq_wfp)
686 apbo_irq_wfp <= ored_irq_wfp;
687 apbo_irq_wfp <= ored_irq_wfp;
687
688
688 END IF;
689 END IF;
689 END PROCESS lpp_lfr_apbreg;
690 END PROCESS lpp_lfr_apbreg;
690
691
691 apbo.pirq <= pirq_temp;
692 apbo.pirq <= pirq_temp;
692
693
693
694
694 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
695 --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
695 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
696 -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
696 -- apbo.pirq(I) <= apbo_irq_ms;
697 -- apbo.pirq(I) <= apbo_irq_ms;
697 -- END GENERATE IRQ_is_PIRQ_MS;
698 -- END GENERATE IRQ_is_PIRQ_MS;
698 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
699 -- IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
699 -- apbo.pirq(I) <= apbo_irq_wfp;
700 -- apbo.pirq(I) <= apbo_irq_wfp;
700 -- END GENERATE IRQ_is_PIRQ_WFP;
701 -- END GENERATE IRQ_is_PIRQ_WFP;
701 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
702 -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
702 -- apbo.pirq(I) <= '0';
703 -- apbo.pirq(I) <= '0';
703 -- END GENERATE IRQ_OTHERS;
704 -- END GENERATE IRQ_OTHERS;
704
705
705 --END GENERATE all_irq;
706 --END GENERATE all_irq;
706
707
707
708
708
709
709 apbo.pindex <= pindex;
710 apbo.pindex <= pindex;
710 apbo.pconfig <= pconfig;
711 apbo.pconfig <= pconfig;
711 apbo.prdata <= prdata;
712 apbo.prdata <= prdata;
712
713
713 -----------------------------------------------------------------------------
714 -----------------------------------------------------------------------------
714 -- IRQ
715 -- IRQ
715 -----------------------------------------------------------------------------
716 -----------------------------------------------------------------------------
716 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
717 irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
717
718
718 PROCESS (HCLK, HRESETn)
719 PROCESS (HCLK, HRESETn)
719 BEGIN -- PROCESS
720 BEGIN -- PROCESS
720 IF HRESETn = '0' THEN -- asynchronous reset (active low)
721 IF HRESETn = '0' THEN -- asynchronous reset (active low)
721 irq_wfp_reg <= (OTHERS => '0');
722 irq_wfp_reg <= (OTHERS => '0');
722 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
723 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
723 irq_wfp_reg <= irq_wfp_reg_s;
724 irq_wfp_reg <= irq_wfp_reg_s;
724 END IF;
725 END IF;
725 END PROCESS;
726 END PROCESS;
726
727
727 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
728 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
728 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
729 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
729 END GENERATE all_irq_wfp;
730 END GENERATE all_irq_wfp;
730
731
731 irq_wfp_ZERO <= (OTHERS => '0');
732 irq_wfp_ZERO <= (OTHERS => '0');
732 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
733 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
733
734
734 -- run_ms <= reg_sp.config_ms_run;
735 -- run_ms <= reg_sp.config_ms_run;
735
736
736 -----------------------------------------------------------------------------
737 -----------------------------------------------------------------------------
737 --
738 --
738 -----------------------------------------------------------------------------
739 -----------------------------------------------------------------------------
739 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
740 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
740 PORT MAP (
741 PORT MAP (
741 clk => HCLK,
742 clk => HCLK,
742 rstn => HRESETn,
743 rstn => HRESETn,
743
744
744 run => '1', --reg_sp.config_ms_run,
745 run => '1', --reg_sp.config_ms_run,
745
746
746 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
747 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
747 reg0_ready_matrix => reg0_ready_matrix_f0,
748 reg0_ready_matrix => reg0_ready_matrix_f0,
748 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
749 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
749 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
750 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
750
751
751 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
752 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
752 reg1_ready_matrix => reg1_ready_matrix_f0,
753 reg1_ready_matrix => reg1_ready_matrix_f0,
753 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
754 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
754 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
755 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
755
756
756 ready_matrix => ready_matrix_f0,
757 ready_matrix => ready_matrix_f0,
757 status_ready_matrix => status_ready_matrix_f0,
758 status_ready_matrix => status_ready_matrix_f0,
758 addr_matrix => addr_matrix_f0,
759 addr_matrix => addr_matrix_f0,
759 matrix_time => matrix_time_f0);
760 matrix_time => matrix_time_f0);
760
761
761 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
762 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
762 PORT MAP (
763 PORT MAP (
763 clk => HCLK,
764 clk => HCLK,
764 rstn => HRESETn,
765 rstn => HRESETn,
765
766
766 run => '1', --reg_sp.config_ms_run,
767 run => '1', --reg_sp.config_ms_run,
767
768
768 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
769 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
769 reg0_ready_matrix => reg0_ready_matrix_f1,
770 reg0_ready_matrix => reg0_ready_matrix_f1,
770 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
771 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
771 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
772 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
772
773
773 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
774 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
774 reg1_ready_matrix => reg1_ready_matrix_f1,
775 reg1_ready_matrix => reg1_ready_matrix_f1,
775 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
776 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
776 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
777 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
777
778
778 ready_matrix => ready_matrix_f1,
779 ready_matrix => ready_matrix_f1,
779 status_ready_matrix => status_ready_matrix_f1,
780 status_ready_matrix => status_ready_matrix_f1,
780 addr_matrix => addr_matrix_f1,
781 addr_matrix => addr_matrix_f1,
781 matrix_time => matrix_time_f1);
782 matrix_time => matrix_time_f1);
782
783
783 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
784 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
784 PORT MAP (
785 PORT MAP (
785 clk => HCLK,
786 clk => HCLK,
786 rstn => HRESETn,
787 rstn => HRESETn,
787
788
788 run => '1', --reg_sp.config_ms_run,
789 run => '1', --reg_sp.config_ms_run,
789
790
790 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
791 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
791 reg0_ready_matrix => reg0_ready_matrix_f2,
792 reg0_ready_matrix => reg0_ready_matrix_f2,
792 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
793 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
793 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
794 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
794
795
795 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
796 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
796 reg1_ready_matrix => reg1_ready_matrix_f2,
797 reg1_ready_matrix => reg1_ready_matrix_f2,
797 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
798 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
798 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
799 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
799
800
800 ready_matrix => ready_matrix_f2,
801 ready_matrix => ready_matrix_f2,
801 status_ready_matrix => status_ready_matrix_f2,
802 status_ready_matrix => status_ready_matrix_f2,
802 addr_matrix => addr_matrix_f2,
803 addr_matrix => addr_matrix_f2,
803 matrix_time => matrix_time_f2);
804 matrix_time => matrix_time_f2);
804
805
805 -----------------------------------------------------------------------------
806 -----------------------------------------------------------------------------
806 all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE
807 all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE
807 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
808 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
808 PORT MAP (
809 PORT MAP (
809 clk => HCLK,
810 clk => HCLK,
810 rstn => HRESETn,
811 rstn => HRESETn,
811
812
812 run => '1', --reg_wp.run,
813 run => '1', --reg_wp.run,
813
814
814 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
815 reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
815 reg0_ready_matrix => reg_ready_buffer_f(2*I),
816 reg0_ready_matrix => reg_ready_buffer_f(2*I),
816 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
817 reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
817 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
818 reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
818
819
819 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
820 reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
820 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
821 reg1_ready_matrix => reg_ready_buffer_f(2*I+1),
821 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
822 reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
822 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
823 reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
823
824
824 ready_matrix => wfp_ready_buffer(I),
825 ready_matrix => wfp_ready_buffer(I),
825 status_ready_matrix => wfp_status_buffer_ready(I),
826 status_ready_matrix => wfp_status_buffer_ready(I),
826 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
827 addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
827 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
828 matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
828 );
829 );
829
830
830 END GENERATE all_wfp_pointer;
831 END GENERATE all_wfp_pointer;
831 -----------------------------------------------------------------------------
832 -----------------------------------------------------------------------------
832
833
833 END beh;
834 END beh;
834
835
835 ------------------------------------------------------------------------------
836 ------------------------------------------------------------------------------
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