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Update lpp_dma (irq)
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_amba.ALL;
32 32 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36 36
37 37 ENTITY lpp_dma_apbreg IS
38 38 GENERIC (
39 39 pindex : INTEGER := 4;
40 40 paddr : INTEGER := 4;
41 41 pmask : INTEGER := 16#fff#;
42 42 pirq : INTEGER := 0);
43 43 PORT (
44 44 -- AMBA AHB system signals
45 45 HCLK : IN STD_ULOGIC;
46 46 HRESETn : IN STD_ULOGIC;
47 47
48 48 -- AMBA APB Slave Interface
49 49 apbi : IN apb_slv_in_type;
50 50 apbo : OUT apb_slv_out_type;
51 51
52 52 -- IN
53 53 ready_matrix_f0_0 : IN STD_LOGIC;
54 54 ready_matrix_f0_1 : IN STD_LOGIC;
55 55 ready_matrix_f1 : IN STD_LOGIC;
56 56 ready_matrix_f2 : IN STD_LOGIC;
57 57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 58 error_bad_component_error : IN STD_LOGIC;
59 59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60
61 61 -- OUT
62 62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 67 status_error_bad_component_error : OUT STD_LOGIC;
68 68
69 69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 70 config_active_interruption_onError : OUT STD_LOGIC;
71 71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 75 );
76 76
77 77 END lpp_dma_apbreg;
78 78
79 79 ARCHITECTURE beh OF lpp_dma_apbreg IS
80 80
81 81 CONSTANT REVISION : INTEGER := 1;
82 82
83 83 CONSTANT pconfig : apb_config_type := (
84 84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 85 1 => apb_iobar(paddr, pmask));
86 86
87 87 TYPE lpp_dma_regs IS RECORD
88 88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 89 config_active_interruption_onError : STD_LOGIC;
90 90 status_ready_matrix_f0_0 : STD_LOGIC;
91 91 status_ready_matrix_f0_1 : STD_LOGIC;
92 92 status_ready_matrix_f1 : STD_LOGIC;
93 93 status_ready_matrix_f2 : STD_LOGIC;
94 94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 95 status_error_bad_component_error : STD_LOGIC;
96 96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 END RECORD;
101 101
102 102 SIGNAL reg : lpp_dma_regs;
103 103
104 104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105
106 106 BEGIN -- beh
107 107
108 108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114 114
115 115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 120 addr_matrix_f2 <= reg.addr_matrix_f2;
121 121
122 122 lpp_dma_apbreg : PROCESS (HCLK, HRESETn)
123 123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 124 BEGIN -- PROCESS lpp_dma_top
125 125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 126 reg.config_active_interruption_onNewMatrix <= '0';
127 127 reg.config_active_interruption_onError <= '0';
128 128 reg.status_ready_matrix_f0_0 <= '0';
129 129 reg.status_ready_matrix_f0_1 <= '0';
130 130 reg.status_ready_matrix_f1 <= '0';
131 131 reg.status_ready_matrix_f2 <= '0';
132 132 reg.status_error_anticipating_empty_fifo <= '0';
133 133 reg.status_error_bad_component_error <= '0';
134 134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 138 prdata <= (OTHERS => '0');
139 139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140 140
141 141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145 145
146 146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148 148
149 149 paddr := "000000";
150 150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 151 prdata <= (OTHERS => '0');
152 152 IF apbi.psel(pindex) = '1' THEN
153 153 -- APB DMA READ --
154 154 CASE paddr(7 DOWNTO 2) IS
155 155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 156 prdata(1) <= reg.config_active_interruption_onError;
157 157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 159 prdata(2) <= reg.status_ready_matrix_f1;
160 160 prdata(3) <= reg.status_ready_matrix_f2;
161 161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 162 prdata(5) <= reg.status_error_bad_component_error;
163 163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 167 WHEN "000110" => prdata <= debug_reg;
168 168 WHEN OTHERS => NULL;
169 169 END CASE;
170 170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 171 -- APB DMA WRITE --
172 172 CASE paddr(7 DOWNTO 2) IS
173 173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 185 WHEN OTHERS => NULL;
186 186 END CASE;
187 187 END IF;
188 188 END IF;
189 189 END IF;
190 190 END PROCESS lpp_dma_apbreg;
191 191
192 apbo.pirq <= (OTHERS => '0');
192 apbo.pirq <= (reg.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
193 ready_matrix_f0_1 OR
194 ready_matrix_f1 OR
195 ready_matrix_f2)
196 )
197 OR
198 (reg.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
199 error_bad_component_error)
200 );
201
202
203
204
205
193 206 apbo.pindex <= pindex;
194 207 apbo.pconfig <= pconfig;
195 208 apbo.prdata <= prdata;
196 209
197 210
198 211 END beh;
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