@@ -1,455 +1,455 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY LFR_em IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk100MHz : IN STD_ULOGIC; |
|
52 | 52 | clk49_152MHz : IN STD_ULOGIC; |
|
53 | 53 | reset : IN STD_ULOGIC; |
|
54 | 54 | |
|
55 | 55 | -- TAG -------------------------------------------------------------------- |
|
56 | 56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
|
57 | 57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
|
58 | 58 | -- UART APB --------------------------------------------------------------- |
|
59 | 59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
|
60 | 60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
|
61 | 61 | -- RAM -------------------------------------------------------------------- |
|
62 | 62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
63 | 63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | nSRAM_BE0 : OUT STD_LOGIC; |
|
65 | 65 | nSRAM_BE1 : OUT STD_LOGIC; |
|
66 | 66 | nSRAM_BE2 : OUT STD_LOGIC; |
|
67 | 67 | nSRAM_BE3 : OUT STD_LOGIC; |
|
68 | 68 | nSRAM_WE : OUT STD_LOGIC; |
|
69 | 69 | nSRAM_CE : OUT STD_LOGIC; |
|
70 | 70 | nSRAM_OE : OUT STD_LOGIC; |
|
71 | 71 | -- SPW -------------------------------------------------------------------- |
|
72 | 72 | spw1_din : IN STD_LOGIC; |
|
73 | 73 | spw1_sin : IN STD_LOGIC; |
|
74 | 74 | spw1_dout : OUT STD_LOGIC; |
|
75 | 75 | spw1_sout : OUT STD_LOGIC; |
|
76 | 76 | spw2_din : IN STD_LOGIC; |
|
77 | 77 | spw2_sin : IN STD_LOGIC; |
|
78 | 78 | spw2_dout : OUT STD_LOGIC; |
|
79 | 79 | spw2_sout : OUT STD_LOGIC; |
|
80 | 80 | -- ADC -------------------------------------------------------------------- |
|
81 | 81 | bias_fail_sw : OUT STD_LOGIC; |
|
82 | 82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
83 | 83 | ADC_smpclk : OUT STD_LOGIC; |
|
84 | 84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
85 | 85 | -- DAC -------------------------------------------------------------------- |
|
86 | 86 | DAC_SDO : OUT STD_LOGIC; |
|
87 | 87 | DAC_SCK : OUT STD_LOGIC; |
|
88 | 88 | DAC_SYNC : OUT STD_LOGIC; |
|
89 | 89 | DAC_CAL_EN : OUT STD_LOGIC; |
|
90 | 90 | -- HK --------------------------------------------------------------------- |
|
91 | 91 | HK_smpclk : OUT STD_LOGIC; |
|
92 | 92 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
93 | 93 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
94 | 94 | --------------------------------------------------------------------------- |
|
95 | 95 | TAG8 : OUT STD_LOGIC; |
|
96 | 96 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
|
97 | 97 | ); |
|
98 | 98 | |
|
99 | 99 | END LFR_em; |
|
100 | 100 | |
|
101 | 101 | |
|
102 | 102 | ARCHITECTURE beh OF LFR_em IS |
|
103 | 103 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
104 | 104 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
105 | 105 | SIGNAL clk_24 : STD_LOGIC := '0'; |
|
106 | 106 | ----------------------------------------------------------------------------- |
|
107 | 107 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 108 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
109 | 109 | |
|
110 | 110 | -- CONSTANTS |
|
111 | 111 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
112 | 112 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
113 | 113 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
114 | 114 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
115 | 115 | |
|
116 | 116 | SIGNAL apbi_ext : apb_slv_in_type; |
|
117 | 117 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
118 | 118 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
119 | 119 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
120 | 120 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
121 | 121 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
122 | 122 | |
|
123 | 123 | -- Spacewire signals |
|
124 | 124 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
125 | 125 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
126 | 126 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
127 | 127 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
128 | 128 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
129 | 129 | SIGNAL spw_clk : STD_LOGIC; |
|
130 | 130 | SIGNAL swni : grspw_in_type; |
|
131 | 131 | SIGNAL swno : grspw_out_type; |
|
132 | 132 | |
|
133 | 133 | --GPIO |
|
134 | 134 | SIGNAL gpioi : gpio_in_type; |
|
135 | 135 | SIGNAL gpioo : gpio_out_type; |
|
136 | 136 | |
|
137 | 137 | -- AD Converter ADS7886 |
|
138 | 138 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
|
139 | 139 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
|
140 | 140 | SIGNAL sample_val : STD_LOGIC; |
|
141 | 141 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
|
142 | 142 | |
|
143 | 143 | ----------------------------------------------------------------------------- |
|
144 | 144 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
145 | 145 | |
|
146 | 146 | ----------------------------------------------------------------------------- |
|
147 | 147 | SIGNAL rstn : STD_LOGIC; |
|
148 | 148 | |
|
149 | 149 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
150 | 150 | SIGNAL LFR_rstn : STD_LOGIC; |
|
151 | 151 | |
|
152 | 152 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
|
153 | 153 | ----------------------------------------------------------------------------- |
|
154 | 154 | SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
155 | 155 | |
|
156 | 156 | BEGIN -- beh |
|
157 | 157 | |
|
158 | 158 | ----------------------------------------------------------------------------- |
|
159 | 159 | -- CLK |
|
160 | 160 | ----------------------------------------------------------------------------- |
|
161 | 161 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); |
|
162 | 162 | |
|
163 | 163 | PROCESS(clk100MHz) |
|
164 | 164 | BEGIN |
|
165 | 165 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
|
166 | 166 | clk_50_s <= NOT clk_50_s; |
|
167 | 167 | END IF; |
|
168 | 168 | END PROCESS; |
|
169 | 169 | |
|
170 | 170 | PROCESS(clk_50_s) |
|
171 | 171 | BEGIN |
|
172 | 172 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
173 | 173 | clk_25 <= NOT clk_25; |
|
174 | 174 | END IF; |
|
175 | 175 | END PROCESS; |
|
176 | 176 | |
|
177 | 177 | PROCESS(clk49_152MHz) |
|
178 | 178 | BEGIN |
|
179 | 179 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
|
180 | 180 | clk_24 <= NOT clk_24; |
|
181 | 181 | END IF; |
|
182 | 182 | END PROCESS; |
|
183 | 183 | |
|
184 | 184 | ----------------------------------------------------------------------------- |
|
185 | 185 | |
|
186 | 186 | PROCESS (clk_25, rstn) |
|
187 | 187 | BEGIN -- PROCESS |
|
188 | 188 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
189 | 189 | led(0) <= '0'; |
|
190 | 190 | led(1) <= '0'; |
|
191 | 191 | led(2) <= '0'; |
|
192 | 192 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
193 | 193 | led(0) <= '0'; |
|
194 | 194 | led(1) <= '1'; |
|
195 | 195 | led(2) <= '1'; |
|
196 | 196 | END IF; |
|
197 | 197 | END PROCESS; |
|
198 | 198 | |
|
199 | 199 | -- |
|
200 | 200 | leon3_soc_1 : leon3_soc |
|
201 | 201 | GENERIC MAP ( |
|
202 | 202 | fabtech => apa3e, |
|
203 | 203 | memtech => apa3e, |
|
204 | 204 | padtech => inferred, |
|
205 | 205 | clktech => inferred, |
|
206 | 206 | disas => 0, |
|
207 | 207 | dbguart => 0, |
|
208 | 208 | pclow => 2, |
|
209 | 209 | clk_freq => 25000, |
|
210 | 210 | IS_RADHARD => 0, |
|
211 | 211 | NB_CPU => 1, |
|
212 | 212 | ENABLE_FPU => 1, |
|
213 | 213 | FPU_NETLIST => 0, |
|
214 | 214 | ENABLE_DSU => 1, |
|
215 | 215 | ENABLE_AHB_UART => 1, |
|
216 | 216 | ENABLE_APB_UART => 1, |
|
217 | 217 | ENABLE_IRQMP => 1, |
|
218 | 218 | ENABLE_GPT => 1, |
|
219 | 219 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
220 | 220 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
221 | 221 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
222 | 222 | ADDRESS_SIZE => 20, |
|
223 | 223 | USES_IAP_MEMCTRLR => 0) |
|
224 | 224 | PORT MAP ( |
|
225 | 225 | clk => clk_25, |
|
226 | 226 | reset => rstn, |
|
227 | 227 | errorn => OPEN, |
|
228 | 228 | |
|
229 | 229 | ahbrxd => TAG1, |
|
230 | 230 | ahbtxd => TAG3, |
|
231 | 231 | urxd1 => TAG2, |
|
232 | 232 | utxd1 => TAG4, |
|
233 | 233 | |
|
234 | 234 | address => address, |
|
235 | 235 | data => data, |
|
236 | 236 | nSRAM_BE0 => nSRAM_BE0, |
|
237 | 237 | nSRAM_BE1 => nSRAM_BE1, |
|
238 | 238 | nSRAM_BE2 => nSRAM_BE2, |
|
239 | 239 | nSRAM_BE3 => nSRAM_BE3, |
|
240 | 240 | nSRAM_WE => nSRAM_WE, |
|
241 | 241 | nSRAM_CE => nSRAM_CE_s, |
|
242 | 242 | nSRAM_OE => nSRAM_OE, |
|
243 | 243 | nSRAM_READY => '0', |
|
244 | 244 | SRAM_MBE => OPEN, |
|
245 | 245 | |
|
246 | 246 | apbi_ext => apbi_ext, |
|
247 | 247 | apbo_ext => apbo_ext, |
|
248 | 248 | ahbi_s_ext => ahbi_s_ext, |
|
249 | 249 | ahbo_s_ext => ahbo_s_ext, |
|
250 | 250 | ahbi_m_ext => ahbi_m_ext, |
|
251 | 251 | ahbo_m_ext => ahbo_m_ext); |
|
252 | 252 | |
|
253 | 253 | |
|
254 | 254 | nSRAM_CE <= nSRAM_CE_s(0); |
|
255 | 255 | |
|
256 | 256 | ------------------------------------------------------------------------------- |
|
257 | 257 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
258 | 258 | ------------------------------------------------------------------------------- |
|
259 | 259 | apb_lfr_management_1 : apb_lfr_management |
|
260 | 260 | GENERIC MAP ( |
|
261 | 261 | tech => apa3e, |
|
262 | 262 | pindex => 6, |
|
263 | 263 | paddr => 6, |
|
264 | 264 | pmask => 16#fff#, |
|
265 | 265 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
266 | 266 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
267 | 267 | PORT MAP ( |
|
268 | 268 | clk25MHz => clk_25, |
|
269 | 269 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
270 | 270 | resetn => rstn, |
|
271 | 271 | grspw_tick => swno.tickout, |
|
272 | 272 | apbi => apbi_ext, |
|
273 | 273 | apbo => apbo_ext(6), |
|
274 | 274 | |
|
275 | 275 | HK_sample => sample_s(8), |
|
276 | 276 | HK_val => sample_val, |
|
277 | 277 | HK_sel => HK_SEL, |
|
278 | 278 | |
|
279 | 279 | DAC_SDO => DAC_SDO, |
|
280 | 280 | DAC_SCK => DAC_SCK, |
|
281 | 281 | DAC_SYNC => DAC_SYNC, |
|
282 | 282 | DAC_CAL_EN => DAC_CAL_EN, |
|
283 | 283 | |
|
284 | 284 | coarse_time => coarse_time, |
|
285 | 285 | fine_time => fine_time, |
|
286 | 286 | LFR_soft_rstn => LFR_soft_rstn |
|
287 | 287 | ); |
|
288 | 288 | |
|
289 | 289 | ----------------------------------------------------------------------- |
|
290 | 290 | --- SpaceWire -------------------------------------------------------- |
|
291 | 291 | ----------------------------------------------------------------------- |
|
292 | 292 | |
|
293 | 293 | -- SPW_EN <= '1'; |
|
294 | 294 | |
|
295 | 295 | spw_clk <= clk_50_s; |
|
296 | 296 | spw_rxtxclk <= spw_clk; |
|
297 | 297 | spw_rxclkn <= NOT spw_rxtxclk; |
|
298 | 298 | |
|
299 | 299 | -- PADS for SPW1 |
|
300 | 300 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
301 | 301 | PORT MAP (spw1_din, dtmp(0)); |
|
302 | 302 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
303 | 303 | PORT MAP (spw1_sin, stmp(0)); |
|
304 | 304 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
305 | 305 | PORT MAP (spw1_dout, swno.d(0)); |
|
306 | 306 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
307 | 307 | PORT MAP (spw1_sout, swno.s(0)); |
|
308 | 308 | -- PADS FOR SPW2 |
|
309 | 309 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
310 | 310 | PORT MAP (spw2_din, dtmp(1)); |
|
311 | 311 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
312 | 312 | PORT MAP (spw2_sin, stmp(1)); |
|
313 | 313 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
314 | 314 | PORT MAP (spw2_dout, swno.d(1)); |
|
315 | 315 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
316 | 316 | PORT MAP (spw2_sout, swno.s(1)); |
|
317 | 317 | |
|
318 | 318 | -- GRSPW PHY |
|
319 | 319 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
320 | 320 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
321 | 321 | spw_phy0 : grspw_phy |
|
322 | 322 | GENERIC MAP( |
|
323 | 323 | tech => apa3e, |
|
324 | 324 | rxclkbuftype => 1, |
|
325 | 325 | scantest => 0) |
|
326 | 326 | PORT MAP( |
|
327 | 327 | rxrst => swno.rxrst, |
|
328 | 328 | di => dtmp(j), |
|
329 | 329 | si => stmp(j), |
|
330 | 330 | rxclko => spw_rxclk(j), |
|
331 | 331 | do => swni.d(j), |
|
332 | 332 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
333 | 333 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
334 | 334 | END GENERATE spw_inputloop; |
|
335 | 335 | |
|
336 | 336 | -- SPW core |
|
337 | 337 | sw0 : grspwm GENERIC MAP( |
|
338 | 338 | tech => apa3e, |
|
339 | 339 | hindex => 1, |
|
340 | 340 | pindex => 5, |
|
341 | 341 | paddr => 5, |
|
342 | 342 | pirq => 11, |
|
343 | 343 | sysfreq => 25000, -- CPU_FREQ |
|
344 | 344 | rmap => 1, |
|
345 | 345 | rmapcrc => 1, |
|
346 | 346 | fifosize1 => 16, |
|
347 | 347 | fifosize2 => 16, |
|
348 | 348 | rxclkbuftype => 1, |
|
349 | 349 | rxunaligned => 0, |
|
350 | 350 | rmapbufs => 4, |
|
351 | 351 | ft => 0, |
|
352 | 352 | netlist => 0, |
|
353 | 353 | ports => 2, |
|
354 | 354 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
355 | 355 | memtech => apa3e, |
|
356 | 356 | destkey => 2, |
|
357 | 357 | spwcore => 1 |
|
358 | 358 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
359 | 359 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
360 | 360 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
361 | 361 | ) |
|
362 | 362 | PORT MAP(rstn, clk_25, spw_rxclk(0), |
|
363 | 363 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
364 | 364 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
365 | 365 | swni, swno); |
|
366 | 366 | |
|
367 | 367 | swni.tickin <= '0'; |
|
368 | 368 | swni.rmapen <= '1'; |
|
369 | 369 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
370 | 370 | swni.tickinraw <= '0'; |
|
371 | 371 | swni.timein <= (OTHERS => '0'); |
|
372 | 372 | swni.dcrstval <= (OTHERS => '0'); |
|
373 | 373 | swni.timerrstval <= (OTHERS => '0'); |
|
374 | 374 | |
|
375 | 375 | ------------------------------------------------------------------------------- |
|
376 | 376 | -- LFR ------------------------------------------------------------------------ |
|
377 | 377 | ------------------------------------------------------------------------------- |
|
378 | 378 | LFR_rstn <= LFR_soft_rstn AND rstn; |
|
379 | 379 | |
|
380 | 380 | lpp_lfr_1 : lpp_lfr |
|
381 | 381 | GENERIC MAP ( |
|
382 | 382 | Mem_use => use_RAM, |
|
383 | 383 | nb_data_by_buffer_size => 32, |
|
384 | 384 | --nb_word_by_buffer_size => 30, |
|
385 | 385 | nb_snapshot_param_size => 32, |
|
386 | 386 | delta_vector_size => 32, |
|
387 | 387 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
388 | 388 | pindex => 15, |
|
389 | 389 | paddr => 15, |
|
390 | 390 | pmask => 16#fff#, |
|
391 | 391 | pirq_ms => 6, |
|
392 | 392 | pirq_wfp => 14, |
|
393 | 393 | hindex => 2, |
|
394 |
top_lfr_version => X"01013 |
|
|
394 | top_lfr_version => X"01013C") -- aa.bb.cc version | |
|
395 | 395 | -- AA : BOARD NUMBER |
|
396 | 396 | -- 0 => MINI_LFR |
|
397 | 397 | -- 1 => EM |
|
398 | 398 | PORT MAP ( |
|
399 | 399 | clk => clk_25, |
|
400 | 400 | rstn => LFR_rstn, |
|
401 | 401 | sample_B => sample_s(2 DOWNTO 0), |
|
402 | 402 | sample_E => sample_s(7 DOWNTO 3), |
|
403 | 403 | sample_val => sample_val, |
|
404 | 404 | apbi => apbi_ext, |
|
405 | 405 | apbo => apbo_ext(15), |
|
406 | 406 | ahbi => ahbi_m_ext, |
|
407 | 407 | ahbo => ahbo_m_ext(2), |
|
408 | 408 | coarse_time => coarse_time, |
|
409 | 409 | fine_time => fine_time, |
|
410 | 410 | data_shaping_BW => bias_fail_sw, |
|
411 | 411 | debug_vector => OPEN, |
|
412 | 412 | debug_vector_ms => OPEN); --, |
|
413 | 413 | --observation_vector_0 => OPEN, |
|
414 | 414 | --observation_vector_1 => OPEN, |
|
415 | 415 | --observation_reg => observation_reg); |
|
416 | 416 | |
|
417 | 417 | |
|
418 | 418 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
419 | 419 | sample_s(I) <= sample(I) & '0' & '0'; |
|
420 | 420 | END GENERATE all_sample; |
|
421 | 421 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
422 | 422 | |
|
423 | 423 | ----------------------------------------------------------------------------- |
|
424 | 424 | -- |
|
425 | 425 | ----------------------------------------------------------------------------- |
|
426 | 426 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
427 | 427 | GENERIC MAP ( |
|
428 | 428 | ChanelCount => 9, |
|
429 | 429 | ncycle_cnv_high => 13, |
|
430 | 430 | ncycle_cnv => 25, |
|
431 | 431 | FILTER_ENABLED => 16#FF#) |
|
432 | 432 | PORT MAP ( |
|
433 | 433 | cnv_clk => clk_24, |
|
434 | 434 | cnv_rstn => rstn, |
|
435 | 435 | cnv => ADC_smpclk_s, |
|
436 | 436 | clk => clk_25, |
|
437 | 437 | rstn => rstn, |
|
438 | 438 | ADC_data => ADC_data, |
|
439 | 439 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
440 | 440 | sample => sample, |
|
441 | 441 | sample_val => sample_val); |
|
442 | 442 | |
|
443 | 443 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
444 | 444 | |
|
445 | 445 | ADC_smpclk <= ADC_smpclk_s; |
|
446 | 446 | HK_smpclk <= ADC_smpclk_s; |
|
447 | 447 | |
|
448 | 448 | TAG8 <= ADC_smpclk_s; |
|
449 | 449 | |
|
450 | 450 | ----------------------------------------------------------------------------- |
|
451 | 451 | -- HK |
|
452 | 452 | ----------------------------------------------------------------------------- |
|
453 | 453 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
454 | 454 | |
|
455 | 455 | END beh; |
@@ -1,507 +1,531 | |||
|
1 | 1 | ---------------------------------------------------------------------------------- |
|
2 | 2 | -- Company: |
|
3 | 3 | -- Engineer: |
|
4 | 4 | -- |
|
5 | 5 | -- Create Date: 11:17:05 07/02/2012 |
|
6 | 6 | -- Design Name: |
|
7 | 7 | -- Module Name: apb_lfr_time_management - Behavioral |
|
8 | 8 | -- Project Name: |
|
9 | 9 | -- Target Devices: |
|
10 | 10 | -- Tool versions: |
|
11 | 11 | -- Description: |
|
12 | 12 | -- |
|
13 | 13 | -- Dependencies: |
|
14 | 14 | -- |
|
15 | 15 | -- Revision: |
|
16 | 16 | -- Revision 0.01 - File Created |
|
17 | 17 | -- Additional Comments: |
|
18 | 18 | -- |
|
19 | 19 | ---------------------------------------------------------------------------------- |
|
20 | 20 | LIBRARY IEEE; |
|
21 | 21 | USE IEEE.STD_LOGIC_1164.ALL; |
|
22 | 22 | USE IEEE.NUMERIC_STD.ALL; |
|
23 | 23 | LIBRARY grlib; |
|
24 | 24 | USE grlib.amba.ALL; |
|
25 | 25 | USE grlib.stdlib.ALL; |
|
26 | 26 | USE grlib.devices.ALL; |
|
27 | 27 | LIBRARY lpp; |
|
28 | 28 | USE lpp.apb_devices_list.ALL; |
|
29 | 29 | USE lpp.general_purpose.ALL; |
|
30 | 30 | USE lpp.lpp_lfr_management.ALL; |
|
31 | 31 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; |
|
32 | 32 | USE lpp.lpp_cna.ALL; |
|
33 | 33 | LIBRARY techmap; |
|
34 | 34 | USE techmap.gencomp.ALL; |
|
35 | 35 | |
|
36 | 36 | |
|
37 | 37 | ENTITY apb_lfr_management IS |
|
38 | 38 | |
|
39 | 39 | GENERIC( |
|
40 | 40 | tech : INTEGER := 0; |
|
41 | 41 | pindex : INTEGER := 0; --! APB slave index |
|
42 | 42 | paddr : INTEGER := 0; --! ADDR field of the APB BAR |
|
43 | 43 | pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR |
|
44 | 44 | FIRST_DIVISION : INTEGER := 374; |
|
45 | 45 | NB_SECOND_DESYNC : INTEGER := 60 |
|
46 | 46 | ); |
|
47 | 47 | |
|
48 | 48 | PORT ( |
|
49 | 49 | clk25MHz : IN STD_LOGIC; --! Clock |
|
50 | 50 | clk24_576MHz : IN STD_LOGIC; --! secondary clock |
|
51 | 51 | resetn : IN STD_LOGIC; --! Reset |
|
52 | 52 | |
|
53 | 53 | grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received |
|
54 | 54 | |
|
55 | 55 | apbi : IN apb_slv_in_type; --! APB slave input signals |
|
56 | 56 | apbo : OUT apb_slv_out_type; --! APB slave output signals |
|
57 | 57 | --------------------------------------------------------------------------- |
|
58 | 58 | HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
59 | 59 | HK_val : IN STD_LOGIC; |
|
60 | 60 | HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 61 | --------------------------------------------------------------------------- |
|
62 | DAC_SDO : OUT STD_LOGIC; | |
|
63 | DAC_SCK : OUT STD_LOGIC; | |
|
64 | DAC_SYNC : OUT STD_LOGIC; | |
|
65 | DAC_CAL_EN : OUT STD_LOGIC; | |
|
62 | DAC_SDO : OUT STD_LOGIC; | |
|
63 | DAC_SCK : OUT STD_LOGIC; | |
|
64 | DAC_SYNC : OUT STD_LOGIC; | |
|
65 | DAC_CAL_EN : OUT STD_LOGIC; | |
|
66 | 66 | --------------------------------------------------------------------------- |
|
67 | 67 | coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time |
|
68 | 68 | fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME |
|
69 | 69 | --------------------------------------------------------------------------- |
|
70 | 70 | LFR_soft_rstn : OUT STD_LOGIC |
|
71 | 71 | ); |
|
72 | 72 | |
|
73 | 73 | END apb_lfr_management; |
|
74 | 74 | |
|
75 | 75 | ARCHITECTURE Behavioral OF apb_lfr_management IS |
|
76 | 76 | |
|
77 | 77 | CONSTANT REVISION : INTEGER := 1; |
|
78 | 78 | CONSTANT pconfig : apb_config_type := ( |
|
79 | 79 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0), |
|
80 | 80 | 1 => apb_iobar(paddr, pmask) |
|
81 | 81 | ); |
|
82 | 82 | |
|
83 | 83 | TYPE apb_lfr_time_management_Reg IS RECORD |
|
84 | 84 | ctrl : STD_LOGIC; |
|
85 | 85 | soft_reset : STD_LOGIC; |
|
86 | 86 | coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
87 | 87 | coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
88 | 88 | fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
89 | 89 | LFR_soft_reset : STD_LOGIC; |
|
90 | 90 | HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
91 | 91 | HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
92 | 92 | HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
93 | 93 | END RECORD; |
|
94 | 94 | SIGNAL r : apb_lfr_time_management_Reg; |
|
95 | 95 | |
|
96 | 96 | SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
97 | 97 | SIGNAL force_tick : STD_LOGIC; |
|
98 | 98 | SIGNAL previous_force_tick : STD_LOGIC; |
|
99 | 99 | SIGNAL soft_tick : STD_LOGIC; |
|
100 | 100 | |
|
101 | 101 | SIGNAL coarsetime_reg_updated : STD_LOGIC; |
|
102 | 102 | SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
103 | 103 | |
|
104 | 104 | --SIGNAL coarse_time_new : STD_LOGIC; |
|
105 | 105 | SIGNAL coarse_time_new_49 : STD_LOGIC; |
|
106 | 106 | SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 107 | SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 108 | |
|
109 | 109 | --SIGNAL fine_time_new : STD_LOGIC; |
|
110 | 110 | --SIGNAL fine_time_new_temp : STD_LOGIC; |
|
111 | 111 | SIGNAL fine_time_new_49 : STD_LOGIC; |
|
112 | 112 | SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
113 | 113 | SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
114 | 114 | SIGNAL tick : STD_LOGIC; |
|
115 | 115 | SIGNAL new_timecode : STD_LOGIC; |
|
116 | 116 | SIGNAL new_coarsetime : STD_LOGIC; |
|
117 | 117 | |
|
118 | 118 | SIGNAL time_new_49 : STD_LOGIC; |
|
119 | 119 | SIGNAL time_new : STD_LOGIC; |
|
120 | 120 | |
|
121 | 121 | ----------------------------------------------------------------------------- |
|
122 | 122 | SIGNAL force_reset : STD_LOGIC; |
|
123 | 123 | SIGNAL previous_force_reset : STD_LOGIC; |
|
124 | 124 | SIGNAL soft_reset : STD_LOGIC; |
|
125 | 125 | SIGNAL soft_reset_sync : STD_LOGIC; |
|
126 | 126 | ----------------------------------------------------------------------------- |
|
127 | 127 | SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
128 | 128 | |
|
129 | 129 | SIGNAL previous_fine_time_bit : STD_LOGIC; |
|
130 | ||
|
130 | ||
|
131 | 131 | SIGNAL rstn_LFR_TM : STD_LOGIC; |
|
132 | 132 | |
|
133 | 133 | ----------------------------------------------------------------------------- |
|
134 | 134 | -- DAC |
|
135 | 135 | ----------------------------------------------------------------------------- |
|
136 |
CONSTANT |
|
|
137 |
CONSTANT |
|
|
138 |
CONSTANT |
|
|
139 |
CONSTANT |
|
|
140 |
CONSTANT |
|
|
141 | ||
|
136 | CONSTANT PRESZ : INTEGER := 8; | |
|
137 | CONSTANT CPTSZ : INTEGER := 16; | |
|
138 | CONSTANT datawidth : INTEGER := 18; | |
|
139 | CONSTANT dacresolution : INTEGER := 12; | |
|
140 | CONSTANT abits : INTEGER := 8; | |
|
141 | ||
|
142 | 142 | SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0); |
|
143 | 143 | SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0); |
|
144 | 144 | SIGNAL Reload : STD_LOGIC; |
|
145 | 145 | SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0); |
|
146 | 146 | SIGNAL WEN : STD_LOGIC; |
|
147 | 147 | SIGNAL LOAD_ADDRESSN : STD_LOGIC; |
|
148 | 148 | SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); |
|
149 | 149 | SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0); |
|
150 | 150 | SIGNAL INTERLEAVED : STD_LOGIC; |
|
151 | 151 | SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
152 | 152 | SIGNAL DAC_CAL_EN_s : STD_LOGIC; |
|
153 | 153 | |
|
154 | SIGNAL HK_debug_mode : STD_LOGIC; | |
|
155 | SIGNAL HK_sel_debug : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
156 | ||
|
154 | 157 | BEGIN |
|
155 | 158 | |
|
156 | 159 | LFR_soft_rstn <= NOT r.LFR_soft_reset; |
|
157 | 160 | |
|
158 | 161 | PROCESS(resetn, clk25MHz) |
|
159 | 162 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
160 | 163 | BEGIN |
|
161 | 164 | |
|
162 | 165 | IF resetn = '0' THEN |
|
163 | 166 | Rdata <= (OTHERS => '0'); |
|
164 | 167 | r.coarse_time_load <= (OTHERS => '0'); |
|
165 | 168 | r.soft_reset <= '0'; |
|
166 | 169 | r.ctrl <= '0'; |
|
167 | 170 | r.LFR_soft_reset <= '1'; |
|
168 | 171 | |
|
169 | 172 | force_tick <= '0'; |
|
170 | 173 | previous_force_tick <= '0'; |
|
171 | 174 | soft_tick <= '0'; |
|
172 | 175 | |
|
173 | 176 | coarsetime_reg_updated <= '0'; |
|
174 | 177 | --DAC |
|
175 | pre <= (OTHERS => '1'); | |
|
176 | N <= (OTHERS => '1'); | |
|
177 | Reload <= '1'; | |
|
178 | DATA_IN <= (OTHERS => '0'); | |
|
179 | WEN <= '1'; | |
|
180 | LOAD_ADDRESSN <= '1'; | |
|
181 | ADDRESS_IN <= (OTHERS => '1'); | |
|
182 | INTERLEAVED <= '0'; | |
|
183 | DAC_CFG <= (OTHERS => '0'); | |
|
178 | pre <= (OTHERS => '1'); | |
|
179 | N <= (OTHERS => '1'); | |
|
180 | Reload <= '1'; | |
|
181 | DATA_IN <= (OTHERS => '0'); | |
|
182 | WEN <= '1'; | |
|
183 | LOAD_ADDRESSN <= '1'; | |
|
184 | ADDRESS_IN <= (OTHERS => '1'); | |
|
185 | INTERLEAVED <= '0'; | |
|
186 | DAC_CFG <= (OTHERS => '0'); | |
|
184 | 187 | -- |
|
185 | DAC_CAL_EN_s <= '0'; | |
|
188 | DAC_CAL_EN_s <= '0'; | |
|
186 | 189 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN |
|
187 | 190 | coarsetime_reg_updated <= '0'; |
|
188 | 191 | |
|
189 | 192 | force_tick <= r.ctrl; |
|
190 | 193 | previous_force_tick <= force_tick; |
|
191 | 194 | IF (previous_force_tick = '0') AND (force_tick = '1') THEN |
|
192 | 195 | soft_tick <= '1'; |
|
193 | 196 | ELSE |
|
194 | 197 | soft_tick <= '0'; |
|
195 | 198 | END IF; |
|
196 | 199 | |
|
197 | 200 | force_reset <= r.soft_reset; |
|
198 | 201 | previous_force_reset <= force_reset; |
|
199 | 202 | IF (previous_force_reset = '0') AND (force_reset = '1') THEN |
|
200 | 203 | soft_reset <= '1'; |
|
201 | 204 | ELSE |
|
202 | 205 | soft_reset <= '0'; |
|
203 | 206 | END IF; |
|
204 | 207 | |
|
205 | 208 | paddr := "000000"; |
|
206 | 209 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
207 | 210 | Rdata <= (OTHERS => '0'); |
|
208 | 211 | |
|
209 | 212 | |
|
210 | 213 | IF apbi.psel(pindex) = '1' THEN |
|
211 | 214 | --APB READ OP |
|
212 | 215 | CASE paddr(7 DOWNTO 2) IS |
|
213 | 216 | WHEN ADDR_LFR_MANAGMENT_CONTROL => |
|
214 | 217 | Rdata(0) <= r.ctrl; |
|
215 | 218 | Rdata(1) <= r.soft_reset; |
|
216 | 219 | Rdata(2) <= r.LFR_soft_reset; |
|
217 | Rdata(31 DOWNTO 3) <= (OTHERS => '0'); | |
|
220 | Rdata(3) <= HK_debug_mode; | |
|
221 | Rdata(5 DOWNTO 4) <= HK_sel_debug; | |
|
222 | Rdata(31 DOWNTO 6) <= (OTHERS => '0'); | |
|
218 | 223 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => |
|
219 | 224 | Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); |
|
220 | 225 | WHEN ADDR_LFR_MANAGMENT_TIME_COARSE => |
|
221 | 226 | Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); |
|
222 | 227 | WHEN ADDR_LFR_MANAGMENT_TIME_FINE => |
|
223 | 228 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
224 | 229 | Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); |
|
225 | 230 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 => |
|
226 | 231 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
227 | 232 | Rdata(15 DOWNTO 0) <= r.HK_temp_0; |
|
228 | 233 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 => |
|
229 | 234 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
230 | 235 | Rdata(15 DOWNTO 0) <= r.HK_temp_1; |
|
231 | 236 | WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 => |
|
232 | 237 | Rdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
233 | 238 | Rdata(15 DOWNTO 0) <= r.HK_temp_2; |
|
234 | 239 | WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL => |
|
235 | 240 | Rdata(3 DOWNTO 0) <= DAC_CFG; |
|
236 | 241 | Rdata(4) <= Reload; |
|
237 | 242 | Rdata(5) <= INTERLEAVED; |
|
238 | 243 | Rdata(6) <= DAC_CAL_EN_s; |
|
239 | 244 | Rdata(31 DOWNTO 7) <= (OTHERS => '0'); |
|
240 | 245 | WHEN ADDR_LFR_MANAGMENT_DAC_PRE => |
|
241 | 246 | Rdata(PRESZ-1 DOWNTO 0) <= pre; |
|
242 | 247 | Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0'); |
|
243 | 248 | WHEN ADDR_LFR_MANAGMENT_DAC_N => |
|
244 | 249 | Rdata(CPTSZ-1 DOWNTO 0) <= N; |
|
245 | 250 | Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0'); |
|
246 | 251 | WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT => |
|
247 | 252 | Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT; |
|
248 | 253 | Rdata(31 DOWNTO abits) <= (OTHERS => '0'); |
|
249 | 254 | WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => |
|
250 | 255 | Rdata(datawidth-1 DOWNTO 0) <= DATA_IN; |
|
251 | 256 | Rdata(31 DOWNTO datawidth) <= (OTHERS => '0'); |
|
252 | 257 | WHEN OTHERS => |
|
253 | 258 | Rdata(31 DOWNTO 0) <= (OTHERS => '0'); |
|
254 | 259 | END CASE; |
|
255 | ||
|
260 | ||
|
256 | 261 | --APB Write OP |
|
257 | 262 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
258 | 263 | CASE paddr(7 DOWNTO 2) IS |
|
259 | 264 | WHEN ADDR_LFR_MANAGMENT_CONTROL => |
|
260 | 265 | r.ctrl <= apbi.pwdata(0); |
|
261 | 266 | r.soft_reset <= apbi.pwdata(1); |
|
262 | 267 | r.LFR_soft_reset <= apbi.pwdata(2); |
|
268 | HK_debug_mode <= apbi.pwdata(3); | |
|
269 | HK_sel_debug <= apbi.pwdata(5 DOWNTO 4); | |
|
263 | 270 | WHEN ADDR_LFR_MANAGMENT_TIME_LOAD => |
|
264 | 271 | r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); |
|
265 | 272 | coarsetime_reg_updated <= '1'; |
|
266 | WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL => | |
|
267 | DAC_CFG <= apbi.pwdata(3 DOWNTO 0); | |
|
268 | Reload <= apbi.pwdata(4); | |
|
269 | INTERLEAVED <= apbi.pwdata(5); | |
|
270 | DAC_CAL_EN_s <= apbi.pwdata(6); | |
|
271 | WHEN ADDR_LFR_MANAGMENT_DAC_PRE => | |
|
272 | pre <= apbi.pwdata(PRESZ-1 DOWNTO 0); | |
|
273 | WHEN ADDR_LFR_MANAGMENT_DAC_N => | |
|
274 | N <= apbi.pwdata(CPTSZ-1 DOWNTO 0); | |
|
275 | WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT => | |
|
276 | ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0); | |
|
277 | LOAD_ADDRESSN <= '0'; | |
|
278 | WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => | |
|
279 | DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0); | |
|
280 | WEN <= '0'; | |
|
273 | WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL => | |
|
274 | DAC_CFG <= apbi.pwdata(3 DOWNTO 0); | |
|
275 | Reload <= apbi.pwdata(4); | |
|
276 | INTERLEAVED <= apbi.pwdata(5); | |
|
277 | DAC_CAL_EN_s <= apbi.pwdata(6); | |
|
278 | WHEN ADDR_LFR_MANAGMENT_DAC_PRE => | |
|
279 | pre <= apbi.pwdata(PRESZ-1 DOWNTO 0); | |
|
280 | WHEN ADDR_LFR_MANAGMENT_DAC_N => | |
|
281 | N <= apbi.pwdata(CPTSZ-1 DOWNTO 0); | |
|
282 | WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT => | |
|
283 | ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0); | |
|
284 | LOAD_ADDRESSN <= '0'; | |
|
285 | WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN => | |
|
286 | DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0); | |
|
287 | WEN <= '0'; | |
|
281 | 288 | |
|
282 | 289 | WHEN OTHERS => |
|
283 | 290 | NULL; |
|
284 | 291 | END CASE; |
|
285 | 292 | ELSE |
|
286 | 293 | LOAD_ADDRESSN <= '1'; |
|
287 | 294 | WEN <= '1'; |
|
288 | 295 | IF r.ctrl = '1' THEN |
|
289 | 296 | r.ctrl <= '0'; |
|
290 | 297 | END IF; |
|
291 | 298 | IF r.soft_reset = '1' THEN |
|
292 | 299 | r.soft_reset <= '0'; |
|
293 | 300 | END IF; |
|
294 | 301 | END IF; |
|
295 | 302 | |
|
296 | 303 | END IF; |
|
297 | 304 | |
|
298 | 305 | END IF; |
|
299 | 306 | END PROCESS; |
|
300 | 307 | |
|
301 | 308 | apbo.pirq <= (OTHERS => '0'); |
|
302 | 309 | apbo.prdata <= Rdata; |
|
303 | 310 | apbo.pconfig <= pconfig; |
|
304 | 311 | apbo.pindex <= pindex; |
|
305 | 312 | |
|
306 | 313 | ----------------------------------------------------------------------------- |
|
307 | 314 | -- IN |
|
308 | 315 | coarse_time <= r.coarse_time; |
|
309 | 316 | fine_time <= r.fine_time; |
|
310 | 317 | coarsetime_reg <= r.coarse_time_load; |
|
311 | 318 | ----------------------------------------------------------------------------- |
|
312 | 319 | |
|
313 | 320 | ----------------------------------------------------------------------------- |
|
314 | 321 | -- OUT |
|
315 | 322 | r.coarse_time <= coarse_time_s; |
|
316 | 323 | r.fine_time <= fine_time_s; |
|
317 | 324 | ----------------------------------------------------------------------------- |
|
318 | 325 | |
|
319 | 326 | ----------------------------------------------------------------------------- |
|
320 | 327 | tick <= grspw_tick OR soft_tick; |
|
321 | 328 | |
|
322 | 329 | SYNC_VALID_BIT_1 : SYNC_VALID_BIT |
|
323 | 330 | GENERIC MAP ( |
|
324 | 331 | NB_FF_OF_SYNC => 2) |
|
325 | 332 | PORT MAP ( |
|
326 | 333 | clk_in => clk25MHz, |
|
327 | 334 | clk_out => clk24_576MHz, |
|
328 | 335 | rstn => resetn, |
|
329 | 336 | sin => tick, |
|
330 | 337 | sout => new_timecode); |
|
331 | 338 | |
|
332 | 339 | SYNC_VALID_BIT_2 : SYNC_VALID_BIT |
|
333 | 340 | GENERIC MAP ( |
|
334 | 341 | NB_FF_OF_SYNC => 2) |
|
335 | 342 | PORT MAP ( |
|
336 | 343 | clk_in => clk25MHz, |
|
337 | 344 | clk_out => clk24_576MHz, |
|
338 | 345 | rstn => resetn, |
|
339 | 346 | sin => coarsetime_reg_updated, |
|
340 | 347 | sout => new_coarsetime); |
|
341 | 348 | |
|
342 | 349 | SYNC_VALID_BIT_3 : SYNC_VALID_BIT |
|
343 | 350 | GENERIC MAP ( |
|
344 | 351 | NB_FF_OF_SYNC => 2) |
|
345 | 352 | PORT MAP ( |
|
346 | 353 | clk_in => clk25MHz, |
|
347 | 354 | clk_out => clk24_576MHz, |
|
348 | 355 | rstn => resetn, |
|
349 | 356 | sin => soft_reset, |
|
350 | 357 | sout => soft_reset_sync); |
|
351 | 358 | |
|
352 | 359 | ----------------------------------------------------------------------------- |
|
353 | 360 | --SYNC_FF_1 : SYNC_FF |
|
354 | 361 | -- GENERIC MAP ( |
|
355 | 362 | -- NB_FF_OF_SYNC => 2) |
|
356 | 363 | -- PORT MAP ( |
|
357 | 364 | -- clk => clk25MHz, |
|
358 | 365 | -- rstn => resetn, |
|
359 | 366 | -- A => fine_time_new_49, |
|
360 | 367 | -- A_sync => fine_time_new_temp); |
|
361 | 368 | |
|
362 | 369 | --lpp_front_detection_1 : lpp_front_detection |
|
363 | 370 | -- PORT MAP ( |
|
364 | 371 | -- clk => clk25MHz, |
|
365 | 372 | -- rstn => resetn, |
|
366 | 373 | -- sin => fine_time_new_temp, |
|
367 | 374 | -- sout => fine_time_new); |
|
368 | 375 | |
|
369 | 376 | --SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
|
370 | 377 | -- GENERIC MAP ( |
|
371 | 378 | -- NB_FF_OF_SYNC => 2) |
|
372 | 379 | -- PORT MAP ( |
|
373 | 380 | -- clk_in => clk24_576MHz, |
|
374 | 381 | -- clk_out => clk25MHz, |
|
375 | 382 | -- rstn => resetn, |
|
376 | 383 | -- sin => coarse_time_new_49, |
|
377 | 384 | -- sout => coarse_time_new); |
|
378 | 385 | |
|
379 | 386 | time_new_49 <= coarse_time_new_49 OR fine_time_new_49; |
|
380 | 387 | |
|
381 | 388 | SYNC_VALID_BIT_4 : SYNC_VALID_BIT |
|
382 | 389 | GENERIC MAP ( |
|
383 | 390 | NB_FF_OF_SYNC => 2) |
|
384 | 391 | PORT MAP ( |
|
385 | 392 | clk_in => clk24_576MHz, |
|
386 | 393 | clk_out => clk25MHz, |
|
387 | 394 | rstn => resetn, |
|
388 | 395 | sin => time_new_49, |
|
389 | 396 | sout => time_new); |
|
390 | 397 | |
|
391 | 398 | |
|
392 | 399 | |
|
393 | 400 | PROCESS (clk25MHz, resetn) |
|
394 | 401 | BEGIN -- PROCESS |
|
395 | 402 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
396 | 403 | fine_time_s <= (OTHERS => '0'); |
|
397 | 404 | coarse_time_s <= (OTHERS => '0'); |
|
398 | 405 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
399 | 406 | IF time_new = '1' THEN |
|
400 | 407 | fine_time_s <= fine_time_49; |
|
401 | 408 | coarse_time_s <= coarse_time_49; |
|
402 | 409 | END IF; |
|
403 | 410 | END IF; |
|
404 | 411 | END PROCESS; |
|
405 | 412 | |
|
406 | 413 | |
|
407 | 414 | rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE |
|
408 | 415 | '0' WHEN soft_reset_sync = '1' ELSE |
|
409 | 416 | '1'; |
|
410 | 417 | |
|
411 | 418 | |
|
412 | 419 | ----------------------------------------------------------------------------- |
|
413 | 420 | -- LFR_TIME_MANAGMENT |
|
414 | 421 | ----------------------------------------------------------------------------- |
|
415 | 422 | lfr_time_management_1 : lfr_time_management |
|
416 | 423 | GENERIC MAP ( |
|
417 | 424 | FIRST_DIVISION => FIRST_DIVISION, |
|
418 | 425 | NB_SECOND_DESYNC => NB_SECOND_DESYNC) |
|
419 | 426 | PORT MAP ( |
|
420 | 427 | clk => clk24_576MHz, |
|
421 | 428 | rstn => rstn_LFR_TM, |
|
422 | 429 | |
|
423 | 430 | tick => new_timecode, |
|
424 | 431 | new_coarsetime => new_coarsetime, |
|
425 | 432 | coarsetime_reg => coarsetime_reg(30 DOWNTO 0), |
|
426 | 433 | |
|
427 | 434 | fine_time => fine_time_49, |
|
428 | 435 | fine_time_new => fine_time_new_49, |
|
429 | 436 | coarse_time => coarse_time_49, |
|
430 | 437 | coarse_time_new => coarse_time_new_49); |
|
431 | 438 | |
|
432 | 439 | ----------------------------------------------------------------------------- |
|
433 | 440 | -- HK |
|
434 | 441 | ----------------------------------------------------------------------------- |
|
435 | 442 | |
|
436 | 443 | PROCESS (clk25MHz, resetn) |
|
437 | 444 | CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT) |
|
438 | 445 | -- for each HK, the update frequency is freq/3 |
|
439 | 446 | -- |
|
440 | 447 | -- for 14, the update frequency is |
|
441 | 448 | -- 4Hz and update for each |
|
442 | 449 | -- HK is 1.33Hz |
|
443 | ||
|
444 | 450 | BEGIN -- PROCESS |
|
445 | 451 | IF resetn = '0' THEN -- asynchronous reset (active low) |
|
446 | 452 | |
|
447 | 453 | r.HK_temp_0 <= (OTHERS => '0'); |
|
448 | 454 | r.HK_temp_1 <= (OTHERS => '0'); |
|
449 | 455 | r.HK_temp_2 <= (OTHERS => '0'); |
|
450 | 456 | |
|
451 | 457 | HK_sel_s <= "00"; |
|
452 | 458 | |
|
453 | 459 | previous_fine_time_bit <= '0'; |
|
454 | 460 | |
|
455 | 461 | ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge |
|
456 | 462 | |
|
457 | 463 | IF HK_val = '1' THEN |
|
458 | 464 | IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN |
|
459 | 465 | previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE); |
|
460 | 466 | CASE HK_sel_s IS |
|
461 | WHEN "00" => r.HK_temp_0 <= HK_sample; HK_sel_s <= "01"; | |
|
462 |
|
|
|
463 | WHEN "10" => r.HK_temp_2 <= HK_sample; HK_sel_s <= "00"; | |
|
467 | WHEN "00" => | |
|
468 | r.HK_temp_0 <= HK_sample; | |
|
469 | IF HK_debug_mode = '1' THEN | |
|
470 | HK_sel_s <= HK_sel_debug; | |
|
471 | ELSE | |
|
472 | HK_sel_s <= "01"; | |
|
473 | END IF; | |
|
474 | WHEN "01" => | |
|
475 | r.HK_temp_1 <= HK_sample; | |
|
476 | IF HK_debug_mode = '1' THEN | |
|
477 | HK_sel_s <= HK_sel_debug; | |
|
478 | ELSE | |
|
479 | HK_sel_s <= "10"; | |
|
480 | END IF; | |
|
481 | WHEN "10" => | |
|
482 | r.HK_temp_2 <= HK_sample; | |
|
483 | IF HK_debug_mode = '1' THEN | |
|
484 | HK_sel_s <= HK_sel_debug; | |
|
485 | ELSE | |
|
486 | HK_sel_s <= "00"; | |
|
487 | END IF; | |
|
464 | 488 | WHEN OTHERS => NULL; |
|
465 | 489 | END CASE; |
|
466 | 490 | END IF; |
|
467 | 491 | END IF; |
|
468 | 492 | |
|
469 | 493 | END IF; |
|
470 | 494 | END PROCESS; |
|
471 | 495 | |
|
472 | 496 | HK_sel <= HK_sel_s; |
|
473 | 497 | |
|
474 | 498 | ----------------------------------------------------------------------------- |
|
475 | 499 | -- DAC |
|
476 | 500 | ----------------------------------------------------------------------------- |
|
477 | 501 | cal : lfr_cal_driver |
|
478 | 502 | GENERIC MAP( |
|
479 | 503 | tech => tech, |
|
480 | 504 | PRESZ => PRESZ, |
|
481 | 505 | CPTSZ => CPTSZ, |
|
482 | 506 | datawidth => datawidth, |
|
483 | 507 | abits => abits |
|
484 | 508 | ) |
|
485 | 509 | PORT MAP( |
|
486 |
clk |
|
|
487 |
rstn |
|
|
488 | ||
|
510 | clk => clk25MHz, | |
|
511 | rstn => resetn, | |
|
512 | ||
|
489 | 513 | pre => pre, |
|
490 | 514 | N => N, |
|
491 | 515 | Reload => Reload, |
|
492 | 516 | DATA_IN => DATA_IN, |
|
493 | 517 | WEN => WEN, |
|
494 | 518 | LOAD_ADDRESSN => LOAD_ADDRESSN, |
|
495 | 519 | ADDRESS_IN => ADDRESS_IN, |
|
496 | 520 | ADDRESS_OUT => ADDRESS_OUT, |
|
497 | 521 | INTERLEAVED => INTERLEAVED, |
|
498 | 522 | DAC_CFG => DAC_CFG, |
|
499 | ||
|
500 |
SYNC |
|
|
501 |
DOUT |
|
|
502 |
SCLK |
|
|
503 |
SMPCLK |
|
|
523 | ||
|
524 | SYNC => DAC_SYNC, | |
|
525 | DOUT => DAC_SDO, | |
|
526 | SCLK => DAC_SCK, | |
|
527 | SMPCLK => OPEN --DAC_SMPCLK | |
|
504 | 528 | ); |
|
505 | 529 | |
|
506 | 530 | DAC_CAL_EN <= DAC_CAL_EN_s; |
|
507 | END Behavioral; No newline at end of file | |
|
531 | END Behavioral; |
General Comments 0
You need to be logged in to leave comments.
Login now