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update due to leon3_soc modification (IAP memory controler)
pellion -
r490:c1e844a21909 (MINI-LFR) WFP_MS-0-1-39 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
196 199 BEGIN -- beh
197 200
198 201 -----------------------------------------------------------------------------
199 202 -- CLK
200 203 -----------------------------------------------------------------------------
201 204
202 205 --PROCESS(clk_50)
203 206 --BEGIN
204 207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
205 208 -- clk_50_s <= NOT clk_50_s;
206 209 -- END IF;
207 210 --END PROCESS;
208 211
209 212 --PROCESS(clk_50_s)
210 213 --BEGIN
211 214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
212 215 -- clk_25 <= NOT clk_25;
213 216 -- END IF;
214 217 --END PROCESS;
215 218
216 219 --PROCESS(clk_49)
217 220 --BEGIN
218 221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
219 222 -- clk_24 <= NOT clk_24;
220 223 -- END IF;
221 224 --END PROCESS;
222 225
223 226 --PROCESS(clk_25)
224 227 --BEGIN
225 228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
226 229 -- rstn_25 <= reset;
227 230 -- END IF;
228 231 --END PROCESS;
229 232
230 233 PROCESS (clk_50, reset)
231 234 BEGIN -- PROCESS
232 235 IF reset = '0' THEN -- asynchronous reset (active low)
233 236 clk_50_s <= '0';
234 237 rstn_50 <= '0';
235 238 rstn_50_d1 <= '0';
236 239 rstn_50_d2 <= '0';
237 240 rstn_50_d3 <= '0';
238 241
239 242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
240 243 clk_50_s <= NOT clk_50_s;
241 244 rstn_50_d1 <= '1';
242 245 rstn_50_d2 <= rstn_50_d1;
243 246 rstn_50_d3 <= rstn_50_d2;
244 247 rstn_50 <= rstn_50_d3;
245 248 END IF;
246 249 END PROCESS;
247 250
248 251 PROCESS (clk_50_s, rstn_50)
249 252 BEGIN -- PROCESS
250 253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
251 254 clk_25 <= '0';
252 255 rstn_25 <= '0';
253 256 rstn_25_d1 <= '0';
254 257 rstn_25_d2 <= '0';
255 258 rstn_25_d3 <= '0';
256 259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
257 260 clk_25 <= NOT clk_25;
258 261 rstn_25_d1 <= '1';
259 262 rstn_25_d2 <= rstn_25_d1;
260 263 rstn_25_d3 <= rstn_25_d2;
261 264 rstn_25 <= rstn_25_d3;
262 265 END IF;
263 266 END PROCESS;
264 267
265 268 PROCESS (clk_49, reset)
266 269 BEGIN -- PROCESS
267 270 IF reset = '0' THEN -- asynchronous reset (active low)
268 271 clk_24 <= '0';
269 272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
270 273 clk_24 <= NOT clk_24;
271 274 END IF;
272 275 END PROCESS;
273 276
274 277 -----------------------------------------------------------------------------
275 278
276 279 PROCESS (clk_25, rstn_25)
277 280 BEGIN -- PROCESS
278 281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
279 282 LED0 <= '0';
280 283 LED1 <= '0';
281 284 LED2 <= '0';
282 285 --IO1 <= '0';
283 286 --IO2 <= '1';
284 287 --IO3 <= '0';
285 288 --IO4 <= '0';
286 289 --IO5 <= '0';
287 290 --IO6 <= '0';
288 291 --IO7 <= '0';
289 292 --IO8 <= '0';
290 293 --IO9 <= '0';
291 294 --IO10 <= '0';
292 295 --IO11 <= '0';
293 296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
294 297 LED0 <= '0';
295 298 LED1 <= '1';
296 299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
297 300 --IO1 <= '1';
298 301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
299 302 --IO3 <= ADC_SDO(0);
300 303 --IO4 <= ADC_SDO(1);
301 304 --IO5 <= ADC_SDO(2);
302 305 --IO6 <= ADC_SDO(3);
303 306 --IO7 <= ADC_SDO(4);
304 307 --IO8 <= ADC_SDO(5);
305 308 --IO9 <= ADC_SDO(6);
306 309 --IO10 <= ADC_SDO(7);
307 310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
308 311 END IF;
309 312 END PROCESS;
310 313
311 314 PROCESS (clk_24, rstn_25)
312 315 BEGIN -- PROCESS
313 316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
314 317 I00_s <= '0';
315 318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
316 319 I00_s <= NOT I00_s;
317 320 END IF;
318 321 END PROCESS;
319 322 -- IO0 <= I00_s;
320 323
321 324 --UARTs
322 325 nCTS1 <= '1';
323 326 nCTS2 <= '1';
324 327 nDCD2 <= '1';
325 328
326 329 --EXT CONNECTOR
327 330
328 331 --SPACE WIRE
329 332
330 333 leon3_soc_1 : leon3_soc
331 334 GENERIC MAP (
332 335 fabtech => apa3e,
333 336 memtech => apa3e,
334 337 padtech => inferred,
335 338 clktech => inferred,
336 339 disas => 0,
337 340 dbguart => 0,
338 341 pclow => 2,
339 342 clk_freq => 25000,
340 343 NB_CPU => 1,
341 344 ENABLE_FPU => 1,
342 345 FPU_NETLIST => 0,
343 346 ENABLE_DSU => 1,
344 347 ENABLE_AHB_UART => 1,
345 348 ENABLE_APB_UART => 1,
346 349 ENABLE_IRQMP => 1,
347 350 ENABLE_GPT => 1,
348 351 NB_AHB_MASTER => NB_AHB_MASTER,
349 352 NB_AHB_SLAVE => NB_AHB_SLAVE,
350 353 NB_APB_SLAVE => NB_APB_SLAVE,
351 ADDRESS_SIZE => 20)
354 ADDRESS_SIZE => 20,
355 USES_IAP_MEMCTRLR => 0)
352 356 PORT MAP (
353 357 clk => clk_25,
354 358 reset => rstn_25,
355 359 errorn => errorn,
356 360 ahbrxd => TXD1,
357 361 ahbtxd => RXD1,
358 362 urxd1 => TXD2,
359 363 utxd1 => RXD2,
360 364 address => SRAM_A,
361 365 data => SRAM_DQ,
362 366 nSRAM_BE0 => SRAM_nBE(0),
363 367 nSRAM_BE1 => SRAM_nBE(1),
364 368 nSRAM_BE2 => SRAM_nBE(2),
365 369 nSRAM_BE3 => SRAM_nBE(3),
366 370 nSRAM_WE => SRAM_nWE,
367 nSRAM_CE => SRAM_CE,
371 nSRAM_CE => SRAM_CE_s,
368 372 nSRAM_OE => SRAM_nOE,
369
373 nSRAM_READY => '0',
374 SRAM_MBE => OPEN,
370 375 apbi_ext => apbi_ext,
371 376 apbo_ext => apbo_ext,
372 377 ahbi_s_ext => ahbi_s_ext,
373 378 ahbo_s_ext => ahbo_s_ext,
374 379 ahbi_m_ext => ahbi_m_ext,
375 380 ahbo_m_ext => ahbo_m_ext);
376 381
382 SRAM_CE <= SRAM_CE_s(0);
377 383 -------------------------------------------------------------------------------
378 384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
379 385 -------------------------------------------------------------------------------
380 386 apb_lfr_time_management_1 : apb_lfr_time_management
381 387 GENERIC MAP (
382 388 pindex => 6,
383 389 paddr => 6,
384 390 pmask => 16#fff#,
385 391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 393 PORT MAP (
388 394 clk25MHz => clk_25,
389 395 clk24_576MHz => clk_24, -- 49.152MHz/2
390 396 resetn => rstn_25,
391 397 grspw_tick => swno.tickout,
392 398 apbi => apbi_ext,
393 399 apbo => apbo_ext(6),
394 400 coarse_time => coarse_time,
395 401 fine_time => fine_time,
396 402 LFR_soft_rstn => LFR_soft_rstn
397 403 );
398 404
399 405 -----------------------------------------------------------------------
400 406 --- SpaceWire --------------------------------------------------------
401 407 -----------------------------------------------------------------------
402 408
403 409 SPW_EN <= '1';
404 410
405 411 spw_clk <= clk_50_s;
406 412 spw_rxtxclk <= spw_clk;
407 413 spw_rxclkn <= NOT spw_rxtxclk;
408 414
409 415 -- PADS for SPW1
410 416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
411 417 PORT MAP (SPW_NOM_DIN, dtmp(0));
412 418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
413 419 PORT MAP (SPW_NOM_SIN, stmp(0));
414 420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
415 421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
416 422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
417 423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
418 424 -- PADS FOR SPW2
419 425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
420 426 PORT MAP (SPW_RED_SIN, dtmp(1));
421 427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 428 PORT MAP (SPW_RED_DIN, stmp(1));
423 429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
424 430 PORT MAP (SPW_RED_DOUT, swno.d(1));
425 431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
426 432 PORT MAP (SPW_RED_SOUT, swno.s(1));
427 433
428 434 -- GRSPW PHY
429 435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
430 436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
431 437 spw_phy0 : grspw_phy
432 438 GENERIC MAP(
433 439 tech => apa3e,
434 440 rxclkbuftype => 1,
435 441 scantest => 0)
436 442 PORT MAP(
437 443 rxrst => swno.rxrst,
438 444 di => dtmp(j),
439 445 si => stmp(j),
440 446 rxclko => spw_rxclk(j),
441 447 do => swni.d(j),
442 448 ndo => swni.nd(j*5+4 DOWNTO j*5),
443 449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
444 450 END GENERATE spw_inputloop;
445 451
446 452 swni.rmapnodeaddr <= (OTHERS => '0');
447 453
448 454 -- SPW core
449 455 sw0 : grspwm GENERIC MAP(
450 456 tech => apa3e,
451 457 hindex => 1,
452 458 pindex => 5,
453 459 paddr => 5,
454 460 pirq => 11,
455 461 sysfreq => 25000, -- CPU_FREQ
456 462 rmap => 1,
457 463 rmapcrc => 1,
458 464 fifosize1 => 16,
459 465 fifosize2 => 16,
460 466 rxclkbuftype => 1,
461 467 rxunaligned => 0,
462 468 rmapbufs => 4,
463 469 ft => 0,
464 470 netlist => 0,
465 471 ports => 2,
466 472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 473 memtech => apa3e,
468 474 destkey => 2,
469 475 spwcore => 1
470 476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 479 )
474 480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
475 481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 483 swni, swno);
478 484
479 485 swni.tickin <= '0';
480 486 swni.rmapen <= '1';
481 487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 488 swni.tickinraw <= '0';
483 489 swni.timein <= (OTHERS => '0');
484 490 swni.dcrstval <= (OTHERS => '0');
485 491 swni.timerrstval <= (OTHERS => '0');
486 492
487 493 -------------------------------------------------------------------------------
488 494 -- LFR ------------------------------------------------------------------------
489 495 -------------------------------------------------------------------------------
490 496
491 497
492 498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
493 499 --LFR_rstn <= rstn_25;
494 500
495 501 lpp_lfr_1 : lpp_lfr
496 502 GENERIC MAP (
497 503 Mem_use => use_RAM,
498 504 nb_data_by_buffer_size => 32,
499 505 nb_snapshot_param_size => 32,
500 506 delta_vector_size => 32,
501 507 delta_vector_size_f0_2 => 7, -- log2(96)
502 508 pindex => 15,
503 509 paddr => 15,
504 510 pmask => 16#fff#,
505 511 pirq_ms => 6,
506 512 pirq_wfp => 14,
507 513 hindex => 2,
508 514 top_lfr_version => X"000127") -- aa.bb.cc version
509 515 PORT MAP (
510 516 clk => clk_25,
511 517 rstn => LFR_rstn,
512 518 sample_B => sample_s(2 DOWNTO 0),
513 519 sample_E => sample_s(7 DOWNTO 3),
514 520 sample_val => sample_val,
515 521 apbi => apbi_ext,
516 522 apbo => apbo_ext(15),
517 523 ahbi => ahbi_m_ext,
518 524 ahbo => ahbo_m_ext(2),
519 525 coarse_time => coarse_time,
520 526 fine_time => fine_time,
521 527 data_shaping_BW => bias_fail_sw_sig,
522 528 debug_vector => lfr_debug_vector,
523 529 debug_vector_ms => lfr_debug_vector_ms
524 530 );
525 531
526 532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
527 533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
528 534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 536 IO0 <= rstn_25;
531 537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
538 544
539 545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
540 546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
541 547 END GENERATE all_sample;
542 548
543 549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
544 550 GENERIC MAP(
545 551 ChannelCount => 8,
546 552 SampleNbBits => 14,
547 553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
548 554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
549 555 PORT MAP (
550 556 -- CONV
551 557 cnv_clk => clk_24,
552 558 cnv_rstn => rstn_25,
553 559 cnv => ADC_nCS_sig,
554 560 -- DATA
555 561 clk => clk_25,
556 562 rstn => rstn_25,
557 563 sck => ADC_CLK_sig,
558 564 sdo => ADC_SDO_sig,
559 565 -- SAMPLE
560 566 sample => sample,
561 567 sample_val => sample_val);
562 568
563 569 --IO10 <= ADC_SDO_sig(5);
564 570 --IO9 <= ADC_SDO_sig(4);
565 571 --IO8 <= ADC_SDO_sig(3);
566 572
567 573 ADC_nCS <= ADC_nCS_sig;
568 574 ADC_CLK <= ADC_CLK_sig;
569 575 ADC_SDO_sig <= ADC_SDO;
570 576
571 577 ----------------------------------------------------------------------
572 578 --- GPIO -----------------------------------------------------------
573 579 ----------------------------------------------------------------------
574 580
575 581 grgpio0 : grgpio
576 582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
577 583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
578 584
579 585 gpioi.sig_en <= (OTHERS => '0');
580 586 gpioi.sig_in <= (OTHERS => '0');
581 587 gpioi.din <= (OTHERS => '0');
582 588 --pio_pad_0 : iopad
583 589 -- GENERIC MAP (tech => CFG_PADTECH)
584 590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
585 591 --pio_pad_1 : iopad
586 592 -- GENERIC MAP (tech => CFG_PADTECH)
587 593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
588 594 --pio_pad_2 : iopad
589 595 -- GENERIC MAP (tech => CFG_PADTECH)
590 596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
591 597 --pio_pad_3 : iopad
592 598 -- GENERIC MAP (tech => CFG_PADTECH)
593 599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
594 600 --pio_pad_4 : iopad
595 601 -- GENERIC MAP (tech => CFG_PADTECH)
596 602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
597 603 --pio_pad_5 : iopad
598 604 -- GENERIC MAP (tech => CFG_PADTECH)
599 605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
600 606 --pio_pad_6 : iopad
601 607 -- GENERIC MAP (tech => CFG_PADTECH)
602 608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
603 609 --pio_pad_7 : iopad
604 610 -- GENERIC MAP (tech => CFG_PADTECH)
605 611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
606 612
607 613 PROCESS (clk_25, rstn_25)
608 614 BEGIN -- PROCESS
609 615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
610 616 -- --IO0 <= '0';
611 617 -- IO1 <= '0';
612 618 -- IO2 <= '0';
613 619 -- IO3 <= '0';
614 620 -- IO4 <= '0';
615 621 -- IO5 <= '0';
616 622 -- IO6 <= '0';
617 623 -- IO7 <= '0';
618 624 IO8 <= '0';
619 625 IO9 <= '0';
620 626 IO10 <= '0';
621 627 IO11 <= '0';
622 628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
623 629 CASE gpioo.dout(2 DOWNTO 0) IS
624 630 WHEN "011" =>
625 631 -- --IO0 <= observation_reg(0 );
626 632 -- IO1 <= observation_reg(1 );
627 633 -- IO2 <= observation_reg(2 );
628 634 -- IO3 <= observation_reg(3 );
629 635 -- IO4 <= observation_reg(4 );
630 636 -- IO5 <= observation_reg(5 );
631 637 -- IO6 <= observation_reg(6 );
632 638 -- IO7 <= observation_reg(7 );
633 639 IO8 <= observation_reg(8);
634 640 IO9 <= observation_reg(9);
635 641 IO10 <= observation_reg(10);
636 642 IO11 <= observation_reg(11);
637 643 WHEN "001" =>
638 644 -- --IO0 <= observation_reg(0 + 12);
639 645 -- IO1 <= observation_reg(1 + 12);
640 646 -- IO2 <= observation_reg(2 + 12);
641 647 -- IO3 <= observation_reg(3 + 12);
642 648 -- IO4 <= observation_reg(4 + 12);
643 649 -- IO5 <= observation_reg(5 + 12);
644 650 -- IO6 <= observation_reg(6 + 12);
645 651 -- IO7 <= observation_reg(7 + 12);
646 652 IO8 <= observation_reg(8 + 12);
647 653 IO9 <= observation_reg(9 + 12);
648 654 IO10 <= observation_reg(10 + 12);
649 655 IO11 <= observation_reg(11 + 12);
650 656 WHEN "010" =>
651 657 -- --IO0 <= observation_reg(0 + 12 + 12);
652 658 -- IO1 <= observation_reg(1 + 12 + 12);
653 659 -- IO2 <= observation_reg(2 + 12 + 12);
654 660 -- IO3 <= observation_reg(3 + 12 + 12);
655 661 -- IO4 <= observation_reg(4 + 12 + 12);
656 662 -- IO5 <= observation_reg(5 + 12 + 12);
657 663 -- IO6 <= observation_reg(6 + 12 + 12);
658 664 -- IO7 <= observation_reg(7 + 12 + 12);
659 665 IO8 <= '0';
660 666 IO9 <= '0';
661 667 IO10 <= '0';
662 668 IO11 <= '0';
663 669 WHEN "000" =>
664 670 -- --IO0 <= observation_vector_0(0 );
665 671 -- IO1 <= observation_vector_0(1 );
666 672 -- IO2 <= observation_vector_0(2 );
667 673 -- IO3 <= observation_vector_0(3 );
668 674 -- IO4 <= observation_vector_0(4 );
669 675 -- IO5 <= observation_vector_0(5 );
670 676 -- IO6 <= observation_vector_0(6 );
671 677 -- IO7 <= observation_vector_0(7 );
672 678 IO8 <= observation_vector_0(8);
673 679 IO9 <= observation_vector_0(9);
674 680 IO10 <= observation_vector_0(10);
675 681 IO11 <= observation_vector_0(11);
676 682 WHEN "100" =>
677 683 -- --IO0 <= observation_vector_1(0 );
678 684 -- IO1 <= observation_vector_1(1 );
679 685 -- IO2 <= observation_vector_1(2 );
680 686 -- IO3 <= observation_vector_1(3 );
681 687 -- IO4 <= observation_vector_1(4 );
682 688 -- IO5 <= observation_vector_1(5 );
683 689 -- IO6 <= observation_vector_1(6 );
684 690 -- IO7 <= observation_vector_1(7 );
685 691 IO8 <= observation_vector_1(8);
686 692 IO9 <= observation_vector_1(9);
687 693 IO10 <= observation_vector_1(10);
688 694 IO11 <= observation_vector_1(11);
689 695 WHEN OTHERS => NULL;
690 696 END CASE;
691 697
692 698 END IF;
693 699 END PROCESS;
694 700 -----------------------------------------------------------------------------
695 701 --
696 702 -----------------------------------------------------------------------------
697 703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
698 704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
699 705 apbo_ext(I) <= apb_none;
700 706 END GENERATE apbo_ext_not_used;
701 707 END GENERATE all_apbo_ext;
702 708
703 709
704 710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
705 711 ahbo_s_ext(I) <= ahbs_none;
706 712 END GENERATE all_ahbo_ext;
707 713
708 714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
709 715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
710 716 ahbo_m_ext(I) <= ahbm_none;
711 717 END GENERATE ahbo_m_ext_not_used;
712 718 END GENERATE all_ahbo_m_ext;
713 719
714 720 END beh;
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