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update due to leon3_soc modification (IAP memory controler)
pellion -
r490:c1e844a21909 (MINI-LFR) WFP_MS-0-1-39 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 --
197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198
196 BEGIN -- beh
199 BEGIN -- beh
197
200
198 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
199 -- CLK
202 -- CLK
200 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
201
204
202 --PROCESS(clk_50)
205 --PROCESS(clk_50)
203 --BEGIN
206 --BEGIN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
207 -- IF clk_50'EVENT AND clk_50 = '1' THEN
205 -- clk_50_s <= NOT clk_50_s;
208 -- clk_50_s <= NOT clk_50_s;
206 -- END IF;
209 -- END IF;
207 --END PROCESS;
210 --END PROCESS;
208
211
209 --PROCESS(clk_50_s)
212 --PROCESS(clk_50_s)
210 --BEGIN
213 --BEGIN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
214 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
212 -- clk_25 <= NOT clk_25;
215 -- clk_25 <= NOT clk_25;
213 -- END IF;
216 -- END IF;
214 --END PROCESS;
217 --END PROCESS;
215
218
216 --PROCESS(clk_49)
219 --PROCESS(clk_49)
217 --BEGIN
220 --BEGIN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
221 -- IF clk_49'EVENT AND clk_49 = '1' THEN
219 -- clk_24 <= NOT clk_24;
222 -- clk_24 <= NOT clk_24;
220 -- END IF;
223 -- END IF;
221 --END PROCESS;
224 --END PROCESS;
222
225
223 --PROCESS(clk_25)
226 --PROCESS(clk_25)
224 --BEGIN
227 --BEGIN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
228 -- IF clk_25'EVENT AND clk_25 = '1' THEN
226 -- rstn_25 <= reset;
229 -- rstn_25 <= reset;
227 -- END IF;
230 -- END IF;
228 --END PROCESS;
231 --END PROCESS;
229
232
230 PROCESS (clk_50, reset)
233 PROCESS (clk_50, reset)
231 BEGIN -- PROCESS
234 BEGIN -- PROCESS
232 IF reset = '0' THEN -- asynchronous reset (active low)
235 IF reset = '0' THEN -- asynchronous reset (active low)
233 clk_50_s <= '0';
236 clk_50_s <= '0';
234 rstn_50 <= '0';
237 rstn_50 <= '0';
235 rstn_50_d1 <= '0';
238 rstn_50_d1 <= '0';
236 rstn_50_d2 <= '0';
239 rstn_50_d2 <= '0';
237 rstn_50_d3 <= '0';
240 rstn_50_d3 <= '0';
238
241
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
242 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
240 clk_50_s <= NOT clk_50_s;
243 clk_50_s <= NOT clk_50_s;
241 rstn_50_d1 <= '1';
244 rstn_50_d1 <= '1';
242 rstn_50_d2 <= rstn_50_d1;
245 rstn_50_d2 <= rstn_50_d1;
243 rstn_50_d3 <= rstn_50_d2;
246 rstn_50_d3 <= rstn_50_d2;
244 rstn_50 <= rstn_50_d3;
247 rstn_50 <= rstn_50_d3;
245 END IF;
248 END IF;
246 END PROCESS;
249 END PROCESS;
247
250
248 PROCESS (clk_50_s, rstn_50)
251 PROCESS (clk_50_s, rstn_50)
249 BEGIN -- PROCESS
252 BEGIN -- PROCESS
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
253 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
251 clk_25 <= '0';
254 clk_25 <= '0';
252 rstn_25 <= '0';
255 rstn_25 <= '0';
253 rstn_25_d1 <= '0';
256 rstn_25_d1 <= '0';
254 rstn_25_d2 <= '0';
257 rstn_25_d2 <= '0';
255 rstn_25_d3 <= '0';
258 rstn_25_d3 <= '0';
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
259 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
257 clk_25 <= NOT clk_25;
260 clk_25 <= NOT clk_25;
258 rstn_25_d1 <= '1';
261 rstn_25_d1 <= '1';
259 rstn_25_d2 <= rstn_25_d1;
262 rstn_25_d2 <= rstn_25_d1;
260 rstn_25_d3 <= rstn_25_d2;
263 rstn_25_d3 <= rstn_25_d2;
261 rstn_25 <= rstn_25_d3;
264 rstn_25 <= rstn_25_d3;
262 END IF;
265 END IF;
263 END PROCESS;
266 END PROCESS;
264
267
265 PROCESS (clk_49, reset)
268 PROCESS (clk_49, reset)
266 BEGIN -- PROCESS
269 BEGIN -- PROCESS
267 IF reset = '0' THEN -- asynchronous reset (active low)
270 IF reset = '0' THEN -- asynchronous reset (active low)
268 clk_24 <= '0';
271 clk_24 <= '0';
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
272 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
270 clk_24 <= NOT clk_24;
273 clk_24 <= NOT clk_24;
271 END IF;
274 END IF;
272 END PROCESS;
275 END PROCESS;
273
276
274 -----------------------------------------------------------------------------
277 -----------------------------------------------------------------------------
275
278
276 PROCESS (clk_25, rstn_25)
279 PROCESS (clk_25, rstn_25)
277 BEGIN -- PROCESS
280 BEGIN -- PROCESS
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
281 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
279 LED0 <= '0';
282 LED0 <= '0';
280 LED1 <= '0';
283 LED1 <= '0';
281 LED2 <= '0';
284 LED2 <= '0';
282 --IO1 <= '0';
285 --IO1 <= '0';
283 --IO2 <= '1';
286 --IO2 <= '1';
284 --IO3 <= '0';
287 --IO3 <= '0';
285 --IO4 <= '0';
288 --IO4 <= '0';
286 --IO5 <= '0';
289 --IO5 <= '0';
287 --IO6 <= '0';
290 --IO6 <= '0';
288 --IO7 <= '0';
291 --IO7 <= '0';
289 --IO8 <= '0';
292 --IO8 <= '0';
290 --IO9 <= '0';
293 --IO9 <= '0';
291 --IO10 <= '0';
294 --IO10 <= '0';
292 --IO11 <= '0';
295 --IO11 <= '0';
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
296 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
294 LED0 <= '0';
297 LED0 <= '0';
295 LED1 <= '1';
298 LED1 <= '1';
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
299 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
297 --IO1 <= '1';
300 --IO1 <= '1';
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
301 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
299 --IO3 <= ADC_SDO(0);
302 --IO3 <= ADC_SDO(0);
300 --IO4 <= ADC_SDO(1);
303 --IO4 <= ADC_SDO(1);
301 --IO5 <= ADC_SDO(2);
304 --IO5 <= ADC_SDO(2);
302 --IO6 <= ADC_SDO(3);
305 --IO6 <= ADC_SDO(3);
303 --IO7 <= ADC_SDO(4);
306 --IO7 <= ADC_SDO(4);
304 --IO8 <= ADC_SDO(5);
307 --IO8 <= ADC_SDO(5);
305 --IO9 <= ADC_SDO(6);
308 --IO9 <= ADC_SDO(6);
306 --IO10 <= ADC_SDO(7);
309 --IO10 <= ADC_SDO(7);
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
310 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
308 END IF;
311 END IF;
309 END PROCESS;
312 END PROCESS;
310
313
311 PROCESS (clk_24, rstn_25)
314 PROCESS (clk_24, rstn_25)
312 BEGIN -- PROCESS
315 BEGIN -- PROCESS
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
316 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
314 I00_s <= '0';
317 I00_s <= '0';
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
318 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
316 I00_s <= NOT I00_s;
319 I00_s <= NOT I00_s;
317 END IF;
320 END IF;
318 END PROCESS;
321 END PROCESS;
319 -- IO0 <= I00_s;
322 -- IO0 <= I00_s;
320
323
321 --UARTs
324 --UARTs
322 nCTS1 <= '1';
325 nCTS1 <= '1';
323 nCTS2 <= '1';
326 nCTS2 <= '1';
324 nDCD2 <= '1';
327 nDCD2 <= '1';
325
328
326 --EXT CONNECTOR
329 --EXT CONNECTOR
327
330
328 --SPACE WIRE
331 --SPACE WIRE
329
332
330 leon3_soc_1 : leon3_soc
333 leon3_soc_1 : leon3_soc
331 GENERIC MAP (
334 GENERIC MAP (
332 fabtech => apa3e,
335 fabtech => apa3e,
333 memtech => apa3e,
336 memtech => apa3e,
334 padtech => inferred,
337 padtech => inferred,
335 clktech => inferred,
338 clktech => inferred,
336 disas => 0,
339 disas => 0,
337 dbguart => 0,
340 dbguart => 0,
338 pclow => 2,
341 pclow => 2,
339 clk_freq => 25000,
342 clk_freq => 25000,
340 NB_CPU => 1,
343 NB_CPU => 1,
341 ENABLE_FPU => 1,
344 ENABLE_FPU => 1,
342 FPU_NETLIST => 0,
345 FPU_NETLIST => 0,
343 ENABLE_DSU => 1,
346 ENABLE_DSU => 1,
344 ENABLE_AHB_UART => 1,
347 ENABLE_AHB_UART => 1,
345 ENABLE_APB_UART => 1,
348 ENABLE_APB_UART => 1,
346 ENABLE_IRQMP => 1,
349 ENABLE_IRQMP => 1,
347 ENABLE_GPT => 1,
350 ENABLE_GPT => 1,
348 NB_AHB_MASTER => NB_AHB_MASTER,
351 NB_AHB_MASTER => NB_AHB_MASTER,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
352 NB_AHB_SLAVE => NB_AHB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
353 NB_APB_SLAVE => NB_APB_SLAVE,
351 ADDRESS_SIZE => 20)
354 ADDRESS_SIZE => 20,
355 USES_IAP_MEMCTRLR => 0)
352 PORT MAP (
356 PORT MAP (
353 clk => clk_25,
357 clk => clk_25,
354 reset => rstn_25,
358 reset => rstn_25,
355 errorn => errorn,
359 errorn => errorn,
356 ahbrxd => TXD1,
360 ahbrxd => TXD1,
357 ahbtxd => RXD1,
361 ahbtxd => RXD1,
358 urxd1 => TXD2,
362 urxd1 => TXD2,
359 utxd1 => RXD2,
363 utxd1 => RXD2,
360 address => SRAM_A,
364 address => SRAM_A,
361 data => SRAM_DQ,
365 data => SRAM_DQ,
362 nSRAM_BE0 => SRAM_nBE(0),
366 nSRAM_BE0 => SRAM_nBE(0),
363 nSRAM_BE1 => SRAM_nBE(1),
367 nSRAM_BE1 => SRAM_nBE(1),
364 nSRAM_BE2 => SRAM_nBE(2),
368 nSRAM_BE2 => SRAM_nBE(2),
365 nSRAM_BE3 => SRAM_nBE(3),
369 nSRAM_BE3 => SRAM_nBE(3),
366 nSRAM_WE => SRAM_nWE,
370 nSRAM_WE => SRAM_nWE,
367 nSRAM_CE => SRAM_CE,
371 nSRAM_CE => SRAM_CE_s,
368 nSRAM_OE => SRAM_nOE,
372 nSRAM_OE => SRAM_nOE,
369
373 nSRAM_READY => '0',
374 SRAM_MBE => OPEN,
370 apbi_ext => apbi_ext,
375 apbi_ext => apbi_ext,
371 apbo_ext => apbo_ext,
376 apbo_ext => apbo_ext,
372 ahbi_s_ext => ahbi_s_ext,
377 ahbi_s_ext => ahbi_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
378 ahbo_s_ext => ahbo_s_ext,
374 ahbi_m_ext => ahbi_m_ext,
379 ahbi_m_ext => ahbi_m_ext,
375 ahbo_m_ext => ahbo_m_ext);
380 ahbo_m_ext => ahbo_m_ext);
376
381
382 SRAM_CE <= SRAM_CE_s(0);
377 -------------------------------------------------------------------------------
383 -------------------------------------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
384 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
379 -------------------------------------------------------------------------------
385 -------------------------------------------------------------------------------
380 apb_lfr_time_management_1 : apb_lfr_time_management
386 apb_lfr_time_management_1 : apb_lfr_time_management
381 GENERIC MAP (
387 GENERIC MAP (
382 pindex => 6,
388 pindex => 6,
383 paddr => 6,
389 paddr => 6,
384 pmask => 16#fff#,
390 pmask => 16#fff#,
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
391 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
392 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 PORT MAP (
393 PORT MAP (
388 clk25MHz => clk_25,
394 clk25MHz => clk_25,
389 clk24_576MHz => clk_24, -- 49.152MHz/2
395 clk24_576MHz => clk_24, -- 49.152MHz/2
390 resetn => rstn_25,
396 resetn => rstn_25,
391 grspw_tick => swno.tickout,
397 grspw_tick => swno.tickout,
392 apbi => apbi_ext,
398 apbi => apbi_ext,
393 apbo => apbo_ext(6),
399 apbo => apbo_ext(6),
394 coarse_time => coarse_time,
400 coarse_time => coarse_time,
395 fine_time => fine_time,
401 fine_time => fine_time,
396 LFR_soft_rstn => LFR_soft_rstn
402 LFR_soft_rstn => LFR_soft_rstn
397 );
403 );
398
404
399 -----------------------------------------------------------------------
405 -----------------------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
406 --- SpaceWire --------------------------------------------------------
401 -----------------------------------------------------------------------
407 -----------------------------------------------------------------------
402
408
403 SPW_EN <= '1';
409 SPW_EN <= '1';
404
410
405 spw_clk <= clk_50_s;
411 spw_clk <= clk_50_s;
406 spw_rxtxclk <= spw_clk;
412 spw_rxtxclk <= spw_clk;
407 spw_rxclkn <= NOT spw_rxtxclk;
413 spw_rxclkn <= NOT spw_rxtxclk;
408
414
409 -- PADS for SPW1
415 -- PADS for SPW1
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
416 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
417 PORT MAP (SPW_NOM_DIN, dtmp(0));
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
418 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_SIN, stmp(0));
419 PORT MAP (SPW_NOM_SIN, stmp(0));
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
420 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
421 PORT MAP (SPW_NOM_DOUT, swno.d(0));
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
422 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
423 PORT MAP (SPW_NOM_SOUT, swno.s(0));
418 -- PADS FOR SPW2
424 -- PADS FOR SPW2
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
425 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
420 PORT MAP (SPW_RED_SIN, dtmp(1));
426 PORT MAP (SPW_RED_SIN, dtmp(1));
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
427 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 PORT MAP (SPW_RED_DIN, stmp(1));
428 PORT MAP (SPW_RED_DIN, stmp(1));
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
429 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
430 PORT MAP (SPW_RED_DOUT, swno.d(1));
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
431 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
432 PORT MAP (SPW_RED_SOUT, swno.s(1));
427
433
428 -- GRSPW PHY
434 -- GRSPW PHY
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
435 --spw1_input: if CFG_SPW_GRSPW = 1 generate
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
436 spw_inputloop : FOR j IN 0 TO 1 GENERATE
431 spw_phy0 : grspw_phy
437 spw_phy0 : grspw_phy
432 GENERIC MAP(
438 GENERIC MAP(
433 tech => apa3e,
439 tech => apa3e,
434 rxclkbuftype => 1,
440 rxclkbuftype => 1,
435 scantest => 0)
441 scantest => 0)
436 PORT MAP(
442 PORT MAP(
437 rxrst => swno.rxrst,
443 rxrst => swno.rxrst,
438 di => dtmp(j),
444 di => dtmp(j),
439 si => stmp(j),
445 si => stmp(j),
440 rxclko => spw_rxclk(j),
446 rxclko => spw_rxclk(j),
441 do => swni.d(j),
447 do => swni.d(j),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
448 ndo => swni.nd(j*5+4 DOWNTO j*5),
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
449 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
444 END GENERATE spw_inputloop;
450 END GENERATE spw_inputloop;
445
451
446 swni.rmapnodeaddr <= (OTHERS => '0');
452 swni.rmapnodeaddr <= (OTHERS => '0');
447
453
448 -- SPW core
454 -- SPW core
449 sw0 : grspwm GENERIC MAP(
455 sw0 : grspwm GENERIC MAP(
450 tech => apa3e,
456 tech => apa3e,
451 hindex => 1,
457 hindex => 1,
452 pindex => 5,
458 pindex => 5,
453 paddr => 5,
459 paddr => 5,
454 pirq => 11,
460 pirq => 11,
455 sysfreq => 25000, -- CPU_FREQ
461 sysfreq => 25000, -- CPU_FREQ
456 rmap => 1,
462 rmap => 1,
457 rmapcrc => 1,
463 rmapcrc => 1,
458 fifosize1 => 16,
464 fifosize1 => 16,
459 fifosize2 => 16,
465 fifosize2 => 16,
460 rxclkbuftype => 1,
466 rxclkbuftype => 1,
461 rxunaligned => 0,
467 rxunaligned => 0,
462 rmapbufs => 4,
468 rmapbufs => 4,
463 ft => 0,
469 ft => 0,
464 netlist => 0,
470 netlist => 0,
465 ports => 2,
471 ports => 2,
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
472 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 memtech => apa3e,
473 memtech => apa3e,
468 destkey => 2,
474 destkey => 2,
469 spwcore => 1
475 spwcore => 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
476 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
477 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
478 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 )
479 )
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
480 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
481 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
482 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 swni, swno);
483 swni, swno);
478
484
479 swni.tickin <= '0';
485 swni.tickin <= '0';
480 swni.rmapen <= '1';
486 swni.rmapen <= '1';
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
487 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 swni.tickinraw <= '0';
488 swni.tickinraw <= '0';
483 swni.timein <= (OTHERS => '0');
489 swni.timein <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
490 swni.dcrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
491 swni.timerrstval <= (OTHERS => '0');
486
492
487 -------------------------------------------------------------------------------
493 -------------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
494 -- LFR ------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
495 -------------------------------------------------------------------------------
490
496
491
497
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
498 LFR_rstn <= LFR_soft_rstn AND rstn_25;
493 --LFR_rstn <= rstn_25;
499 --LFR_rstn <= rstn_25;
494
500
495 lpp_lfr_1 : lpp_lfr
501 lpp_lfr_1 : lpp_lfr
496 GENERIC MAP (
502 GENERIC MAP (
497 Mem_use => use_RAM,
503 Mem_use => use_RAM,
498 nb_data_by_buffer_size => 32,
504 nb_data_by_buffer_size => 32,
499 nb_snapshot_param_size => 32,
505 nb_snapshot_param_size => 32,
500 delta_vector_size => 32,
506 delta_vector_size => 32,
501 delta_vector_size_f0_2 => 7, -- log2(96)
507 delta_vector_size_f0_2 => 7, -- log2(96)
502 pindex => 15,
508 pindex => 15,
503 paddr => 15,
509 paddr => 15,
504 pmask => 16#fff#,
510 pmask => 16#fff#,
505 pirq_ms => 6,
511 pirq_ms => 6,
506 pirq_wfp => 14,
512 pirq_wfp => 14,
507 hindex => 2,
513 hindex => 2,
508 top_lfr_version => X"000127") -- aa.bb.cc version
514 top_lfr_version => X"000127") -- aa.bb.cc version
509 PORT MAP (
515 PORT MAP (
510 clk => clk_25,
516 clk => clk_25,
511 rstn => LFR_rstn,
517 rstn => LFR_rstn,
512 sample_B => sample_s(2 DOWNTO 0),
518 sample_B => sample_s(2 DOWNTO 0),
513 sample_E => sample_s(7 DOWNTO 3),
519 sample_E => sample_s(7 DOWNTO 3),
514 sample_val => sample_val,
520 sample_val => sample_val,
515 apbi => apbi_ext,
521 apbi => apbi_ext,
516 apbo => apbo_ext(15),
522 apbo => apbo_ext(15),
517 ahbi => ahbi_m_ext,
523 ahbi => ahbi_m_ext,
518 ahbo => ahbo_m_ext(2),
524 ahbo => ahbo_m_ext(2),
519 coarse_time => coarse_time,
525 coarse_time => coarse_time,
520 fine_time => fine_time,
526 fine_time => fine_time,
521 data_shaping_BW => bias_fail_sw_sig,
527 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
528 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
529 debug_vector_ms => lfr_debug_vector_ms
524 );
530 );
525
531
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
532 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
533 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
534 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
535 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
536 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
537 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
538 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
539 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
540 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
541 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
542 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
543 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
538
544
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
545 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
546 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
541 END GENERATE all_sample;
547 END GENERATE all_sample;
542
548
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
549 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
544 GENERIC MAP(
550 GENERIC MAP(
545 ChannelCount => 8,
551 ChannelCount => 8,
546 SampleNbBits => 14,
552 SampleNbBits => 14,
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
553 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
554 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
549 PORT MAP (
555 PORT MAP (
550 -- CONV
556 -- CONV
551 cnv_clk => clk_24,
557 cnv_clk => clk_24,
552 cnv_rstn => rstn_25,
558 cnv_rstn => rstn_25,
553 cnv => ADC_nCS_sig,
559 cnv => ADC_nCS_sig,
554 -- DATA
560 -- DATA
555 clk => clk_25,
561 clk => clk_25,
556 rstn => rstn_25,
562 rstn => rstn_25,
557 sck => ADC_CLK_sig,
563 sck => ADC_CLK_sig,
558 sdo => ADC_SDO_sig,
564 sdo => ADC_SDO_sig,
559 -- SAMPLE
565 -- SAMPLE
560 sample => sample,
566 sample => sample,
561 sample_val => sample_val);
567 sample_val => sample_val);
562
568
563 --IO10 <= ADC_SDO_sig(5);
569 --IO10 <= ADC_SDO_sig(5);
564 --IO9 <= ADC_SDO_sig(4);
570 --IO9 <= ADC_SDO_sig(4);
565 --IO8 <= ADC_SDO_sig(3);
571 --IO8 <= ADC_SDO_sig(3);
566
572
567 ADC_nCS <= ADC_nCS_sig;
573 ADC_nCS <= ADC_nCS_sig;
568 ADC_CLK <= ADC_CLK_sig;
574 ADC_CLK <= ADC_CLK_sig;
569 ADC_SDO_sig <= ADC_SDO;
575 ADC_SDO_sig <= ADC_SDO;
570
576
571 ----------------------------------------------------------------------
577 ----------------------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
578 --- GPIO -----------------------------------------------------------
573 ----------------------------------------------------------------------
579 ----------------------------------------------------------------------
574
580
575 grgpio0 : grgpio
581 grgpio0 : grgpio
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
582 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
583 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
578
584
579 gpioi.sig_en <= (OTHERS => '0');
585 gpioi.sig_en <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
586 gpioi.sig_in <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
587 gpioi.din <= (OTHERS => '0');
582 --pio_pad_0 : iopad
588 --pio_pad_0 : iopad
583 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
590 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
585 --pio_pad_1 : iopad
591 --pio_pad_1 : iopad
586 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
593 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
588 --pio_pad_2 : iopad
594 --pio_pad_2 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
596 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
591 --pio_pad_3 : iopad
597 --pio_pad_3 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
599 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
594 --pio_pad_4 : iopad
600 --pio_pad_4 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
602 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
597 --pio_pad_5 : iopad
603 --pio_pad_5 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
605 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
600 --pio_pad_6 : iopad
606 --pio_pad_6 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
607 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
608 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
603 --pio_pad_7 : iopad
609 --pio_pad_7 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
610 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
611 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
606
612
607 PROCESS (clk_25, rstn_25)
613 PROCESS (clk_25, rstn_25)
608 BEGIN -- PROCESS
614 BEGIN -- PROCESS
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
615 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
610 -- --IO0 <= '0';
616 -- --IO0 <= '0';
611 -- IO1 <= '0';
617 -- IO1 <= '0';
612 -- IO2 <= '0';
618 -- IO2 <= '0';
613 -- IO3 <= '0';
619 -- IO3 <= '0';
614 -- IO4 <= '0';
620 -- IO4 <= '0';
615 -- IO5 <= '0';
621 -- IO5 <= '0';
616 -- IO6 <= '0';
622 -- IO6 <= '0';
617 -- IO7 <= '0';
623 -- IO7 <= '0';
618 IO8 <= '0';
624 IO8 <= '0';
619 IO9 <= '0';
625 IO9 <= '0';
620 IO10 <= '0';
626 IO10 <= '0';
621 IO11 <= '0';
627 IO11 <= '0';
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
628 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
623 CASE gpioo.dout(2 DOWNTO 0) IS
629 CASE gpioo.dout(2 DOWNTO 0) IS
624 WHEN "011" =>
630 WHEN "011" =>
625 -- --IO0 <= observation_reg(0 );
631 -- --IO0 <= observation_reg(0 );
626 -- IO1 <= observation_reg(1 );
632 -- IO1 <= observation_reg(1 );
627 -- IO2 <= observation_reg(2 );
633 -- IO2 <= observation_reg(2 );
628 -- IO3 <= observation_reg(3 );
634 -- IO3 <= observation_reg(3 );
629 -- IO4 <= observation_reg(4 );
635 -- IO4 <= observation_reg(4 );
630 -- IO5 <= observation_reg(5 );
636 -- IO5 <= observation_reg(5 );
631 -- IO6 <= observation_reg(6 );
637 -- IO6 <= observation_reg(6 );
632 -- IO7 <= observation_reg(7 );
638 -- IO7 <= observation_reg(7 );
633 IO8 <= observation_reg(8);
639 IO8 <= observation_reg(8);
634 IO9 <= observation_reg(9);
640 IO9 <= observation_reg(9);
635 IO10 <= observation_reg(10);
641 IO10 <= observation_reg(10);
636 IO11 <= observation_reg(11);
642 IO11 <= observation_reg(11);
637 WHEN "001" =>
643 WHEN "001" =>
638 -- --IO0 <= observation_reg(0 + 12);
644 -- --IO0 <= observation_reg(0 + 12);
639 -- IO1 <= observation_reg(1 + 12);
645 -- IO1 <= observation_reg(1 + 12);
640 -- IO2 <= observation_reg(2 + 12);
646 -- IO2 <= observation_reg(2 + 12);
641 -- IO3 <= observation_reg(3 + 12);
647 -- IO3 <= observation_reg(3 + 12);
642 -- IO4 <= observation_reg(4 + 12);
648 -- IO4 <= observation_reg(4 + 12);
643 -- IO5 <= observation_reg(5 + 12);
649 -- IO5 <= observation_reg(5 + 12);
644 -- IO6 <= observation_reg(6 + 12);
650 -- IO6 <= observation_reg(6 + 12);
645 -- IO7 <= observation_reg(7 + 12);
651 -- IO7 <= observation_reg(7 + 12);
646 IO8 <= observation_reg(8 + 12);
652 IO8 <= observation_reg(8 + 12);
647 IO9 <= observation_reg(9 + 12);
653 IO9 <= observation_reg(9 + 12);
648 IO10 <= observation_reg(10 + 12);
654 IO10 <= observation_reg(10 + 12);
649 IO11 <= observation_reg(11 + 12);
655 IO11 <= observation_reg(11 + 12);
650 WHEN "010" =>
656 WHEN "010" =>
651 -- --IO0 <= observation_reg(0 + 12 + 12);
657 -- --IO0 <= observation_reg(0 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
658 -- IO1 <= observation_reg(1 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
659 -- IO2 <= observation_reg(2 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
660 -- IO3 <= observation_reg(3 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
661 -- IO4 <= observation_reg(4 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
662 -- IO5 <= observation_reg(5 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
663 -- IO6 <= observation_reg(6 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
664 -- IO7 <= observation_reg(7 + 12 + 12);
659 IO8 <= '0';
665 IO8 <= '0';
660 IO9 <= '0';
666 IO9 <= '0';
661 IO10 <= '0';
667 IO10 <= '0';
662 IO11 <= '0';
668 IO11 <= '0';
663 WHEN "000" =>
669 WHEN "000" =>
664 -- --IO0 <= observation_vector_0(0 );
670 -- --IO0 <= observation_vector_0(0 );
665 -- IO1 <= observation_vector_0(1 );
671 -- IO1 <= observation_vector_0(1 );
666 -- IO2 <= observation_vector_0(2 );
672 -- IO2 <= observation_vector_0(2 );
667 -- IO3 <= observation_vector_0(3 );
673 -- IO3 <= observation_vector_0(3 );
668 -- IO4 <= observation_vector_0(4 );
674 -- IO4 <= observation_vector_0(4 );
669 -- IO5 <= observation_vector_0(5 );
675 -- IO5 <= observation_vector_0(5 );
670 -- IO6 <= observation_vector_0(6 );
676 -- IO6 <= observation_vector_0(6 );
671 -- IO7 <= observation_vector_0(7 );
677 -- IO7 <= observation_vector_0(7 );
672 IO8 <= observation_vector_0(8);
678 IO8 <= observation_vector_0(8);
673 IO9 <= observation_vector_0(9);
679 IO9 <= observation_vector_0(9);
674 IO10 <= observation_vector_0(10);
680 IO10 <= observation_vector_0(10);
675 IO11 <= observation_vector_0(11);
681 IO11 <= observation_vector_0(11);
676 WHEN "100" =>
682 WHEN "100" =>
677 -- --IO0 <= observation_vector_1(0 );
683 -- --IO0 <= observation_vector_1(0 );
678 -- IO1 <= observation_vector_1(1 );
684 -- IO1 <= observation_vector_1(1 );
679 -- IO2 <= observation_vector_1(2 );
685 -- IO2 <= observation_vector_1(2 );
680 -- IO3 <= observation_vector_1(3 );
686 -- IO3 <= observation_vector_1(3 );
681 -- IO4 <= observation_vector_1(4 );
687 -- IO4 <= observation_vector_1(4 );
682 -- IO5 <= observation_vector_1(5 );
688 -- IO5 <= observation_vector_1(5 );
683 -- IO6 <= observation_vector_1(6 );
689 -- IO6 <= observation_vector_1(6 );
684 -- IO7 <= observation_vector_1(7 );
690 -- IO7 <= observation_vector_1(7 );
685 IO8 <= observation_vector_1(8);
691 IO8 <= observation_vector_1(8);
686 IO9 <= observation_vector_1(9);
692 IO9 <= observation_vector_1(9);
687 IO10 <= observation_vector_1(10);
693 IO10 <= observation_vector_1(10);
688 IO11 <= observation_vector_1(11);
694 IO11 <= observation_vector_1(11);
689 WHEN OTHERS => NULL;
695 WHEN OTHERS => NULL;
690 END CASE;
696 END CASE;
691
697
692 END IF;
698 END IF;
693 END PROCESS;
699 END PROCESS;
694 -----------------------------------------------------------------------------
700 -----------------------------------------------------------------------------
695 --
701 --
696 -----------------------------------------------------------------------------
702 -----------------------------------------------------------------------------
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
703 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
704 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
699 apbo_ext(I) <= apb_none;
705 apbo_ext(I) <= apb_none;
700 END GENERATE apbo_ext_not_used;
706 END GENERATE apbo_ext_not_used;
701 END GENERATE all_apbo_ext;
707 END GENERATE all_apbo_ext;
702
708
703
709
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
710 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
705 ahbo_s_ext(I) <= ahbs_none;
711 ahbo_s_ext(I) <= ahbs_none;
706 END GENERATE all_ahbo_ext;
712 END GENERATE all_ahbo_ext;
707
713
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
714 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
715 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
710 ahbo_m_ext(I) <= ahbm_none;
716 ahbo_m_ext(I) <= ahbm_none;
711 END GENERATE ahbo_m_ext_not_used;
717 END GENERATE ahbo_m_ext_not_used;
712 END GENERATE all_ahbo_m_ext;
718 END GENERATE all_ahbo_m_ext;
713
719
714 END beh;
720 END beh;
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