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Update arbitration in front of FFT based on Pong Status
pellion -
r382:bd4b3b04474b (MINI-LFR) WFP_MS-0-1-18 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 BEGIN -- beh
180 180
181 181 -----------------------------------------------------------------------------
182 182 -- CLK
183 183 -----------------------------------------------------------------------------
184 184
185 185 PROCESS(clk_50)
186 186 BEGIN
187 187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 188 clk_50_s <= NOT clk_50_s;
189 189 END IF;
190 190 END PROCESS;
191 191
192 192 PROCESS(clk_50_s)
193 193 BEGIN
194 194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 195 clk_25 <= NOT clk_25;
196 196 END IF;
197 197 END PROCESS;
198 198
199 199 PROCESS(clk_49)
200 200 BEGIN
201 201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 202 clk_24 <= NOT clk_24;
203 203 END IF;
204 204 END PROCESS;
205 205
206 206 -----------------------------------------------------------------------------
207 207
208 208 PROCESS (clk_25, reset)
209 209 BEGIN -- PROCESS
210 210 IF reset = '0' THEN -- asynchronous reset (active low)
211 211 LED0 <= '0';
212 212 LED1 <= '0';
213 213 LED2 <= '0';
214 214 --IO1 <= '0';
215 215 --IO2 <= '1';
216 216 --IO3 <= '0';
217 217 --IO4 <= '0';
218 218 --IO5 <= '0';
219 219 --IO6 <= '0';
220 220 --IO7 <= '0';
221 221 --IO8 <= '0';
222 222 --IO9 <= '0';
223 223 --IO10 <= '0';
224 224 --IO11 <= '0';
225 225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 226 LED0 <= '0';
227 227 LED1 <= '1';
228 228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 229 --IO1 <= '1';
230 230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 231 --IO3 <= ADC_SDO(0);
232 232 --IO4 <= ADC_SDO(1);
233 233 --IO5 <= ADC_SDO(2);
234 234 --IO6 <= ADC_SDO(3);
235 235 --IO7 <= ADC_SDO(4);
236 236 --IO8 <= ADC_SDO(5);
237 237 --IO9 <= ADC_SDO(6);
238 238 --IO10 <= ADC_SDO(7);
239 239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 240 END IF;
241 241 END PROCESS;
242 242
243 243 PROCESS (clk_24, reset)
244 244 BEGIN -- PROCESS
245 245 IF reset = '0' THEN -- asynchronous reset (active low)
246 246 I00_s <= '0';
247 247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 248 I00_s <= NOT I00_s ;
249 249 END IF;
250 250 END PROCESS;
251 251 -- IO0 <= I00_s;
252 252
253 253 --UARTs
254 254 nCTS1 <= '1';
255 255 nCTS2 <= '1';
256 256 nDCD2 <= '1';
257 257
258 258 --EXT CONNECTOR
259 259
260 260 --SPACE WIRE
261 261
262 262 leon3_soc_1 : leon3_soc
263 263 GENERIC MAP (
264 264 fabtech => apa3e,
265 265 memtech => apa3e,
266 266 padtech => inferred,
267 267 clktech => inferred,
268 268 disas => 0,
269 269 dbguart => 0,
270 270 pclow => 2,
271 271 clk_freq => 25000,
272 272 NB_CPU => 1,
273 273 ENABLE_FPU => 1,
274 274 FPU_NETLIST => 0,
275 275 ENABLE_DSU => 1,
276 276 ENABLE_AHB_UART => 1,
277 277 ENABLE_APB_UART => 1,
278 278 ENABLE_IRQMP => 1,
279 279 ENABLE_GPT => 1,
280 280 NB_AHB_MASTER => NB_AHB_MASTER,
281 281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 282 NB_APB_SLAVE => NB_APB_SLAVE)
283 283 PORT MAP (
284 284 clk => clk_25,
285 285 reset => reset,
286 286 errorn => errorn,
287 287 ahbrxd => TXD1,
288 288 ahbtxd => RXD1,
289 289 urxd1 => TXD2,
290 290 utxd1 => RXD2,
291 291 address => SRAM_A,
292 292 data => SRAM_DQ,
293 293 nSRAM_BE0 => SRAM_nBE(0),
294 294 nSRAM_BE1 => SRAM_nBE(1),
295 295 nSRAM_BE2 => SRAM_nBE(2),
296 296 nSRAM_BE3 => SRAM_nBE(3),
297 297 nSRAM_WE => SRAM_nWE,
298 298 nSRAM_CE => SRAM_CE,
299 299 nSRAM_OE => SRAM_nOE,
300 300
301 301 apbi_ext => apbi_ext,
302 302 apbo_ext => apbo_ext,
303 303 ahbi_s_ext => ahbi_s_ext,
304 304 ahbo_s_ext => ahbo_s_ext,
305 305 ahbi_m_ext => ahbi_m_ext,
306 306 ahbo_m_ext => ahbo_m_ext);
307 307
308 308 -------------------------------------------------------------------------------
309 309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 310 -------------------------------------------------------------------------------
311 311 apb_lfr_time_management_1 : apb_lfr_time_management
312 312 GENERIC MAP (
313 313 pindex => 6,
314 314 paddr => 6,
315 315 pmask => 16#fff#,
316 316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 318 PORT MAP (
319 319 clk25MHz => clk_25,
320 320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 321 resetn => reset,
322 322 grspw_tick => swno.tickout,
323 323 apbi => apbi_ext,
324 324 apbo => apbo_ext(6),
325 325 coarse_time => coarse_time,
326 326 fine_time => fine_time);
327 327
328 328 -----------------------------------------------------------------------
329 329 --- SpaceWire --------------------------------------------------------
330 330 -----------------------------------------------------------------------
331 331
332 332 SPW_EN <= '1';
333 333
334 334 spw_clk <= clk_50_s;
335 335 spw_rxtxclk <= spw_clk;
336 336 spw_rxclkn <= NOT spw_rxtxclk;
337 337
338 338 -- PADS for SPW1
339 339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 347 -- PADS FOR SPW2
348 348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 351 PORT MAP (SPW_RED_DIN, stmp(1));
352 352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356 356
357 357 -- GRSPW PHY
358 358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 360 spw_phy0 : grspw_phy
361 361 GENERIC MAP(
362 362 tech => apa3e,
363 363 rxclkbuftype => 1,
364 364 scantest => 0)
365 365 PORT MAP(
366 366 rxrst => swno.rxrst,
367 367 di => dtmp(j),
368 368 si => stmp(j),
369 369 rxclko => spw_rxclk(j),
370 370 do => swni.d(j),
371 371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 373 END GENERATE spw_inputloop;
374 374
375 375 -- SPW core
376 376 sw0 : grspwm GENERIC MAP(
377 377 tech => apa3e,
378 378 hindex => 1,
379 379 pindex => 5,
380 380 paddr => 5,
381 381 pirq => 11,
382 382 sysfreq => 25000, -- CPU_FREQ
383 383 rmap => 1,
384 384 rmapcrc => 1,
385 385 fifosize1 => 16,
386 386 fifosize2 => 16,
387 387 rxclkbuftype => 1,
388 388 rxunaligned => 0,
389 389 rmapbufs => 4,
390 390 ft => 0,
391 391 netlist => 0,
392 392 ports => 2,
393 393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 394 memtech => apa3e,
395 395 destkey => 2,
396 396 spwcore => 1
397 397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 400 )
401 401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 404 swni, swno);
405 405
406 406 swni.tickin <= '0';
407 407 swni.rmapen <= '1';
408 408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 409 swni.tickinraw <= '0';
410 410 swni.timein <= (OTHERS => '0');
411 411 swni.dcrstval <= (OTHERS => '0');
412 412 swni.timerrstval <= (OTHERS => '0');
413 413
414 414 -------------------------------------------------------------------------------
415 415 -- LFR ------------------------------------------------------------------------
416 416 -------------------------------------------------------------------------------
417 417 lpp_lfr_1 : lpp_lfr
418 418 GENERIC MAP (
419 419 Mem_use => use_RAM,
420 420 nb_data_by_buffer_size => 32,
421 421 nb_word_by_buffer_size => 30,
422 422 nb_snapshot_param_size => 32,
423 423 delta_vector_size => 32,
424 424 delta_vector_size_f0_2 => 7, -- log2(96)
425 425 pindex => 15,
426 426 paddr => 15,
427 427 pmask => 16#fff#,
428 428 pirq_ms => 6,
429 429 pirq_wfp => 14,
430 430 hindex => 2,
431 top_lfr_version => X"000111") -- aa.bb.cc version
431 top_lfr_version => X"000112") -- aa.bb.cc version
432 432 PORT MAP (
433 433 clk => clk_25,
434 434 rstn => reset,
435 435 sample_B => sample_s(2 DOWNTO 0),
436 436 sample_E => sample_s(7 DOWNTO 3),
437 437 sample_val => sample_val,
438 438 apbi => apbi_ext,
439 439 apbo => apbo_ext(15),
440 440 ahbi => ahbi_m_ext,
441 441 ahbo => ahbo_m_ext(2),
442 442 coarse_time => coarse_time,
443 443 fine_time => fine_time,
444 444 data_shaping_BW => bias_fail_sw_sig,
445 445 observation_vector_0=> observation_vector_0,
446 446 observation_vector_1 => observation_vector_1,
447 447 observation_reg => observation_reg);
448 448
449 449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 451 END GENERATE all_sample;
452 452
453 453
454 454
455 455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 456 GENERIC MAP(
457 457 ChannelCount => 8,
458 458 SampleNbBits => 14,
459 459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 461 PORT MAP (
462 462 -- CONV
463 463 cnv_clk => clk_24,
464 464 cnv_rstn => reset,
465 465 cnv => ADC_nCS_sig,
466 466 -- DATA
467 467 clk => clk_25,
468 468 rstn => reset,
469 469 sck => ADC_CLK_sig,
470 470 sdo => ADC_SDO_sig,
471 471 -- SAMPLE
472 472 sample => sample,
473 473 sample_val => sample_val);
474 474
475 475 --IO10 <= ADC_SDO_sig(5);
476 476 --IO9 <= ADC_SDO_sig(4);
477 477 --IO8 <= ADC_SDO_sig(3);
478 478
479 479 ADC_nCS <= ADC_nCS_sig;
480 480 ADC_CLK <= ADC_CLK_sig;
481 481 ADC_SDO_sig <= ADC_SDO;
482 482
483 483 ----------------------------------------------------------------------
484 484 --- GPIO -----------------------------------------------------------
485 485 ----------------------------------------------------------------------
486 486
487 487 grgpio0 : grgpio
488 488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490 490
491 491 --pio_pad_0 : iopad
492 492 -- GENERIC MAP (tech => CFG_PADTECH)
493 493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 494 --pio_pad_1 : iopad
495 495 -- GENERIC MAP (tech => CFG_PADTECH)
496 496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 497 --pio_pad_2 : iopad
498 498 -- GENERIC MAP (tech => CFG_PADTECH)
499 499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 500 --pio_pad_3 : iopad
501 501 -- GENERIC MAP (tech => CFG_PADTECH)
502 502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 503 --pio_pad_4 : iopad
504 504 -- GENERIC MAP (tech => CFG_PADTECH)
505 505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 506 --pio_pad_5 : iopad
507 507 -- GENERIC MAP (tech => CFG_PADTECH)
508 508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 509 --pio_pad_6 : iopad
510 510 -- GENERIC MAP (tech => CFG_PADTECH)
511 511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 512 --pio_pad_7 : iopad
513 513 -- GENERIC MAP (tech => CFG_PADTECH)
514 514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515 515
516 516 PROCESS (clk_25, reset)
517 517 BEGIN -- PROCESS
518 518 IF reset = '0' THEN -- asynchronous reset (active low)
519 519 IO0 <= '0';
520 520 IO1 <= '0';
521 521 IO2 <= '0';
522 522 IO3 <= '0';
523 523 IO4 <= '0';
524 524 IO5 <= '0';
525 525 IO6 <= '0';
526 526 IO7 <= '0';
527 527 IO8 <= '0';
528 528 IO9 <= '0';
529 529 IO10 <= '0';
530 530 IO11 <= '0';
531 531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "000" =>
533 WHEN "011" =>
534 534 IO0 <= observation_reg(0 );
535 535 IO1 <= observation_reg(1 );
536 536 IO2 <= observation_reg(2 );
537 537 IO3 <= observation_reg(3 );
538 538 IO4 <= observation_reg(4 );
539 539 IO5 <= observation_reg(5 );
540 540 IO6 <= observation_reg(6 );
541 541 IO7 <= observation_reg(7 );
542 542 IO8 <= observation_reg(8 );
543 543 IO9 <= observation_reg(9 );
544 544 IO10 <= observation_reg(10);
545 545 IO11 <= observation_reg(11);
546 546 WHEN "001" =>
547 547 IO0 <= observation_reg(0 + 12);
548 548 IO1 <= observation_reg(1 + 12);
549 549 IO2 <= observation_reg(2 + 12);
550 550 IO3 <= observation_reg(3 + 12);
551 551 IO4 <= observation_reg(4 + 12);
552 552 IO5 <= observation_reg(5 + 12);
553 553 IO6 <= observation_reg(6 + 12);
554 554 IO7 <= observation_reg(7 + 12);
555 555 IO8 <= observation_reg(8 + 12);
556 556 IO9 <= observation_reg(9 + 12);
557 557 IO10 <= observation_reg(10 + 12);
558 558 IO11 <= observation_reg(11 + 12);
559 559 WHEN "010" =>
560 560 IO0 <= observation_reg(0 + 12 + 12);
561 561 IO1 <= observation_reg(1 + 12 + 12);
562 562 IO2 <= observation_reg(2 + 12 + 12);
563 563 IO3 <= observation_reg(3 + 12 + 12);
564 564 IO4 <= observation_reg(4 + 12 + 12);
565 565 IO5 <= observation_reg(5 + 12 + 12);
566 566 IO6 <= observation_reg(6 + 12 + 12);
567 567 IO7 <= observation_reg(7 + 12 + 12);
568 568 IO8 <= '0';
569 569 IO9 <= '0';
570 570 IO10 <= '0';
571 571 IO11 <= '0';
572 WHEN "011" =>
572 WHEN "000" =>
573 573 IO0 <= observation_vector_0(0 );
574 574 IO1 <= observation_vector_0(1 );
575 575 IO2 <= observation_vector_0(2 );
576 576 IO3 <= observation_vector_0(3 );
577 577 IO4 <= observation_vector_0(4 );
578 578 IO5 <= observation_vector_0(5 );
579 579 IO6 <= observation_vector_0(6 );
580 580 IO7 <= observation_vector_0(7 );
581 581 IO8 <= observation_vector_0(8 );
582 582 IO9 <= observation_vector_0(9 );
583 583 IO10 <= observation_vector_0(10);
584 584 IO11 <= observation_vector_0(11);
585 585 WHEN "100" =>
586 586 IO0 <= observation_vector_1(0 );
587 587 IO1 <= observation_vector_1(1 );
588 588 IO2 <= observation_vector_1(2 );
589 589 IO3 <= observation_vector_1(3 );
590 590 IO4 <= observation_vector_1(4 );
591 591 IO5 <= observation_vector_1(5 );
592 592 IO6 <= observation_vector_1(6 );
593 593 IO7 <= observation_vector_1(7 );
594 594 IO8 <= observation_vector_1(8 );
595 595 IO9 <= observation_vector_1(9 );
596 596 IO10 <= observation_vector_1(10);
597 597 IO11 <= observation_vector_1(11);
598 598 WHEN OTHERS => NULL;
599 599 END CASE;
600 600
601 601 END IF;
602 602 END PROCESS;
603 603
604 604 END beh;
Show file before | Show file after | Hide comments
@@ -1,970 +1,972
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0 : OUT STD_LOGIC;
53 53 ready_matrix_f1 : OUT STD_LOGIC;
54 54 ready_matrix_f2 : OUT STD_LOGIC;
55 55 error_bad_component_error : OUT STD_LOGIC;
56 56 error_buffer_full : OUT STD_LOGIC;
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 --
61 61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC;
66 66 status_ready_matrix_f1 : IN STD_LOGIC;
67 67 status_ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 70 config_active_interruption_onError : IN STD_LOGIC;
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78 78
79 79 );
80 80 END;
81 81
82 82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 83
84 84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89
90 90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95
96 96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102
103 103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL error_wen_f0 : STD_LOGIC;
109 109 SIGNAL error_wen_f1 : STD_LOGIC;
110 110 SIGNAL error_wen_f2 : STD_LOGIC;
111 111
112 112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116 116
117 117 -----------------------------------------------------------------------------
118 118 -- FSM / SWITCH SELECT CHANNEL
119 119 -----------------------------------------------------------------------------
120 120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123 123
124 124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 128
129 129 -----------------------------------------------------------------------------
130 130 -- FSM LOAD FFT
131 131 -----------------------------------------------------------------------------
132 132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135 135
136 136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 137 SIGNAL sample_load : STD_LOGIC;
138 138 SIGNAL sample_valid : STD_LOGIC;
139 139 SIGNAL sample_valid_r : STD_LOGIC;
140 140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 141
142 142
143 143 -----------------------------------------------------------------------------
144 144 -- FFT
145 145 -----------------------------------------------------------------------------
146 146 SIGNAL fft_read : STD_LOGIC;
147 147 SIGNAL fft_pong : STD_LOGIC;
148 148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150 SIGNAL fft_data_valid : STD_LOGIC;
151 151 SIGNAL fft_ready : STD_LOGIC;
152 152 -----------------------------------------------------------------------------
153 153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 154 -----------------------------------------------------------------------------
155 155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 158 SIGNAL current_fifo_empty : STD_LOGIC;
159 159 SIGNAL current_fifo_locked : STD_LOGIC;
160 160 SIGNAL current_fifo_full : STD_LOGIC;
161 161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 162
163 163 -----------------------------------------------------------------------------
164 164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 172 -----------------------------------------------------------------------------
173 173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 176
177 177 SIGNAL SM_correlation_start : STD_LOGIC;
178 178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 179 SIGNAL SM_correlation_done : STD_LOGIC;
180 180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 183 SIGNAL SM_correlation_begin : STD_LOGIC;
184 184
185 185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188 188
189 189 SIGNAL current_matrix_write : STD_LOGIC;
190 190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 191 -----------------------------------------------------------------------------
192 192 SIGNAL fifo_0_ready : STD_LOGIC;
193 193 SIGNAL fifo_1_ready : STD_LOGIC;
194 194 SIGNAL fifo_ongoing : STD_LOGIC;
195 195
196 196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 200 -----------------------------------------------------------------------------
201 201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 207
208 208 -----------------------------------------------------------------------------
209 209 -- TIME REG & INFOs
210 210 -----------------------------------------------------------------------------
211 211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 212
213 213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217 217
218 218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 222
223 223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 225 --SIGNAL time_update_f1 : STD_LOGIC;
226 226 --SIGNAL time_update_f2 : STD_LOGIC;
227 227 --
228 228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231 231
232 232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 236 -----------------------------------------------------------------------------
237 237 SIGNAL ping_npong : STD_LOGIC;
238 238 SIGNAL sample_load_reg : STD_LOGIC;
239 239
240 240 BEGIN
241 241
242 242
243 243 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
244 244
245 245
246 246 switch_f0_inst : spectral_matrix_switch_f0
247 247 PORT MAP (
248 248 clk => clk,
249 249 rstn => rstn,
250 250
251 251 sample_wen => sample_f0_wen,
252 252
253 253 fifo_A_empty => sample_f0_A_empty,
254 254 fifo_A_full => sample_f0_A_full,
255 255 fifo_A_wen => sample_f0_A_wen,
256 256
257 257 fifo_B_empty => sample_f0_B_empty,
258 258 fifo_B_full => sample_f0_B_full,
259 259 fifo_B_wen => sample_f0_B_wen,
260 260
261 261 error_wen => error_wen_f0); -- TODO
262 262
263 263 -----------------------------------------------------------------------------
264 264 -- FIFO IN
265 265 -----------------------------------------------------------------------------
266 266 lppFIFOxN_f0_a : lppFIFOxN
267 267 GENERIC MAP (
268 268 tech => 0,
269 269 Mem_use => Mem_use,
270 270 Data_sz => 16,
271 271 Addr_sz => 8,
272 272 FifoCnt => 5)
273 273 PORT MAP (
274 274 clk => clk,
275 275 rstn => rstn,
276 276
277 277 ReUse => (OTHERS => '0'),
278 278
279 279 wen => sample_f0_A_wen,
280 280 wdata => sample_f0_wdata,
281 281
282 282 ren => sample_f0_A_ren,
283 283 rdata => sample_f0_A_rdata,
284 284
285 285 empty => sample_f0_A_empty,
286 286 full => sample_f0_A_full,
287 287 almost_full => OPEN);
288 288
289 289 lppFIFOxN_f0_b : lppFIFOxN
290 290 GENERIC MAP (
291 291 tech => 0,
292 292 Mem_use => Mem_use,
293 293 Data_sz => 16,
294 294 Addr_sz => 8,
295 295 FifoCnt => 5)
296 296 PORT MAP (
297 297 clk => clk,
298 298 rstn => rstn,
299 299
300 300 ReUse => (OTHERS => '0'),
301 301
302 302 wen => sample_f0_B_wen,
303 303 wdata => sample_f0_wdata,
304 304 ren => sample_f0_B_ren,
305 305 rdata => sample_f0_B_rdata,
306 306 empty => sample_f0_B_empty,
307 307 full => sample_f0_B_full,
308 308 almost_full => OPEN);
309 309
310 310 lppFIFOxN_f1 : lppFIFOxN
311 311 GENERIC MAP (
312 312 tech => 0,
313 313 Mem_use => Mem_use,
314 314 Data_sz => 16,
315 315 Addr_sz => 8,
316 316 FifoCnt => 5)
317 317 PORT MAP (
318 318 clk => clk,
319 319 rstn => rstn,
320 320
321 321 ReUse => (OTHERS => '0'),
322 322
323 323 wen => sample_f1_wen,
324 324 wdata => sample_f1_wdata,
325 325 ren => sample_f1_ren,
326 326 rdata => sample_f1_rdata,
327 327 empty => sample_f1_empty,
328 328 full => sample_f1_full,
329 329 almost_full => sample_f1_almost_full);
330 330
331 331
332 332 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
333 333
334 334 PROCESS (clk, rstn)
335 335 BEGIN -- PROCESS
336 336 IF rstn = '0' THEN -- asynchronous reset (active low)
337 337 one_sample_f1_full <= '0';
338 338 error_wen_f1 <= '0';
339 339 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
340 340 IF sample_f1_full = "00000" THEN
341 341 one_sample_f1_full <= '0';
342 342 ELSE
343 343 one_sample_f1_full <= '1';
344 344 END IF;
345 345 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
346 346 END IF;
347 347 END PROCESS;
348 348
349 349
350 350 lppFIFOxN_f2 : lppFIFOxN
351 351 GENERIC MAP (
352 352 tech => 0,
353 353 Mem_use => Mem_use,
354 354 Data_sz => 16,
355 355 Addr_sz => 8,
356 356 FifoCnt => 5)
357 357 PORT MAP (
358 358 clk => clk,
359 359 rstn => rstn,
360 360
361 361 ReUse => (OTHERS => '0'),
362 362
363 363 wen => sample_f2_wen,
364 364 wdata => sample_f2_wdata,
365 365 ren => sample_f2_ren,
366 366 rdata => sample_f2_rdata,
367 367 empty => sample_f2_empty,
368 368 full => sample_f2_full,
369 369 almost_full => OPEN);
370 370
371 371
372 372 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
373 373
374 374 PROCESS (clk, rstn)
375 375 BEGIN -- PROCESS
376 376 IF rstn = '0' THEN -- asynchronous reset (active low)
377 377 one_sample_f2_full <= '0';
378 378 error_wen_f2 <= '0';
379 379 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
380 380 IF sample_f2_full = "00000" THEN
381 381 one_sample_f2_full <= '0';
382 382 ELSE
383 383 one_sample_f2_full <= '1';
384 384 END IF;
385 385 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
386 386 END IF;
387 387 END PROCESS;
388 388
389 389 -----------------------------------------------------------------------------
390 390 -- FSM SELECT CHANNEL
391 391 -----------------------------------------------------------------------------
392 392 PROCESS (clk, rstn)
393 393 BEGIN
394 394 IF rstn = '0' THEN
395 395 state_fsm_select_channel <= IDLE;
396 396 ELSIF clk'EVENT AND clk = '1' THEN
397 397 CASE state_fsm_select_channel IS
398 398 WHEN IDLE =>
399 399 IF sample_f1_full = "11111" THEN
400 400 state_fsm_select_channel <= SWITCH_F1;
401 401 ELSIF sample_f1_almost_full = "00000" THEN
402 402 IF sample_f0_A_full = "11111" THEN
403 403 state_fsm_select_channel <= SWITCH_F0_A;
404 404 ELSIF sample_f0_B_full = "11111" THEN
405 405 state_fsm_select_channel <= SWITCH_F0_B;
406 406 ELSIF sample_f2_full = "11111" THEN
407 407 state_fsm_select_channel <= SWITCH_F2;
408 408 END IF;
409 409 END IF;
410 410
411 411 WHEN SWITCH_F0_A =>
412 412 IF sample_f0_A_empty = "11111" THEN
413 413 state_fsm_select_channel <= IDLE;
414 414 END IF;
415 415 WHEN SWITCH_F0_B =>
416 416 IF sample_f0_B_empty = "11111" THEN
417 417 state_fsm_select_channel <= IDLE;
418 418 END IF;
419 419 WHEN SWITCH_F1 =>
420 420 IF sample_f1_empty = "11111" THEN
421 421 state_fsm_select_channel <= IDLE;
422 422 END IF;
423 423 WHEN SWITCH_F2 =>
424 424 IF sample_f2_empty = "11111" THEN
425 425 state_fsm_select_channel <= IDLE;
426 426 END IF;
427 427 WHEN OTHERS => NULL;
428 428 END CASE;
429 429
430 430 END IF;
431 431 END PROCESS;
432 432
433 433 PROCESS (clk, rstn)
434 434 BEGIN
435 435 IF rstn = '0' THEN
436 436 pre_state_fsm_select_channel <= IDLE;
437 437 ELSIF clk'EVENT AND clk = '1' THEN
438 438 pre_state_fsm_select_channel <= state_fsm_select_channel;
439 439 END IF;
440 440 END PROCESS;
441 441
442 442
443 443 -----------------------------------------------------------------------------
444 444 -- SWITCH SELECT CHANNEL
445 445 -----------------------------------------------------------------------------
446 446 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
447 447 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
448 448 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
449 449 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
450 450 (OTHERS => '1');
451 451
452 452 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
453 453 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
454 454 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
455 455 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
456 456 (OTHERS => '0');
457 457
458 458 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
459 459 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
460 460 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
461 461 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
462 462
463 463
464 464 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
465 465 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
466 466 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
467 467 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
468 468
469 469
470 470 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
471 471 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
472 472 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
473 473 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
474 474
475 475 -----------------------------------------------------------------------------
476 476 -- FSM LOAD FFT
477 477 -----------------------------------------------------------------------------
478 478
479 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
479 sample_ren <= sample_ren_s WHEN ping_npong = fft_pong AND sample_load = '1' ELSE
480 (OTHERS => '1');
480 481
481 482 PROCESS (clk, rstn)
482 483 BEGIN
483 484 IF rstn = '0' THEN
484 485 sample_ren_s <= (OTHERS => '1');
485 486 state_fsm_load_FFT <= IDLE;
486 487 status_MS_input <= (OTHERS => '0');
487 488 --next_state_fsm_load_FFT <= IDLE;
488 489 --sample_valid <= '0';
489 490 ELSIF clk'EVENT AND clk = '1' THEN
490 491 CASE state_fsm_load_FFT IS
491 492 WHEN IDLE =>
492 493 --sample_valid <= '0';
493 494 sample_ren_s <= (OTHERS => '1');
494 495 IF sample_full = "11111" AND sample_load = '1' THEN
495 496 state_fsm_load_FFT <= FIFO_1;
496 497 status_MS_input <= status_channel;
497 498 END IF;
498 499
499 500 WHEN FIFO_1 =>
500 501 sample_ren_s <= "1111" & NOT(sample_load);
501 502 IF sample_empty(0) = '1' THEN
502 503 sample_ren_s <= (OTHERS => '1');
503 504 state_fsm_load_FFT <= FIFO_2;
504 505 END IF;
505 506
506 507 WHEN FIFO_2 =>
507 508 sample_ren_s <= "111" & NOT(sample_load) & '1';
508 509 IF sample_empty(1) = '1' THEN
509 510 sample_ren_s <= (OTHERS => '1');
510 511 state_fsm_load_FFT <= FIFO_3;
511 512 END IF;
512 513
513 514 WHEN FIFO_3 =>
514 515 sample_ren_s <= "11" & NOT(sample_load) & "11";
515 516 IF sample_empty(2) = '1' THEN
516 517 sample_ren_s <= (OTHERS => '1');
517 518 state_fsm_load_FFT <= FIFO_4;
518 519 END IF;
519 520
520 521 WHEN FIFO_4 =>
521 522 sample_ren_s <= '1' & NOT(sample_load) & "111";
522 523 IF sample_empty(3) = '1' THEN
523 524 sample_ren_s <= (OTHERS => '1');
524 525 state_fsm_load_FFT <= FIFO_5;
525 526 END IF;
526 527
527 528 WHEN FIFO_5 =>
528 529 sample_ren_s <= NOT(sample_load) & "1111";
529 530 IF sample_empty(4) = '1' THEN
530 531 sample_ren_s <= (OTHERS => '1');
531 532 state_fsm_load_FFT <= IDLE;
532 533 END IF;
533 534 WHEN OTHERS => NULL;
534 535 END CASE;
535 536 END IF;
536 537 END PROCESS;
537 538
538 539 PROCESS (clk, rstn)
539 540 BEGIN
540 541 IF rstn = '0' THEN
541 542 sample_valid_r <= '0';
542 543 next_state_fsm_load_FFT <= IDLE;
543 544 ELSIF clk'EVENT AND clk = '1' THEN
544 545 next_state_fsm_load_FFT <= state_fsm_load_FFT;
545 546 IF sample_ren_s = "11111" THEN
546 547 sample_valid_r <= '0';
547 548 ELSE
548 549 sample_valid_r <= '1';
549 550 END IF;
550 551 END IF;
551 552 END PROCESS;
552 553
553 554 -- sample_valid <= sample_valid_r AND sample_load;
554 sample_valid <= sample_valid_r AND (sample_load AND (ping_npong AND fft_pong));
555 sample_valid <= sample_valid_r AND sample_load WHEN ping_npong = fft_pong ELSE '0';
555 556
556 557 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
557 558 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
558 559 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
559 560 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
560 561 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
561 562
562 563 -----------------------------------------------------------------------------
563 564 -- FFT
564 565 -----------------------------------------------------------------------------
565 566 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
566 567 PORT MAP (
567 568 clk => clk,
568 569 rstn => rstn,
569 570 sample_valid => sample_valid,
570 571 fft_read => fft_read,
571 572 sample_data => sample_data,
572 573 sample_load => sample_load,
573 574 fft_pong => fft_pong,
574 575 fft_data_im => fft_data_im,
575 576 fft_data_re => fft_data_re,
576 577 fft_data_valid => fft_data_valid,
577 578 fft_ready => fft_ready);
578 579
579 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
580 observation_vector_0(11 DOWNTO 0) <= "0000" & --11 10 9 8
581 sample_load_reg & --7
582 ping_npong & --6
583 fft_ready & --5
580 584 fft_data_valid & --4
581 585 fft_pong & --3
582 586 sample_load & --2
583 587 fft_read & --1
584 588 sample_valid; --0
585 589
586 590 -----------------------------------------------------------------------------
587 591 PROCESS (clk, rstn)
588 592 BEGIN
589 593 IF rstn = '0' THEN
590 ping_npong <= '0';
591 sample_load_reg <= '0';
594 ping_npong <= '0';
595 sample_load_reg <= '0';
592 596 ELSIF clk'event AND clk = '1' THEN
593 597 sample_load_reg <= sample_load;
594 598 IF sample_load_reg = '1' AND sample_load = '0' THEN
595 599 ping_npong <= NOT ping_npong;
596 600 END IF;
597 601 END IF;
598 602 END PROCESS;
599 603
600 604 -----------------------------------------------------------------------------
601 605 PROCESS (clk, rstn)
602 606 BEGIN
603 607 IF rstn = '0' THEN
604 608 state_fsm_load_MS_memory <= IDLE;
605 609 current_fifo_load <= "00001";
606 610 ELSIF clk'EVENT AND clk = '1' THEN
607 611 CASE state_fsm_load_MS_memory IS
608 612 WHEN IDLE =>
609 613 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
610 614 state_fsm_load_MS_memory <= LOAD_FIFO;
611 615 END IF;
612 616 WHEN LOAD_FIFO =>
613 617 IF current_fifo_full = '1' THEN
614 618 state_fsm_load_MS_memory <= TRASH_FFT;
615 619 END IF;
616 620 WHEN TRASH_FFT =>
617 621 IF fft_ready = '0' THEN
618 622 state_fsm_load_MS_memory <= IDLE;
619 623 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
620 624 END IF;
621 625 WHEN OTHERS => NULL;
622 626 END CASE;
623 627
624 628 END IF;
625 629 END PROCESS;
626 630
627 631 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
628 632 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
629 633 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
630 634 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
631 635 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
632 636
633 637 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
634 638 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
635 639 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
636 640 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
637 641 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
638 642
639 643 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
640 644 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
641 645 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
642 646 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
643 647 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
644 648
645 649 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
646 650
647 651 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
648 652 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
649 653 AND state_fsm_load_MS_memory = LOAD_FIFO
650 654 AND current_fifo_load(I) = '1'
651 655 ELSE '1';
652 656 END GENERATE all_fifo;
653 657
654 658 PROCESS (clk, rstn)
655 659 BEGIN
656 660 IF rstn = '0' THEN
657 661 MEM_IN_SM_wen <= (OTHERS => '1');
658 662 ELSIF clk'EVENT AND clk = '1' THEN
659 663 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
660 664 END IF;
661 665 END PROCESS;
662 666
663 667 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
664 668 (fft_data_im & fft_data_re) &
665 669 (fft_data_im & fft_data_re) &
666 670 (fft_data_im & fft_data_re) &
667 671 (fft_data_im & fft_data_re);
668 672 -----------------------------------------------------------------------------
669 673
670 674
671 675 -----------------------------------------------------------------------------
672 676 Mem_In_SpectralMatrix : lppFIFOxN
673 677 GENERIC MAP (
674 678 tech => 0,
675 679 Mem_use => Mem_use,
676 680 Data_sz => 32, --16,
677 681 Addr_sz => 7, --8
678 682 FifoCnt => 5)
679 683 PORT MAP (
680 684 clk => clk,
681 685 rstn => rstn,
682 686
683 687 ReUse => MEM_IN_SM_ReUse,
684 688
685 689 wen => MEM_IN_SM_wen,
686 690 wdata => MEM_IN_SM_wData,
687 691
688 692 ren => MEM_IN_SM_ren,
689 693 rdata => MEM_IN_SM_rData,
690 694 full => MEM_IN_SM_Full,
691 695 empty => MEM_IN_SM_Empty,
692 696 almost_full => OPEN);
693 697
694 698 -----------------------------------------------------------------------------
695 699
696 observation_vector_1(11 DOWNTO 0) <= "0000" &
700 observation_vector_1(11 DOWNTO 0) <= '0' &
701 SM_correlation_done & --4
702 SM_correlation_auto & --3
703 SM_correlation_start &
697 704 SM_correlation_start & --7
698 705 status_MS_input(1 DOWNTO 0)& --6..5
699 706 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
700 707
701 observation_vector_0(11 DOWNTO 6) <= MEM_IN_SM_locked(0) &
702 SM_correlation_done & --4
703 SM_correlation_auto & --3
704 SM_correlation_start & --2
705 status_component(5 DOWNTO 4); --1..0
706 708 -----------------------------------------------------------------------------
707 709 MS_control_1 : MS_control
708 710 PORT MAP (
709 711 clk => clk,
710 712 rstn => rstn,
711 713
712 714 current_status_ms => status_MS_input,
713 715
714 716 fifo_in_lock => MEM_IN_SM_locked,
715 717 fifo_in_data => MEM_IN_SM_rdata,
716 718 fifo_in_full => MEM_IN_SM_Full,
717 719 fifo_in_empty => MEM_IN_SM_Empty,
718 720 fifo_in_ren => MEM_IN_SM_ren,
719 721 fifo_in_reuse => MEM_IN_SM_ReUse,
720 722
721 723 fifo_out_data => SM_in_data,
722 724 fifo_out_ren => SM_in_ren,
723 725 fifo_out_empty => SM_in_empty,
724 726
725 727 current_status_component => status_component,
726 728
727 729 correlation_start => SM_correlation_start,
728 730 correlation_auto => SM_correlation_auto,
729 731 correlation_done => SM_correlation_done);
730 732
731 733
732 734 MS_calculation_1 : MS_calculation
733 735 PORT MAP (
734 736 clk => clk,
735 737 rstn => rstn,
736 738
737 739 fifo_in_data => SM_in_data,
738 740 fifo_in_ren => SM_in_ren,
739 741 fifo_in_empty => SM_in_empty,
740 742
741 743 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
742 744 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
743 745 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
744 746
745 747 correlation_start => SM_correlation_start,
746 748 correlation_auto => SM_correlation_auto,
747 749 correlation_begin => SM_correlation_begin,
748 750 correlation_done => SM_correlation_done);
749 751
750 752 -----------------------------------------------------------------------------
751 753 PROCESS (clk, rstn)
752 754 BEGIN -- PROCESS
753 755 IF rstn = '0' THEN -- asynchronous reset (active low)
754 756 current_matrix_write <= '0';
755 757 current_matrix_wait_empty <= '1';
756 758 status_component_fifo_0 <= (OTHERS => '0');
757 759 status_component_fifo_1 <= (OTHERS => '0');
758 760 status_component_fifo_0_end <= '0';
759 761 status_component_fifo_1_end <= '0';
760 762 SM_correlation_done_reg1 <= '0';
761 763 SM_correlation_done_reg2 <= '0';
762 764 SM_correlation_done_reg3 <= '0';
763 765
764 766 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
765 767 SM_correlation_done_reg1 <= SM_correlation_done;
766 768 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
767 769 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
768 770 status_component_fifo_0_end <= '0';
769 771 status_component_fifo_1_end <= '0';
770 772 IF SM_correlation_begin = '1' THEN
771 773 IF current_matrix_write = '0' THEN
772 774 status_component_fifo_0 <= status_component;
773 775 ELSE
774 776 status_component_fifo_1 <= status_component;
775 777 END IF;
776 778 END IF;
777 779
778 780 IF SM_correlation_done_reg3 = '1' THEN
779 781 IF current_matrix_write = '0' THEN
780 782 status_component_fifo_0_end <= '1';
781 783 ELSE
782 784 status_component_fifo_1_end <= '1';
783 785 END IF;
784 786 current_matrix_wait_empty <= '1';
785 787 current_matrix_write <= NOT current_matrix_write;
786 788 END IF;
787 789
788 790 IF current_matrix_wait_empty <= '1' THEN
789 791 IF current_matrix_write = '0' THEN
790 792 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
791 793 ELSE
792 794 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
793 795 END IF;
794 796 END IF;
795 797
796 798 END IF;
797 799 END PROCESS;
798 800
799 801 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
800 802 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
801 803 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
802 804 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
803 805 '1' WHEN current_matrix_wait_empty = '1' ELSE
804 806 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
805 807 MEM_OUT_SM_Full(1);
806 808
807 809 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
808 810 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
809 811
810 812 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
811 813 -----------------------------------------------------------------------------
812 814
813 815 Mem_Out_SpectralMatrix : lppFIFOxN
814 816 GENERIC MAP (
815 817 tech => 0,
816 818 Mem_use => Mem_use,
817 819 Data_sz => 32,
818 820 Addr_sz => 8,
819 821 FifoCnt => 2)
820 822 PORT MAP (
821 823 clk => clk,
822 824 rstn => rstn,
823 825
824 826 ReUse => (OTHERS => '0'),
825 827
826 828 wen => MEM_OUT_SM_Write,
827 829 wdata => MEM_OUT_SM_Data_in,
828 830
829 831 ren => MEM_OUT_SM_Read,
830 832 rdata => MEM_OUT_SM_Data_out,
831 833
832 834 full => MEM_OUT_SM_Full,
833 835 empty => MEM_OUT_SM_Empty,
834 836 almost_full => OPEN);
835 837
836 838 -----------------------------------------------------------------------------
837 839 -- MEM_OUT_SM_Read <= "00";
838 840 PROCESS (clk, rstn)
839 841 BEGIN
840 842 IF rstn = '0' THEN
841 843 fifo_0_ready <= '0';
842 844 fifo_1_ready <= '0';
843 845 fifo_ongoing <= '0';
844 846 ELSIF clk'EVENT AND clk = '1' THEN
845 847 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
846 848 fifo_ongoing <= '1';
847 849 fifo_0_ready <= '0';
848 850 ELSIF status_component_fifo_0_end = '1' THEN
849 851 fifo_0_ready <= '1';
850 852 END IF;
851 853
852 854 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
853 855 fifo_ongoing <= '0';
854 856 fifo_1_ready <= '0';
855 857 ELSIF status_component_fifo_1_end = '1' THEN
856 858 fifo_1_ready <= '1';
857 859 END IF;
858 860
859 861 END IF;
860 862 END PROCESS;
861 863
862 864 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
863 865 '1' WHEN fifo_0_ready = '0' ELSE
864 866 FSM_DMA_fifo_ren;
865 867
866 868 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
867 869 '1' WHEN fifo_1_ready = '0' ELSE
868 870 FSM_DMA_fifo_ren;
869 871
870 872 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
871 873 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
872 874 '1';
873 875
874 876 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
875 877 status_component_fifo_1;
876 878
877 879 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
878 880 MEM_OUT_SM_Data_out(63 DOWNTO 32);
879 881
880 882 -----------------------------------------------------------------------------
881 883 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
882 884 PORT MAP (
883 885 HCLK => clk,
884 886 HRESETn => rstn,
885 887
886 888 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
887 889 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
888 890 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
889 891 fifo_data => FSM_DMA_fifo_data,
890 892 fifo_empty => FSM_DMA_fifo_empty,
891 893 fifo_ren => FSM_DMA_fifo_ren,
892 894
893 895 dma_addr => dma_addr,
894 896 dma_data => dma_data,
895 897 dma_valid => dma_valid,
896 898 dma_valid_burst => dma_valid_burst,
897 899 dma_ren => dma_ren,
898 900 dma_done => dma_done,
899 901
900 902 ready_matrix_f0 => ready_matrix_f0,
901 903 ready_matrix_f1 => ready_matrix_f1,
902 904 ready_matrix_f2 => ready_matrix_f2,
903 905
904 906 error_bad_component_error => error_bad_component_error,
905 907 error_buffer_full => error_buffer_full,
906 908
907 909 debug_reg => debug_reg,
908 910 status_ready_matrix_f0 => status_ready_matrix_f0,
909 911 status_ready_matrix_f1 => status_ready_matrix_f1,
910 912 status_ready_matrix_f2 => status_ready_matrix_f2,
911 913
912 914 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
913 915 config_active_interruption_onError => config_active_interruption_onError,
914 916
915 917 addr_matrix_f0 => addr_matrix_f0,
916 918 addr_matrix_f1 => addr_matrix_f1,
917 919 addr_matrix_f2 => addr_matrix_f2,
918 920
919 921 matrix_time_f0 => matrix_time_f0,
920 922 matrix_time_f1 => matrix_time_f1,
921 923 matrix_time_f2 => matrix_time_f2
922 924 );
923 925 -----------------------------------------------------------------------------
924 926
925 927
926 928
927 929
928 930
929 931 -----------------------------------------------------------------------------
930 932 -- TIME MANAGMENT
931 933 -----------------------------------------------------------------------------
932 934 all_time <= coarse_time & fine_time;
933 935 --
934 936 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
935 937 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
936 938 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
937 939 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
938 940
939 941 all_time_reg: FOR I IN 0 TO 3 GENERATE
940 942
941 943 PROCESS (clk, rstn)
942 944 BEGIN
943 945 IF rstn = '0' THEN
944 946 f_empty_reg(I) <= '1';
945 947 ELSIF clk'event AND clk = '1' THEN
946 948 f_empty_reg(I) <= f_empty(I);
947 949 END IF;
948 950 END PROCESS;
949 951
950 952 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
951 953
952 954 s_m_t_m_f0_A : spectral_matrix_time_managment
953 955 PORT MAP (
954 956 clk => clk,
955 957 rstn => rstn,
956 958 time_in => all_time,
957 959 update_1 => time_update_f(I),
958 960 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
959 961 );
960 962
961 963 END GENERATE all_time_reg;
962 964
963 965 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
964 966 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
965 967 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
966 968 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
967 969
968 970 -----------------------------------------------------------------------------
969 971
970 END Behavioral;
972 END Behavioral; No newline at end of file
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