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modif alexis - CNA
pellion -
r539:ba59fa3696fb (LFR-EM) WFP_MS_1-1-62 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY LFR_em IS
49 49
50 50 PORT (
51 51 clk100MHz : IN STD_ULOGIC;
52 52 clk49_152MHz : IN STD_ULOGIC;
53 53 reset : IN STD_ULOGIC;
54 54
55 55 -- TAG --------------------------------------------------------------------
56 56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 58 -- UART APB ---------------------------------------------------------------
59 59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 61 -- RAM --------------------------------------------------------------------
62 62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 nSRAM_BE0 : OUT STD_LOGIC;
65 65 nSRAM_BE1 : OUT STD_LOGIC;
66 66 nSRAM_BE2 : OUT STD_LOGIC;
67 67 nSRAM_BE3 : OUT STD_LOGIC;
68 68 nSRAM_WE : OUT STD_LOGIC;
69 69 nSRAM_CE : OUT STD_LOGIC;
70 70 nSRAM_OE : OUT STD_LOGIC;
71 71 -- SPW --------------------------------------------------------------------
72 72 spw1_din : IN STD_LOGIC;
73 73 spw1_sin : IN STD_LOGIC;
74 74 spw1_dout : OUT STD_LOGIC;
75 75 spw1_sout : OUT STD_LOGIC;
76 76 spw2_din : IN STD_LOGIC;
77 77 spw2_sin : IN STD_LOGIC;
78 78 spw2_dout : OUT STD_LOGIC;
79 79 spw2_sout : OUT STD_LOGIC;
80 80 -- ADC --------------------------------------------------------------------
81 81 bias_fail_sw : OUT STD_LOGIC;
82 82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 83 ADC_smpclk : OUT STD_LOGIC;
84 84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 85 -- DAC --------------------------------------------------------------------
86 86 DAC_SDO : OUT STD_LOGIC;
87 87 DAC_SCK : OUT STD_LOGIC;
88 88 DAC_SYNC : OUT STD_LOGIC;
89 89 DAC_CAL_EN : OUT STD_LOGIC;
90 90 -- HK ---------------------------------------------------------------------
91 91 HK_smpclk : OUT STD_LOGIC;
92 92 ADC_OEB_bar_HK : OUT STD_LOGIC;
93 93 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
94 94 ---------------------------------------------------------------------------
95 95 TAG8 : OUT STD_LOGIC;
96 96 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
97 97 );
98 98
99 99 END LFR_em;
100 100
101 101
102 102 ARCHITECTURE beh OF LFR_em IS
103 103 SIGNAL clk_50_s : STD_LOGIC := '0';
104 104 SIGNAL clk_25 : STD_LOGIC := '0';
105 105 SIGNAL clk_24 : STD_LOGIC := '0';
106 106 -----------------------------------------------------------------------------
107 107 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
109 109
110 110 -- CONSTANTS
111 111 CONSTANT CFG_PADTECH : INTEGER := inferred;
112 112 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
113 113 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
114 114 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
115 115
116 116 SIGNAL apbi_ext : apb_slv_in_type;
117 117 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
118 118 SIGNAL ahbi_s_ext : ahb_slv_in_type;
119 119 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
120 120 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
121 121 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
122 122
123 123 -- Spacewire signals
124 124 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 125 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 126 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 127 SIGNAL spw_rxtxclk : STD_ULOGIC;
128 128 SIGNAL spw_rxclkn : STD_ULOGIC;
129 129 SIGNAL spw_clk : STD_LOGIC;
130 130 SIGNAL swni : grspw_in_type;
131 131 SIGNAL swno : grspw_out_type;
132 132
133 133 --GPIO
134 134 SIGNAL gpioi : gpio_in_type;
135 135 SIGNAL gpioo : gpio_out_type;
136 136
137 137 -- AD Converter ADS7886
138 138 SIGNAL sample : Samples14v(8 DOWNTO 0);
139 139 SIGNAL sample_s : Samples(8 DOWNTO 0);
140 140 SIGNAL sample_val : STD_LOGIC;
141 141 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
142 142
143 143 -----------------------------------------------------------------------------
144 144 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 145
146 146 -----------------------------------------------------------------------------
147 147 SIGNAL rstn : STD_LOGIC;
148 148
149 149 SIGNAL LFR_soft_rstn : STD_LOGIC;
150 150 SIGNAL LFR_rstn : STD_LOGIC;
151 151
152 152 SIGNAL ADC_smpclk_s : STD_LOGIC;
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
155 155
156 156 BEGIN -- beh
157 157
158 158 -----------------------------------------------------------------------------
159 159 -- CLK
160 160 -----------------------------------------------------------------------------
161 161 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
162 162
163 163 PROCESS(clk100MHz)
164 164 BEGIN
165 165 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
166 166 clk_50_s <= NOT clk_50_s;
167 167 END IF;
168 168 END PROCESS;
169 169
170 170 PROCESS(clk_50_s)
171 171 BEGIN
172 172 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
173 173 clk_25 <= NOT clk_25;
174 174 END IF;
175 175 END PROCESS;
176 176
177 177 PROCESS(clk49_152MHz)
178 178 BEGIN
179 179 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
180 180 clk_24 <= NOT clk_24;
181 181 END IF;
182 182 END PROCESS;
183 183
184 184 -----------------------------------------------------------------------------
185 185
186 186 PROCESS (clk_25, rstn)
187 187 BEGIN -- PROCESS
188 188 IF rstn = '0' THEN -- asynchronous reset (active low)
189 189 led(0) <= '0';
190 190 led(1) <= '0';
191 191 led(2) <= '0';
192 192 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
193 193 led(0) <= '0';
194 194 led(1) <= '1';
195 195 led(2) <= '1';
196 196 END IF;
197 197 END PROCESS;
198 198
199 199 --
200 200 leon3_soc_1 : leon3_soc
201 201 GENERIC MAP (
202 202 fabtech => apa3e,
203 203 memtech => apa3e,
204 204 padtech => inferred,
205 205 clktech => inferred,
206 206 disas => 0,
207 207 dbguart => 0,
208 208 pclow => 2,
209 209 clk_freq => 25000,
210 210 IS_RADHARD => 0,
211 211 NB_CPU => 1,
212 212 ENABLE_FPU => 1,
213 213 FPU_NETLIST => 0,
214 214 ENABLE_DSU => 1,
215 215 ENABLE_AHB_UART => 1,
216 216 ENABLE_APB_UART => 1,
217 217 ENABLE_IRQMP => 1,
218 218 ENABLE_GPT => 1,
219 219 NB_AHB_MASTER => NB_AHB_MASTER,
220 220 NB_AHB_SLAVE => NB_AHB_SLAVE,
221 221 NB_APB_SLAVE => NB_APB_SLAVE,
222 222 ADDRESS_SIZE => 20,
223 223 USES_IAP_MEMCTRLR => 0)
224 224 PORT MAP (
225 225 clk => clk_25,
226 226 reset => rstn,
227 227 errorn => OPEN,
228 228
229 229 ahbrxd => TAG1,
230 230 ahbtxd => TAG3,
231 231 urxd1 => TAG2,
232 232 utxd1 => TAG4,
233 233
234 234 address => address,
235 235 data => data,
236 236 nSRAM_BE0 => nSRAM_BE0,
237 237 nSRAM_BE1 => nSRAM_BE1,
238 238 nSRAM_BE2 => nSRAM_BE2,
239 239 nSRAM_BE3 => nSRAM_BE3,
240 240 nSRAM_WE => nSRAM_WE,
241 241 nSRAM_CE => nSRAM_CE_s,
242 242 nSRAM_OE => nSRAM_OE,
243 243 nSRAM_READY => '0',
244 244 SRAM_MBE => OPEN,
245 245
246 246 apbi_ext => apbi_ext,
247 247 apbo_ext => apbo_ext,
248 248 ahbi_s_ext => ahbi_s_ext,
249 249 ahbo_s_ext => ahbo_s_ext,
250 250 ahbi_m_ext => ahbi_m_ext,
251 251 ahbo_m_ext => ahbo_m_ext);
252 252
253 253
254 254 nSRAM_CE <= nSRAM_CE_s(0);
255 255
256 256 -------------------------------------------------------------------------------
257 257 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
258 258 -------------------------------------------------------------------------------
259 259 apb_lfr_management_1 : apb_lfr_management
260 260 GENERIC MAP (
261 261 tech => apa3e,
262 262 pindex => 6,
263 263 paddr => 6,
264 264 pmask => 16#fff#,
265 265 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
266 266 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
267 267 PORT MAP (
268 268 clk25MHz => clk_25,
269 269 clk24_576MHz => clk_24, -- 49.152MHz/2
270 270 resetn => rstn,
271 271 grspw_tick => swno.tickout,
272 272 apbi => apbi_ext,
273 273 apbo => apbo_ext(6),
274 274
275 275 HK_sample => sample_s(8),
276 276 HK_val => sample_val,
277 277 HK_sel => HK_SEL,
278 278
279 279 DAC_SDO => DAC_SDO,
280 280 DAC_SCK => DAC_SCK,
281 281 DAC_SYNC => DAC_SYNC,
282 282 DAC_CAL_EN => DAC_CAL_EN,
283 283
284 284 coarse_time => coarse_time,
285 285 fine_time => fine_time,
286 286 LFR_soft_rstn => LFR_soft_rstn
287 287 );
288 288
289 289 -----------------------------------------------------------------------
290 290 --- SpaceWire --------------------------------------------------------
291 291 -----------------------------------------------------------------------
292 292
293 293 -- SPW_EN <= '1';
294 294
295 295 spw_clk <= clk_50_s;
296 296 spw_rxtxclk <= spw_clk;
297 297 spw_rxclkn <= NOT spw_rxtxclk;
298 298
299 299 -- PADS for SPW1
300 300 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
301 301 PORT MAP (spw1_din, dtmp(0));
302 302 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
303 303 PORT MAP (spw1_sin, stmp(0));
304 304 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
305 305 PORT MAP (spw1_dout, swno.d(0));
306 306 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
307 307 PORT MAP (spw1_sout, swno.s(0));
308 308 -- PADS FOR SPW2
309 309 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
310 310 PORT MAP (spw2_din, dtmp(1));
311 311 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
312 312 PORT MAP (spw2_sin, stmp(1));
313 313 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
314 314 PORT MAP (spw2_dout, swno.d(1));
315 315 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
316 316 PORT MAP (spw2_sout, swno.s(1));
317 317
318 318 -- GRSPW PHY
319 319 --spw1_input: if CFG_SPW_GRSPW = 1 generate
320 320 spw_inputloop : FOR j IN 0 TO 1 GENERATE
321 321 spw_phy0 : grspw_phy
322 322 GENERIC MAP(
323 323 tech => apa3e,
324 324 rxclkbuftype => 1,
325 325 scantest => 0)
326 326 PORT MAP(
327 327 rxrst => swno.rxrst,
328 328 di => dtmp(j),
329 329 si => stmp(j),
330 330 rxclko => spw_rxclk(j),
331 331 do => swni.d(j),
332 332 ndo => swni.nd(j*5+4 DOWNTO j*5),
333 333 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
334 334 END GENERATE spw_inputloop;
335 335
336 336 -- SPW core
337 337 sw0 : grspwm GENERIC MAP(
338 338 tech => apa3e,
339 339 hindex => 1,
340 340 pindex => 5,
341 341 paddr => 5,
342 342 pirq => 11,
343 343 sysfreq => 25000, -- CPU_FREQ
344 344 rmap => 1,
345 345 rmapcrc => 1,
346 346 fifosize1 => 16,
347 347 fifosize2 => 16,
348 348 rxclkbuftype => 1,
349 349 rxunaligned => 0,
350 350 rmapbufs => 4,
351 351 ft => 0,
352 352 netlist => 0,
353 353 ports => 2,
354 354 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
355 355 memtech => apa3e,
356 356 destkey => 2,
357 357 spwcore => 1
358 358 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
359 359 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
360 360 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
361 361 )
362 362 PORT MAP(rstn, clk_25, spw_rxclk(0),
363 363 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
364 364 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
365 365 swni, swno);
366 366
367 367 swni.tickin <= '0';
368 368 swni.rmapen <= '1';
369 369 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
370 370 swni.tickinraw <= '0';
371 371 swni.timein <= (OTHERS => '0');
372 372 swni.dcrstval <= (OTHERS => '0');
373 373 swni.timerrstval <= (OTHERS => '0');
374 374
375 375 -------------------------------------------------------------------------------
376 376 -- LFR ------------------------------------------------------------------------
377 377 -------------------------------------------------------------------------------
378 378 LFR_rstn <= LFR_soft_rstn AND rstn;
379 379
380 380 lpp_lfr_1 : lpp_lfr
381 381 GENERIC MAP (
382 382 Mem_use => use_RAM,
383 383 nb_data_by_buffer_size => 32,
384 384 --nb_word_by_buffer_size => 30,
385 385 nb_snapshot_param_size => 32,
386 386 delta_vector_size => 32,
387 387 delta_vector_size_f0_2 => 7, -- log2(96)
388 388 pindex => 15,
389 389 paddr => 15,
390 390 pmask => 16#fff#,
391 391 pirq_ms => 6,
392 392 pirq_wfp => 14,
393 393 hindex => 2,
394 top_lfr_version => X"01013D") -- aa.bb.cc version
394 top_lfr_version => X"01013E") -- aa.bb.cc version
395 395 -- AA : BOARD NUMBER
396 396 -- 0 => MINI_LFR
397 397 -- 1 => EM
398 398 PORT MAP (
399 399 clk => clk_25,
400 400 rstn => LFR_rstn,
401 401 sample_B => sample_s(2 DOWNTO 0),
402 402 sample_E => sample_s(7 DOWNTO 3),
403 403 sample_val => sample_val,
404 404 apbi => apbi_ext,
405 405 apbo => apbo_ext(15),
406 406 ahbi => ahbi_m_ext,
407 407 ahbo => ahbo_m_ext(2),
408 408 coarse_time => coarse_time,
409 409 fine_time => fine_time,
410 410 data_shaping_BW => bias_fail_sw,
411 411 debug_vector => OPEN,
412 412 debug_vector_ms => OPEN); --,
413 413 --observation_vector_0 => OPEN,
414 414 --observation_vector_1 => OPEN,
415 415 --observation_reg => observation_reg);
416 416
417 417
418 418 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
419 419 sample_s(I) <= sample(I) & '0' & '0';
420 420 END GENERATE all_sample;
421 421 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
422 422
423 423 -----------------------------------------------------------------------------
424 424 --
425 425 -----------------------------------------------------------------------------
426 426 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
427 427 GENERIC MAP (
428 428 ChanelCount => 9,
429 429 ncycle_cnv_high => 13,
430 430 ncycle_cnv => 25,
431 431 FILTER_ENABLED => 16#FF#)
432 432 PORT MAP (
433 433 cnv_clk => clk_24,
434 434 cnv_rstn => rstn,
435 435 cnv => ADC_smpclk_s,
436 436 clk => clk_25,
437 437 rstn => rstn,
438 438 ADC_data => ADC_data,
439 439 ADC_nOE => ADC_OEB_bar_CH_s,
440 440 sample => sample,
441 441 sample_val => sample_val);
442 442
443 443 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
444 444
445 445 ADC_smpclk <= ADC_smpclk_s;
446 446 HK_smpclk <= ADC_smpclk_s;
447 447
448 448 TAG8 <= ADC_smpclk_s;
449 449
450 450 -----------------------------------------------------------------------------
451 451 -- HK
452 452 -----------------------------------------------------------------------------
453 453 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
454 454
455 455 END beh;
Show file before | Show file after | Hide comments
@@ -1,105 +1,105
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2015, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@member.fsf.org
21 21 ------------------------------------------------------------------------------
22 22
23 23
24 24 LIBRARY IEEE;
25 25 USE IEEE.STD_LOGIC_1164.ALL;
26 26 USE IEEE.NUMERIC_STD.ALL;
27 27
28 28 ENTITY SPI_DAC_DRIVER IS
29 29 GENERIC(
30 30 datawidth : INTEGER := 16;
31 31 MSBFIRST : INTEGER := 1
32 32 );
33 33 PORT (
34 34 clk : IN STD_LOGIC;
35 35 rstn : IN STD_LOGIC;
36 36 DATA : IN STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
37 37 SMP_CLK : IN STD_LOGIC;
38 38 SYNC : OUT STD_LOGIC;
39 39 DOUT : OUT STD_LOGIC;
40 40 SCLK : OUT STD_LOGIC
41 41 );
42 42 END ENTITY SPI_DAC_DRIVER;
43 43
44 44 ARCHITECTURE behav OF SPI_DAC_DRIVER IS
45 45 SIGNAL SHIFTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
46 46 SIGNAL INPUTREG : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0) := (OTHERS => '0');
47 47 SIGNAL SMP_CLK_R : STD_LOGIC := '0';
48 48 SIGNAL shiftcnt : INTEGER := 0;
49 49 SIGNAL shifting : STD_LOGIC := '0';
50 50 SIGNAL shifting_R : STD_LOGIC := '0';
51 51 BEGIN
52 52
53 53 DOUT <= SHIFTREG(datawidth-1);
54 54
55 55 MSB : IF MSBFIRST = 1 GENERATE
56 56 INPUTREG <= DATA;
57 57 END GENERATE;
58 58
59 59 LSB : IF MSBFIRST = 0 GENERATE
60 60 INPUTREG(datawidth-1 DOWNTO 0) <= DATA(0 TO datawidth-1);
61 61 END GENERATE;
62 62
63 63 SCLK <= clk;
64 64
65 65 PROCESS(clk, rstn)
66 66 BEGIN
67 67 IF rstn = '0' then
68 shifting_R <= '0';
68 -- shifting_R <= '0';
69 69 SMP_CLK_R <= '0';
70 70 ELSIF clk'EVENT AND clk = '1' then
71 71 SMP_CLK_R <= SMP_CLK;
72 shifting_R <= shifting;
72 -- shifting_R <= shifting;
73 73 END IF;
74 74 END PROCESS;
75 75
76 76 PROCESS(clk, rstn)
77 77 BEGIN
78 78 IF rstn = '0' then
79 79 shifting <= '0';
80 80 SHIFTREG <= (OTHERS => '0');
81 81 SYNC <= '0';
82 82 shiftcnt <= 0;
83 83 ELSIF clk'EVENT AND clk = '1' then
84 84 IF(SMP_CLK = '1' and SMP_CLK_R = '0') THEN
85 85 SYNC <= '1';
86 86 shifting <= '1';
87 87 ELSE
88 88 SYNC <= '0';
89 89 IF shiftcnt = datawidth-1 THEN
90 90 shifting <= '0';
91 91 END IF;
92 92 END IF;
93 93 IF shifting = '1' then
94 94 shiftcnt <= shiftcnt + 1;
95 95 SHIFTREG <= SHIFTREG (datawidth-2 DOWNTO 0) & '0';
96 96 ELSE
97 97 SHIFTREG <= INPUTREG;
98 98 shiftcnt <= 0;
99 99 END IF;
100 100 END IF;
101 101 END PROCESS;
102 102
103 103 END ARCHITECTURE behav;
104 104
105 105
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