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1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 11:17:05 07/02/2012
5 -- Create Date: 11:17:05 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: apb_lfr_time_management - Behavioral
7 -- Module Name: apb_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.general_purpose.ALL;
30 USE lpp.lpp_lfr_management.ALL;
30 USE lpp.lpp_lfr_management.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 USE lpp.lpp_cna.ALL;
32 USE lpp.lpp_cna.ALL;
33 LIBRARY techmap;
33 LIBRARY techmap;
34 USE techmap.gencomp.ALL;
34 USE techmap.gencomp.ALL;
35
35
36
36
37 ENTITY apb_lfr_management IS
37 ENTITY apb_lfr_management IS
38
38
39 GENERIC(
39 GENERIC(
40 tech : INTEGER := 0;
40 tech : INTEGER := 0;
41 pindex : INTEGER := 0; --! APB slave index
41 pindex : INTEGER := 0; --! APB slave index
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 FIRST_DIVISION : INTEGER := 374;
44 FIRST_DIVISION : INTEGER := 374;
45 NB_SECOND_DESYNC : INTEGER := 60
45 NB_SECOND_DESYNC : INTEGER := 60
46 );
46 );
47
47
48 PORT (
48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
49 clk25MHz : IN STD_LOGIC; --! Clock
50 clk24_576MHz : IN STD_LOGIC; --! secondary clock
50 clk24_576MHz : IN STD_LOGIC; --! secondary clock
51 resetn : IN STD_LOGIC; --! Reset
51 resetn : IN STD_LOGIC; --! Reset
52
52
53 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
53 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54
54
55 apbi : IN apb_slv_in_type; --! APB slave input signals
55 apbi : IN apb_slv_in_type; --! APB slave input signals
56 apbo : OUT apb_slv_out_type; --! APB slave output signals
56 apbo : OUT apb_slv_out_type; --! APB slave output signals
57 ---------------------------------------------------------------------------
57 ---------------------------------------------------------------------------
58 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
58 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
59 HK_val : IN STD_LOGIC;
59 HK_val : IN STD_LOGIC;
60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 DAC_SDO : OUT STD_LOGIC;
62 DAC_SDO : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
63 DAC_SCK : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
64 DAC_SYNC : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
65 DAC_CAL_EN : OUT STD_LOGIC;
66 ---------------------------------------------------------------------------
66 ---------------------------------------------------------------------------
67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
67 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
68 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
69 ---------------------------------------------------------------------------
69 ---------------------------------------------------------------------------
70 LFR_soft_rstn : OUT STD_LOGIC
70 LFR_soft_rstn : OUT STD_LOGIC
71 );
71 );
72
72
73 END apb_lfr_management;
73 END apb_lfr_management;
74
74
75 ARCHITECTURE Behavioral OF apb_lfr_management IS
75 ARCHITECTURE Behavioral OF apb_lfr_management IS
76
76
77 CONSTANT REVISION : INTEGER := 1;
77 CONSTANT REVISION : INTEGER := 1;
78 CONSTANT pconfig : apb_config_type := (
78 CONSTANT pconfig : apb_config_type := (
79 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
79 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
80 1 => apb_iobar(paddr, pmask)
80 1 => apb_iobar(paddr, pmask)
81 );
81 );
82
82
83 TYPE apb_lfr_time_management_Reg IS RECORD
83 TYPE apb_lfr_time_management_Reg IS RECORD
84 ctrl : STD_LOGIC;
84 ctrl : STD_LOGIC;
85 soft_reset : STD_LOGIC;
85 soft_reset : STD_LOGIC;
86 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
86 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
87 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
88 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 LFR_soft_reset : STD_LOGIC;
89 LFR_soft_reset : STD_LOGIC;
90 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
90 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 END RECORD;
93 END RECORD;
94 SIGNAL r : apb_lfr_time_management_Reg;
94 SIGNAL r : apb_lfr_time_management_Reg;
95
95
96 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL force_tick : STD_LOGIC;
97 SIGNAL force_tick : STD_LOGIC;
98 SIGNAL previous_force_tick : STD_LOGIC;
98 SIGNAL previous_force_tick : STD_LOGIC;
99 SIGNAL soft_tick : STD_LOGIC;
99 SIGNAL soft_tick : STD_LOGIC;
100
100
101 SIGNAL coarsetime_reg_updated : STD_LOGIC;
101 SIGNAL coarsetime_reg_updated : STD_LOGIC;
102 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
102 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
103
103
104 --SIGNAL coarse_time_new : STD_LOGIC;
104 --SIGNAL coarse_time_new : STD_LOGIC;
105 SIGNAL coarse_time_new_49 : STD_LOGIC;
105 SIGNAL coarse_time_new_49 : STD_LOGIC;
106 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
106 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
108
108
109 --SIGNAL fine_time_new : STD_LOGIC;
109 --SIGNAL fine_time_new : STD_LOGIC;
110 --SIGNAL fine_time_new_temp : STD_LOGIC;
110 --SIGNAL fine_time_new_temp : STD_LOGIC;
111 SIGNAL fine_time_new_49 : STD_LOGIC;
111 SIGNAL fine_time_new_49 : STD_LOGIC;
112 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
112 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 SIGNAL tick : STD_LOGIC;
114 SIGNAL tick : STD_LOGIC;
115 SIGNAL new_timecode : STD_LOGIC;
115 SIGNAL new_timecode : STD_LOGIC;
116 SIGNAL new_coarsetime : STD_LOGIC;
116 SIGNAL new_coarsetime : STD_LOGIC;
117
117
118 SIGNAL time_new_49 : STD_LOGIC;
118 SIGNAL time_new_49 : STD_LOGIC;
119 SIGNAL time_new : STD_LOGIC;
119 SIGNAL time_new : STD_LOGIC;
120
120
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 SIGNAL force_reset : STD_LOGIC;
122 SIGNAL force_reset : STD_LOGIC;
123 SIGNAL previous_force_reset : STD_LOGIC;
123 SIGNAL previous_force_reset : STD_LOGIC;
124 SIGNAL soft_reset : STD_LOGIC;
124 SIGNAL soft_reset : STD_LOGIC;
125 SIGNAL soft_reset_sync : STD_LOGIC;
125 SIGNAL soft_reset_sync : STD_LOGIC;
126 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128
128
129 SIGNAL previous_fine_time_bit : STD_LOGIC;
129 SIGNAL previous_fine_time_bit : STD_LOGIC;
130
130
131 SIGNAL rstn_LFR_TM : STD_LOGIC;
131 SIGNAL rstn_LFR_TM : STD_LOGIC;
132
132
133 -----------------------------------------------------------------------------
133 -----------------------------------------------------------------------------
134 -- DAC
134 -- DAC
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136 CONSTANT PRESZ : INTEGER := 8;
136 CONSTANT PRESZ : INTEGER := 8;
137 CONSTANT CPTSZ : INTEGER := 16;
137 CONSTANT CPTSZ : INTEGER := 16;
138 CONSTANT datawidth : INTEGER := 18;
138 CONSTANT datawidth : INTEGER := 18;
139 CONSTANT dacresolution : INTEGER := 12;
139 CONSTANT dacresolution : INTEGER := 12;
140 CONSTANT abits : INTEGER := 8;
140 CONSTANT abits : INTEGER := 8;
141
141
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
142 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
143 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 SIGNAL Reload : STD_LOGIC;
144 SIGNAL Reload : STD_LOGIC;
145 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
145 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 SIGNAL WEN : STD_LOGIC;
146 SIGNAL WEN : STD_LOGIC;
147 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
147 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
148 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 SIGNAL INTERLEAVED : STD_LOGIC;
150 SIGNAL INTERLEAVED : STD_LOGIC;
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
152 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153
153
154 SIGNAL HK_debug_mode : STD_LOGIC;
155 SIGNAL HK_sel_debug : STD_LOGIC_VECTOR(1 DOWNTO 0);
156
157 BEGIN
154 BEGIN
158
155
159 LFR_soft_rstn <= NOT r.LFR_soft_reset;
156 LFR_soft_rstn <= NOT r.LFR_soft_reset;
160
157
161 PROCESS(resetn, clk25MHz)
158 PROCESS(resetn, clk25MHz)
162 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
159 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
163 BEGIN
160 BEGIN
164
161
165 IF resetn = '0' THEN
162 IF resetn = '0' THEN
166 Rdata <= (OTHERS => '0');
163 Rdata <= (OTHERS => '0');
167 r.coarse_time_load <= (OTHERS => '0');
164 r.coarse_time_load <= (OTHERS => '0');
168 r.soft_reset <= '0';
165 r.soft_reset <= '0';
169 r.ctrl <= '0';
166 r.ctrl <= '0';
170 r.LFR_soft_reset <= '1';
167 r.LFR_soft_reset <= '1';
171
168
172 force_tick <= '0';
169 force_tick <= '0';
173 previous_force_tick <= '0';
170 previous_force_tick <= '0';
174 soft_tick <= '0';
171 soft_tick <= '0';
175
172
176 coarsetime_reg_updated <= '0';
173 coarsetime_reg_updated <= '0';
177 --DAC
174 --DAC
178 pre <= (OTHERS => '1');
175 pre <= (OTHERS => '1');
179 N <= (OTHERS => '1');
176 N <= (OTHERS => '1');
180 Reload <= '1';
177 Reload <= '1';
181 DATA_IN <= (OTHERS => '0');
178 DATA_IN <= (OTHERS => '0');
182 WEN <= '1';
179 WEN <= '1';
183 LOAD_ADDRESSN <= '1';
180 LOAD_ADDRESSN <= '1';
184 ADDRESS_IN <= (OTHERS => '1');
181 ADDRESS_IN <= (OTHERS => '1');
185 INTERLEAVED <= '0';
182 INTERLEAVED <= '0';
186 DAC_CFG <= (OTHERS => '0');
183 DAC_CFG <= (OTHERS => '0');
187 --
184 --
188 DAC_CAL_EN_s <= '0';
185 DAC_CAL_EN_s <= '0';
189 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
186 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
190 coarsetime_reg_updated <= '0';
187 coarsetime_reg_updated <= '0';
191
188
192 force_tick <= r.ctrl;
189 force_tick <= r.ctrl;
193 previous_force_tick <= force_tick;
190 previous_force_tick <= force_tick;
194 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
191 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
195 soft_tick <= '1';
192 soft_tick <= '1';
196 ELSE
193 ELSE
197 soft_tick <= '0';
194 soft_tick <= '0';
198 END IF;
195 END IF;
199
196
200 force_reset <= r.soft_reset;
197 force_reset <= r.soft_reset;
201 previous_force_reset <= force_reset;
198 previous_force_reset <= force_reset;
202 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
199 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
203 soft_reset <= '1';
200 soft_reset <= '1';
204 ELSE
201 ELSE
205 soft_reset <= '0';
202 soft_reset <= '0';
206 END IF;
203 END IF;
207
204
208 paddr := "000000";
205 paddr := "000000";
209 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
206 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
210 Rdata <= (OTHERS => '0');
207 Rdata <= (OTHERS => '0');
211
208
212 LOAD_ADDRESSN <= '1';
209 LOAD_ADDRESSN <= '1';
213 WEN <= '1';
210 WEN <= '1';
214
211
215 IF apbi.psel(pindex) = '1' THEN
212 IF apbi.psel(pindex) = '1' THEN
216 --APB READ OP
213 --APB READ OP
217 CASE paddr(7 DOWNTO 2) IS
214 CASE paddr(7 DOWNTO 2) IS
218 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
215 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
219 Rdata(0) <= r.ctrl;
216 Rdata(0) <= r.ctrl;
220 Rdata(1) <= r.soft_reset;
217 Rdata(1) <= r.soft_reset;
221 Rdata(2) <= r.LFR_soft_reset;
218 Rdata(2) <= r.LFR_soft_reset;
222 Rdata(3) <= HK_debug_mode;
219 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
223 Rdata(5 DOWNTO 4) <= HK_sel_debug;
224 Rdata(31 DOWNTO 6) <= (OTHERS => '0');
225 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
220 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
226 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
221 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
227 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
222 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
228 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
223 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
229 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
224 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
230 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
225 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
231 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
226 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
232 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
227 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
233 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
228 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
234 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
229 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
235 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
230 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
236 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
231 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
237 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
232 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
238 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
233 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
239 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
234 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
240 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
235 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
241 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
236 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
242 Rdata(3 DOWNTO 0) <= DAC_CFG;
237 Rdata(3 DOWNTO 0) <= DAC_CFG;
243 Rdata(4) <= Reload;
238 Rdata(4) <= Reload;
244 Rdata(5) <= INTERLEAVED;
239 Rdata(5) <= INTERLEAVED;
245 Rdata(6) <= DAC_CAL_EN_s;
240 Rdata(6) <= DAC_CAL_EN_s;
246 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
241 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
247 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
242 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
248 Rdata(PRESZ-1 DOWNTO 0) <= pre;
243 Rdata(PRESZ-1 DOWNTO 0) <= pre;
249 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
244 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
250 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
245 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
251 Rdata(CPTSZ-1 DOWNTO 0) <= N;
246 Rdata(CPTSZ-1 DOWNTO 0) <= N;
252 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
247 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
253 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
248 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
254 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
249 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
255 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
250 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
256 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
251 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
257 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
252 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
258 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
253 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
259 WHEN OTHERS =>
254 WHEN OTHERS =>
260 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
255 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
261 END CASE;
256 END CASE;
262
257
263 --APB Write OP
258 --APB Write OP
264 IF (apbi.pwrite AND apbi.penable) = '1' THEN
259 IF (apbi.pwrite AND apbi.penable) = '1' THEN
265 CASE paddr(7 DOWNTO 2) IS
260 CASE paddr(7 DOWNTO 2) IS
266 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
261 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
267 r.ctrl <= apbi.pwdata(0);
262 r.ctrl <= apbi.pwdata(0);
268 r.soft_reset <= apbi.pwdata(1);
263 r.soft_reset <= apbi.pwdata(1);
269 r.LFR_soft_reset <= apbi.pwdata(2);
264 r.LFR_soft_reset <= apbi.pwdata(2);
270 HK_debug_mode <= apbi.pwdata(3);
271 HK_sel_debug <= apbi.pwdata(5 DOWNTO 4);
272 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
265 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
273 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
266 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
274 coarsetime_reg_updated <= '1';
267 coarsetime_reg_updated <= '1';
275 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
268 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
276 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
269 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
277 Reload <= apbi.pwdata(4);
270 Reload <= apbi.pwdata(4);
278 INTERLEAVED <= apbi.pwdata(5);
271 INTERLEAVED <= apbi.pwdata(5);
279 DAC_CAL_EN_s <= apbi.pwdata(6);
272 DAC_CAL_EN_s <= apbi.pwdata(6);
280 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
273 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
281 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
274 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
282 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
275 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
283 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
276 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
284 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
277 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
285 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
278 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
286 LOAD_ADDRESSN <= '0';
279 LOAD_ADDRESSN <= '0';
287 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
280 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
288 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
281 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
289 WEN <= '0';
282 WEN <= '0';
290
283
291 WHEN OTHERS =>
284 WHEN OTHERS =>
292 NULL;
285 NULL;
293 END CASE;
286 END CASE;
294 ELSE
287 ELSE
295 IF r.ctrl = '1' THEN
288 IF r.ctrl = '1' THEN
296 r.ctrl <= '0';
289 r.ctrl <= '0';
297 END IF;
290 END IF;
298 IF r.soft_reset = '1' THEN
291 IF r.soft_reset = '1' THEN
299 r.soft_reset <= '0';
292 r.soft_reset <= '0';
300 END IF;
293 END IF;
301 END IF;
294 END IF;
302
295
303 END IF;
296 END IF;
304
297
305 END IF;
298 END IF;
306 END PROCESS;
299 END PROCESS;
307
300
308 apbo.pirq <= (OTHERS => '0');
301 apbo.pirq <= (OTHERS => '0');
309 apbo.prdata <= Rdata;
302 apbo.prdata <= Rdata;
310 apbo.pconfig <= pconfig;
303 apbo.pconfig <= pconfig;
311 apbo.pindex <= pindex;
304 apbo.pindex <= pindex;
312
305
313 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
314 -- IN
307 -- IN
315 coarse_time <= r.coarse_time;
308 coarse_time <= r.coarse_time;
316 fine_time <= r.fine_time;
309 fine_time <= r.fine_time;
317 coarsetime_reg <= r.coarse_time_load;
310 coarsetime_reg <= r.coarse_time_load;
318 -----------------------------------------------------------------------------
311 -----------------------------------------------------------------------------
319
312
320 -----------------------------------------------------------------------------
313 -----------------------------------------------------------------------------
321 -- OUT
314 -- OUT
322 r.coarse_time <= coarse_time_s;
315 r.coarse_time <= coarse_time_s;
323 r.fine_time <= fine_time_s;
316 r.fine_time <= fine_time_s;
324 -----------------------------------------------------------------------------
317 -----------------------------------------------------------------------------
325
318
326 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
327 tick <= grspw_tick OR soft_tick;
320 tick <= grspw_tick OR soft_tick;
328
321
329 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
322 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
330 GENERIC MAP (
323 GENERIC MAP (
331 NB_FF_OF_SYNC => 2)
324 NB_FF_OF_SYNC => 2)
332 PORT MAP (
325 PORT MAP (
333 clk_in => clk25MHz,
326 clk_in => clk25MHz,
334 clk_out => clk24_576MHz,
327 clk_out => clk24_576MHz,
335 rstn => resetn,
328 rstn => resetn,
336 sin => tick,
329 sin => tick,
337 sout => new_timecode);
330 sout => new_timecode);
338
331
339 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
332 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
340 GENERIC MAP (
333 GENERIC MAP (
341 NB_FF_OF_SYNC => 2)
334 NB_FF_OF_SYNC => 2)
342 PORT MAP (
335 PORT MAP (
343 clk_in => clk25MHz,
336 clk_in => clk25MHz,
344 clk_out => clk24_576MHz,
337 clk_out => clk24_576MHz,
345 rstn => resetn,
338 rstn => resetn,
346 sin => coarsetime_reg_updated,
339 sin => coarsetime_reg_updated,
347 sout => new_coarsetime);
340 sout => new_coarsetime);
348
341
349 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
342 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
350 GENERIC MAP (
343 GENERIC MAP (
351 NB_FF_OF_SYNC => 2)
344 NB_FF_OF_SYNC => 2)
352 PORT MAP (
345 PORT MAP (
353 clk_in => clk25MHz,
346 clk_in => clk25MHz,
354 clk_out => clk24_576MHz,
347 clk_out => clk24_576MHz,
355 rstn => resetn,
348 rstn => resetn,
356 sin => soft_reset,
349 sin => soft_reset,
357 sout => soft_reset_sync);
350 sout => soft_reset_sync);
358
351
359 -----------------------------------------------------------------------------
352 -----------------------------------------------------------------------------
360 --SYNC_FF_1 : SYNC_FF
353 --SYNC_FF_1 : SYNC_FF
361 -- GENERIC MAP (
354 -- GENERIC MAP (
362 -- NB_FF_OF_SYNC => 2)
355 -- NB_FF_OF_SYNC => 2)
363 -- PORT MAP (
356 -- PORT MAP (
364 -- clk => clk25MHz,
357 -- clk => clk25MHz,
365 -- rstn => resetn,
358 -- rstn => resetn,
366 -- A => fine_time_new_49,
359 -- A => fine_time_new_49,
367 -- A_sync => fine_time_new_temp);
360 -- A_sync => fine_time_new_temp);
368
361
369 --lpp_front_detection_1 : lpp_front_detection
362 --lpp_front_detection_1 : lpp_front_detection
370 -- PORT MAP (
363 -- PORT MAP (
371 -- clk => clk25MHz,
364 -- clk => clk25MHz,
372 -- rstn => resetn,
365 -- rstn => resetn,
373 -- sin => fine_time_new_temp,
366 -- sin => fine_time_new_temp,
374 -- sout => fine_time_new);
367 -- sout => fine_time_new);
375
368
376 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
369 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
377 -- GENERIC MAP (
370 -- GENERIC MAP (
378 -- NB_FF_OF_SYNC => 2)
371 -- NB_FF_OF_SYNC => 2)
379 -- PORT MAP (
372 -- PORT MAP (
380 -- clk_in => clk24_576MHz,
373 -- clk_in => clk24_576MHz,
381 -- clk_out => clk25MHz,
374 -- clk_out => clk25MHz,
382 -- rstn => resetn,
375 -- rstn => resetn,
383 -- sin => coarse_time_new_49,
376 -- sin => coarse_time_new_49,
384 -- sout => coarse_time_new);
377 -- sout => coarse_time_new);
385
378
386 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
379 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
387
380
388 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
381 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
389 GENERIC MAP (
382 GENERIC MAP (
390 NB_FF_OF_SYNC => 2)
383 NB_FF_OF_SYNC => 2)
391 PORT MAP (
384 PORT MAP (
392 clk_in => clk24_576MHz,
385 clk_in => clk24_576MHz,
393 clk_out => clk25MHz,
386 clk_out => clk25MHz,
394 rstn => resetn,
387 rstn => resetn,
395 sin => time_new_49,
388 sin => time_new_49,
396 sout => time_new);
389 sout => time_new);
397
390
398
391
399
392
400 PROCESS (clk25MHz, resetn)
393 PROCESS (clk25MHz, resetn)
401 BEGIN -- PROCESS
394 BEGIN -- PROCESS
402 IF resetn = '0' THEN -- asynchronous reset (active low)
395 IF resetn = '0' THEN -- asynchronous reset (active low)
403 fine_time_s <= (OTHERS => '0');
396 fine_time_s <= (OTHERS => '0');
404 coarse_time_s <= (OTHERS => '0');
397 coarse_time_s <= (OTHERS => '0');
405 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
398 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
406 IF time_new = '1' THEN
399 IF time_new = '1' THEN
407 fine_time_s <= fine_time_49;
400 fine_time_s <= fine_time_49;
408 coarse_time_s <= coarse_time_49;
401 coarse_time_s <= coarse_time_49;
409 END IF;
402 END IF;
410 END IF;
403 END IF;
411 END PROCESS;
404 END PROCESS;
412
405
413
406
414 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
407 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
415 '0' WHEN soft_reset_sync = '1' ELSE
408 '0' WHEN soft_reset_sync = '1' ELSE
416 '1';
409 '1';
417
410
418
411
419 -----------------------------------------------------------------------------
412 -----------------------------------------------------------------------------
420 -- LFR_TIME_MANAGMENT
413 -- LFR_TIME_MANAGMENT
421 -----------------------------------------------------------------------------
414 -----------------------------------------------------------------------------
422 lfr_time_management_1 : lfr_time_management
415 lfr_time_management_1 : lfr_time_management
423 GENERIC MAP (
416 GENERIC MAP (
424 FIRST_DIVISION => FIRST_DIVISION,
417 FIRST_DIVISION => FIRST_DIVISION,
425 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
418 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
426 PORT MAP (
419 PORT MAP (
427 clk => clk24_576MHz,
420 clk => clk24_576MHz,
428 rstn => rstn_LFR_TM,
421 rstn => rstn_LFR_TM,
429
422
430 tick => new_timecode,
423 tick => new_timecode,
431 new_coarsetime => new_coarsetime,
424 new_coarsetime => new_coarsetime,
432 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
425 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
433
426
434 fine_time => fine_time_49,
427 fine_time => fine_time_49,
435 fine_time_new => fine_time_new_49,
428 fine_time_new => fine_time_new_49,
436 coarse_time => coarse_time_49,
429 coarse_time => coarse_time_49,
437 coarse_time_new => coarse_time_new_49);
430 coarse_time_new => coarse_time_new_49);
438
431
439 -----------------------------------------------------------------------------
432 -----------------------------------------------------------------------------
440 -- HK
433 -- HK
441 -----------------------------------------------------------------------------
434 -----------------------------------------------------------------------------
442
435
443 PROCESS (clk25MHz, resetn)
436 PROCESS (clk25MHz, resetn)
444 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
437 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
445 -- for each HK, the update frequency is freq/3
438 -- for each HK, the update frequency is freq/3
446 --
439 --
447 -- for 14, the update frequency is
440 -- for 14, the update frequency is
448 -- 4Hz and update for each
441 -- 4Hz and update for each
449 -- HK is 1.33Hz
442 -- HK is 1.33Hz
450 BEGIN -- PROCESS
443 BEGIN -- PROCESS
451 IF resetn = '0' THEN -- asynchronous reset (active low)
444 IF resetn = '0' THEN -- asynchronous reset (active low)
452
445
453 r.HK_temp_0 <= (OTHERS => '0');
446 r.HK_temp_0 <= (OTHERS => '0');
454 r.HK_temp_1 <= (OTHERS => '0');
447 r.HK_temp_1 <= (OTHERS => '0');
455 r.HK_temp_2 <= (OTHERS => '0');
448 r.HK_temp_2 <= (OTHERS => '0');
456
449
457 HK_sel_s <= "00";
450 HK_sel_s <= "00";
458
451
459 previous_fine_time_bit <= '0';
452 previous_fine_time_bit <= '0';
460
453
461 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
454 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
462
455
463 IF HK_val = '1' THEN
456 IF HK_val = '1' THEN
464 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
457 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
465 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
458 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
466 CASE HK_sel_s IS
459 CASE HK_sel_s IS
467 WHEN "00" =>
460 WHEN "00" =>
468 r.HK_temp_0 <= HK_sample;
461 r.HK_temp_0 <= HK_sample;
469 IF HK_debug_mode = '1' THEN
470 HK_sel_s <= HK_sel_debug;
471 ELSE
472 HK_sel_s <= "01";
462 HK_sel_s <= "01";
473 END IF;
474 WHEN "01" =>
463 WHEN "01" =>
475 r.HK_temp_1 <= HK_sample;
464 r.HK_temp_1 <= HK_sample;
476 IF HK_debug_mode = '1' THEN
477 HK_sel_s <= HK_sel_debug;
478 ELSE
479 HK_sel_s <= "10";
465 HK_sel_s <= "10";
480 END IF;
481 WHEN "10" =>
466 WHEN "10" =>
482 r.HK_temp_2 <= HK_sample;
467 r.HK_temp_2 <= HK_sample;
483 IF HK_debug_mode = '1' THEN
484 HK_sel_s <= HK_sel_debug;
485 ELSE
486 HK_sel_s <= "00";
468 HK_sel_s <= "00";
487 END IF;
488 WHEN OTHERS => NULL;
469 WHEN OTHERS => NULL;
489 END CASE;
470 END CASE;
490 END IF;
471 END IF;
491 END IF;
472 END IF;
492
473
493 END IF;
474 END IF;
494 END PROCESS;
475 END PROCESS;
495
476
496 HK_sel <= HK_sel_s;
477 HK_sel <= HK_sel_s;
497
478
498 -----------------------------------------------------------------------------
479 -----------------------------------------------------------------------------
499 -- DAC
480 -- DAC
500 -----------------------------------------------------------------------------
481 -----------------------------------------------------------------------------
501 cal : lfr_cal_driver
482 cal : lfr_cal_driver
502 GENERIC MAP(
483 GENERIC MAP(
503 tech => tech,
484 tech => tech,
504 PRESZ => PRESZ,
485 PRESZ => PRESZ,
505 CPTSZ => CPTSZ,
486 CPTSZ => CPTSZ,
506 datawidth => datawidth,
487 datawidth => datawidth,
507 abits => abits
488 abits => abits
508 )
489 )
509 PORT MAP(
490 PORT MAP(
510 clk => clk25MHz,
491 clk => clk25MHz,
511 rstn => resetn,
492 rstn => resetn,
512
493
513 pre => pre,
494 pre => pre,
514 N => N,
495 N => N,
515 Reload => Reload,
496 Reload => Reload,
516 DATA_IN => DATA_IN,
497 DATA_IN => DATA_IN,
517 WEN => WEN,
498 WEN => WEN,
518 LOAD_ADDRESSN => LOAD_ADDRESSN,
499 LOAD_ADDRESSN => LOAD_ADDRESSN,
519 ADDRESS_IN => ADDRESS_IN,
500 ADDRESS_IN => ADDRESS_IN,
520 ADDRESS_OUT => ADDRESS_OUT,
501 ADDRESS_OUT => ADDRESS_OUT,
521 INTERLEAVED => INTERLEAVED,
502 INTERLEAVED => INTERLEAVED,
522 DAC_CFG => DAC_CFG,
503 DAC_CFG => DAC_CFG,
523
504
524 SYNC => DAC_SYNC,
505 SYNC => DAC_SYNC,
525 DOUT => DAC_SDO,
506 DOUT => DAC_SDO,
526 SCLK => DAC_SCK,
507 SCLK => DAC_SCK,
527 SMPCLK => OPEN --DAC_SMPCLK
508 SMPCLK => OPEN --DAC_SMPCLK
528 );
509 );
529
510
530 DAC_CAL_EN <= DAC_CAL_EN_s;
511 DAC_CAL_EN <= DAC_CAL_EN_s;
531 END Behavioral;
512 END Behavioral;
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