HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r619:b515d4c55e1d

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r619:b515d4c55e1d simu_with_Leon3

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designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +3 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.sim.ALL;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             USE lpp.lpp_bootloader_pkg.ALL;
             --library proasic3l;
             --use proasic3l.all;
             ENTITY LFR_EQM IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 USE_BOOTLOADER         : INTEGER := 0;
                 USE_ADCDRIVER          : INTEGER := 1;
                 tech                   : INTEGER := apa3e;
                 tech_leon              : INTEGER := apa3e;
                 DEBUG_FORCE_DATA_DMA   : INTEGER := 0;
                 USE_DEBUG_VECTOR       : INTEGER := 0
                 );
               PORT (
                 clk50MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 TAG          : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
                 -- TAG --------------------------------------------------------------------
                 --TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 --TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 --TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 --TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(18 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_MBE      : INOUT   STD_LOGIC;   -- new
                 nSRAM_E1       : OUT   STD_LOGIC;   -- new
                 nSRAM_E2       : OUT   STD_LOGIC;   -- new
             --    nSRAM_SCRUB    : OUT   STD_LOGIC;   -- new
                 nSRAM_W        : OUT   STD_LOGIC;   -- new
                 nSRAM_G        : OUT   STD_LOGIC;   -- new
                 nSRAM_BUSY     : IN   STD_LOGIC;   -- new
                 -- SPW --------------------------------------------------------------------
                 spw1_en        : OUT   STD_LOGIC;   -- new
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_en        : OUT   STD_LOGIC;   -- new
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- DAC --------------------------------------------------------------------
                 DAC_SDO    : OUT STD_LOGIC;
                 DAC_SCK    : OUT STD_LOGIC;
                 DAC_SYNC   : OUT STD_LOGIC;
                 DAC_CAL_EN : OUT STD_LOGIC;
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0)--;
                 ---------------------------------------------------------------------------
             --    TAG8           : OUT   STD_LOGIC
                 );
             END LFR_EQM;
             ARCHITECTURE beh OF LFR_EQM IS
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn_25 : STD_LOGIC;
               SIGNAL rstn_24 : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL clk50MHz_int : STD_LOGIC := '0';
               SIGNAL clk_25_int      : STD_LOGIC := '0';
               component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
               SIGNAL rstn_50 : STD_LOGIC;
               SIGNAL clk_lock : STD_LOGIC;
               SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
               SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL     ahbrxd: STD_LOGIC;
               SIGNAL     ahbtxd: STD_LOGIC;
               SIGNAL     urxd1 : STD_LOGIC;
               SIGNAL     utxd1 : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK_LOCK
               -----------------------------------------------------------------------------
               rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
               PROCESS (clk50MHz_int, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN         -- asynchronous reset (active low)
                   clk_lock <= '0';
                   clk_busy_counter <= (OTHERS => '0');
                   nSRAM_BUSY_reg <= '0';
                 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN  -- rising clock edge
                   nSRAM_BUSY_reg <= nSRAM_BUSY;
                   IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
                     IF clk_busy_counter = "1111"  THEN
                       clk_lock <= '1';
                     ELSE
                       clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
               rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
               --clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
               clk50MHz_int <= clk50MHz;
               PROCESS(clk50MHz_int)
               BEGIN
                 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
                   --clk_25_int <= NOT clk_25_int;
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               --clk_pad_25 : clkint  port map (A => clk_25_int, Y => clk_25 );
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
             --  clk_49 <= clk49_152MHz;
               -----------------------------------------------------------------------------
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => tech_leon,
                   memtech         => tech_leon,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 19,
                   USES_IAP_MEMCTRLR => 1,
                   BYPASS_EDAC_MEMCTRLR => '0',
-                  SRBANKSZ          => 8)
+                  SRBANKSZ          => 8,
+                  SLOW_TIMING_EMULATION => 0
+                  )
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn_25,
                   errorn => OPEN,
                   ahbrxd => ahbrxd,                   -- INPUT
                   ahbtxd => ahbtxd,                   -- OUTPUT
                   urxd1  => urxd1,                   -- INPUT
                   utxd1  => utxd1,                   -- OUTPUT
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => OPEN,
                   nSRAM_BE1 => OPEN,
                   nSRAM_BE2 => OPEN,
                   nSRAM_BE3 => OPEN,
                   nSRAM_WE  => nSRAM_W,
                   nSRAM_CE  => nSRAM_CE,
                   nSRAM_OE  => nSRAM_G,
                   nSRAM_READY => nSRAM_BUSY,
                   SRAM_MBE    => nSRAM_MBE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               nSRAM_E1 <= nSRAM_CE(0);
               nSRAM_E2 <= nSRAM_CE(1);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   tech             => tech,
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   --FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz          => clk_25,
                   resetn_25MHz      => rstn_25,      --      TODO
                   --clk24_576MHz      => clk_24,          -- 49.152MHz/2
                   --resetn_24_576MHz  => rstn_24,      --      TODO
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   DAC_SDO           => DAC_SDO,
                   DAC_SCK            => DAC_SCK,
                   DAC_SYNC          => DAC_SYNC,
                   DAC_CAL_EN        => DAC_CAL_EN,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               ------------------------------------------------------------------------------
               -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
               ------------------------------------------------------------------------------
               spw1_en   <= '1';
               spw2_en   <= '1';
               ------------------------------------------------------------------------------
               -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
               ------------------------------------------------------------------------------
               --spw_clk     <= clk50MHz;
               --spw_rxtxclk <= spw_clk;
               --spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => tech_leon,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => tech_leon,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => tech_leon,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1),
                          clk50MHz_int,
                          clk50MHz_int,
             --             spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 50 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => Mem_use,
                   tech                   => tech,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"020153",  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                                                         --      2 => EQM (with A3PE3000)
                   DEBUG_FORCE_DATA_DMA  => DEBUG_FORCE_DATA_DMA)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => debug_vector,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
                 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                   GENERIC MAP (
                     ChanelCount     => 9,
                     ncycle_cnv_high => 12,
                     ncycle_cnv      => 25,
                     FILTER_ENABLED  => 16#FF#)
                   PORT MAP (
                     cnv_clk    => clk_24,
                     cnv_rstn   => rstn_24,
                     cnv        => ADC_smpclk_s,
                     clk        => clk_25,
                     rstn       => rstn_25,
                     ADC_data   => ADC_data,
                     ADC_nOE    => ADC_OEB_bar_CH_s,
                     sample     => sample,
                     sample_val => sample_val);
               END GENERATE USE_ADCDRIVER_true;
               USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
                 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                   GENERIC MAP (
                     ChanelCount     => 9,
                     ncycle_cnv_high => 25,
                     ncycle_cnv      => 50,
                     FILTER_ENABLED  => 16#FF#)
                   PORT MAP (
                     cnv_clk    => clk_24,
                     cnv_rstn   => rstn_24,
                     cnv        => ADC_smpclk_s,
                     clk        => clk_25,
                     rstn       => rstn_25,
                     ADC_data   => ADC_data,
                     ADC_nOE    => OPEN,
                     sample     => OPEN,
                     sample_val => sample_val);
                 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
                 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
                   ramp_generator_1: ramp_generator
                     GENERIC MAP (
                       DATA_SIZE           => 14,
                       VALUE_UNSIGNED_INIT => 2**I,
                       VALUE_UNSIGNED_INCR => 0,
                       VALUE_UNSIGNED_MASK => 16#3FFF#)
                     PORT MAP (
                       clk         => clk_25,
                       rstn        => rstn_25,
                       new_data    => sample_val,
                       output_data => sample(I) );
                 END GENERATE all_sample;
               END GENERATE USE_ADCDRIVER_false;
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
                 lpp_bootloader_1: lpp_bootloader
                   GENERIC MAP (
                     pindex => 13,
                     paddr  => 13,
                     pmask  => 16#fff#,
                     hindex => 3,
                     haddr  => 0,
                     hmask  => 16#fff#)
                   PORT MAP (
                     HCLK    => clk_25,
                     HRESETn => rstn_25,
                     apbi    => apbi_ext,
                     apbo    => apbo_ext(13),
                     ahbsi   => ahbi_s_ext,
                     ahbso   => ahbo_s_ext(3));
               END GENERATE inst_bootloader;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
                 PROCESS (clk_25, rstn_25)
                 BEGIN  -- PROCESS
                   IF rstn_25 = '0' THEN             -- asynchronous reset (active low)
                     TAG <= (OTHERS => '0');
                   ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
                     TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
                   END IF;
                 END PROCESS;
               END GENERATE USE_DEBUG_VECTOR_IF;
               USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
                 ahbrxd <= TAG(1);
                 TAG(3) <= ahbtxd;
                 urxd1  <= TAG(2);
                 TAG(4) <= utxd1;
                 TAG(8) <= nSRAM_BUSY;
               END GENERATE USE_DEBUG_VECTOR_IF2;
             END beh;

designs/LFR-em-WFP_MS/LFR-em.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1           : IN    STD_ULOGIC;  -- DSU rx data
                 TAG3           : OUT   STD_ULOGIC;  -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2           : IN    STD_ULOGIC;  -- UART1 rx data
                 TAG4           : OUT   STD_ULOGIC;  -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address        : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data           : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0      : OUT   STD_LOGIC;
                 nSRAM_BE1      : OUT   STD_LOGIC;
                 nSRAM_BE2      : OUT   STD_LOGIC;
                 nSRAM_BE3      : OUT   STD_LOGIC;
                 nSRAM_WE       : OUT   STD_LOGIC;
                 nSRAM_CE       : OUT   STD_LOGIC;
                 nSRAM_OE       : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din       : IN    STD_LOGIC;
                 spw1_sin       : IN    STD_LOGIC;
                 spw1_dout      : OUT   STD_LOGIC;
                 spw1_sout      : OUT   STD_LOGIC;
                 spw2_din       : IN    STD_LOGIC;
                 spw2_sin       : IN    STD_LOGIC;
                 spw2_dout      : OUT   STD_LOGIC;
                 spw2_sout      : OUT   STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT   STD_LOGIC;
                 ADC_OEB_bar_CH : OUT   STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT   STD_LOGIC;
                 ADC_data       : IN    STD_LOGIC_VECTOR(13 DOWNTO 0);
                 -- DAC --------------------------------------------------------------------
                 DAC_SDO    : OUT STD_LOGIC;
                 DAC_SCK    : OUT STD_LOGIC;
                 DAC_SYNC   : OUT STD_LOGIC;
                 DAC_CAL_EN : OUT STD_LOGIC;
                 -- HK ---------------------------------------------------------------------
                 HK_smpclk      : OUT   STD_LOGIC;
                 ADC_OEB_bar_HK : OUT   STD_LOGIC;
                 HK_SEL         : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8           : OUT   STD_LOGIC;
                 led            : OUT   STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
             --==========================================================================
             --  USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
             --  when enabled, chip enable polarity should be reversed and bank size also
             --  MINILFR      -> 1 bank of 4MBytes   -> SRBANKSZ=9
             --  LFR EQM & FM -> 2 banks of 2MBytes  -> SRBANKSZ=8
             --==========================================================================
               CONSTANT USE_IAP_MEMCTRL : integer := 1;
             --==========================================================================
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(8 DOWNTO 0);
               SIGNAL sample_s    : Samples(8 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL  ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn_25 : STD_LOGIC;
               SIGNAL rstn_24 : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
               ----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL nSRAM_READY : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
               rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   IS_RADHARD      => 0,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
-                  ENABLE_AHB_UART => 1,
+                  ENABLE_AHB_UART => 0,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20,
                   USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
                   BYPASS_EDAC_MEMCTRLR => '0',
                   SRBANKSZ          => 9)
                 PORT MAP (
                   clk    => clk_25,
                   reset  => rstn_25,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   ahbtxd => TAG3,
                   urxd1  => TAG2,
                   utxd1  => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE_s,
                   nSRAM_OE  => nSRAM_OE,
                   nSRAM_READY => nSRAM_READY,
                   SRAM_MBE    => '0',
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   nSRAM_READY <= '1';
                 ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
                   nSRAM_READY <= '1';
                 END IF;
               END PROCESS;
               IAP:if USE_IAP_MEMCTRL = 1 GENERATE
                 nSRAM_CE <= not nSRAM_CE_s(0);
               END GENERATE;
               NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
                 nSRAM_CE <=  nSRAM_CE_s(0);
               END GENERATE;
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_management_1 : apb_lfr_management
                 GENERIC MAP (
                   tech             => apa3e,
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
             --      FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz          => clk_25,
                   resetn_25MHz      => rstn_25,      --      TODO
             --      clk24_576MHz      => clk_24,          -- 49.152MHz/2
             --      resetn_24_576MHz  => rstn_24,      --      TODO
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   HK_sample     => sample_s(8),
                   HK_val        => sample_val,
                   HK_sel        => HK_SEL,
                   DAC_SDO           => DAC_SDO,
                   DAC_SCK            => DAC_SCK,
                   DAC_SYNC          => DAC_SYNC,
                   DAC_CAL_EN        => DAC_CAL_EN,
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   tech                   => inferred,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"010153",  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                   DEBUG_FORCE_DATA_DMA  => 0)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw,
                   debug_vector    => OPEN,
                   debug_vector_ms => OPEN);     --,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 9,
                   ncycle_cnv_high => 12,
                   ncycle_cnv      => 25,
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_24,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn_25,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,
                   sample_val => sample_val);
               ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
               -----------------------------------------------------------------------------
               -- HK
               -----------------------------------------------------------------------------
               ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
             END beh;

designs/UT8ER1M32-test-board/Makefile +2 -1

             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=UT8ER1M32_test_board_top
             BOARD=UT8ER1M32-test-board
             include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
             DEVICE=$(PART)-$(PACKAGE)$(SPEED)
             UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
             QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
             EFFORT=high
             XSTOPT=
             SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
             VHDLSYNFILES=	UT8ER1M32-test-board_top.vhd
             PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean
             TECHLIBS = proasic3e
             LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
             	tmtc openchip hynix ihp gleichmann micron usbhc
             DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
             	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
             	./amba_lcd_16x2_ctrlr \
             	./general_purpose/lpp_AMR \
             	./general_purpose/lpp_balise \
             	./general_purpose/lpp_delay \
             	./dsp/lpp_fft \
             	./lpp_bootloader \
             	./lpp_cna \
             	./lpp_demux \
             	./lpp_matrix \
             	./lpp_uart \
             	./lpp_usb \
             	./lpp_Header \
             	./lpp_sim \
             	./lpp_lfr_pkg \
             	./lpp_debug_lfr_pkg \
-            	./lpp_top_lfr
+            	./lpp_top_lfr \
+            	./lfr_management
             FILESKIP =lpp_lfr_ms.vhd \
             	i2cmst.vhd \
             	APB_MULTI_DIODE.vhd \
             	APB_SIMPLE_DIODE.vhd \
             	Top_MatrixSpec.vhd \
             	APB_FFT.vhd \
             	async_1Mx16.vhd \
             	CY7C1061DV33.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile
             ##################  project specific targets ##########################

designs/UT8ER1M32-test-board/UT8ER1M32-test-board_top.vhd +45 -13

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY UT8ER1M32_test_board_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_nCE1  : OUT   STD_LOGIC;
                 SRAM_nCE2  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_MBE    : INOUT    STD_LOGIC;
                 SRAM_nBUSY  : IN    STD_LOGIC;
                 --SRAM_nSCRUB : IN    STD_LOGIC;
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(18 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END UT8ER1M32_test_board_top;
             ARCHITECTURE beh OF UT8ER1M32_test_board_top IS
               SIGNAL clk_25 : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time  :  STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time    :  STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
               SIGNAL  ahbrxd : STD_ULOGIC;            -- DSU rx data
               SIGNAL  ahbtxd : STD_ULOGIC;            -- DSU tx data
               -- UART APB ---------------------------------------------------------------
               SIGNAL  urxd1 :  STD_ULOGIC;             -- UART1 rx data
               SIGNAL  utxd1 :  STD_ULOGIC;             -- UART1 tx data
                                                        --
               SIGNAL I00_s : STD_LOGIC;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 1;
               SIGNAL  apbi_ext    :  apb_slv_in_type;
               SIGNAL  apbo_ext    :  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5  DOWNTO 5):= (OTHERS => apb_none);
               SIGNAL  ahbi_s_ext  :  ahb_slv_in_type;
               SIGNAL  ahbo_s_ext  :  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3  DOWNTO 3):= (OTHERS => ahbs_none);
               SIGNAL  ahbi_m_ext  :  AHB_Mst_In_Type;
               SIGNAL  ahbo_m_ext  :  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
               --SRAM-----------------------------------------------------------------------
               SIGNAL  SRAM_CE    :   STD_LOGIC_VECTOR(1 downto 0);
+              SIGNAL rstn_25 : STD_LOGIC;
+              SIGNAL rstn_50 : STD_LOGIC;
+              SIGNAL rstn_49 : STD_LOGIC;
+              SIGNAL clk_lock : STD_LOGIC;
+              SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
+              SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
             BEGIN  -- beh
+              rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN);
+              PROCESS (clk_50, rstn_50)
+              BEGIN  -- PROCESS
+                IF rstn_50 = '0' THEN         -- asynchronous reset (active low)
+                  clk_lock         <= '0';
+                  clk_busy_counter <= (OTHERS => '0');
+                  nSRAM_BUSY_reg    <= '0';
+                ELSIF clk_50'event AND clk_50 = '1' THEN  -- rising clock edge
+                  nSRAM_BUSY_reg <= SRAM_nBUSY;
+                  IF nSRAM_BUSY_reg = '1' AND SRAM_nBUSY = '0' THEN
+                    IF clk_busy_counter = "1111"  THEN
+                      clk_lock <= '1';
+                    ELSE
+                      clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
+                    END IF;
+                  END IF;
+                END IF;
+              END PROCESS;
+              rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               PROCESS(clk_50)
               BEGIN
                 IF clk_50'EVENT AND clk_50 = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
+              PROCESS (clk_49, rstn_49)
-              PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                IF rstn_49 = '0' THEN                 -- asynchronous reset (active low)
                   I00_s  <= '0';
                 ELSIF clk_49'event AND clk_49 = '1' THEN  -- rising clock edge
-                    I00_s  <= NOT I00_s;
+                  I00_s  <= NOT I00_s;
-                  END IF;
+                END IF;
               END PROCESS;
               nCTS1  <= '1';
               SRAM_nCE1    <=  SRAM_CE(0);
               SRAM_nCE2    <=  SRAM_CE(1);
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 0,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 19,
-                  USES_IAP_MEMCTRLR => 1)
+                  USES_IAP_MEMCTRLR => 1,
+                  BYPASS_EDAC_MEMCTRLR => '0',
+                  SRBANKSZ          => 8,
+                  SLOW_TIMING_EMULATION => 1
+                  )
                 PORT MAP (
                   clk         => clk_25,
-                  reset       => reset,
+                  reset       => rstn_25,
                   errorn      => errorn,
                   ahbrxd      => TXD1,
                   ahbtxd      => RXD1,
                   urxd1       => TXD2,
                   utxd1       => RXD2,
                   address     => SRAM_A,
                   data        => SRAM_DQ,
                   nSRAM_BE0   => LED0,
                   nSRAM_BE1   => LED1,
                   nSRAM_BE2   => LED2,
                   nSRAM_BE3   => open,
                   nSRAM_WE    => SRAM_nWE,
                   nSRAM_CE    => SRAM_CE,
                   nSRAM_OE    => SRAM_nOE,
                   nSRAM_READY => SRAM_nBUSY,
                   SRAM_MBE    => SRAM_MBE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
+            END beh;
-            END beh;
  No newline at end of file

lib/lpp/lpp_leon3_soc/leon3_soc.vhd +29 -8

             -----------------------------------------------------------------------------
             --  LEON3 Demonstration design
             --  Copyright (C) 2004 Jiri Gaisler, Gaisler Research
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 2 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;              -- PLE
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             LIBRARY iap;
             USE iap.memctrl.ALL;
             ENTITY leon3_soc IS
               GENERIC (
                 fabtech           : INTEGER := axcel;--apa3e;
                 memtech           : INTEGER := axcel;--apa3e;
                 padtech           : INTEGER := inferred;
                 clktech           : INTEGER := inferred;
                 disas             : INTEGER := 0;      -- Enable disassembly to console
                 dbguart           : INTEGER := 0;      -- Print UART on console
                 pclow             : INTEGER := 2;
                 --
                 clk_freq          : INTEGER := 25000;  --kHz
                 --
                 IS_RADHARD        : INTEGER := 1;
                 --
                 NB_CPU            : INTEGER := 1;
                 ENABLE_FPU        : INTEGER := 1;
                 FPU_NETLIST       : INTEGER := 0;
                 ENABLE_DSU        : INTEGER := 1;
                 ENABLE_AHB_UART   : INTEGER := 1;
                 ENABLE_APB_UART   : INTEGER := 1;
                 ENABLE_IRQMP      : INTEGER := 1;
                 ENABLE_GPT        : INTEGER := 1;
                 --
                 NB_AHB_MASTER     : INTEGER := 1;
                 NB_AHB_SLAVE      : INTEGER := 1;
                 NB_APB_SLAVE      : INTEGER := 1;
                 --
                 ADDRESS_SIZE      : INTEGER := 19;
                 USES_IAP_MEMCTRLR : INTEGER := 1;
                 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
-                SRBANKSZ          : INTEGER := 8
+                SRBANKSZ          : INTEGER := 8;
+                SLOW_TIMING_EMULATION : integer := 0
                 );
               PORT (
                 clk   : IN STD_ULOGIC;
                 reset : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT   apb_slv_in_type;
                 apbo_ext    : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT   ahb_slv_in_type;
                 ahbo_s_ext  : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT   AHB_Mst_In_Type;
                 ahbo_m_ext  : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
                 );
             END;
             ARCHITECTURE Behavioral OF leon3_soc IS
               -----------------------------------------------------------------------------
               -- CONFIG -------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- Clock generator
               CONSTANT CFG_CLKMUL    : INTEGER := (1);
               CONSTANT CFG_CLKDIV    : INTEGER := (1);  -- divide 50MHz by 2 to get 25MHz
               CONSTANT CFG_OCLKDIV   : INTEGER := (1);
               CONSTANT CFG_CLK_NOFB  : INTEGER := 0;
               -- LEON3 processor core
               CONSTANT CFG_LEON3     : INTEGER := 1;
               CONSTANT CFG_NCPU      : INTEGER := NB_CPU;
               CONSTANT CFG_NWIN      : INTEGER := (8);  -- to be compatible with BCC and RCC
               CONSTANT CFG_V8        : INTEGER := 0;
               CONSTANT CFG_MAC       : INTEGER := 0;
               CONSTANT CFG_SVT       : INTEGER := 0;
               CONSTANT CFG_RSTADDR   : INTEGER := 16#00000#;
               CONSTANT CFG_LDDEL     : INTEGER := (1);
               CONSTANT CFG_NWP       : INTEGER := (0);
               CONSTANT CFG_PWD       : INTEGER := 1*2;
               CONSTANT CFG_FPU       : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
               -- 1*(8 + 16 * 0) => grfpu-light
               -- 1*(8 + 16 * 1) => netlist
               -- 0*(8 + 16 * 0) => No FPU
               -- 0*(8 + 16 * 1) => No FPU;
               CONSTANT CFG_ICEN      : INTEGER := 1;
               CONSTANT CFG_ISETS     : INTEGER := 1;
               CONSTANT CFG_ISETSZ    : INTEGER := 4;
               CONSTANT CFG_ILINE     : INTEGER := 4;
               CONSTANT CFG_IREPL     : INTEGER := 0;
               CONSTANT CFG_ILOCK     : INTEGER := 0;
               CONSTANT CFG_ILRAMEN   : INTEGER := 0;
               CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
               CONSTANT CFG_ILRAMSZ   : INTEGER := 1;
               CONSTANT CFG_DCEN      : INTEGER := 1;
               CONSTANT CFG_DSETS     : INTEGER := 1;
               CONSTANT CFG_DSETSZ    : INTEGER := 4;
               CONSTANT CFG_DLINE     : INTEGER := 4;
               CONSTANT CFG_DREPL     : INTEGER := 0;
               CONSTANT CFG_DLOCK     : INTEGER := 0;
               CONSTANT CFG_DSNOOP    : INTEGER := 0 + 0 + 4*0;
               CONSTANT CFG_DLRAMEN   : INTEGER := 0;
               CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
               CONSTANT CFG_DLRAMSZ   : INTEGER := 1;
               CONSTANT CFG_MMUEN     : INTEGER := 0;
               CONSTANT CFG_ITLBNUM   : INTEGER := 2;
               CONSTANT CFG_DTLBNUM   : INTEGER := 2;
               CONSTANT CFG_TLB_TYPE  : INTEGER := 1 + 0*2;
               CONSTANT CFG_TLB_REP   : INTEGER := 1;
               CONSTANT CFG_DSU   : INTEGER := ENABLE_DSU;
               CONSTANT CFG_ITBSZ : INTEGER := 0;
               CONSTANT CFG_ATBSZ : INTEGER := 0;
               -- AMBA settings
               CONSTANT CFG_DEFMST  : INTEGER := (0);
               CONSTANT CFG_RROBIN  : INTEGER := 1;
               CONSTANT CFG_SPLIT   : INTEGER := 0;
               CONSTANT CFG_AHBIO   : INTEGER := 16#FFF#;
               CONSTANT CFG_APBADDR : INTEGER := 16#800#;
               -- DSU UART
               CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
               -- LEON2 memory controller
               CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
               -- UART 1
               CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
               CONSTANT CFG_UART1_FIFO   : INTEGER := 1;
               -- LEON3 interrupt controller
               CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
               -- Modular timer
               CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
               CONSTANT CFG_GPT_NTIM   : INTEGER := (2);
               CONSTANT CFG_GPT_SW     : INTEGER := (8);
               CONSTANT CFG_GPT_TW     : INTEGER := (32);
               CONSTANT CFG_GPT_IRQ    : INTEGER := (8);
               CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
               CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
               CONSTANT CFG_GPT_WDOG   : INTEGER := 16#0#;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- SIGNALs
               -----------------------------------------------------------------------------
               CONSTANT maxahbmsp  : INTEGER            := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
               -- CLK & RST --
               SIGNAL   clk2x      : STD_ULOGIC;
               SIGNAL   clkmn      : STD_ULOGIC;
               SIGNAL   clkm       : STD_ULOGIC;
               SIGNAL   rstn       : STD_ULOGIC;
               SIGNAL   rstraw     : STD_ULOGIC;
               SIGNAL   pciclk     : STD_ULOGIC;
               SIGNAL   sdclkl     : STD_ULOGIC;
               SIGNAL   cgi        : clkgen_in_type;
               SIGNAL   cgo        : clkgen_out_type;
               --- AHB / APB
               SIGNAL   apbi       : apb_slv_in_type;
               SIGNAL   apbo       : apb_slv_out_vector := (OTHERS => apb_none);
               SIGNAL   ahbsi      : ahb_slv_in_type;
               SIGNAL   ahbso      : ahb_slv_out_vector := (OTHERS => ahbs_none);
               SIGNAL   ahbmi      : ahb_mst_in_type;
               SIGNAL   ahbmo      : ahb_mst_out_vector := (OTHERS => ahbm_none);
               --UART
               SIGNAL   ahbuarti   : uart_in_type;
               SIGNAL   ahbuarto   : uart_out_type;
               SIGNAL   apbuarti   : uart_in_type;
               SIGNAL   apbuarto   : uart_out_type;
               --MEM CTRLR
               SIGNAL   memi       : memory_in_type;
               SIGNAL   memo       : memory_out_type;
               SIGNAL   wpo        : wprot_out_type;
               SIGNAL   sdo        : sdram_out_type;
               SIGNAL   mbe        : STD_LOGIC;      -- enable memory programming
               SIGNAL   mbe_drive  : STD_LOGIC;      -- drive the MBE memory signal
               SIGNAL   nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL   nSRAM_OE_s : STD_LOGIC;
               --IRQ
               SIGNAL   irqi       : irq_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   irqo       : irq_out_vector(0 TO CFG_NCPU-1);
               --Timer
               SIGNAL   gpti       : gptimer_in_type;
               SIGNAL   gpto       : gptimer_out_type;
               --DSU
               SIGNAL   dbgi       : l3_debug_in_vector(0 TO CFG_NCPU-1);
               SIGNAL   dbgo       : l3_debug_out_vector(0 TO CFG_NCPU-1);
               SIGNAL   dsui       : dsu_in_type;
               SIGNAL   dsuo       : dsu_out_type;
               -----------------------------------------------------------------------------
+              SIGNAL memo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
+              SIGNAL memi_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN
             ----------------------------------------------------------------------
             ---  Reset and Clock generation  -------------------------------------
             ----------------------------------------------------------------------
               cgi.pllctrl <= "00";
               cgi.pllrst  <= rstraw;
               rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
               clkgen0 : clkgen                      -- clock generator
                 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
                              CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
                 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
             ----------------------------------------------------------------------
             ---  LEON3 processor / DSU / IRQ  ------------------------------------
             ----------------------------------------------------------------------
               l3 : IF CFG_LEON3 = 1 GENERATE
                 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
                     u0 : leon3s                       -- LEON3 processor
                       GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
 , CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
                                    CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
                                    CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
                                    CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
                                    CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
                       PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
                                 irqi(i), irqo(i), dbgi(i), dbgo(i));
                   END GENERATE leon3_non_radhard;
                   leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
                     cpu : leon3ft
                       GENERIC MAP (
                         HINDEX     => i,  --: integer;             --CPU_HINDEX,
                         FABTECH    => fabtech,        --CFG_TECH,
                         MEMTECH    => memtech,        --CFG_TECH,
                         NWINDOWS   => CFG_NWIN,       --CFG_NWIN,
                         DSU        => CFG_DSU,        --condSel (HAS_DEBUG, 1, 0),
                         FPU        => CFG_FPU,        --CFG_FPU,
                         V8         => CFG_V8,         --CFG_V8,
                         CP         => 0,              --CFG_CP,
                         MAC        => CFG_MAC,        --CFG_MAC,
                         PCLOW      => pclow,          --CFG_PCLOW,
                         NOTAG      => 0,              --CFG_NOTAG,
                         NWP        => CFG_NWP,        --CFG_NWP,
                         ICEN       => CFG_ICEN,       --CFG_ICEN,
                         IREPL      => CFG_IREPL,      --CFG_IREPL,
                         ISETS      => CFG_ISETS,      --CFG_ISETS,
                         ILINESIZE  => CFG_ILINE,      --CFG_ILINE,
                         ISETSIZE   => CFG_ISETSZ,     --CFG_ISETSZ,
                         ISETLOCK   => CFG_ILOCK,      --CFG_ILOCK,
                         DCEN       => CFG_DCEN,       --CFG_DCEN,
                         DREPL      => CFG_DREPL,      --CFG_DREPL,
                         DSETS      => CFG_DSETS,      --CFG_DSETS,
                         DLINESIZE  => CFG_DLINE,      --CFG_DLINE,
                         DSETSIZE   => CFG_DSETSZ,     --CFG_DSETSZ,
                         DSETLOCK   => CFG_DLOCK,      --CFG_DLOCK,
                         DSNOOP     => CFG_DSNOOP,     --CFG_DSNOOP,
                         ILRAM      => CFG_ILRAMEN,    --CFG_ILRAMEN,
                         ILRAMSIZE  => CFG_ILRAMSZ,    --CFG_ILRAMSZ,
                         ILRAMSTART => CFG_ILRAMADDR,  --CFG_ILRAMADDR,
                         DLRAM      => CFG_DLRAMEN,    --CFG_DLRAMEN,
                         DLRAMSIZE  => CFG_DLRAMSZ,    --CFG_DLRAMSZ,
                         DLRAMSTART => CFG_DLRAMADDR,  --CFG_DLRAMADDR,
                         MMUEN      => CFG_MMUEN,      --CFG_MMUEN,
                         ITLBNUM    => CFG_ITLBNUM,    --CFG_ITLBNUM,
                         DTLBNUM    => CFG_DTLBNUM,    --CFG_DTLBNUM,
                         TLB_TYPE   => CFG_TLB_TYPE,   --CFG_TLB_TYPE,
                         TLB_REP    => CFG_TLB_REP,    --CFG_TLB_REP,
                         LDDEL      => CFG_LDDEL,      --CFG_LDDEL,
                         DISAS      => disas,          --condSel (SIM_ENABLED, 1, 0),
                         TBUF       => CFG_ITBSZ,      --CFG_ITBSZ,
                         PWD        => CFG_PWD,        --CFG_PWD,
                         SVT        => CFG_SVT,        --CFG_SVT,
                         RSTADDR    => CFG_RSTADDR,    --CFG_RSTADDR,
                         SMP        => CFG_NCPU-1,     --CFG_NCPU-1,
                         IUFT       => 2,  --: integer range 0 to 4;--CFG_IUFT_EN,
                         FPFT       => 1,  --: integer range 0 to 4;--CFG_FPUFT_EN,
                         CMFT       => 1,  --: integer range 0 to 1;--CFG_CACHE_FT_EN,
                         IUINJ      => 0,  --: integer;             --CFG_RF_ERRINJ,
                         CEINJ      => 0,  --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
                         CACHED     => 0,  --: integer;             --CFG_DFIXED,
                         NETLIST    => 0,  --: integer;             --CFG_LEON3_NETLIST,
                         SCANTEST   => 0,  --: integer;             --CFG_SCANTEST,
                         MMUPGSZ    => 0,  --: integer range 0 to 5;--CFG_MMU_PAGE,
                         BP         => 1)              --CFG_BP
                       PORT MAP (                      --
                         rstn  => rstn,                --rst_n,
                         clk   => clkm,                --clk,
                         ahbi  => ahbmi,               --ahbmi,
                         ahbo  => ahbmo(i),             --ahbmo(CPU_HINDEX),
                         ahbsi => ahbsi,               --ahbsi,
                         ahbso => ahbso,               --ahbso,
                         irqi  => irqi(i),             --irqi(CPU_HINDEX),
                         irqo  => irqo(i),             --irqo(CPU_HINDEX),
                         dbgi  => dbgi(i),             --dbgi(CPU_HINDEX),
                         dbgo  => dbgo(i),             --dbgo(CPU_HINDEX),
                         gclk  => clkm                 --clk
                         );
                   END GENERATE leon3_radhard_i;
                 END GENERATE;
                 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
                 dsugen : IF CFG_DSU = 1 GENERATE
                   dsu0 : dsu3                       -- LEON3 Debug Support Unit
                     GENERIC MAP (hindex => 0,       --      TODO : hindex => 2
                                  haddr => 16#900#, hmask => 16#F00#,
                                  ncpu   => CFG_NCPU, tbits => 30, tech => memtech,
                                  irq => 0, kbytes => CFG_ATBSZ)
                     PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),--      TODO :ahbso(2)
                               dbgo, dbgi, dsui, dsuo);
                   dsui.enable <= '1';
                   dsui.break  <= '0';
                 END GENERATE;
               END GENERATE;
               nodsu : IF CFG_DSU = 0 GENERATE
                 ahbso(0)    <= ahbs_none;
                 dsuo.tstop  <= '0';
                 dsuo.active <= '0';
               END GENERATE;
               irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
                 irqctrl0 : irqmp                    -- interrupt controller
                   GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
                   PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
               END GENERATE;
               irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
                 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
                   irqi(i).irl <= "0000";
                 END GENERATE;
                 apbo(2) <= apb_none;
               END GENERATE;
             ----------------------------------------------------------------------
             ---  Memory controllers  ---------------------------------------------
             ----------------------------------------------------------------------
               ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
                 memctrlr : mctrl GENERIC MAP (
                   hindex  => 2,
                   pindex  => 0,
                   paddr   => 0,
                   srbanks => 1
                   )
                   PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
                 memi.bexcn <= '1';
                 memi.brdyn <= '1';
                 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.ramoen(0);
               END GENERATE;
               IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
                 memctrlr : srctrle_0ws
                   GENERIC MAP(
                     hindex   => 2,                  -- TODO : hindex   => 0
                     pindex   => 0,
                     paddr    => 0,
                     srbanks  => 2,
                     banksz   => SRBANKSZ,                  --512k * 32
                     rmw      => 1,
                     --Aeroflex memory generics:
                     mbpedac  => BYPASS_EDAC_MEMCTRLR,
                     mprog    => 1,          -- program memory by default values after reset
                     mpsrate  => 15,                 -- default scrub rate period
                     mpb2s    => 14,                  -- default busy to scrub delay
                     mpapb    => 1,                  -- instantiate apb register
                     mchipcnt => 2,
                     mpenall  => 1  -- when 0 program only E1 chip, else program all dies
                     )
                   PORT MAP (
                     rst       => rstn,
                     clk       => clkm,
                     ahbsi     => ahbsi,
                     ahbso     => ahbso(2),          -- TODO :ahbso(0),
                     apbi      => apbi,
                     apbo      => apbo(0),
                     sri       => memi,
                     sro       => memo,
                     --Aeroflex memory signals:
                     ucerr     => OPEN,              -- uncorrectable error signal
                     mbe       => mbe,               -- enable memory programming
                     mbe_drive => mbe_drive          -- drive the MBE memory signal
                     );
                 memi.brdyn <= nSRAM_READY;
                 mbe_pad : iopad
                   GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP(pad => SRAM_MBE,
                            i   => mbe,
                            en  => mbe_drive,
                            o   => memi.bexcn);
                 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
                 nSRAM_OE_s <= memo.oen;
               END GENERATE;
               memi.writen <= '1';
               memi.wrn    <= "1111";
               memi.bwidth <= "10";
+              -----------------------------------------------------------------------------
+              -- SLOW TIMING EMULATION
+              -----------------------------------------------------------------------------
+              SLOW_TIMING_EMULATION_ON: IF SLOW_TIMING_EMULATION = 1 GENERATE
+                PROCESS (clkm, rstn)
+                BEGIN  -- PROCESS
+                  IF rstn = '0' THEN                -- asynchronous reset (active low)
+                    memi.data <= (OTHERS => '0');
+                    memo_data <= (OTHERS => '0');
+                  ELSIF clkm'event AND clkm = '1' THEN  -- rising clock edge
+                    memi.data <= memi_data;
+                    memo_data <= memo.data;
+                  END IF;
+                END PROCESS;
+              END GENERATE SLOW_TIMING_EMULATION_ON;
+              SLOW_TIMING_EMULATION_OFF: IF SLOW_TIMING_EMULATION = 0 GENERATE
+                memi.data <= memi_data;
+                memo_data <= memo.data;
+              END GENERATE SLOW_TIMING_EMULATION_OFF;
               bdr : FOR i IN 0 TO 3 GENERATE
                 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
                   PORT MAP (
                     data(31-i*8 DOWNTO 24-i*8),
-                    memo.data(31-i*8 DOWNTO 24-i*8),
+                    memo_data(31-i*8 DOWNTO 24-i*8),
                     memo.bdrive(i),
-                    memi.data(31-i*8 DOWNTO 24-i*8));
+                    memi_data(31-i*8 DOWNTO 24-i*8));
               END GENERATE;
+              -----------------------------------------------------------------------------
               addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
                 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
               rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
               oen_pad  : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
               nBWE_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_WE, memo.writen);
               nBWa_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
               nBWb_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
               nBWc_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
               nBWd_pad : outpad GENERIC MAP (tech  => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
             ----------------------------------------------------------------------
             ---  AHB CONTROLLER  -------------------------------------------------
             ----------------------------------------------------------------------
               ahb0 : ahbctrl                        -- AHB arbiter/multiplexer
                 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
                              rrobin  => CFG_RROBIN, ioaddr => CFG_AHBIO,
                              ioen    => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
                 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
             ----------------------------------------------------------------------
             ---  AHB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               dcomgen : IF CFG_AHB_UART = 1 GENERATE
                 dcom0 : ahbuart
                   GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
                   PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
                 dsurx_pad : inpad GENERIC MAP (tech  => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
                 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
               END GENERATE;
               nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB Bridge  -----------------------------------------------------
             ----------------------------------------------------------------------
               apb0 : apbctrl                        -- AHB/APB bridge
                 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
                 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
             ----------------------------------------------------------------------
             ---  GPT Timer  ------------------------------------------------------
             ----------------------------------------------------------------------
               gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
                 timer0 : gptimer                    -- timer unit
                   GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
                                sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
                                nbits  => CFG_GPT_TW)
                   PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
                 gpti.dhalt  <= dsuo.tstop;
                 gpti.extclk <= '0';
               END GENERATE;
               notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
             ----------------------------------------------------------------------
             ---  APB UART  -------------------------------------------------------
             ----------------------------------------------------------------------
               ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
                 uart1 : apbuart                     -- UART 1
                   GENERIC MAP (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
                                fifosize => CFG_UART1_FIFO)
                   PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
                 apbuarti.rxd    <= urxd1;
                 apbuarti.extclk <= '0';
                 utxd1           <= apbuarto.txd;
                 apbuarti.ctsn   <= '0';
               END GENERATE;
               noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
             -------------------------------------------------------------------------------
             -- AMBA BUS -------------------------------------------------------------------
             -------------------------------------------------------------------------------
               -- APB --------------------------------------------------------------------
               apbi_ext <= apbi;
               all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
                 max_16_apb : IF I + 5 < 16 GENERATE
                   apbo(I+5) <= apbo_ext(I+5);
                 END GENERATE max_16_apb;
               END GENERATE all_apb;
               -- AHB_Slave --------------------------------------------------------------
               ahbi_s_ext <= ahbsi;
               all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
                 max_16_ahbs : IF I + 3 < 16 GENERATE
                   ahbso(I+3) <= ahbo_s_ext(I+3);
                 END GENERATE max_16_ahbs;
               END GENERATE all_ahbs;
               -- AHB_Master -------------------------------------------------------------
               ahbi_m_ext <= ahbmi;
               all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
                 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
                   ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
                 END GENERATE max_16_ahbm;
               END GENERATE all_ahbm;
             END Behavioral;

lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd +2 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             PACKAGE lpp_leon3_soc_pkg IS
               type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
               type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
               type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
               COMPONENT leon3_soc
                 GENERIC (
                   fabtech         : INTEGER;
                   memtech         : INTEGER;
                   padtech         : INTEGER;
                   clktech         : INTEGER;
                   disas           : INTEGER;
                   dbguart         : INTEGER;
                   pclow           : INTEGER;
                   clk_freq        : INTEGER;
                   IS_RADHARD      : INTEGER;
                   NB_CPU          : INTEGER;
                   ENABLE_FPU      : INTEGER;
                   FPU_NETLIST     : INTEGER;
                   ENABLE_DSU      : INTEGER;
                   ENABLE_AHB_UART : INTEGER;
                   ENABLE_APB_UART : INTEGER;
                   ENABLE_IRQMP    : INTEGER;
                   ENABLE_GPT      : INTEGER;
                   NB_AHB_MASTER   : INTEGER;
                   NB_AHB_SLAVE    : INTEGER;
                   NB_APB_SLAVE    : INTEGER;
                   ADDRESS_SIZE    : INTEGER;
                   USES_IAP_MEMCTRLR : INTEGER;
                   BYPASS_EDAC_MEMCTRLR : STD_LOGIC;
-                  SRBANKSZ        : INTEGER := 8
+                  SRBANKSZ        : INTEGER := 8;
+                  SLOW_TIMING_EMULATION : integer := 0
                 );
               PORT (
                 clk    : IN STD_ULOGIC;
                 reset  : IN STD_ULOGIC;
                 errorn : OUT STD_ULOGIC;
                 -- UART AHB ---------------------------------------------------------------
                 ahbrxd : IN  STD_ULOGIC;            -- DSU rx data
                 ahbtxd : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 urxd1 : IN  STD_ULOGIC;             -- UART1 rx data
                 utxd1 : OUT STD_ULOGIC;             -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address     : OUT   STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
                 data        : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0   : OUT   STD_LOGIC;
                 nSRAM_BE1   : OUT   STD_LOGIC;
                 nSRAM_BE2   : OUT   STD_LOGIC;
                 nSRAM_BE3   : OUT   STD_LOGIC;
                 nSRAM_WE    : OUT   STD_LOGIC;
                 nSRAM_CE    : OUT   STD_LOGIC_VECTOR(1 downto 0);
                 nSRAM_OE    : OUT   STD_LOGIC;
                 nSRAM_READY : IN    STD_LOGIC;
                 SRAM_MBE    : INOUT STD_LOGIC;
                 -- APB --------------------------------------------------------------------
                 apbi_ext    : OUT apb_slv_in_type;
                 apbo_ext    : IN  soc_apb_slv_out_vector(NB_APB_SLAVE-1+5  DOWNTO 5);
                 -- AHB_Slave --------------------------------------------------------------
                 ahbi_s_ext  : OUT ahb_slv_in_type;
                 ahbo_s_ext  : IN  soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3  DOWNTO 3);
                 -- AHB_Master -------------------------------------------------------------
                 ahbi_m_ext  : OUT AHB_Mst_In_Type;
                 ahbo_m_ext  : IN  soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
               END COMPONENT;
               --COMPONENT leon3ft_soc
               --  GENERIC (
               --    fabtech         : INTEGER;
               --    memtech         : INTEGER;
               --    padtech         : INTEGER;
               --    clktech         : INTEGER;
               --    disas           : INTEGER;
               --    dbguart         : INTEGER;
               --    pclow           : INTEGER;
               --    clk_freq        : INTEGER;
               --    NB_CPU          : INTEGER;
               --    ENABLE_FPU      : INTEGER;
               --    FPU_NETLIST     : INTEGER;
               --    ENABLE_DSU      : INTEGER;
               --    ENABLE_AHB_UART : INTEGER;
               --    ENABLE_APB_UART : INTEGER;
               --    ENABLE_IRQMP    : INTEGER;
               --    ENABLE_GPT      : INTEGER;
               --    NB_AHB_MASTER   : INTEGER;
               --    NB_AHB_SLAVE    : INTEGER;
               --    NB_APB_SLAVE    : INTEGER);
               --  PORT (
               --    clk        : IN    STD_ULOGIC;
               --    reset      : IN    STD_ULOGIC;
               --    errorn     : OUT   STD_ULOGIC;
               --    ahbrxd     : IN    STD_ULOGIC;
               --    ahbtxd     : OUT   STD_ULOGIC;
               --    urxd1      : IN    STD_ULOGIC;
               --    utxd1      : OUT   STD_ULOGIC;
               --    address    : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
               --    data       : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
               --    nSRAM_BE0  : OUT   STD_LOGIC;
               --    nSRAM_BE1  : OUT   STD_LOGIC;
               --    nSRAM_BE2  : OUT   STD_LOGIC;
               --    nSRAM_BE3  : OUT   STD_LOGIC;
               --    nSRAM_WE   : OUT   STD_LOGIC;
               --    nSRAM_CE   : OUT   STD_LOGIC;
               --    nSRAM_OE   : OUT   STD_LOGIC;
               --    apbi_ext   : OUT   apb_slv_in_type;
               --    apbo_ext   : IN    soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
               --    ahbi_s_ext : OUT   ahb_slv_in_type;
               --    ahbo_s_ext : IN    soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
               --    ahbi_m_ext : OUT   AHB_Mst_In_Type;
               --    ahbo_m_ext : IN    soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
               --END COMPONENT;
             END;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +7 -4

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 tech                   : INTEGER := inferred;
                 nb_data_by_buffer_size : INTEGER := 32;
                 nb_snapshot_param_size : INTEGER := 32;
                 delta_vector_size      : INTEGER := 32;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 15;
                 paddr    : INTEGER := 15;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 6;
                 pirq_wfp : INTEGER := 14;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"020153";
-                DEBUG_FORCE_DATA_DMA : INTEGER := 0
+                DEBUG_FORCE_DATA_DMA : INTEGER := 0;
+                RTL_DESIGN_LIGHT     : INTEGER := 0;
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC;
                 --
                 debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               SIGNAL data_shaping_R2  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f1_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f2_data_sim : Samples(5 DOWNTO 0);
               SIGNAL sample_f3_data_sim : Samples(5 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
             --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
             --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL length_matrix_f0         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f1         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f2         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               -- WFP
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               --SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL wfp_error_buffer_full   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full      : STD_LOGIC;
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_fifo_data        : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_data_debug  : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);      --21-04-2015
               SIGNAL dma_fifo_ren         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_new       : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_addr      : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_buffer_length    : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
               SIGNAL dma_buffer_full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_grant_error      : STD_LOGIC;
               SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_time        :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f0_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f1_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f2_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f3_time     :  STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               sample_time <= coarse_time & fine_time;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
-                  Mem_use => Mem_use)
+                  Mem_use          => Mem_use,
+                  RTL_DESIGN_LIGHT => RTL_DESIGN_LIGHT)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   sample_time      => sample_time,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   data_shaping_R2  => data_shaping_R2,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data,
                   sample_f0_time   => sample_f0_time,
                   sample_f1_time   => sample_f1_time,
                   sample_f2_time   => sample_f2_time,
                   sample_f3_time   => sample_f3_time
                   );
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
             --      run_ms => OPEN,--run_ms,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   length_matrix_f0  => length_matrix_f0,
                   length_matrix_f1  => length_matrix_f1,
                   length_matrix_f2  => length_matrix_f2,
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   data_shaping_R2   => data_shaping_R2,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => OPEN,
                   start_date        => start_date,
                   wfp_status_buffer_ready => wfp_status_buffer_ready,
                   wfp_addr_buffer         => wfp_addr_buffer,
                   wfp_length_buffer       => wfp_length_buffer,
                   wfp_ready_buffer        => wfp_ready_buffer,
                   wfp_buffer_time         => wfp_buffer_time,
                   wfp_error_buffer_full   => wfp_error_buffer_full,
                   -------------------------------------------------------------------------
                   sample_f3_v     => sample_f3_data(1*16-1 DOWNTO 0*16),
                   sample_f3_e1    => sample_f3_data(2*16-1 DOWNTO 1*16),
                   sample_f3_e2    => sample_f3_data(3*16-1 DOWNTO 2*16),
                   sample_f3_valid => sample_f3_val,
                   debug_vector => apb_reg_debug_vector
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => tech,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => '1',--run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_new_err    => status_new_err,
                   status_buffer_ready => wfp_status_buffer_ready,
                   addr_buffer         => wfp_addr_buffer,
                   length_buffer       => wfp_length_buffer,
                   ready_buffer        => wfp_ready_buffer,
                   buffer_time         => wfp_buffer_time,
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
             --      fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
                   data_f0_time                 => sample_f0_time,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
                   data_f1_time                 => sample_f1_time,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
                   data_f2_time                 => sample_f2_time,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
                   data_f3_time                 => sample_f3_time,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   dma_fifo_data        => dma_fifo_data(32*4-1 DOWNTO 0),
                   dma_fifo_ren         => dma_fifo_ren(3 DOWNTO 0),
                   dma_buffer_new       => dma_buffer_new(3 DOWNTO 0),
                   dma_buffer_addr      => dma_buffer_addr(32*4-1 DOWNTO 0),
                   dma_buffer_length    => dma_buffer_length(26*4-1 DOWNTO 0),
                   dma_buffer_full      => dma_buffer_full(3 DOWNTO 0),
                   dma_buffer_full_err  => dma_buffer_full_err(3 DOWNTO 0)
                   );
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
                                NOT(sample_f2_val) & NOT(sample_f2_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
-                  Mem_use => Mem_use)
+                  Mem_use => Mem_use,
+                  WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_ms,
                   start_date => start_date,
                   coarse_time => coarse_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f0_time  => sample_f0_time,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f1_time  => sample_f1_time,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
                   sample_f2_time  => sample_f2_time,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   dma_fifo_data        => dma_fifo_data((4+1)*32-1 DOWNTO 4*32),    -- OUT
                   dma_fifo_ren         => dma_fifo_ren(4),                          -- IN
                   dma_buffer_new       => dma_buffer_new(4),                        -- OUT
                   dma_buffer_addr      => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32),  -- OUT
                   dma_buffer_length    => dma_buffer_length((4+1)*26-1 DOWNTO 4*26),  -- OUT
                   dma_buffer_full      => dma_buffer_full(4),                       -- IN
                   dma_buffer_full_err  => dma_buffer_full_err(4),                   -- IN
                   --REG
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0 => length_matrix_f0,
                   length_matrix_f1 => length_matrix_f1,
                   length_matrix_f2 => length_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   debug_vector   => debug_vector_ms);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   dma_fifo_data_forced_gen <= X"00040003";
                 ELSIF clk'event AND clk = '1' THEN
                   IF dma_fifo_ren(0) = '0' THEN
                     CASE dma_fifo_data_forced_gen IS
                       WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
                       WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
                       WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
                       WHEN OTHERS => NULL;
                     END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
               dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
               dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
               dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
               dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
               dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
               DMA_SubSystem_1 : DMA_SubSystem
                 GENERIC MAP (
                   hindex     => hindex,
                   CUSTOM_DMA => 1)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_dma,
                   ahbi => ahbi,
                   ahbo => ahbo,
                   fifo_burst_valid => dma_fifo_burst_valid,  --fifo_burst_valid,
                   fifo_data        => dma_fifo_data_debug,         --fifo_data,
                   fifo_ren         => dma_fifo_ren,          --fifo_ren,
                   buffer_new      => dma_buffer_new,       --buffer_new,
                   buffer_addr     => dma_buffer_addr,      --buffer_addr,
                   buffer_length   => dma_buffer_length,    --buffer_length,
                   buffer_full     => dma_buffer_full,      --buffer_full,
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error,
                   debug_vector    => debug_vector(8 DOWNTO 0)
                   );     --grant_error);
               -----------------------------------------------------------------------------
               -- OBSERVATION for SIMULATION
               all_channel_sim: FOR I IN 0 TO 5 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     sample_f0_data_sim(I) <= (OTHERS => '0');
                     sample_f1_data_sim(I) <= (OTHERS => '0');
                     sample_f2_data_sim(I) <= (OTHERS => '0');
                     sample_f3_data_sim(I) <= (OTHERS => '0');
                   ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                     IF sample_f0_val = '1' THEN sample_f0_data_sim(I) <= sample_f0_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f1_val = '1' THEN sample_f1_data_sim(I) <= sample_f1_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f2_val = '1' THEN sample_f2_data_sim(I) <= sample_f2_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                     IF sample_f3_val = '1' THEN sample_f3_data_sim(I) <= sample_f3_data(((I+1)*16)-1 DOWNTO (I*16)); END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_channel_sim;
               -----------------------------------------------------------------------------
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_filter.vhd +36 -29

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.lpp_lfr_filter_coeff.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr_filter IS
               GENERIC(
-                Mem_use                 : INTEGER := use_RAM
+                Mem_use                 : INTEGER := use_RAM;
+                RTL_DESIGN_LIGHT        : INTEGER := 0
                 );
               PORT (
                 sample           : IN Samples(7 DOWNTO 0);
                 sample_val       : IN STD_LOGIC;
                 sample_time      : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 --
                 data_shaping_SP0 : IN STD_LOGIC;
                 data_shaping_SP1 : IN STD_LOGIC;
                 data_shaping_R0  : IN STD_LOGIC;
                 data_shaping_R1  : IN STD_LOGIC;
                 data_shaping_R2  : IN STD_LOGIC;
                 --
                 sample_f0_val   : OUT STD_LOGIC;
                 sample_f1_val   : OUT STD_LOGIC;
                 sample_f2_val   : OUT STD_LOGIC;
                 sample_f3_val   : OUT STD_LOGIC;
                 --
                 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                 --
                 sample_f0_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 sample_f1_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 sample_f2_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 sample_f3_time  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END lpp_lfr_filter;
             ARCHITECTURE tb OF lpp_lfr_filter IS
               COMPONENT Downsampling
                 GENERIC (
                   ChanelCount : INTEGER;
                   SampleSize  : INTEGER;
                   DivideParam : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_in_val  : IN  STD_LOGIC;
                   sample_in      : IN  samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
                   sample_out_val : OUT STD_LOGIC;
                   sample_out     : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               CONSTANT ChanelCount     : INTEGER := 8;
               -----------------------------------------------------------------------------
               SIGNAL   sample_val_delay : STD_LOGIC;
               -----------------------------------------------------------------------------
               CONSTANT Coef_SZ          : INTEGER := 9;
               CONSTANT CoefCntPerCel    : INTEGER := 6;
               CONSTANT CoefPerCel       : INTEGER := 5;
               CONSTANT Cels_count       : INTEGER := 5;
               --SIGNAL coefs                    : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL coefs_v2                 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
               SIGNAL sample_filter_in         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               --SIGNAL sample_filter_out        : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               --
               SIGNAL sample_filter_v2_out_sim     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_filter_v2_out_val : STD_LOGIC;
               SIGNAL sample_filter_v2_out     : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_data_shaping_out_val     : STD_LOGIC;
               SIGNAL sample_data_shaping_out         : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_data_shaping_f0_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_s        : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f1_f0_s     : STD_LOGIC_VECTOR(17 DOWNTO 0);
               SIGNAL sample_data_shaping_f2_f1_s     : STD_LOGIC_VECTOR(17 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_filter_v2_out_val_s      : STD_LOGIC;
               SIGNAL sample_filter_v2_out_s          : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               -----------------------------------------------------------------------------
             --  SIGNAL sample_f0_val                   : STD_LOGIC;
               SIGNAL sample_f0                       : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f0_s                     : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
               --
             --  SIGNAL sample_f1_val                   : STD_LOGIC;
               SIGNAL sample_f0_f1_s                  : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f1_s                     : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f1                       : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               --
             --  SIGNAL sample_f2_val                   : STD_LOGIC;
               SIGNAL sample_f2                       : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_s                 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_filter            : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f2_filter                : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f2_cic                   : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f2_cic_val               : STD_LOGIC;
               SIGNAL sample_f2_filter_val            : STD_LOGIC;
               SIGNAL sample_f3                       : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_s                 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_filter            : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f3_filter                : samplT(5 DOWNTO 0, 17 DOWNTO 0);
               SIGNAL sample_f3_cic                   : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_f3_cic_val               : STD_LOGIC;
               SIGNAL sample_f3_filter_val            : STD_LOGIC;
               -----------------------------------------------------------------------------
               --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f0_val_s : STD_LOGIC;
               SIGNAL sample_f1_val_s : STD_LOGIC;
               SIGNAL sample_f1_val_ss : STD_LOGIC;
               SIGNAL sample_f2_val_s : STD_LOGIC;
               SIGNAL sample_f3_val_s : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- CONFIG FILTER IIR f0 to f1
               -----------------------------------------------------------------------------
               CONSTANT f0_to_f1_CEL_NUMBER           : INTEGER := 5;
               CONSTANT f0_to_f1_COEFFICIENT_SIZE     : INTEGER := 10;
               CONSTANT f0_to_f1_POINT_POSITION       : INTEGER := 8;
               CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
                 (
                   (1.0, -1.61171504942096,  1.0, 1.0, -1.68876443778669,  0.908610171614583),
                   (1.0, -1.53324505744412,  1.0, 1.0, -1.51088513595779,  0.732564401274351),
                   (1.0, -1.30646173160060,  1.0, 1.0, -1.30571711968384,  0.546869268827102),
                   (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406,  0.358436944718464),
                   (1.0,  1.24322747034001,  1.0, 1.0, -0.929530176676438, 0.224862726961691)
                 );
               CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
                 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
               CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
                 :=  get_IIR_CEL_FILTER_CONFIG(
                   f0_to_f1_COEFFICIENT_SIZE,
                   f0_to_f1_POINT_POSITION,
                   f0_to_f1_CEL_NUMBER,
                   f0_to_f1_sos,
                   f0_to_f1_gain);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- CONFIG FILTER IIR f2 and f3
               -----------------------------------------------------------------------------
               CONSTANT f2_f3_CEL_NUMBER           : INTEGER := 5;
               CONSTANT f2_f3_COEFFICIENT_SIZE     : INTEGER := 10;
               CONSTANT f2_f3_POINT_POSITION       : INTEGER := 8;
               CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
                 (
                   (1.0, -1.61171504942096,  1.0, 1.0, -1.68876443778669,  0.908610171614583),
                   (1.0, -1.53324505744412,  1.0, 1.0, -1.51088513595779,  0.732564401274351),
                   (1.0, -1.30646173160060,  1.0, 1.0, -1.30571711968384,  0.546869268827102),
                   (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406,  0.358436944718464),
                   (1.0,  1.24322747034001,  1.0, 1.0, -0.929530176676438, 0.224862726961691)
                 );
               CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
                 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
               CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
                 :=  get_IIR_CEL_FILTER_CONFIG(
                   f2_f3_COEFFICIENT_SIZE,
                   f2_f3_POINT_POSITION,
                   f2_f3_CEL_NUMBER,
                   f2_f3_sos,
                   f2_f3_gain);
               -----------------------------------------------------------------------------
               SIGNAL sample_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f0_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f1_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f2_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f3_time_reg           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f0_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_f1_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL sample_f2_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL sample_f3_time_s           : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN              -- asynchronous reset (active low)
                   sample_val_delay <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_val_delay <= sample_val;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
                 SampleLoop : FOR j IN 0 TO 15 GENERATE
                   sample_filter_in(i, j) <= sample(i)(j);
                 END GENERATE;
                 sample_filter_in(i, 16) <= sample(i)(15);
                 sample_filter_in(i, 17) <= sample(i)(15);
               END GENERATE;
               coefs_v2 <= CoefsInitValCst_v2;
               IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => Coef_SZ,
                   Coef_Nb      => 25,
                   Coef_sel_SZ  => 5,
                   Cels_count   => Cels_count,
                   ChanelsCount => ChanelCount)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => 7,
                   coefs          => coefs_v2,
                   sample_in_val  => sample_val_delay,
                   sample_in      => sample_filter_in,
                   sample_out_val => sample_filter_v2_out_val,
                   sample_out     => sample_filter_v2_out);
               -- TIME --
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_time_reg           <= (OTHERS => '0');
                   sample_filter_v2_out_time <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF sample_val = '1' THEN
                     sample_time_reg <= sample_time;
                   END IF;
                   IF sample_filter_v2_out_val = '1' THEN
                     sample_filter_v2_out_time <= sample_time_reg;
                   END IF;
                 END IF;
               END PROCESS;
               ----------
               --for simulation/observation-------------------------------------------------
               ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE
                 all_bit: FOR J IN 0 TO 17 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN                  -- asynchronous reset (active low)
                       sample_filter_v2_out_sim(I,J) <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF sample_filter_v2_out_val = '1' THEN
                         sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J);
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_bit;
               END GENERATE ALL_channel_f0_sim;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- DATA_SHAPING
               -----------------------------------------------------------------------------
               all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
                 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
                 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
                 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
               END GENERATE all_data_shaping_in_loop;
               sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
               sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_data_shaping_out_val <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   sample_data_shaping_out_val <= sample_filter_v2_out_val;
                 END IF;
               END PROCESS;
               SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     sample_data_shaping_out(0, j) <= '0';
                     sample_data_shaping_out(1, j) <= '0';
                     sample_data_shaping_out(2, j) <= '0';
                     sample_data_shaping_out(3, j) <= '0';
                     sample_data_shaping_out(4, j) <= '0';
                     sample_data_shaping_out(5, j) <= '0';
                     sample_data_shaping_out(6, j) <= '0';
                     sample_data_shaping_out(7, j) <= '0';
                   ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                     sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
                     IF data_shaping_SP0 = '1' THEN
                       sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
                     ELSE
                       sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
                     END IF;
                     IF data_shaping_SP1 = '1' THEN
                       sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
                     ELSE
                       sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
                     END IF;
                     sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
                     sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
                     sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
                     sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
                     sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
                   END IF;
                 END PROCESS;
               END GENERATE;
               sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
               ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
                 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
                   sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
                 END GENERATE;
               END GENERATE;
               -----------------------------------------------------------------------------
               -- F0 -- @24.576 kHz
               -----------------------------------------------------------------------------
               Downsampling_f0 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 8,
                   SampleSize  => 16,
                   DivideParam => 4)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_filter_v2_out_val_s,
                   sample_in      => sample_filter_v2_out_s,
                   sample_out_val => sample_f0_val_s,
                   sample_out     => sample_f0);
               -- TIME --
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_f0_time_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN
                   IF sample_f0_val_s = '1' THEN
                     sample_f0_time_reg <= sample_filter_v2_out_time;
                   END IF;
                 END IF;
               END PROCESS;
               sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
               sample_f0_time   <= sample_f0_time_s;
               ----------
               sample_f0_val <= sample_f0_val_s;
               all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_wdata_s(I)      <= sample_f0(0, I);  -- V
                 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I);  -- E1
                 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I);  -- E2
                 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I);  -- B1
                 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I);  -- B2
                 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I);  -- B3
               END GENERATE all_bit_sample_f0;
               -----------------------------------------------------------------------------
               -- F1 -- @4096 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_f1_s(0,I) <=  sample_f0(0,I);  --V
                 sample_f0_f1_s(1,I) <=  sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
                 sample_f0_f1_s(2,I) <=  sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
                 sample_f0_f1_s(3,I) <=  sample_f0(5,I);  --B1
                 sample_f0_f1_s(4,I) <=  sample_f0(6,I);  --B2
                 sample_f0_f1_s(5,I) <=  sample_f0(7,I);  --B3
               END GENERATE all_bit_sample_f0_f1;
               all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
                 sample_f0_f1_s(0,I) <= sample_f0(0,15);
                 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
                 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
                 sample_f0_f1_s(3,I) <= sample_f0(5,15);  --B1
                 sample_f0_f1_s(4,I) <= sample_f0(6,15);  --B2
                 sample_f0_f1_s(5,I) <= sample_f0(7,15);  --B3
               END GENERATE all_bit_sample_f0_f1_extended;
               IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,          -- use_RAM
                   Sample_SZ    => 18,
                   Coef_SZ      => f0_to_f1_COEFFICIENT_SIZE,
                   Coef_Nb      => f0_to_f1_CEL_NUMBER*5,
                   Coef_sel_SZ  => 5,
                   Cels_count   => f0_to_f1_CEL_NUMBER,
                   ChanelsCount => 6)
                 PORT MAP (
                   rstn           => rstn,
                   clk            => clk,
                   virg_pos       => f0_to_f1_POINT_POSITION,
                   coefs          => coefs_iir_cel_f0_to_f1,
                   sample_in_val  => sample_f0_val_s,
                   sample_in      => sample_f0_f1_s,
                   sample_out_val => sample_f1_val_s,
                   sample_out     => sample_f1_s);
               Downsampling_f1 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 18,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f1_val_s,
                   sample_in      => sample_f1_s,
                   sample_out_val => sample_f1_val_ss,
                   sample_out     => sample_f1);
               sample_f1_val <= sample_f1_val_ss;
               -- TIME --
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_f1_time_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN
                   IF sample_f1_val_ss = '1' THEN
                     sample_f1_time_reg <= sample_f0_time_s;
                   END IF;
                 END IF;
               END PROCESS;
               sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
               sample_f1_time   <= sample_f1_time_s;
               ----------
               all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
                 END GENERATE all_channel_sample_f1;
               END GENERATE all_bit_sample_f1;
               -----------------------------------------------------------------------------
               -- F2 -- @256 Hz
               -- F3 -- @16 Hz
               -----------------------------------------------------------------------------
               all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
                 sample_f0_s(0, I) <= sample_f0(0, I);  -- V
                 sample_f0_s(1, I) <= sample_f0(1, I);  -- E1
                 sample_f0_s(2, I) <= sample_f0(2, I);  -- E2
                 sample_f0_s(3, I) <= sample_f0(5, I);  -- B1
                 sample_f0_s(4, I) <= sample_f0(6, I);  -- B2
                 sample_f0_s(5, I) <= sample_f0(7, I);  -- B3
                 sample_f0_s(6, I) <= sample_f0(3, I);  --
                 sample_f0_s(7, I) <= sample_f0(4, I);  --
               END GENERATE all_bit_sample_f0_s;
               cic_lfr_1: cic_lfr_r2
                 GENERIC MAP (
                   tech         => 0,
                   use_RAM_nCEL => Mem_use)
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   run                => '1',
                   param_r2           => data_shaping_R2,
                   data_in            => sample_f0_s,
                   data_in_valid      => sample_f0_val_s,
                   data_out_16        => sample_f2_cic,
                   data_out_16_valid  => sample_f2_cic_val,
                   data_out_256       => sample_f3_cic,
                   data_out_256_valid => sample_f3_cic_val);
               all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
                 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
                   sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
                   sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
                 END GENERATE all_bit_sample_f_cic;
                 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
                 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
                 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
                 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
               END GENERATE all_channel_sample_f_cic;
+              NO_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 1 GENERATE
-              IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
+                sample_f2_filter_val <= sample_f2_cic_val;
-                GENERIC MAP (
+                sample_f2_filter     <= sample_f2_cic_filter;
-                  tech         => 0,
+                sample_f3_filter_val <= sample_f3_cic_val;
-                  Mem_use      => Mem_use,
+                sample_f3_filter     <= sample_f3_cic_filter;
-                  Sample_SZ    => 18,
+              END GENERATE NO_IIR_FILTER_f2_f3;
-                  Coef_SZ      => f2_f3_COEFFICIENT_SIZE,
-                  Coef_Nb      => f2_f3_CEL_NUMBER*5,
-                  Coef_sel_SZ  => 5,
-                  Cels_count   => f2_f3_CEL_NUMBER,
-                  ChanelsCount => 6)
-                PORT MAP (
-                  rstn            => rstn,
-                  clk             => clk,
-                  virg_pos        => f2_f3_POINT_POSITION,
-                  coefs           => coefs_iir_cel_f2_f3,
-                  sample_in1_val  => sample_f2_cic_val,
+              YES_IIR_FILTER_f2_f3: IF RTL_DESIGN_LIGHT = 0 GENERATE
-                  sample_in1      => sample_f2_cic_filter,
+                IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
+                  GENERIC MAP (
-                  sample_in2_val  => sample_f3_cic_val,
+                    tech         => 0,
-                  sample_in2      => sample_f3_cic_filter,
+                    Mem_use      => Mem_use,
+                    Sample_SZ    => 18,
-                  sample_out1_val => sample_f2_filter_val,
+                    Coef_SZ      => f2_f3_COEFFICIENT_SIZE,
-                  sample_out1     => sample_f2_filter,
+                    Coef_Nb      => f2_f3_CEL_NUMBER*5,
-                  sample_out2_val => sample_f3_filter_val,
+                    Coef_sel_SZ  => 5,
-                  sample_out2     => sample_f3_filter);
+                    Cels_count   => f2_f3_CEL_NUMBER,
+                    ChanelsCount => 6)
+                  PORT MAP (
+                    rstn            => rstn,
+                    clk             => clk,
+                    virg_pos        => f2_f3_POINT_POSITION,
+                    coefs           => coefs_iir_cel_f2_f3,
+                    sample_in1_val  => sample_f2_cic_val,
+                    sample_in1      => sample_f2_cic_filter,
+                    sample_in2_val  => sample_f3_cic_val,
+                    sample_in2      => sample_f3_cic_filter,
+                    sample_out1_val => sample_f2_filter_val,
+                    sample_out1     => sample_f2_filter,
+                    sample_out2_val => sample_f3_filter_val,
+                    sample_out2     => sample_f3_filter);
+              END GENERATE YES_IIR_FILTER_f2_f3;
               all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
                 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
                   sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
                   sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
                 END GENERATE all_bit_sample_f_filter;
               END GENERATE all_channel_sample_f_filter;
               -----------------------------------------------------------------------------
               Downsampling_f2 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f2_filter_val ,
                   sample_in      => sample_f2_cic_s,
                   sample_out_val => sample_f2_val_s,
                   sample_out     => sample_f2);
               sample_f2_val <= sample_f2_val_s;
               all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
                 END GENERATE all_channel_sample_f2;
               END GENERATE all_bit_sample_f2;
               -----------------------------------------------------------------------------
               Downsampling_f3 : Downsampling
                 GENERIC MAP (
                   ChanelCount => 6,
                   SampleSize  => 16,
                   DivideParam => 6)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_in_val  => sample_f3_filter_val ,
                   sample_in      => sample_f3_cic_s,
                   sample_out_val => sample_f3_val_s,
                   sample_out     => sample_f3);
               sample_f3_val <= sample_f3_val_s;
               all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
                 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
                   sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
                 END GENERATE all_channel_sample_f3;
               END GENERATE all_bit_sample_f3;
               -----------------------------------------------------------------------------
               -- TIME --
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_f2_time_reg <= (OTHERS => '0');
                   sample_f3_time_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN
                   IF sample_f2_val_s = '1' THEN  sample_f2_time_reg <= sample_f0_time_s; END IF;
                   IF sample_f3_val_s = '1' THEN  sample_f3_time_reg <= sample_f0_time_s; END IF;
                 END IF;
               END PROCESS;
               sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
               sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
               ----------
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               sample_f0_wdata <= sample_f0_wdata_s;
               sample_f1_wdata <= sample_f1_wdata_s;
               sample_f2_wdata <= sample_f2_wdata_s;
               sample_f3_wdata <= sample_f3_wdata_s;
             END tb;

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +4 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
-                Mem_use : INTEGER := use_RAM
+                Mem_use : INTEGER := use_RAM;
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 run  : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 --fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 sample_f0_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 sample_f1_time  : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 sample_f2_time  : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
                 dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
                 dma_buffer_new      : OUT STD_LOGIC;                      --TODOx
                 dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
                 dma_buffer_full     : IN  STD_LOGIC;                      --TODO
                 dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
                 -- Reg out
                 ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
             --    error_bad_component_error : OUT STD_LOGIC;                  -- TODO
                 error_buffer_full         : OUT STD_LOGIC;                  -- TODO
                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
                 addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 length_matrix_f0                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f1                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f2                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);  -- TODO
                 ---------------------------------------------------------------------------
                 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
             --  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
               SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
               SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
               SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read                 : STD_LOGIC;
               SIGNAL fft_pong                 : STD_LOGIC;
               SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid           : STD_LOGIC;
               SIGNAL fft_data_valid_pre       : STD_LOGIC;
               SIGNAL fft_ready                : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty       : STD_LOGIC;
               SIGNAL current_fifo_locked      : STD_LOGIC;
               SIGNAL current_fifo_full        : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
               SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_correlation_start     : STD_LOGIC;
               SIGNAL SM_correlation_auto      : STD_LOGIC;
               SIGNAL SM_correlation_done      : STD_LOGIC;
               SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
               SIGNAL SM_correlation_begin     : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
               SIGNAL current_matrix_write      : STD_LOGIC;
               SIGNAL current_matrix_wait_empty : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_0_ready              : STD_LOGIC;
               SIGNAL fifo_1_ready              : STD_LOGIC;
               SIGNAL fifo_ongoing              : STD_LOGIC;
               SIGNAL fifo_ongoing_reg          : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty_Threshold    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
               SIGNAL all_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_reg_f    : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --SIGNAL time_update_f0_A : STD_LOGIC;
               --SIGNAL time_update_f0_B : STD_LOGIC;
               --SIGNAL time_update_f1   : STD_LOGIC;
               --SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
               SIGNAL fft_ready_reg         : STD_LOGIC;
               SIGNAL fft_ready_rising_down : STD_LOGIC;
               SIGNAL sample_load_reg         : STD_LOGIC;
               SIGNAL sample_load_rising_down : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_f1_wen_head     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_head_in  : STD_LOGIC;
               SIGNAL sample_f1_wen_head_out : STD_LOGIC;
               SIGNAL sample_f1_full_head_in : STD_LOGIC;
               SIGNAL sample_f1_full_head_out : STD_LOGIC;
               SIGNAL sample_f1_empty_head_in : STD_LOGIC;
               SIGNAL sample_f1_wdata_head   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL ongoing : STD_LOGIC;
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_f0_wen_s <= (OTHERS => '1');
                   sample_f1_wen_s <= (OTHERS => '1');
                   sample_f2_wen_s <= (OTHERS => '1');
                   ongoing <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF ongoing = '1' THEN
                     sample_f0_wen_s <= sample_f0_wen;
                     sample_f1_wen_s <= sample_f1_wen;
                     sample_f2_wen_s <= sample_f2_wen;
                   ELSE
                     IF start_date = coarse_time(30 DOWNTO 0) THEN
                       ongoing <= '1';
                     END IF;
                     sample_f0_wen_s <= (OTHERS => '1');
                     sample_f1_wen_s <= (OTHERS => '1');
                     sample_f2_wen_s <= (OTHERS => '1');
                   END IF;
                 END IF;
               END PROCESS;
               error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen_s,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen   => sample_f0_A_wen,
                   wdata => sample_f0_wdata,
                   ren   => sample_f0_A_ren,
                   rdata => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               -- sample_f1_wen   in
               -- sample_f1_wdata in
               -- sample_f1_full  OUT
               sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
               sample_f1_full_head_in  <= '0' WHEN sample_f1_full  = "00000" ELSE '1';
               sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
               lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   in_wen   => sample_f1_wen_head_in,
                   in_data  => sample_f1_wdata,
                   in_full  => sample_f1_full_head_in,
                   in_empty => sample_f1_empty_head_in,
                   out_write_error => error_wen_f1,
                   out_wen  => sample_f1_wen_head_out,
                   out_data => sample_f1_wdata_head,
                   out_full => sample_f1_full_head_out);
               sample_f1_wen_head    <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f1_wen_head,
                   wdata       => sample_f1_wdata_head,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   --error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f2_wen_s,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
                   select_channel <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
                         select_channel <= "10";
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
                           select_channel <= "00";
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
                           select_channel <= "01";
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
                           select_channel <= "11";
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   select_channel_reg <= (OTHERS => '0');
                   --pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_channel_reg <= select_channel;
                   --pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
               --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
               --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
               --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
               --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
                               sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
                               sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
                             sample_ren_s    WHEN sample_load = '1' ELSE
                             (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
                   select_fifo        <= "000";
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         sample_ren_s       <= "11111";
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
                         select_fifo        <= "000";
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s            <= "11111";
                         state_fsm_load_FFT      <= WAIT_STATE;
                         next_state_fsm_load_FFT <= FIFO_2;
                         select_fifo <= "001";
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s            <= "11111";
                         state_fsm_load_FFT      <= WAIT_STATE;
                         next_state_fsm_load_FFT <= FIFO_3;
                         select_fifo <= "010";
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s            <= "11111";
                         state_fsm_load_FFT      <= WAIT_STATE;
                         next_state_fsm_load_FFT  <= FIFO_4;
                         select_fifo <= "011";
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s            <= "11111";
                         state_fsm_load_FFT      <= WAIT_STATE;
                         next_state_fsm_load_FFT <= FIFO_5;
                         select_fifo <= "100";
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s            <= (OTHERS => '1');
                         state_fsm_load_FFT      <= WAIT_STATE;
                         next_state_fsm_load_FFT <= IDLE;
                         --state_fsm_load_FFT <= IDLE;
                         select_fifo <= "000";
                       END IF;
                     WHEN WAIT_STATE =>
                       sample_ren_s       <= (OTHERS => '1');
                       IF sample_load = '1' THEN
                         state_fsm_load_FFT <= WAIT_STATE_2 ;
                       END IF;
                     WHEN WAIT_STATE_2 =>
                       sample_ren_s       <= (OTHERS => '1');
                       IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
                         state_fsm_load_FFT <= next_state_fsm_load_FFT;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                    -- asynchronous reset (active low)
                   fft_data_valid_pre <= '0';
                 ELSIF clk'event AND clk = '1' THEN    -- rising clock edge
                   fft_data_valid_pre <= fft_data_valid;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
                   select_fifo_reg <= (OTHERS => '0');
                   --next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_fifo_reg <= select_fifo;
                   --next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
               --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
               --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
               --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
               --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
               --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
                              sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
                              sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
                              sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
+                GENERIC MAP (
+                  WINDOWS_HAANNING_PARAM_SIZE => WINDOWS_HAANNING_PARAM_SIZE)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_valid   => sample_valid,
                   fft_read       => fft_read,
                   sample_data    => sample_data,
                   sample_load    => sample_load,
                   fft_pong       => fft_pong,
                   fft_data_im    => fft_data_im,
                   fft_data_re    => fft_data_re,
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
               debug_vector(0) <= fft_data_valid;
               debug_vector(1) <= fft_ready;
               debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
               -----------------------------------------------------------------------------
               fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
               sample_load_rising_down <= sample_load_reg AND NOT sample_load;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fft_ready_reg     <= '0';
                   sample_load_reg   <= '0';
                   fft_ongoing_counter <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   fft_ready_reg    <= fft_ready;
                   sample_load_reg  <= sample_load;
                   IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
                     fft_ongoing_counter <= '0';
             --        CASE fft_ongoing_counter IS
             --          WHEN "01" => fft_ongoing_counter <= "00";
             ----          WHEN "10" => fft_ongoing_counter <= "01";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
                     fft_ongoing_counter <= '1';
             --        CASE fft_ongoing_counter IS
             --          WHEN "00" => fft_ongoing_counter <= "01";
             ----          WHEN "01" => fft_ongoing_counter <= "10";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load        <= "00001";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                    MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                    MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                    MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                    MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
                 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                       AND state_fsm_load_MS_memory = LOAD_FIFO
                                       AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,                    --16,
                   Addr_sz => 7,                     --8
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   run   => (OTHERS => '1'),
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren         => MEM_IN_SM_ren,
                   rdata       => MEM_IN_SM_rData,
                   full        => MEM_IN_SM_Full,
                   empty       => MEM_IN_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               MS_control_1 : MS_control
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   current_status_ms => status_MS_input,
                   fifo_in_lock  => MEM_IN_SM_locked,
                   fifo_in_data  => MEM_IN_SM_rdata,
                   fifo_in_full  => MEM_IN_SM_Full,
                   fifo_in_empty => MEM_IN_SM_Empty,
                   fifo_in_ren   => MEM_IN_SM_ren,
                   fifo_in_reuse => MEM_IN_SM_ReUse,
                   fifo_out_data  => SM_in_data,
                   fifo_out_ren   => SM_in_ren,
                   fifo_out_empty => SM_in_empty,
                   current_status_component => status_component,
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_done  => SM_correlation_done);
               MS_calculation_1 : MS_calculation
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   fifo_in_data  => SM_in_data,
                   fifo_in_ren   => SM_in_ren,
                   fifo_in_empty => SM_in_empty,
                   fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
                   fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
                   fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_begin => SM_correlation_begin,
                   correlation_done  => SM_correlation_done);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_matrix_write        <= '0';
                   current_matrix_wait_empty   <= '1';
                   status_component_fifo_0     <= (OTHERS => '0');
                   status_component_fifo_1     <= (OTHERS => '0');
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   SM_correlation_done_reg1    <= '0';
                   SM_correlation_done_reg2    <= '0';
                   SM_correlation_done_reg3    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   SM_correlation_done_reg1    <= SM_correlation_done;
                   SM_correlation_done_reg2    <= SM_correlation_done_reg1;
                   SM_correlation_done_reg3    <= SM_correlation_done_reg2;
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0 <= status_component(53 DOWNTO 4);
                     ELSE
                       status_component_fifo_1 <= status_component(53 DOWNTO 4);
                     END IF;
                   END IF;
                   IF SM_correlation_done_reg3 = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0_end <= '1';
                     ELSE
                       status_component_fifo_1_end <= '1';
                     END IF;
                     current_matrix_wait_empty <= '1';
                     current_matrix_write      <= NOT current_matrix_write;
                   END IF;
                   IF current_matrix_wait_empty <= '1' THEN
                     IF current_matrix_write = '0' THEN
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
                     ELSE
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
                                    '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                                    '1'                WHEN current_matrix_wait_empty = '1' ELSE
                                    MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                                    MEM_OUT_SM_Full(1);
               MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
               MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
               MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
               -----------------------------------------------------------------------------
               --Mem_Out_SpectralMatrix : lppFIFOxN
               --  GENERIC MAP (
               --    tech    => 0,
               --    Mem_use => Mem_use,
               --    Data_sz => 32,
               --    Addr_sz => 8,
               --    FifoCnt => 2)
               --  PORT MAP (
               --    clk  => clk,
               --    rstn => rstn,
               --    ReUse => (OTHERS => '0'),
               --    run   => (OTHERS => '1'),
               --    wen   => MEM_OUT_SM_Write,
               --    wdata => MEM_OUT_SM_Data_in,
               --    ren   => MEM_OUT_SM_Read,
               --    rdata => MEM_OUT_SM_Data_out,
               --    full        => MEM_OUT_SM_Full,
               --    empty       => MEM_OUT_SM_Empty,
               --    almost_full => OPEN);
               all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
                 Mem_Out_SpectralMatrix_I: lpp_fifo
                   GENERIC MAP (
                     tech                  => 0,
                     Mem_use               => Mem_use,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 1,
                     DataSz                => 32,
                     AddrSz                => 8)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => MEM_OUT_SM_Read(I),
                     rdata           => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
                     wen             => MEM_OUT_SM_Write(I),
                     wdata           => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
                     empty           => MEM_OUT_SM_Empty(I),
                     full            => MEM_OUT_SM_Full(I),
                     full_almost     => OPEN,
                     empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
                     full_threshold  => OPEN);
               END GENERATE all_Mem_Out_SpectralMatrix;
               -----------------------------------------------------------------------------
             --  MEM_OUT_SM_Read <= "00";
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fifo_0_ready <= '0';
                   fifo_1_ready <= '0';
                   fifo_ongoing <= '0';
                   fifo_ongoing_reg <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   fifo_ongoing_reg <= fifo_ongoing;
                   IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
                     fifo_ongoing <= '1';
                     fifo_0_ready <= '0';
                   ELSIF status_component_fifo_0_end = '1' THEN
                     fifo_0_ready <= '1';
                   END IF;
                   IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
                     fifo_ongoing <= '0';
                     fifo_1_ready <= '0';
                   ELSIF status_component_fifo_1_end = '1' THEN
                     fifo_1_ready <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                                     '1' WHEN fifo_0_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
                                     '1' WHEN fifo_1_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
                                     MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                                     '1';
               FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
                                      status_component_fifo_1;
               FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing_reg = '0' ELSE
                                    MEM_OUT_SM_Data_out(63 DOWNTO 32);
               FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1'  ELSE
                                               MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1'  ELSE
                                               '1';
               -----------------------------------------------------------------------------
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),       --IN
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),       --IN
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),      --IN
               --    fifo_data             => FSM_DMA_fifo_data,                     --IN
               --    fifo_empty            => FSM_DMA_fifo_empty,                    --IN
               --    fifo_empty_threshold  => FSM_DMA_fifo_empty_threshold,          --IN
               --    fifo_ren              => FSM_DMA_fifo_ren,                      --OUT
               lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   fifo_matrix_type       => FSM_DMA_fifo_status(5 DOWNTO 4),
                   fifo_matrix_time       => FSM_DMA_fifo_status(53 DOWNTO 6),
                   fifo_data              => FSM_DMA_fifo_data,
                   fifo_empty             => FSM_DMA_fifo_empty,
                   fifo_empty_threshold   => FSM_DMA_fifo_empty_threshold,
                   fifo_ren               => FSM_DMA_fifo_ren,
                   dma_fifo_valid_burst   => dma_fifo_burst_valid,
                   dma_fifo_data          => dma_fifo_data,
                   dma_fifo_ren           => dma_fifo_ren,
                   dma_buffer_new         => dma_buffer_new,
                   dma_buffer_addr        => dma_buffer_addr,
                   dma_buffer_length      => dma_buffer_length,
                   dma_buffer_full        => dma_buffer_full,
                   dma_buffer_full_err    => dma_buffer_full_err,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0       => length_matrix_f0,
                   length_matrix_f1       => length_matrix_f1,
                   length_matrix_f2       => length_matrix_f2,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   matrix_time_f0         => matrix_time_f0,
                   matrix_time_f1         => matrix_time_f1,
                   matrix_time_f2         => matrix_time_f2,
                   error_buffer_full      => error_buffer_full);
               --dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
               --dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
               --dma_buffer_new      : OUT STD_LOGIC;                      --TODO
               --dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
               --dma_buffer_full     : IN  STD_LOGIC;                      --TODO
               --dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
               ---- Reg out
               --ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
               --error_bad_component_error : OUT STD_LOGIC;                  -- TODO
               --error_buffer_full         : OUT STD_LOGIC;                  -- TODO
               ---- Reg In
               --status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
               --addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
               --  PORT MAP (
               --    HCLK    => clk,
               --    HRESETn => rstn,
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
               --    fifo_data             => FSM_DMA_fifo_data,
               --    fifo_empty            => FSM_DMA_fifo_empty,
               --    fifo_ren              => FSM_DMA_fifo_ren,
               --    dma_addr        => dma_addr,
               --    dma_data        => dma_data,
               --    dma_valid       => dma_valid,
               --    dma_valid_burst => dma_valid_burst,
               --    dma_ren         => dma_ren,
               --    dma_done        => dma_done,
               --    ready_matrix_f0 => ready_matrix_f0,
               --    ready_matrix_f1 => ready_matrix_f1,
               --    ready_matrix_f2 => ready_matrix_f2,
               --    error_bad_component_error => error_bad_component_error,
               --    error_buffer_full         => error_buffer_full,
               --    debug_reg              => debug_reg,
               --    status_ready_matrix_f0 => status_ready_matrix_f0,
               --    status_ready_matrix_f1 => status_ready_matrix_f1,
               --    status_ready_matrix_f2 => status_ready_matrix_f2,
               --    config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
               --    config_active_interruption_onError     => config_active_interruption_onError,
               --    addr_matrix_f0 => addr_matrix_f0,
               --    addr_matrix_f1 => addr_matrix_f1,
               --    addr_matrix_f2 => addr_matrix_f2,
               --    matrix_time_f0 => matrix_time_f0,
               --    matrix_time_f1 => matrix_time_f1,
               --    matrix_time_f2 => matrix_time_f2
               --    );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
               all_time <= sample_f2_time & sample_f1_time & sample_f0_time & sample_f0_time;
               --all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
               f_empty(2) <= '1' WHEN sample_f1_empty   = "11111" ELSE '0';
               f_empty(3) <= '1' WHEN sample_f2_empty   = "11111" ELSE '0';
               all_time_reg: FOR I IN 0 TO 3 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     f_empty_reg(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN
                     f_empty_reg(I) <= f_empty(I);
                   END IF;
                 END PROCESS;
                 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
                 s_m_t_m_f0_A : spectral_matrix_time_managment
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
                     time_in  => all_time((I+1)*48-1 DOWNTO I*48),
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_time_reg;
               time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
               time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
               time_reg_f1   <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
               time_reg_f2   <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd +21 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             USE lpp.window_function_pkg.ALL;
             ENTITY lpp_lfr_ms_FFT IS
+              GENERIC (
+                WINDOWS_HAANNING_PARAM_SIZE : INTEGER := 15
+                );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 -- IN
                 sample_valid : IN STD_LOGIC;
                 fft_read     : IN STD_LOGIC;
                 sample_data  : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
                 sample_load  : OUT STD_LOGIC;
                 --OUT
                 fft_pong       : OUT STD_LOGIC;
                 fft_data_im    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                 fft_data_re    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                 fft_data_valid : OUT STD_LOGIC;
                 fft_ready      : OUT STD_LOGIC
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS
               SIGNAL data_win       : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_win_valid : STD_LOGIC;
+              SIGNAL data_in_reg       : STD_LOGIC_VECTOR(15 DOWNTO 0);
+              SIGNAL data_in_reg_valid : STD_LOGIC;
             BEGIN
+              PROCESS (clk, rstn)
+              BEGIN  -- PROCESS
+                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                  data_in_reg       <= (OTHERS => '0');
+                  data_in_reg_valid <= '0';
+                ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
+                  data_in_reg       <= sample_data;
+                  data_in_reg_valid <= sample_valid;
+                END IF;
+              END PROCESS;
               window_hanning: window_function
                 GENERIC MAP (
                   SIZE_DATA          => 16,
-                  SIZE_PARAM         => 15,
+                  SIZE_PARAM         => WINDOWS_HAANNING_PARAM_SIZE,
                   NB_POINT_BY_WINDOW => 256)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   restart_window => '0',
-                  data_in        => sample_data,
+                  data_in        => data_in_reg,
-                  data_in_valid  => sample_valid,
+                  data_in_valid  => data_in_reg_valid,
                   data_out       => data_win,
                   data_out_valid => data_win_valid);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               CoreFFT_1 : CoreFFT
                 GENERIC MAP (
                   LOGPTS      => gLOGPTS,
                   LOGLOGPTS   => gLOGLOGPTS,
                   WSIZE       => gWSIZE,
                   TWIDTH      => gTWIDTH,
                   DWIDTH      => gDWIDTH,
                   TDWIDTH     => gTDWIDTH,
                   RND_MODE    => gRND_MODE,
                   SCALE_MODE  => gSCALE_MODE,
                   PTS         => gPTS,
                   HALFPTS     => gHALFPTS,
                   inBuf_RWDLY => gInBuf_RWDLY)
                 PORT MAP (
                   clk       => clk,
                   ifiStart  => '0',                 -- '1'
                   ifiNreset => rstn,
                   ifiD_valid => data_win_valid,       -- IN
                   ifiRead_y  => fft_read,
                   ifiD_im    => (OTHERS => '0'),    -- IN
                   ifiD_re    => data_win,        -- IN
                   ifoLoad    => sample_load,        -- IN
                   ifoPong    => fft_pong,
                   ifoY_im    => fft_data_im,
                   ifoY_re    => fft_data_re,
                   ifoY_valid => fft_data_valid,
                   ifoY_rdy   => fft_ready);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +10 -3

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_lfr_pkg IS
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms_test
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   clk  : IN STD_LOGIC;
                   rstn : IN STD_LOGIC;
                   -- TIME
                   coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                   fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                   --
                   sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   --
                   sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   --
                   sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   ---------------------------------------------------------------------------
                   error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   --
                   --sample_ren   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                   --sample_full  : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                   --sample_empty : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
                   -- IN
                   MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                   -----------------------------------------------------------------------------
                   status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
                   SM_in_data       : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
                   SM_in_ren        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   SM_in_empty      : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   SM_correlation_start : OUT STD_LOGIC;
                   SM_correlation_auto  : OUT STD_LOGIC;
                   SM_correlation_done  : IN  STD_LOGIC
                   );
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms
                 GENERIC (
-                  Mem_use : INTEGER);
+                  Mem_use : INTEGER;
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   start_date             : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   coarse_time            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   sample_f0_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f0_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f1_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f1_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f2_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f2_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f2_time         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   dma_fifo_burst_valid   : OUT STD_LOGIC;
                   dma_fifo_data          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren           : IN  STD_LOGIC;
                   dma_buffer_new         : OUT STD_LOGIC;
                   dma_buffer_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length      : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full        : IN  STD_LOGIC;
                   dma_buffer_full_err    : IN  STD_LOGIC;
                   ready_matrix_f0        : OUT STD_LOGIC;
                   ready_matrix_f1        : OUT STD_LOGIC;
                   ready_matrix_f2        : OUT STD_LOGIC;
                   error_buffer_full      : OUT STD_LOGIC;
                   error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   status_ready_matrix_f0 : IN  STD_LOGIC;
                   status_ready_matrix_f1 : IN  STD_LOGIC;
                   status_ready_matrix_f2 : IN  STD_LOGIC;
                   addr_matrix_f0         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   matrix_time_f0         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   debug_vector           : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_fsmdma
                 PORT (
                   clk                    : IN  STD_ULOGIC;
                   rstn                   : IN  STD_ULOGIC;
                   run                    : IN  STD_LOGIC;
                   fifo_matrix_type       : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   fifo_matrix_time       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty             : IN  STD_LOGIC;
                   fifo_empty_threshold   : IN  STD_LOGIC;
                   fifo_ren               : OUT STD_LOGIC;
                   dma_fifo_valid_burst   : OUT STD_LOGIC;
                   dma_fifo_data          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren           : IN  STD_LOGIC;
                   dma_buffer_new         : OUT STD_LOGIC;
                   dma_buffer_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length      : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full        : IN  STD_LOGIC;
                   dma_buffer_full_err    : IN  STD_LOGIC;
                   status_ready_matrix_f0 : IN  STD_LOGIC;
                   status_ready_matrix_f1 : IN  STD_LOGIC;
                   status_ready_matrix_f2 : IN  STD_LOGIC;
                   addr_matrix_f0         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_matrix_f0        : OUT STD_LOGIC;
                   ready_matrix_f1        : OUT STD_LOGIC;
                   ready_matrix_f2        : OUT STD_LOGIC;
                   matrix_time_f0         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error_buffer_full      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_lfr_ms_FFT
+                GENERIC (
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_valid   : IN  STD_LOGIC;
                   fft_read       : IN  STD_LOGIC;
                   sample_data    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_load    : OUT STD_LOGIC;
                   fft_pong       : OUT STD_LOGIC;
                   fft_data_im    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_re    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_valid : OUT STD_LOGIC;
                   fft_ready      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_lfr_filter
                 GENERIC (
-                  Mem_use : INTEGER);
+                  Mem_use                 : INTEGER;
+                  RTL_DESIGN_LIGHT        : INTEGER
+                  );
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   sample_time      : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   data_shaping_SP1 : IN  STD_LOGIC;
                   data_shaping_R0  : IN  STD_LOGIC;
                   data_shaping_R1  : IN  STD_LOGIC;
                   data_shaping_R2  : IN  STD_LOGIC;
                   sample_f0_val    : OUT STD_LOGIC;
                   sample_f1_val    : OUT STD_LOGIC;
                   sample_f2_val    : OUT STD_LOGIC;
                   sample_f3_val    : OUT STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f0_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f1_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f2_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   sample_f3_time   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_lfr
                 GENERIC (
                   Mem_use                : INTEGER;
                   tech                   : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
             --      nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0);
-                  DEBUG_FORCE_DATA_DMA   : INTEGER
+                  DEBUG_FORCE_DATA_DMA   : INTEGER;
+                  RTL_DESIGN_LIGHT       : INTEGER;
+                  WINDOWS_HAANNING_PARAM_SIZE : INTEGER
                   );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   debug_vector    : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
                   debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                   );
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_WFP_nMS
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_apbreg
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   HCLK                    : IN  STD_ULOGIC;
                   HRESETn                 : IN  STD_ULOGIC;
                   apbi                    : IN  apb_slv_in_type;
                   apbo                    : OUT apb_slv_out_type;
             --      run_ms                  : OUT STD_LOGIC;
                   ready_matrix_f0         : IN  STD_LOGIC;
                   ready_matrix_f1         : IN  STD_LOGIC;
                   ready_matrix_f2         : IN  STD_LOGIC;
                   error_buffer_full       : IN  STD_LOGIC;
                   error_input_fifo_write  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
                   status_ready_matrix_f0  : OUT STD_LOGIC;
                   status_ready_matrix_f1  : OUT STD_LOGIC;
                   status_ready_matrix_f2  : OUT STD_LOGIC;
                   addr_matrix_f0          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   matrix_time_f0          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   status_new_err          : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW         : OUT STD_LOGIC;
                   data_shaping_SP0        : OUT STD_LOGIC;
                   data_shaping_SP1        : OUT STD_LOGIC;
                   data_shaping_R0         : OUT STD_LOGIC;
                   data_shaping_R1         : OUT STD_LOGIC;
                   data_shaping_R2         : OUT STD_LOGIC;
                   delta_snapshot          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0_2              : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   delta_f1                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f2                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   nb_data_by_buffer       : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param       : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0               : OUT STD_LOGIC;
                   enable_f1               : OUT STD_LOGIC;
                   enable_f2               : OUT STD_LOGIC;
                   enable_f3               : OUT STD_LOGIC;
                   burst_f0                : OUT STD_LOGIC;
                   burst_f1                : OUT STD_LOGIC;
                   burst_f2                : OUT STD_LOGIC;
                   run                     : OUT STD_LOGIC;
                   start_date              : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   wfp_ready_buffer        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wfp_buffer_time         : IN  STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                   wfp_error_buffer_full   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   sample_f3_v             : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_f3_e1            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_f3_e2            : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_f3_valid         : IN  STD_LOGIC;
                   debug_vector            : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_ms
                 GENERIC (
                   Mem_use                 : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq_ms                 : INTEGER;
                   pirq_wfp                : INTEGER;
                   hindex_wfp              : INTEGER;
                   hindex_ms               : INTEGER);
                 PORT (
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   sample_B         : IN  Samples14v(2 DOWNTO 0);
                   sample_E         : IN  Samples14v(4 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   apbi             : IN  apb_slv_in_type;
                   apbo             : OUT apb_slv_out_type;
                   ahbi_ms          : IN  AHB_Mst_In_Type;
                   ahbo_ms          : OUT AHB_Mst_Out_Type;
                   data_shaping_BW  : OUT STD_LOGIC;
                   matrix_time_f0_0 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1 : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1   : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2   : IN  STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_apbreg_ms_pointer
                 PORT (
                   clk                      : IN  STD_LOGIC;
                   rstn                     : IN  STD_LOGIC;
                   run                      : IN  STD_LOGIC;
                   reg0_status_ready_matrix : IN  STD_LOGIC;
                   reg0_ready_matrix        : OUT STD_LOGIC;
                   reg0_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg0_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   reg1_status_ready_matrix : IN  STD_LOGIC;
                   reg1_ready_matrix        : OUT STD_LOGIC;
                   reg1_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg1_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   ready_matrix             : IN  STD_LOGIC;
                   status_ready_matrix      : OUT STD_LOGIC;
                   addr_matrix              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time              : IN  STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_reg_head
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   in_wen          : IN  STD_LOGIC;
                   in_data         : IN  STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   in_full         : IN  STD_LOGIC;
                   in_empty        : IN  STD_LOGIC;
                   out_write_error : OUT STD_LOGIC;
                   out_wen         : OUT STD_LOGIC;
                   out_data        : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   out_full        : OUT STD_LOGIC);
               END COMPONENT;
             END lpp_lfr_pkg;

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