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1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_uart_Driver.h"
5
6
7 int main()
8 {
9 int i=0;
10 int data;
11 char temp[256];
12
13 int TblSinA[256] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255} ;
14 int TblSinAB[256] = {255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129,128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0} ;
15 int TblSinB[256] = {100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100} ;
16 int TblSinBC[256] = {128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,244,245,246,247,248,249,250,251,252,253,254,255,256,255,254,253,252,251,250,249,248,247,246,245,244,243,242,241,240,239,238,237,236,235,234,233,232,231,230,229,228,227,226,225,224,223,222,221,220,219,218,217,216,215,214,213,212,211,210,209,208,207,206,205,204,203,202,201,200,199,198,197,196,195,194,193,192,191,190,189,188,187,186,185,184,183,182,181,180,179,178,177,176,175,174,173,172,171,170,169,168,167,166,165,164,163,162,161,160,159,158,157,156,155,154,153,152,151,150,149,148,147,146,145,144,143,142,141,140,139,138,137,136,135,134,133,132,131,130,129} ;
17 int TblSinC[256] = {128,127,126,125,124,123,122,121,120,119,118,117,116,115,114,113,112,111,110,109,108,107,106,105,104,103,102,101,100,99,98,97,96,95,94,93,92,91,90,89,88,87,86,85,84,83,82,81,80,79,78,77,76,75,74,73,72,71,70,69,68,67,66,65,64,63,62,61,60,59,58,57,56,55,54,53,52,51,50,49,48,47,46,45,44,43,42,41,40,39,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127} ;
18
19 UART_Device* uart0 = openUART(0);
20 FIFO_Device* fifotry = openFIFO(0);
21 FIFO_Device* fifoIn = openFIFO(1);
22 FIFO_Device* fifoOut = openFIFO(2);
23
24 printf("\nDebut Main\n\n");
25
26 FillFifo(fifoIn,0,TblSinA,256);
27 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
28
29 FillFifo(fifoIn,1,TblSinAB,256);
30 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
31
32 FillFifo(fifoIn,2,TblSinB,256);
33 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
34
35 FillFifo(fifoIn,3,TblSinBC,256);
36 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
37
38 FillFifo(fifoIn,4,TblSinC,256);
39 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
40
41
42 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
43 printf("\nFull 1\n");
44 while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
45 printf("\nFull 2\n");
46
47 while(1){
48
49 sprintf(temp,"PONG A\n\r");
50 uartputs(uart0,temp);
51
52 while(i<257){
53 data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]);
54 i++;
55 sprintf(temp,"%d\n\r",data);
56 uartputs(uart0,temp);
57 }
58
59 i=0;
60 sprintf(temp,"PONG B\n\r");
61 uartputs(uart0,temp);
62
63 while(i<257){
64 data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]);
65 i++;
66 sprintf(temp,"%d\n\r",data);
67 uartputs(uart0,temp);
68 }
69
70 i=0;
71 }
72 printf("\nFin Main\n\n");
73 return 0;
74 }
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1 #GRLIB=../..
2 TOP=leon3mp
3 BOARD=Projet-LeonLFR-A3P3K-Sheldon
4 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
5 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
6 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
7 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
8 EFFORT=high
9 XSTOPT=
10 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
11 VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd Top_Data_Acquisition.vhd
12 VHDLSIMFILES=testbench.vhd TB_Data_Acquisition.vhd
13 SIMTOP=testbench
14 SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
15 SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
16 PDC=$(GRLIB)/boards/$(BOARD)/Projet-LeonLFR-A3P3K-Sheldon.pdc
17 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
18 CLEAN=soft-clean
19
20 TECHLIBS = proasic3
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
23 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 pci grusbhc haps slink ascs pwm coremp7 spi ac97
25
26 FILESKIP = i2cmst.vhd
27
28 #TECHLIBS = unisim
29 include $(GRLIB)/bin/Makefile
30 include $(GRLIB)/software/leon3/Makefile
31
32 my-clean: clean
33 -rm -rf *~
34
35 ################## project specific targets ##########################
36
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 library ieee;
22 use ieee.std_logic_1164.all;
23 library grlib;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library gaisler;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
33 library esa;
34 use esa.memoryctrl.all;
35 use work.config.all;
36 library lpp;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
48
49 entity leon3mp is
50 generic (
51 fabtech : integer := CFG_FABTECH;
52 memtech : integer := CFG_MEMTECH;
53 padtech : integer := CFG_PADTECH;
54 clktech : integer := CFG_CLKTECH;
55 disas : integer := CFG_DISAS; -- Enable disassembly to console
56 dbguart : integer := CFG_DUART; -- Print UART on console
57 pclow : integer := CFG_PCLOW
58 );
59 port (
60 clk50MHz : in std_ulogic;
61 reset : in std_ulogic;
62 ramclk : out std_logic;
63
64 ahbrxd : in std_ulogic; -- DSU rx data
65 ahbtxd : out std_ulogic; -- DSU tx data
66 dsubre : in std_ulogic;
67 dsuact : out std_ulogic;
68 urxd1 : in std_ulogic; -- UART1 rx data
69 utxd1 : out std_ulogic; -- UART1 tx data
70 errorn : out std_ulogic;
71
72 address : out std_logic_vector(18 downto 0);
73 data : inout std_logic_vector(31 downto 0);
74 gpio : inout std_logic_vector(6 downto 0); -- I/O port
75
76 nBWa : out std_logic;
77 nBWb : out std_logic;
78 nBWc : out std_logic;
79 nBWd : out std_logic;
80 nBWE : out std_logic;
81 nADSC : out std_logic;
82 nADSP : out std_logic;
83 nADV : out std_logic;
84 nGW : out std_logic;
85 nCE1 : out std_logic;
86 CE2 : out std_logic;
87 nCE3 : out std_logic;
88 nOE : out std_logic;
89 MODE : out std_logic;
90 SSRAM_CLK : out std_logic;
91 ZZ : out std_logic;
92 ---------------------------------------------------------------------
93 --- AJOUT TEST ------------------------In/Out-----------------------
94 ---------------------------------------------------------------------
95 -- UART
96 UART_RXD : in std_logic;
97 UART_TXD : out std_logic;
98 -- ADC
99 -- ADC_in : in AD7688_in(4 downto 0);
100 -- ADC_out : out AD7688_out;
101 -- Bias_Fails : out std_logic;
102 -- CNA
103 -- DAC_SYNC : out std_logic;
104 -- DAC_SCLK : out std_logic;
105 -- DAC_DATA : out std_logic;
106 -- Diver
107 SPW1_EN : out std_logic;
108 SPW2_EN : out std_logic;
109 TEST : out std_logic_vector(3 downto 0);
110
111 BP : in std_logic;
112 ---------------------------------------------------------------------
113 led : out std_logic_vector(1 downto 0)
114 );
115 end;
116
117 architecture Behavioral of leon3mp is
118
119 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
120 CFG_GRETH+CFG_AHB_JTAG;
121 constant maxahbm : integer := maxahbmsp;
122
123 --Clk & Rst g�n�
124 signal vcc : std_logic_vector(4 downto 0);
125 signal gnd : std_logic_vector(4 downto 0);
126 signal resetnl : std_ulogic;
127 signal clk2x : std_ulogic;
128 signal lclk : std_ulogic;
129 signal lclk2x : std_ulogic;
130 signal clkm : std_ulogic;
131 signal rstn : std_ulogic;
132 signal rstraw : std_ulogic;
133 signal pciclk : std_ulogic;
134 signal sdclkl : std_ulogic;
135 signal cgi : clkgen_in_type;
136 signal cgo : clkgen_out_type;
137 --- AHB / APB
138 signal apbi : apb_slv_in_type;
139 signal apbo : apb_slv_out_vector := (others => apb_none);
140 signal ahbsi : ahb_slv_in_type;
141 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
142 signal ahbmi : ahb_mst_in_type;
143 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
144 --UART
145 signal ahbuarti : uart_in_type;
146 signal ahbuarto : uart_out_type;
147 signal apbuarti : uart_in_type;
148 signal apbuarto : uart_out_type;
149 --MEM CTRLR
150 signal memi : memory_in_type;
151 signal memo : memory_out_type;
152 signal wpo : wprot_out_type;
153 signal sdo : sdram_out_type;
154 --IRQ
155 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
156 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
157 --Timer
158 signal gpti : gptimer_in_type;
159 signal gpto : gptimer_out_type;
160 --GPIO
161 signal gpioi : gpio_in_type;
162 signal gpioo : gpio_out_type;
163 --DSU
164 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
165 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
166 signal dsui : dsu_in_type;
167 signal dsuo : dsu_out_type;
168
169 ---------------------------------------------------------------------
170 --- AJOUT TEST ------------------------Signaux----------------------
171 ---------------------------------------------------------------------
172 -- FIFOs
173 signal FifoIN_Full : std_logic_vector(4 downto 0);
174 signal FifoIN_Empty : std_logic_vector(4 downto 0);
175 signal FifoIN_Data : std_logic_vector(79 downto 0);
176
177 signal FifoINT_Full : std_logic_vector(4 downto 0);
178 signal FifoINT_Data : std_logic_vector(79 downto 0);
179
180 signal FifoOUT_FullV : std_logic;
181 signal FifoOUT_Full : std_logic_vector(1 downto 0);
182 signal Matrix_WriteV : std_logic_vector(0 downto 0);
183
184 -- MATRICE SPECTRALE
185 signal Matrix_Write : std_logic;
186 signal Matrix_Read : std_logic_vector(1 downto 0);
187 signal Matrix_Result : std_logic_vector(31 downto 0);
188
189 signal TopSM_Start : std_logic;
190 signal TopSM_Statu : std_logic_vector(3 downto 0);
191 signal TopSM_Read : std_logic_vector(4 downto 0);
192 signal TopSM_Data1 : std_logic_vector(15 downto 0);
193 signal TopSM_Data2 : std_logic_vector(15 downto 0);
194
195 signal Disp_FlagError : std_logic;
196 signal Disp_Pong : std_logic;
197 signal Disp_Write : std_logic_vector(1 downto 0);--
198 signal Disp_Data : std_logic_vector(63 downto 0);--
199 signal Dma_acq : std_logic;
200
201 -- FFT
202 signal Drive_Write : std_logic;
203 signal Drive_Read : std_logic_vector(4 downto 0);
204 signal Drive_DataRE : std_logic_vector(15 downto 0);
205 signal Drive_DataIM : std_logic_vector(15 downto 0);
206
207 signal Start : std_logic;
208 signal RstnFFT : std_logic;
209 signal FFT_Load : std_logic;
210 signal FFT_Ready : std_logic;
211 signal FFT_Valid : std_logic;
212 signal FFT_DataRE : std_logic_vector(15 downto 0);
213 signal FFT_DataIM : std_logic_vector(15 downto 0);
214
215 signal Link_Read : std_logic;
216 signal Link_Write : std_logic_vector(4 downto 0);
217 signal Link_ReUse : std_logic_vector(4 downto 0);
218 signal Link_Data : std_logic_vector(79 downto 0);
219
220 -- ADC
221 signal SmplClk : std_logic;
222 signal ADC_DataReady : std_logic;
223 signal ADC_SmplOut : Samples_out(4 downto 0);
224 signal enableADC : std_logic;
225
226 signal WG_Write : std_logic_vector(4 downto 0);
227 signal WG_ReUse : std_logic_vector(4 downto 0);
228 signal WG_DATA : std_logic_vector(79 downto 0);
229 signal s_out : std_logic_vector(79 downto 0);
230
231 signal fuller : std_logic_vector(4 downto 0);
232 signal reader : std_logic_vector(4 downto 0);
233 signal try : std_logic_vector(1 downto 0);
234 signal TXDint : std_logic;
235
236 -- IIR Filter
237 signal sample_clk_out : std_logic;
238
239 signal Rd : std_logic_vector(0 downto 0);
240 signal Ept : std_logic_vector(4 downto 0);
241
242 signal Bwr : std_logic_vector(0 downto 0);
243 signal Bre : std_logic_vector(0 downto 0);
244 signal DataTMP : std_logic_vector(15 downto 0);
245 signal FullUp : std_logic_vector(0 downto 0);
246 signal EmptyUp : std_logic_vector(0 downto 0);
247 signal FullDown : std_logic_vector(0 downto 0);
248 signal EmptyDown : std_logic_vector(0 downto 0);
249 ---------------------------------------------------------------------
250 constant IOAEN : integer := CFG_CAN;
251 constant boardfreq : integer := 50000;
252
253 begin
254
255 ---------------------------------------------------------------------
256 --- AJOUT TEST -------------------------------------IPs-------------
257 ---------------------------------------------------------------------
258 led(1 downto 0) <= gpio(1 downto 0);
259
260 --- COM USB ---------------------------------------------------------
261 -- MemIn0 : APB_FifoWrite
262 -- generic map (5,5, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
263 -- port map (clkm,rstn,apbi,USB_Read,open,open,InOutData,apbo(5));
264 --
265 -- BUF0 : APB_USB
266 -- generic map (6,6,DataMax => 1024)
267 -- port map(clkm,rstn,flagC,flagB,ifclk,sloe,USB_Read,USB_Write,pktend,fifoadr,InOutData,apbi,apbo(6));
268 --
269 -- MemOut0 : APB_FifoRead
270 -- generic map (7,7, Data_sz => 8, Addr_sz => 8, addr_max_int => 256)
271 -- port map (clkm,rstn,apbi,USB_Write,open,open,InOutData,apbo(7));
272 --
273 --slrd <= usb_Read;
274 --slwr <= usb_Write;
275
276 --- CNA -------------------------------------------------------------
277
278 -- CONV : APB_CNA
279 -- generic map (5,5)
280 -- port map(clkm,rstn,apbi,apbo(5),DAC_SYNC,DAC_SCLK,DAC_DATA);
281
282 --TEST(0) <= SmplClk;
283 --TEST(1) <= WG_Write(0);
284 --TEST(2) <= Fuller(0);
285 --TEST(3) <= s_out(s_out'length-1);
286
287
288 --SPW1_EN <= '1';
289 --SPW2_EN <= '0';
290
291 --- CAN -------------------------------------------------------------
292
293 -- Divider : Clk_divider
294 -- generic map(OSC_freqHz => 24_576_000, TargetFreq_Hz => 24_576)
295 -- Port map(clkm,rstn,SmplClk);
296 --
297 -- ADC : AD7688_drvr
298 -- generic map (ChanelCount => 5, clkkHz => 24_576)
299 -- port map (clkm,rstn,enableADC,SmplClk,ADC_DataReady,ADC_SmplOut,ADC_in,ADC_out);
300 --
301 -- WG : WriteGen_ADC
302 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
303 --
304 --enableADC <= gpio(0);
305 --Bias_Fails <= '0';
306 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
307 --
308 --
309 -- MemIn1 : APB_FIFO
310 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
311 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
312
313 --- FFT -------------------------------------------------------------
314
315 MemIn : APB_FIFO
316 generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
317 port map (clkm,rstn,clkm,clkm,(others => '0'),Drive_Read,(others => '1'),FifoIN_Empty,FifoIN_Full,FifoIN_Data,(others => '0'),open,open,apbi,apbo(8));
318
319 DRIVE : Driver_FFT
320 generic map(Data_sz => 16)
321 port map(clkm,rstn,FFT_Load,FifoIN_Empty,FifoIN_Data,Drive_Write,Drive_Read,Drive_DataRE,Drive_DataIM);
322
323 Start <= '0';
324
325 FFT : CoreFFT
326 generic map(
327 LOGPTS => gLOGPTS,
328 LOGLOGPTS => gLOGLOGPTS,
329 WSIZE => gWSIZE,
330 TWIDTH => gTWIDTH,
331 DWIDTH => gDWIDTH,
332 TDWIDTH => gTDWIDTH,
333 RND_MODE => gRND_MODE,
334 SCALE_MODE => gSCALE_MODE,
335 PTS => gPTS,
336 HALFPTS => gHALFPTS,
337 inBuf_RWDLY => gInBuf_RWDLY)
338 port map(clkm,start,rstn,Drive_Write,Link_Read,Drive_DataIM,Drive_DataRE,FFT_Load,open,FFT_DataIM,FFT_DataRE,FFT_Valid,FFT_Ready);
339
340 LINK : Linker_FFT
341 generic map(Data_sz => 16)
342 port map(clkm,rstn,FFT_Ready,FFT_Valid,FifoINT_Full,FFT_DataRE,FFT_DataIM,Link_Read,Link_Write,Link_ReUse,Link_Data);
343
344 ----- LINK MEMORY -------------------------------------------------------
345
346 -- MemOut : APB_FIFO
347 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
348 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
349
350 MemInt : lppFIFOxN
351 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
352 port map(rstn,clkm,clkm,Link_ReUse,Link_Write,TopSM_Read,Link_Data,FifoINT_Data,FifoINT_Full,open);
353
354 -- MemIn : APB_FIFO
355 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
356 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
357
358 ----- MATRICE SPECTRALE ---------------------5 FIFO Input---------------
359
360 TopSM : TopSpecMatrix
361 generic map (Input_SZ => 16)
362 port map(clkm,rstn,Matrix_Write,Matrix_Read,FifoINT_Full,FifoINT_Data,TopSM_Start,TopSM_Read,TopSM_Statu,TopSM_Data1,TopSM_Data2);
363
364 SM : SpectralMatrix
365 generic map (Input_SZ => 16, Result_SZ => 32)
366 port map(clkm,rstn,TopSM_Start,TopSM_Data1,TopSM_Data2,TopSM_Statu,Matrix_Read,Matrix_Write,Matrix_Result);
367
368 Dma_acq <= '1';
369
370 DISP : Dispatch
371 generic map(Data_SZ => 32)
372 port map(clkm,rstn,Dma_acq,Matrix_Result,Matrix_Write,FifoOUT_Full,Disp_Data,Disp_Write,Disp_Pong,Disp_FlagError);
373
374 MemOut : APB_FIFO
375 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
376 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Disp_Write,open,FifoOUT_Full,open,Disp_Data,open,open,apbi,apbo(9));
377
378 ----- FIFO -------------------------------------------------------------
379
380 Memtest : APB_FIFO
381 generic map (pindex => 5, paddr => 5, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
382 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(5));
383
384 --***************************************TEST DEMI-FIFO********************************************************************************
385 -- MemIn : APB_FIFO
386 -- generic map (pindex => 8, paddr => 8, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 0, W => 1)
387 -- port map (clkm,rstn,clkm,clkm,(others => '0'),Bre,(others => '1'),EmptyUp,FullUp,DataTMP,(others => '0'),open,open,apbi,apbo(8));
388 --
389 -- Pont : Bridge
390 -- port map(clkm,rstn,EmptyUp(0),FullDown(0),Bwr(0),Bre(0));
391 --
392 -- MemOut : APB_FIFO
393 -- generic map (pindex => 9, paddr => 9, FifoCnt => 1, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
394 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),Bwr,EmptyDown,FullDown,open,DataTMP,open,open,apbi,apbo(9));
395 --*************************************************************************************************************************************
396
397 --- UART -------------------------------------------------------------
398
399 COM0 : APB_UART
400 generic map (pindex => 4, paddr => 4)
401 port map (clkm,rstn,apbi,apbo(4),UART_TXD,UART_RXD);
402
403 --- DELAY ------------------------------------------------------------
404
405 -- Delay0 : APB_Delay
406 -- generic map (pindex => 4, paddr => 4)
407 -- port map (clkm,rstn,apbi,apbo(4));
408
409 --- IIR Filter -------------------------------------------------------
410 --Test(0) <= sample_clk_out;
411 --
412 --
413 -- IIR1: APB_IIR_Filter
414 -- generic map(
415 -- tech => CFG_MEMTECH,
416 -- pindex => 8,
417 -- paddr => 8,
418 -- Sample_SZ => Sample_SZ,
419 -- ChanelsCount => ChanelsCount,
420 -- Coef_SZ => Coef_SZ,
421 -- CoefCntPerCel => CoefCntPerCel,
422 -- Cels_count => Cels_count,
423 -- virgPos => virgPos
424 -- )
425 -- port map(
426 -- rst => rstn,
427 -- clk => clkm,
428 -- apbi => apbi,
429 -- apbo => apbo(8),
430 -- sample_clk_out => sample_clk_out,
431 -- GOtest => Test(1),
432 -- CoefsInitVal => (others => '1')
433 -- );
434 ----------------------------------------------------------------------
435
436 ----------------------------------------------------------------------
437 --- Reset and Clock generation -------------------------------------
438 ----------------------------------------------------------------------
439
440 vcc <= (others => '1'); gnd <= (others => '0');
441 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
442
443 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
444
445
446 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
447
448 clkgen0 : clkgen -- clock generator
449 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
450 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
451 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
452
453 ramclk <= clkm;
454 process(lclk2x)
455 begin
456 if lclk2x'event and lclk2x = '1' then
457 lclk <= not lclk;
458 end if;
459 end process;
460
461 ----------------------------------------------------------------------
462 --- LEON3 processor / DSU / IRQ ------------------------------------
463 ----------------------------------------------------------------------
464
465 l3 : if CFG_LEON3 = 1 generate
466 cpu : for i in 0 to CFG_NCPU-1 generate
467 u0 : leon3s -- LEON3 processor
468 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
469 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
470 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
471 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
472 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
473 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
474 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
475 irqi(i), irqo(i), dbgi(i), dbgo(i));
476 end generate;
477 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
478
479 dsugen : if CFG_DSU = 1 generate
480 dsu0 : dsu3 -- LEON3 Debug Support Unit
481 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
482 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
483 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
484 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
485 dsui.enable <= '1';
486 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
487 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
488 end generate;
489 end generate;
490
491 nodsu : if CFG_DSU = 0 generate
492 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
493 end generate;
494
495 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
496 irqctrl0 : irqmp -- interrupt controller
497 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
498 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
499 end generate;
500 irq3 : if CFG_IRQ3_ENABLE = 0 generate
501 x : for i in 0 to CFG_NCPU-1 generate
502 irqi(i).irl <= "0000";
503 end generate;
504 apbo(2) <= apb_none;
505 end generate;
506
507 ----------------------------------------------------------------------
508 --- Memory controllers ---------------------------------------------
509 ----------------------------------------------------------------------
510
511 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
512 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
513
514 memi.brdyn <= '1'; memi.bexcn <= '1';
515 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
516
517 bdr : for i in 0 to 3 generate
518 data_pad : iopadv generic map (tech => padtech, width => 8)
519 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
520 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
521 end generate;
522
523
524 addr_pad : outpadv generic map (width => 19, tech => padtech)
525 port map (address, memo.address(20 downto 2));
526
527
528 SSRAM_0:entity ssram_plugin
529 generic map (tech => padtech)
530 port map
531 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
532
533 ----------------------------------------------------------------------
534 --- AHB CONTROLLER -------------------------------------------------
535 ----------------------------------------------------------------------
536
537 ahb0 : ahbctrl -- AHB arbiter/multiplexer
538 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
539 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
540 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
541 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
542
543 ----------------------------------------------------------------------
544 --- AHB UART -------------------------------------------------------
545 ----------------------------------------------------------------------
546
547 dcomgen : if CFG_AHB_UART = 1 generate
548 dcom0: ahbuart -- Debug UART
549 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
550 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
551 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
552 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
553 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
554 end generate;
555 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
556
557 ----------------------------------------------------------------------
558 --- APB Bridge -----------------------------------------------------
559 ----------------------------------------------------------------------
560
561 apb0 : apbctrl -- AHB/APB bridge
562 generic map (hindex => 1, haddr => CFG_APBADDR)
563 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
564
565 ----------------------------------------------------------------------
566 --- GPT Timer ------------------------------------------------------
567 ----------------------------------------------------------------------
568
569 gpt : if CFG_GPT_ENABLE /= 0 generate
570 timer0 : gptimer -- timer unit
571 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
572 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
573 nbits => CFG_GPT_TW)
574 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
575 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
576 -- led(4) <= gpto.wdog;
577 end generate;
578 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
579
580
581 ----------------------------------------------------------------------
582 --- APB UART -------------------------------------------------------
583 ----------------------------------------------------------------------
584
585 ua1 : if CFG_UART1_ENABLE /= 0 generate
586 uart1 : apbuart -- UART 1
587 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
588 fifosize => CFG_UART1_FIFO)
589 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
590 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
591 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
592 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
593 end generate;
594 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
595
596 ----------------------------------------------------------------------
597 --- GPIO -----------------------------------------------------------
598 ----------------------------------------------------------------------
599
600 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
601 grgpio0: grgpio
602 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
603 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
604
605 pio_pads : for i in 0 to 6 generate
606 pio_pad : iopad generic map (tech => padtech)
607 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
608 end generate;
609 end generate;
610
611
612 end Behavioral; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity DEMUX is
27 generic(
28 Data_sz : integer range 1 to 32 := 16);
29 port(
30 clk : in std_logic;
31 rstn : in std_logic;
32
33 Read : in std_logic_vector(4 downto 0);
34 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
35
36 EmptyF0a : in std_logic_vector(4 downto 0);
37 EmptyF0b : in std_logic_vector(4 downto 0);
38 EmptyF1 : in std_logic_vector(4 downto 0);
39 EmptyF2 : in std_logic_vector(4 downto 0);
40
41 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
45
46 Read_DEMUX : out std_logic_vector(19 downto 0);
47 Empty : out std_logic_vector(4 downto 0);
48 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
49 );
50 end entity;
51
52
53 architecture ar_DEMUX of DEMUX is
54
55 type etat is (eX,e0,e1,e2,e3);
56 signal ect : etat;
57
58 signal pong : std_logic;
59
60 signal DataCpt_reg : std_logic_vector(3 downto 0);
61 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
62
63 signal Countf0 : integer;
64 signal Countf1 : integer;
65
66 begin
67 process(clk,rstn)
68 begin
69 if(rstn='0')then
70 ect <= e0;
71 pong <= '0';
72 Countf0 <= 1;
73 Countf1 <= 0;
74
75 elsif(clk'event and clk='1')then
76 DataCpt_reg <= DataCpt;
77
78 case ect is
79
80 when e0 =>
81 if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then
82 pong <= not pong;
83 if(Countf0 = 5)then
84 Countf0 <= 0;
85 ect <= e2;
86 else
87 Countf0 <= Countf0 + 1;
88 ect <= e1;
89 end if;
90 end if;
91
92 when e1 =>
93 if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then
94 pong <= not pong;
95 if(Countf0 = 5)then
96 Countf0 <= 0;
97 ect <= e2;
98 else
99 Countf0 <= Countf0 + 1;
100 ect <= e0;
101 end if;
102 end if;
103
104 when e2 =>
105 if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then
106 if(Countf1 = 15)then
107 Countf1 <= 0;
108 ect <= e3;
109 else
110 Countf1 <= Countf1 + 1;
111 if(pong = '0')then
112 ect <= e0;
113 else
114 ect <= e1;
115 end if;
116 end if;
117 end if;
118
119 when e3 =>
120 if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then
121 if(pong = '0')then
122 ect <= e0;
123 else
124 ect <= e1;
125 end if;
126 end if;
127
128 when others =>
129 null;
130
131 end case;
132 end if;
133 end process;
134
135 with ect select
136 Empty <= EmptyF0a when e0,
137 EmptyF0b when e1,
138 EmptyF1 when e2,
139 EmptyF2 when e3,
140 (others => '1') when others;
141
142 with ect select
143 Data <= DataF0a when e0,
144 DataF0b when e1,
145 DataF1 when e2,
146 DataF2 when e3,
147 (others => '0') when others;
148
149 with ect select
150 Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0,
151 Dummy_Read & Dummy_Read & Read & Dummy_Read when e1,
152 Dummy_Read & Read & Dummy_Read & Dummy_Read when e2,
153 Read & Dummy_Read & Dummy_Read & Dummy_Read when e3,
154 (others => '1') when others;
155
156
157
158
159 end architecture;
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
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1 -- WatchFlag.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity WatchFlag is
7 port(
8 clk : in std_logic;
9 rstn : in std_logic;
10
11 FullF0a : in std_logic_vector(4 downto 0);
12 FullF0b : in std_logic_vector(4 downto 0);
13 FullF1 : in std_logic_vector(4 downto 0);
14 FullF2 : in std_logic_vector(4 downto 0);
15
16 EmptyF0a : in std_logic_vector(4 downto 0);
17 EmptyF0b : in std_logic_vector(4 downto 0);
18 EmptyF1 : in std_logic_vector(4 downto 0);
19 EmptyF2 : in std_logic_vector(4 downto 0);
20
21 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
22 );
23 end entity;
24
25
26 architecture ar_WatchFlag of WatchFlag is
27
28 constant FlagSet : std_logic_vector(4 downto 0) := (others =>'1');
29
30 begin
31 process(clk,rstn)
32 begin
33 if(rstn='0')then
34 DataCpt <= (others => '0');
35
36 elsif(clk'event and clk='1')then
37
38 if(FullF0a = FlagSet)then
39 DataCpt(0) <= '1';
40 elsif(EmptyF0a = FlagSet)then
41 DataCpt(0) <= '0';
42 end if;
43
44 if(FullF0b = FlagSet)then
45 DataCpt(1) <= '1';
46 elsif(EmptyF0b = FlagSet)then
47 DataCpt(1) <= '0';
48 end if;
49
50 if(FullF1 = FlagSet)then
51 DataCpt(2) <= '1';
52 elsif(EmptyF1 = FlagSet)then
53 DataCpt(2) <= '0';
54 end if;
55
56 if(FullF2 = FlagSet)then
57 DataCpt(3) <= '1';
58 elsif(EmptyF2 = FlagSet)then
59 DataCpt(3) <= '0';
60 end if;
61
62 end if;
63 end process;
64
65 end architecture; No newline at end of file
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@@ -0,0 +1,81
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
32 package lpp_demux is
33
34 component DEMUX is
35 generic(
36 Data_sz : integer range 1 to 32 := 16);
37 port(
38 clk : in std_logic;
39 rstn : in std_logic;
40
41 Read : in std_logic_vector(4 downto 0);
42 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
61 component WatchFlag is
62 port(
63 clk : in std_logic;
64 rstn : in std_logic;
65
66 FullF0a : in std_logic_vector(4 downto 0);
67 FullF0b : in std_logic_vector(4 downto 0);
68 FullF1 : in std_logic_vector(4 downto 0);
69 FullF2 : in std_logic_vector(4 downto 0);
70
71 EmptyF0a : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
73 EmptyF1 : in std_logic_vector(4 downto 0);
74 EmptyF2 : in std_logic_vector(4 downto 0);
75
76 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
77 );
78 end component;
79
80
81 end; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity TopSpecMatrix is
27 generic(
28 Input_SZ : integer := 16);
29 port(
30 clk : in std_logic;
31 rstn : in std_logic;
32 Write : in std_logic;
33 ReadIn : in std_logic_vector(1 downto 0);
34 Full : in std_logic_vector(4 downto 0);
35 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
36 Start : out std_logic;
37 ReadOut : out std_logic_vector(4 downto 0);
38 Statu : out std_logic_vector(3 downto 0);
39 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
40 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
41 );
42 end entity;
43
44 architecture ar_TopSpecMatrix of TopSpecMatrix is
45
46 type etat is (eX,e0,e1,e2);
47 signal ect : etat;
48
49 signal DataCount : integer range 0 to 256 := 0;
50 signal StatuINT : integer range 1 to 15 := 1;
51
52 signal Write_reg : std_logic;
53 signal Full_int : std_logic_vector(1 downto 0);
54
55 begin
56 process(clk,rstn)
57 begin
58
59 if(rstn='0')then
60 DataCount <= 0;
61 StatuINT <= 1;
62 Write_reg <= '0';
63 Start <= '0';
64 ect <= e0;
65
66 elsif(clk'event and clk='1')then
67 Write_reg <= Write;
68
69 if(Write_reg='1' and Write='0')then
70 if(DataCount=256)then
71 DataCount <= 0;
72 else
73 DataCount <= DataCount + 1;
74 end if;
75 end if;
76
77
78 case ect is
79
80 when e0 =>
81 if(Full_int = "11")then
82 Start <= '1';
83 if(StatuINT=1 or StatuINT=3 or StatuINT=6 or StatuINT=10 or StatuINT=15)then
84 ect <= e1;
85 else
86 ect <= e2;
87 end if;
88 end if;
89
90 when e1 =>
91 if(DataCount=128)then
92 if(StatuINT=15)then
93 StatuINT <= 1;
94 else
95 StatuINT <= StatuINT + 1;
96 end if;
97 DataCount <= 0;
98 Start <= '0';
99 ect <= e0;
100 end if;
101
102 when e2 =>
103 if(DataCount=256)then
104 DataCount <= 0;
105 StatuINT <= StatuINT + 1;
106 Start <= '0';
107 ect <= e0;
108 end if;
109
110 when others =>
111 null;
112
113 end case;
114 end if;
115 end process;
116
117 Statu <= std_logic_vector(to_unsigned(StatuINT,4));
118
119 with StatuINT select
120 DATA1 <= Data(15 downto 0) when 1,
121 Data(15 downto 0) when 2,
122 Data(31 downto 16) when 3,
123 Data(15 downto 0) when 4,
124 Data(31 downto 16) when 5,
125 Data(47 downto 32) when 6,
126 Data(15 downto 0) when 7,
127 Data(31 downto 16) when 8,
128 Data(47 downto 32) when 9,
129 Data(63 downto 48) when 10,
130 Data(15 downto 0) when 11,
131 Data(31 downto 16) when 12,
132 Data(47 downto 32) when 13,
133 Data(63 downto 48) when 14,
134 Data(79 downto 64) when 15,
135 X"0000" when others;
136
137
138 with StatuINT select
139 DATA2 <= (others => '0') when 1,
140 Data(31 downto 16) when 2,
141 (others => '0') when 3,
142 Data(47 downto 32) when 4,
143 Data(47 downto 32) when 5,
144 (others => '0') when 6,
145 Data(63 downto 48) when 7,
146 Data(63 downto 48) when 8,
147 Data(63 downto 48) when 9,
148 (others => '0') when 10,
149 Data(79 downto 64) when 11,
150 Data(79 downto 64) when 12,
151 Data(79 downto 64) when 13,
152 Data(79 downto 64) when 14,
153 (others => '0') when 15,
154 X"0000" when others;
155
156 with StatuINT select
157 ReadOut <= "1111" & not READin(0) when 1,
158 "111" & not READin(1) & not READin(0) when 2,
159 "111" & not READin(0) & '1' when 3,
160 "11" & not READin(1) & '1' & not READin(0) when 4,
161 "11" & not READin(1) & not READin(0) & '1' when 5,
162 "11" & not READin(0) & "11" when 6,
163 "1" & not READin(1) & "11" & not READin(0) when 7,
164 '1' & not READin(1) & '1' & not READin(0) & '1' when 8,
165 '1' & not READin(1) & not READin(0) & "11" when 9,
166 '1' & not READin(0) & "111" when 10,
167 not READin(1) & "111" & not READin(0) when 11,
168 not READin(1) & "11" & not READin(0) & '1' when 12,
169 not READin(1) & '1' & not READin(0) & "11" when 13,
170 not READin(1) & not READin(0) & "111" when 14,
171 not READin(0) & "1111" when 15,
172 "11111" when others;
173
174 with StatuINT select
175 Full_int <= Full(0) & Full(0) when 1,
176 Full(1) & Full(0) when 2,
177 Full(1) & Full(1) when 3,
178 Full(2) & Full(0) when 4,
179 Full(2) & Full(1) when 5,
180 Full(2) & Full(2) when 6,
181 Full(3) & Full(0) when 7,
182 Full(3) & Full(1) when 8,
183 Full(3) & Full(2) when 9,
184 Full(3) & Full(3) when 10,
185 Full(4) & Full(0) when 11,
186 Full(4) & Full(1) when 12,
187 Full(4) & Full(2) when 13,
188 Full(4) & Full(3) when 14,
189 Full(4) & Full(4) when 15,
190 "00" when others;
191
192 end architecture;
193
194
195
196
197
198
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1 #!/bin/bash
2 # both $1 and $2 are absolute paths (biginning with /)
3 # returns $2 relative to $1
4
5 source=$1
6 target=$2
7
8 common_part=$source # for now
9 result="" # for now
10
11 while [[ "${target#$common_part}" == "${target}" ]]; do
12 # no match, means that candidate common part is not correct
13 # go up one level (reduce common part)
14 common_part="$(dirname $common_part)"
15 # and record that we went back, with correct / handling
16 if [[ -z $result ]]; then
17 result=".."
18 else
19 result="../$result"
20 fi
21 done
22
23 if [[ $common_part == "/" ]]; then
24 # special case for root (no common path)
25 result="$result/"
26 fi
27
28 # since we now have identified the common part,
29 # compute the non-common part
30 forward_part="${target#$common_part}"
31
32 # and now stick all parts together
33 if [[ -n $result ]] && [[ -n $forward_part ]]; then
34 result="$result$forward_part"
35 elif [[ -n $forward_part ]]; then
36 # extra slash removal
37 result="${forward_part:1}"
38 fi
39
40 echo $result
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@@ -1,44 +1,44
1 #------------------------------------------------------------------------------
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
8 #-- (at your option) any later version.
9 #--
9 #--
10 #-- This program is distributed in the hope that it will be useful,
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
13 #-- GNU General Public License for more details.
14 #--
14 #--
15 #-- You should have received a copy of the GNU General Public License
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
18 #------------------------------------------------------------------------------
19
19
20 include ../../rules.mk
20 include ../../rules.mk
21 LIBDIR = ../../lib
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_delay_Driver -lapb_fifo_Driver -lapb_uart_Driver -lapb_gpio_Driver
24 LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions
25 INPUTFILE=main.c
25 INPUTFILE=main.c
26 EXEC=BenchFFT+Matrix.bin
26 EXEC=BenchFFT+Matrix.bin
27 OUTBINDIR=bin/
27 OUTBINDIR=bin/
28
28
29
29
30 .PHONY:bin
30 .PHONY:bin
31
31
32 all:bin
32 all:bin
33 @echo $(EXEC)" file created"
33 @echo $(EXEC)" file created"
34
34
35 clean:
35 clean:
36 rm -f *.{o,a}
36 rm -f *.{o,a}
37
37
38
38
39
39
40 help:ruleshelp
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
43 @echo " clean : removes temporary files"
44
44
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@@ -1,80 +1,73
1 #include <stdio.h>
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_uart_Driver.h"
4 #include "apb_uart_Driver.h"
5 #include "apb_delay_Driver.h"
6 #include "apb_fft_Driver.h"
7
8
5
9 int main()
6 int main()
10 {
7 {
11 int i;
8 int i=0;
12 int data1,data2;
9 int data;
13 char temp[256];
10 char temp[256];
14 int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
15 int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
16 int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ;
17
11
18 /* int TblSin5K[256] = {0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872,0xD0E1,0xC980,0xC256,0xBB6A,0xB4C3,0xAE69,0xA861,0xA2B1,0x9D60,0x9872,0x93ED,0x8FD5,0x8C2F,0x88FD,0x8644,0x8405,0x8244,0x8102,0x8041,0x8000,0x8041,0x8102,0x8244,0x8405,0x8644,0x88FD,0x8C2F,0x8FD5,0x93ED,0x9872,0x9D60,0xA2B1,0xA861,0xAE69,0xB4C3,0xBB6A,0xC256,0xC980,0xD0E1,0xD872,0xE02B,0xE804,0xEFF5,0xF7F6,0x0000,0x080A,0x100B,0x17FC,0x1FD5,0x278E,0x2F1F,0x3680,0x3DAA,0x4496,0x4B3D,0x5197,0x579F,0x5D4F,0x62A0,0x678E,0x6C13,0x702B,0x73D1,0x7703,0x79BC,0x7BFB,0x7DBC,0x7EFE,0x7FBF,0x7FFF,0x7FBF,0x7EFE,0x7DBC,0x7BFB,0x79BC,0x7703,0x73D1,0x702B,0x6C13,0x678E,0x62A0,0x5D4F,0x579F,0x5197,0x4B3D,0x4496,0x3DAA,0x3680,0x2F1F,0x278E,0x1FD5,0x17FC,0x100B,0x080A,0x0000,0xF7F6,0xEFF5,0xE804,0xE02B,0xD872};
12 int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
19 int TblSin8K[256] = {0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA,0x489C,0x52D3,0x5C33,0x64A5,0x6C13,0x7269,0x7798,0x7B92,0x7E4C,0x7FBF,0x7FE9,0x7EC7,0x7C5E,0x78B4,0x73D1,0x6DC3,0x669A,0x5E67,0x5540,0x4B3D,0x4077,0x350A,0x2915,0x1CB5,0x100B,0x0337,0xF65C,0xE999,0xDD10,0xD0E1,0xC52C,0xBA10,0xAFA8,0xA610,0x9D60,0x95AF,0x8F11,0x8997,0x854F,0x8244,0x807F,0x8003,0x80D1,0x82E9,0x8644,0x8AD9,0x909E,0x9782,0x9F75,0xA861,0xB22F,0xBCC7,0xC80D,0xD3E3,0xE02B,0xECC5,0xF992,0x066E,0x133B,0x1FD5,0x2C1D,0x37F3,0x4339,0x4DD1,0x579F,0x608B,0x687E,0x6F62,0x7527,0x79BC,0x7D17,0x7F2F,0x7FFD,0x7F81,0x7DBC,0x7AB1,0x7669,0x70EF,0x6A51,0x62A0,0x59F0,0x5058,0x45F0,0x3AD4,0x2F1F,0x22F0,0x1667,0x09A4,0xFCC9,0xEFF5,0xE34B,0xD6EB,0xCAF6,0xBF89,0xB4C3,0xAAC0,0xA199,0x9966,0x923D,0x8C2F,0x874C,0x83A2,0x8139,0x8017,0x8041,0x81B4,0x846E,0x8868,0x8D97,0x93ED,0x9B5B,0xA3CD,0xAD2D,0xB764,0xC256,0xCDE7,0xD9FB,0xE670,0xF327,0x0000,0x0CD9,0x1990,0x2605,0x3219,0x3DAA};
13 int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD};
20 int TblSin11K[256] = {0x0000,0x11A3,0x22F0,0x3392,0x4339,0x5197,0x5E67,0x696A,0x7269,0x793B,0x7DBC,0x7FD7,0x7F81,0x7CBD,0x7798,0x702B,0x669A,0x5B14,0x4DD1,0x3F12,0x2F1F,0x1E46,0x0CD9,0xFB2D,0xE999,0xD872,0xC80D,0xB8B8,0xAAC0,0x9E68,0x93ED,0x8B82,0x854F,0x8174,0x8003,0x8102,0x846E,0x8A36,0x923D,0x9C5B,0xA861,0xB612,0xC52C,0xD566,0xE670,0xF7F6,0x09A4,0x1B23,0x2C1D,0x3C40,0x4B3D,0x58CA,0x64A5,0x6E95,0x7669,0x7BFB,0x7F2F,0x7FF6,0x7E4C,0x7A39,0x73D1,0x6B34,0x608B,0x540B,0x45F0,0x3680,0x2605,0x14D1,0x0337,0xF18E,0xE02B,0xCF63,0xBF89,0xB0EA,0xA3CD,0x9872,0x8F11,0x87D8,0x82E9,0x805D,0x8041,0x8294,0x874C,0x8E52,0x9782,0xA2B1,0xAFA8,0xBE27,0xCDE7,0xDE9D,0xEFF5,0x019C,0x133B,0x247C,0x350A,0x4496,0x52D3,0x5F7B,0x6A51,0x7320,0x79BC,0x7E06,0x7FE9,0x7F5B,0x7C5E,0x7703,0x6F62,0x65A1,0x59F0,0x4C88,0x3DAA,0x2D9F,0x1CB5,0x0B3F,0xF992,0xE804,0xD6EB,0xC69B,0xB764,0xA98F,0x9D60,0x9313,0x8AD9,0x84DC,0x8139,0x8000,0x8139,0x84DC,0x8AD9,0x9313,0x9D60,0xA98F,0xB764,0xC69B,0xD6EB,0xE804,0xF992,0x0B3F,0x1CB5,0x2D9F,0x3DAA,0x4C88,0x59F0,0x65A1,0x6F62,0x7703,0x7C5E,0x7F5B,0x7FE9,0x7E06,0x79BC,0x7320,0x6A51,0x5F7B,0x52D3,0x4496,0x350A,0x247C,0x133B,0x019C,0xEFF5,0xDE9D,0xCDE7,0xBE27,0xAFA8,0xA2B1,0x9782,0x8E52,0x874C,0x8294,0x8041,0x805D,0x82E9,0x87D8,0x8F11,0x9872,0xA3CD,0xB0EA,0xBF89,0xCF63,0xE02B,0xF18E,0x0337,0x14D1,0x2605,0x3680,0x45F0,0x540B,0x608B,0x6B34,0x73D1,0x7A39,0x7E4C,0x7FF6,0x7F2F,0x7BFB,0x7669,0x6E95,0x64A5,0x58CA,0x4B3D,0x3C40,0x2C1D,0x1B23,0x09A4,0xF7F6,0xE670,0xD566,0xC52C,0xB612,0xA861,0x9C5B,0x923D,0x8A36,0x846E,0x8102,0x8003,0x8174,0x854F,0x8B82,0x93ED,0x9E68,0xAAC0,0xB8B8,0xC80D,0xD872,0xE999,0xFB2D,0x0CD9,0x1E46,0x2F1F,0x3F12,0x4DD1,0x5B14,0x669A,0x702B,0x7798,0x7CBD,0x7F81,0x7FD7,0x7DBC,0x793B,0x7269,0x696A,0x5E67,0x5197,0x4339,0x3392,0x22F0,0x11A3,0x0000,0xEE5D,0xDD10,0xCC6E,0xBCC7,0xAE69};
14 int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
21 */ int TblSin15K[256] = {0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872,0x8C2F,0x8405,0x8041,0x8102,0x8644,0x8FD5,0x9D60,0xAE69,0xC256,0xD872,0xEFF5,0x080A,0x1FD5,0x3680,0x4B3D,0x5D4F,0x6C13,0x7703,0x7DBC,0x8000,0x7DBC,0x7703,0x6C13,0x5D4F,0x4B3D,0x3680,0x1FD5,0x080A,0xEFF5,0xD872,0xC256,0xAE69,0x9D60,0x8FD5,0x8644,0x8102,0x8041,0x8405,0x8C2F,0x9872,0xA861,0xBB6A,0xD0E1,0xE804,0x0000,0x17FC,0x2F1F,0x4496,0x579F,0x678E,0x73D1,0x7BFB,0x7FBF,0x7EFE,0x79BC,0x702B,0x62A0,0x5197,0x3DAA,0x278E,0x100B,0xF7F6,0xE02B,0xC980,0xB4C3,0xA2B1,0x93ED,0x88FD,0x8244,0x8000,0x8244,0x88FD,0x93ED,0xA2B1,0xB4C3,0xC980,0xE02B,0xF7F6,0x100B,0x278E,0x3DAA,0x5197,0x62A0,0x702B,0x79BC,0x7EFE,0x7FBF,0x7BFB,0x73D1,0x678E,0x579F,0x4496,0x2F1F,0x17FC,0x0000,0xE804,0xD0E1,0xBB6A,0xA861,0x9872};
15 int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C};
22 int TblSin19K[256] = {0x0000,0x1E46,0x3AD4,0x540B,0x687E,0x7703,0x7EC7,0x7F5B,0x78B4,0x6B34,0x579F,0x3F12,0x22F0,0x04D3,0xE670,0xC980,0xAFA8,0x9A5F,0x8AD9,0x81FA,0x8041,0x85C7,0x923D,0xA4EC,0xBCC7,0xD872,0xF65C,0x14D1,0x3219,0x4C88,0x62A0,0x7320,0x7D17,0x7FF6,0x7B92,0x702B,0x5E67,0x4748,0x2C1D,0x0E72,0xEFF5,0xD261,0xB764,0xA085,0x8F11,0x8405,0x8003,0x8343,0x8D97,0x9E68,0xB4C3,0xCF63,0xECC5,0x0B3F,0x2915,0x4496,0x5C33,0x6E95,0x7AB1,0x7FD7,0x7DBC,0x747E,0x64A5,0x4F16,0x350A,0x17FC,0xF992,0xDB84,0xBF89,0xA736,0x93ED,0x86C5,0x807F,0x8174,0x8997,0x9872,0xAD2D,0xC69B,0xE34B,0x019C,0x1FD5,0x3C40,0x5540,0x696A,0x7798,0x7EFE,0x7F2F,0x7828,0x6A51,0x5671,0x3DAA,0x2163,0x0337,0xE4DD,0xC80D,0xAE69,0x9966,0x8A36,0x81B4,0x805D,0x8644,0x9313,0xA610,0xBE27,0xD9FB,0xF7F6,0x1667,0x3392,0x4DD1,0x63A5,0x73D1,0x7D6C,0x7FE9,0x7B24,0x6F62,0x5D4F,0x45F0,0x2A9A,0x0CD9,0xEE5D,0xD0E1,0xB612,0x9F75,0x8E52,0x83A2,0x8000,0x83A2,0x8E52,0x9F75,0xB612,0xD0E1,0xEE5D,0x0CD9,0x2A9A,0x45F0,0x5D4F,0x6F62,0x7B24,0x7FE9,0x7D6C,0x73D1,0x63A5,0x4DD1,0x3392,0x1667,0xF7F6,0xD9FB,0xBE27,0xA610,0x9313,0x8644,0x805D,0x81B4,0x8A36,0x9966,0xAE69,0xC80D,0xE4DD,0x0337,0x2163,0x3DAA,0x5671,0x6A51,0x7828,0x7F2F,0x7EFE,0x7798,0x696A,0x5540,0x3C40,0x1FD5,0x019C,0xE34B,0xC69B,0xAD2D,0x9872,0x8997,0x8174,0x807F,0x86C5,0x93ED,0xA736,0xBF89,0xDB84,0xF992,0x17FC,0x350A,0x4F16,0x64A5,0x747E,0x7DBC,0x7FD7,0x7AB1,0x6E95,0x5C33,0x4496,0x2915,0x0B3F,0xECC5,0xCF63,0xB4C3,0x9E68,0x8D97,0x8343,0x8003,0x8405,0x8F11,0xA085,0xB764,0xD261,0xEFF5,0x0E72,0x2C1D,0x4748,0x5E67,0x702B,0x7B92,0x7FF6,0x7D17,0x7320,0x62A0,0x4C88,0x3219,0x14D1,0xF65C,0xD872,0xBCC7,0xA4EC,0x923D,0x85C7,0x8041,0x81FA,0x8AD9,0x9A5F,0xAFA8,0xC980,0xE670,0x04D3,0x22F0,0x3F12,0x579F,0x6B34,0x78B4,0x7F5B,0x7EC7,0x7703,0x687E,0x540B,0x3AD4,0x1E46,0x0000,0xE1BA,0xC52C,0xABF5,0x9782,0x88FD};
16 int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E};
23 int Table[256];
24
17
25 FFT_Device* fft0 = openFFT(0);
18 UART_Device* uart0 = openUART(0);
26 DELAY_Device* delay = openDELAY(0);
19 FIFO_Device* fifotry = openFIFO(0);
27 UART_Device* uart0 = openUART(0);
20 FIFO_Device* fifoIn = openFIFO(1);
28 FIFO_Device* fifoIn = openFIFO(0);
21 FIFO_Device* fifoOut = openFIFO(2);
29 FIFO_Device* fifoOut = openFIFO(1);
30
22
31 printf("\nDebut Main\n\n");
23 printf("\nDebut Main\n\n");
32
24
33 Setup(delay,30000000);
25 FillFifo(fifoIn,0,TblSinA,256);
34
35 FftInput(TblSinA,fft0,delay);
36 FftOutput(Table,fft0);
37 /*for (i = 0 ; i < 256 ; i=i+2)
38 {
39 sprintf(temp,"%x\t%x\n\r",Table[i],Table[i+1]);
40 uartputs(uart0,temp);
41 }*/
42 FillFifo(fifoIn,0,Table);
43 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
26 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
44
27
45 FftInput(TblSinAB,fft0,delay);
28 FillFifo(fifoIn,1,TblSinAB,256);
46 FftOutput(Table,fft0);
47 FillFifo(fifoIn,1,Table);
48 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
29 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
49
30
50 FftInput(TblSinB,fft0,delay);
31 FillFifo(fifoIn,2,TblSinB,256);
51 FftOutput(Table,fft0);
52 FillFifo(fifoIn,2,Table);
53 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
32 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
54
33
55 FftInput(TblSin15K,fft0,delay);
34 FillFifo(fifoIn,3,TblSinBC,256);
56 FftOutput(Table,fft0);
57 FillFifo(fifoIn,3,Table);
58 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
35 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
59
36
60 FftInput(TblSin19K,fft0,delay);
37 FillFifo(fifoIn,4,TblSinC,256);
61 FftOutput(Table,fft0);
62 FillFifo(fifoIn,4,Table);
63 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
38 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
64 printf("ok");
39
65 while(1){
40
41 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
42 printf("\nFull 1\n");
43 while((fifoOut->FIFOreg[(2*1)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
44 printf("\nFull 2\n");
45
46 while(1){
47
48 sprintf(temp,"PONG A\n\r");
49 uartputs(uart0,temp);
66
50
67 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
51 while(i<257){
52 data = (fifoOut->FIFOreg[(2*0)+FIFO_RWdata]);
53 i++;
54 sprintf(temp,"%d\n\r",data);
55 uartputs(uart0,temp);
56 }
68
57
69 data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
58 i=0;
70 data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
59 sprintf(temp,"PONG B\n\r");
60 uartputs(uart0,temp);
71
61
72 sprintf(temp,"%d\t%d\n\r",data1,data2);
62 while(i<257){
63 data = (fifoOut->FIFOreg[(2*1)+FIFO_RWdata]);
64 i++;
65 sprintf(temp,"%d\n\r",data);
73 uartputs(uart0,temp);
66 uartputs(uart0,temp);
67 }
68
69 i=0;
74 }
70 }
75 printf("\nFin Main\n\n");
71 printf("\nFin Main\n\n");
76 return 0;
72 return 0;
77 }
73 }
78
79
80
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@@ -1,44 +1,44
1 #------------------------------------------------------------------------------
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
8 #-- (at your option) any later version.
9 #--
9 #--
10 #-- This program is distributed in the hope that it will be useful,
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
13 #-- GNU General Public License for more details.
14 #--
14 #--
15 #-- You should have received a copy of the GNU General Public License
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
18 #------------------------------------------------------------------------------
19
19
20 include ../../rules.mk
20 include ../../rules.mk
21 LIBDIR = ../../lib
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_uart_Driver -lapb_delay_Driver
24 LIBS=-lapb_fifo_Driver -lapb_uart_Driver -llpp_apb_functions
25 INPUTFILE=main.c
25 INPUTFILE=main.c
26 EXEC=BenchFFT.bin
26 EXEC=BenchFFT.bin
27 OUTBINDIR=bin/
27 OUTBINDIR=bin/
28
28
29
29
30 .PHONY:bin
30 .PHONY:bin
31
31
32 all:bin
32 all:bin
33 @echo $(EXEC)" file created"
33 @echo $(EXEC)" file created"
34
34
35 clean:
35 clean:
36 rm -f *.{o,a}
36 rm -f *.{o,a}
37
37
38
38
39
39
40 help:ruleshelp
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
43 @echo " clean : removes temporary files"
44
44
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@@ -1,45 +1,51
1 #include <stdio.h>
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
3 #include "apb_uart_Driver.h"
4 #include "apb_uart_Driver.h"
4 #include "apb_fft_Driver.h"
5 //#include "TableTest.h"
5 #include "apb_delay_Driver.h"
6
6
7
7
8 int main()
8 int main()
9 {
9 {
10 int i=0,j=0;
11 int data1,data2;
10 char temp[256];
12 char temp[256];
11 int i;
13
12 int Table[256];
14 int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
13 //Somme de 2 sinus//
15 int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD};
14 //int Tablo[256] = {0x00000000,0x0DA20000,0x1B080000,0x27F70000,0x34380000,0x3F960000,0x49E10000,0x52F10000,0x5AA10000,0x60D60000,0x657D0000,0x688C0000,0x69FE0000,0x69DB0000,0x68310000,0x65170000,0x60A90000,0x5B0D0000,0x546D0000,0x4CF90000,0x44E30000,0x3C610000,0x33AA0000,0x2AF40000,0x22750000,0x1A610000,0x12E70000,0x0C310000,0x06660000,0x01A30000,0xFE010000,0xFB8E0000,0xFA520000,0xFA4D0000,0xFB770000,0xFDBE0000,0x010A0000,0x053E0000,0x0A330000,0x0FBF0000,0x15B30000,0x1BDE0000,0x220C0000,0x28080000,0x2D9D0000,0x329B0000,0x36D20000,0x3A170000,0x3C440000,0x3D390000,0x3CDE0000,0x3B210000,0x37F90000,0x33650000,0x2D6D0000,0x26210000,0x1D990000,0x13F30000,0x09570000,0xFDF10000,0xF1F20000,0xE58F0000,0xD9030000,0xCC870000,0xC0560000,0xB4AA0000,0xA9BC0000,0x9FBF0000,0x96E40000,0x8F570000,0x893A0000,0x84AB0000,0x81BF0000,0x80830000,0x80FB0000,0x83220000,0x86EC0000,0x8C430000,0x93090000,0x9B1B0000,0xA44D0000,0xAE700000,0xB9500000,0xC4B40000,0xD0630000,0xDC240000,0xE7BD0000,0xF2F60000,0xFD9A0000,0x077A0000,0x106B0000,0x18480000,0x1EF30000,0x24570000,0x28650000,0x2B160000,0x2C6F0000,0x2C790000,0x2B470000,0x28F30000,0x259E0000,0x216E0000,0x1C8F0000,0x17310000,0x11860000,0x0BC10000,0x06170000,0x00BA0000,0xFBDD0000,0xF7AC0000,0xF44F0000,0xF1EA0000,0xF09C0000,0xF0790000,0xF1900000,0xF3E80000,0xF77E0000,0xFC4A0000,0x02370000,0x092E0000,0x110E0000,0x19AF0000,0x22E40000,0x2C7C0000,0x36420000,0x3FFF0000,0x497C0000,0x52810000,0x5AD70000,0x624B0000,0x68AD0000,0x6DD40000,0x71990000,0x73E10000,0x74950000,0x73A60000,0x71100000,0x6CD60000,0x67040000,0x5FAD0000,0x56EE0000,0x4CEA0000,0x41CD0000,0x35C50000,0x29070000,0x1BCC0000,0x0E4E0000,0x00CA0000,0xF37C0000,0xE69C0000,0xDA620000,0xCF040000,0xC4AE0000,0xBB8B0000,0xB3BC0000,0xAD5C0000,0xA87D0000,0xA5290000,0xA3630000,0xA3220000,0xA4590000,0xA6EF0000,0xAAC80000,0xAFBD0000,0xB5A40000,0xBC4F0000,0xC38B0000,0xCB220000,0xD2E00000,0xDA8E0000,0xE1F70000,0xE8EC0000,0xEF3C0000,0xF4C10000,0xF9560000,0xFCDF0000,0xFF470000,0x007F0000,0x00850000,0xFF5C0000,0xFD0B0000,0xF9A80000,0xF54B0000,0xF0170000,0xEA320000,0xE3C90000,0xDD0B0000,0xD62B0000,0xCF5F0000,0xC8DA0000,0xC2D30000,0xBD7A0000,0xB8FF0000,0xB58D0000,0xB3490000,0xB2510000,0xB2BE0000,0xB49F0000,0xB7FC0000,0xBCD60000,0xC3220000,0xCAD10000,0xD3C70000,0xDDE50000,0xE9030000,0xF4F20000,0x01800000,0x0E770000,0x1B9D0000,0x28B70000,0x35880000,0x41D70000,0x4D6C0000,0x58100000,0x61950000,0x69D00000,0x709C0000,0x75DE0000,0x79800000,0x7B750000,0x7BBB0000,0x7A570000,0x77550000,0x72CB0000,0x6CD70000,0x659E0000,0x5D490000,0x54090000,0x4A110000,0x3F980000,0x34D80000,0x2A090000,0x1F630000,0x151D0000,0x0B690000,0x02760000,0xFA6F0000,0xF3730000,0xEDA10000,0xE90B0000,0xE5BF0000,0xE3C00000,0xE30A0000,0xE38F0000,0xE53D0000,0xE7F80000,0xEB9D0000,0xF0050000,0xF5030000,0xFA680000,0x00000000,0x05980000,0x0AFD0000,0x0FFB0000,0x14630000,0x18080000};
16 int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
15 //1 Sinus//
17 int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C};
16 int Tablo[256] = {0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000};
18 int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E};
17 printf("Debut Main\n\n");
19
18 UART_Device* uart0 = openUART(0);
20 UART_Device* uart0 = openUART(0);
19 FFT_Device* fft0 = openFFT(0);
21 FIFO_Device* fifotry = openFIFO(0);
20 DELAY_Device* delay = openDELAY(0);
22 FIFO_Device* fifoIn = openFIFO(1);
23 FIFO_Device* fifoOut = openFIFO(2);
24
25 printf("\nDebut Main\n\n");
21
26
22 printf("addr_fft: %x\n",(unsigned int)fft0);
27 FillFifo(fifoIn,0,TblSinA,256);
23 printf("addr_uart: %x\n\n",(unsigned int)uart0);
28 FillFifo(fifoIn,1,TblSinAB,256);
24 printf("cfg_fft: %x\n",fft0->ConfigReg);
29 FillFifo(fifoIn,2,TblSinB,256);
25 printf("cfg_uart: %x\n\n",uart0->ConfigReg);
30 FillFifo(fifoIn,3,TblSinBC,256);
31 FillFifo(fifoIn,4,TblSinC,256);
32
33 while(j<5){
34 while((fifoOut->FIFOreg[(2*j)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
26
35
27 while(1)
36 sprintf(temp,"FIFO %d\n\r",j);
28 {
37 uartputs(uart0,temp);
29 FftInput(Tablo,fft0,delay);
38 //while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS
30 /* for (i = 0 ; i < 256 ; i++)
39 while(i < 128){
31 {
40 data1 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex;
32 sprintf(temp,"%x/in",Tablo[i]);
41 data2 = (fifoOut->FIFOreg[(2*j)+FIFO_RWdata]) & Mask_4hex;
33 uartputs(uart0,temp);
42 i++;
34 }*/
43 sprintf(temp,"%d\t%d\n\r",data1,data2);
35
36 FftOutput(Table,fft0);
37 for (i = 0 ; i < 128 ; i++)
38 {
39 sprintf(temp,"%x/out",Table[i]);
40 uartputs(uart0,temp);
44 uartputs(uart0,temp);
41 }
45 }
46 i=0;
47 j++;
42 }
48 }
49 printf("\nFin Main\n\n");
43 return 0;
50 return 0;
44 }
51 }
45
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@@ -1,174 +1,174
1 #include <stdio.h>
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_Matrix_Driver.h"
4 #include "apb_Matrix_Driver.h"
5 #include "apb_uart_Driver.h"
5 #include "apb_uart_Driver.h"
6 #include "apb_gpio_Driver.h"
6 #include "apb_gpio_Driver.h"
7
7
8 ///////////// Matrix With 2 FIFO Input /////////////////////////////////////////////
8 ///////////// Matrix With 2 FIFO Input /////////////////////////////////////////////
9 int main()
9 int main()
10 {
10 {
11 int i=0,save;
11 int i=0,save;
12 char temp[256];
12 char temp[256];
13 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
13 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
14 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
14 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
15 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
15 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
16 // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
16 // int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
17 // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
17 // int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
18 int Table[256];
18 int Table[256];
19
19
20
20
21 FIFO_Device* fifoX = openFIFO(0);
21 FIFO_Device* fifoX = openFIFO(0);
22 UART_Device* uart0 = openUART(0);
22 UART_Device* uart0 = openUART(0);
23 FIFO_Device* fifoIn = openFIFO(1);
23 FIFO_Device* fifoIn = openFIFO(1);
24 MATRIX_Device* mspec = openMatrix(0);
24 MATRIX_Device* mspec = openMatrix(0);
25 FIFO_Device* fifoOut = openFIFO(2);
25 FIFO_Device* fifoOut = openFIFO(2);
26 GPIO_Device* gpio0 = openGPIO(0);
26 GPIO_Device* gpio0 = openGPIO(0);
27
27
28 printf("\nDebut Main\n\n");
28 printf("\nDebut Main\n\n");
29
29
30 gpio0->oen = 0x3;
30 gpio0->oen = 0x3;
31 gpio0->Dout = 0x0;
31 gpio0->Dout = 0x0;
32
32
33 ///////////////////////////////////////////////////////////////////////////
33 ///////////////////////////////////////////////////////////////////////////
34 mspec->Statu = 2;
34 mspec->Statu = 2;
35 FillFifo(fifoIn,0,TblB1);
35 FillFifo(fifoIn,0,TblB1,256);
36 FillFifo(fifoIn,1,TblB2);
36 FillFifo(fifoIn,1,TblB2,256);
37 gpio0->Dout = 0x1;
37 gpio0->Dout = 0x1;
38
38
39 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
39 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
40 {
40 {
41 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
41 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
42 i++;
42 i++;
43 }
43 }
44 save = i;
44 save = i;
45 gpio0->Dout = 0x2;
45 gpio0->Dout = 0x2;
46
46
47 sprintf(temp,"\nReels\tImaginaires\n\r");
47 sprintf(temp,"\nReels\tImaginaires\n\r");
48 uartputs(uart0,temp);
48 uartputs(uart0,temp);
49 for (i = 0 ; i < save ; i+=2)
49 for (i = 0 ; i < save ; i+=2)
50 {
50 {
51 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
51 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
52 uartputs(uart0,temp);
52 uartputs(uart0,temp);
53 }
53 }
54 i = 0;
54 i = 0;
55 gpio0->Dout = 0x0;
55 gpio0->Dout = 0x0;
56
56
57 ///////////////////////////////////////////////////////////////////////////
57 ///////////////////////////////////////////////////////////////////////////
58 mspec->Statu = 1;
58 mspec->Statu = 1;
59 FillFifo(fifoIn,0,TblB1);
59 FillFifo(fifoIn,0,TblB1,256);
60 gpio0->Dout = 0x1;
60 gpio0->Dout = 0x1;
61 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
61 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
62 {
62 {
63 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
63 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
64 i++;
64 i++;
65 }
65 }
66 save = i;
66 save = i;
67 gpio0->Dout = 0x2;
67 gpio0->Dout = 0x2;
68
68
69 sprintf(temp,"\nReels\n\r");
69 sprintf(temp,"\nReels\n\r");
70 uartputs(uart0,temp);
70 uartputs(uart0,temp);
71 for (i = 0 ; i < save ; i++)
71 for (i = 0 ; i < save ; i++)
72 {
72 {
73 sprintf(temp,"%d\n\r",Table[i]);
73 sprintf(temp,"%d\n\r",Table[i]);
74 uartputs(uart0,temp);
74 uartputs(uart0,temp);
75 }
75 }
76 i = 0;
76 i = 0;
77 gpio0->Dout = 0x0;
77 gpio0->Dout = 0x0;
78
78
79 ///////////////////////////////////////////////////////////////////////////
79 ///////////////////////////////////////////////////////////////////////////
80 mspec->Statu = 4;
80 mspec->Statu = 4;
81 FillFifo(fifoIn,0,TblB1);
81 FillFifo(fifoIn,0,TblB1,256);
82 FillFifo(fifoIn,1,TblB3);
82 FillFifo(fifoIn,1,TblB3,256);
83 gpio0->Dout = 0x1;
83 gpio0->Dout = 0x1;
84
84
85 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
85 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty) // TANT QUE empty a 0 ALORS
86 {
86 {
87 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
87 Table[i] = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
88 i++;
88 i++;
89 }
89 }
90 save = i;
90 save = i;
91 gpio0->Dout = 0x2;
91 gpio0->Dout = 0x2;
92
92
93 sprintf(temp,"\nReels\tImaginaires\n\r");
93 sprintf(temp,"\nReels\tImaginaires\n\r");
94 uartputs(uart0,temp);
94 uartputs(uart0,temp);
95 for (i = 0 ; i < save ; i+=2)
95 for (i = 0 ; i < save ; i+=2)
96 {
96 {
97 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
97 sprintf(temp,"%d\t%d\n\r",Table[i],Table[i+1]);
98 uartputs(uart0,temp);
98 uartputs(uart0,temp);
99 }
99 }
100 i = 0;
100 i = 0;
101 gpio0->Dout = 0x0;
101 gpio0->Dout = 0x0;
102
102
103 printf("\nFin Main\n\n");
103 printf("\nFin Main\n\n");
104 return 0;
104 return 0;
105 }
105 }
106
106
107
107
108 ///////////// Matrix With 5 FIFO Input /////////////////////////////////////////////
108 ///////////// Matrix With 5 FIFO Input /////////////////////////////////////////////
109 int main2()
109 int main2()
110 {
110 {
111 int save1,save2;
111 int save1,save2;
112 char temp[256];
112 char temp[256];
113 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
113 int TblB1[256] = {0x0001,0x0002,0x0003,0x0004,0x0005,0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100};
114 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
114 int TblB2[256] = {0x0006,0x0007,0x0008,0x0009,0x000A,0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105};
115 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
115 int TblB3[256] = {0x000B,0x000C,0x000D,0x000E,0x000F,0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A};
116 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
116 int TblE1[256] = {0x0010,0x0011,0x0012,0x0013,0x0014,0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F};
117 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
117 int TblE2[256] = {0x0015,0x0016,0x0017,0x0018,0x0019,0x001A,0x001B,0x001C,0x001D,0x001E,0x001F,0x0020,0x0021,0x0022,0x0023,0x0024,0x0025,0x0026,0x0027,0x0028,0x0029,0x002A,0x002B,0x002C,0x002D,0x002E,0x002F,0x0030,0x0031,0x0032,0x0033,0x0034,0x0035,0x0036,0x0037,0x0038,0x0039,0x003A,0x003B,0x003C,0x003D,0x003E,0x003F,0x0040,0x0041,0x0042,0x0043,0x0044,0x0045,0x0046,0x0047,0x0048,0x0049,0x004A,0x004B,0x004C,0x004D,0x004E,0x004F,0x0050,0x0051,0x0052,0x0053,0x0054,0x0055,0x0056,0x0057,0x0058,0x0059,0x005A,0x005B,0x005C,0x005D,0x005E,0x005F,0x0060,0x0061,0x0062,0x0063,0x0064,0x0065,0x0066,0x0067,0x0068,0x0069,0x006A,0x006B,0x006C,0x006D,0x006E,0x006F,0x0070,0x0071,0x0072,0x0073,0x0074,0x0075,0x0076,0x0077,0x0078,0x0079,0x007A,0x007B,0x007C,0x007D,0x007E,0x007F,0x0080,0x0081,0x0082,0x0083,0x0084,0x0085,0x0086,0x0087,0x0088,0x0089,0x008A,0x008B,0x008C,0x008D,0x008E,0x008F,0x0090,0x0091,0x0092,0x0093,0x0094,0x0095,0x0096,0x0097,0x0098,0x0099,0x009A,0x009B,0x009C,0x009D,0x009E,0x009F,0x00A0,0x00A1,0x00A2,0x00A3,0x00A4,0x00A5,0x00A6,0x00A7,0x00A8,0x00A9,0x00AA,0x00AB,0x00AC,0x00AD,0x00AE,0x00AF,0x00B0,0x00B1,0x00B2,0x00B3,0x00B4,0x00B5,0x00B6,0x00B7,0x00B8,0x00B9,0x00BA,0x00BB,0x00BC,0x00BD,0x00BE,0x00BF,0x00C0,0x00C1,0x00C2,0x00C3,0x00C4,0x00C5,0x00C6,0x00C7,0x00C8,0x00C9,0x00CA,0x00CB,0x00CC,0x00CD,0x00CE,0x00CF,0x00D0,0x00D1,0x00D2,0x00D3,0x00D4,0x00D5,0x00D6,0x00D7,0x00D8,0x00D9,0x00DA,0x00DB,0x00DC,0x00DD,0x00DE,0x00DF,0x00E0,0x00E1,0x00E2,0x00E3,0x00E4,0x00E5,0x00E6,0x00E7,0x00E8,0x00E9,0x00EA,0x00EB,0x00EC,0x00ED,0x00EE,0x00EF,0x00F0,0x00F1,0x00F2,0x00F3,0x00F4,0x00F5,0x00F6,0x00F7,0x00F8,0x00F9,0x00FA,0x00FB,0x00FC,0x00FD,0x00FE,0x00FF,0x0100,0x0101,0x0102,0x0103,0x0104,0x0105,0x0106,0x0107,0x0108,0x0109,0x010A,0x010B,0x010C,0x010D,0x010E,0x010F,0x0110,0x0111,0x0112,0x0113,0x0114};
118
118
119 FIFO_Device* fifoX = openFIFO(0);
119 FIFO_Device* fifoX = openFIFO(0);
120 UART_Device* uart0 = openUART(0);
120 UART_Device* uart0 = openUART(0);
121 FIFO_Device* fifoIn = openFIFO(1);
121 FIFO_Device* fifoIn = openFIFO(1);
122 FIFO_Device* fifoOut = openFIFO(2);
122 FIFO_Device* fifoOut = openFIFO(2);
123
123
124 printf("\nDebut Main\n\n");
124 printf("\nDebut Main\n\n");
125
125
126 FillFifo(fifoIn,0,TblB1);
126 FillFifo(fifoIn,0,TblB1,256);
127 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
127 fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*0)+FIFO_Ctrl] | FIFO_ReUse);
128
128
129 FillFifo(fifoIn,1,TblB2);
129 FillFifo(fifoIn,1,TblB2,256);
130 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
130 fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*1)+FIFO_Ctrl] | FIFO_ReUse);
131
131
132 FillFifo(fifoIn,2,TblB3);
132 FillFifo(fifoIn,2,TblB3,256);
133 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
133 fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*2)+FIFO_Ctrl] | FIFO_ReUse);
134
134
135 FillFifo(fifoIn,3,TblE1);
135 FillFifo(fifoIn,3,TblE1,256);
136 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
136 fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*3)+FIFO_Ctrl] | FIFO_ReUse);
137
137
138 FillFifo(fifoIn,4,TblE2);
138 FillFifo(fifoIn,4,TblE2,256);
139
139
140 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
140 fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] = (fifoIn->FIFOreg[(2*4)+FIFO_Ctrl] | FIFO_ReUse);
141
141
142 while(1){
142 while(1){
143
143
144 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
144 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
145
145
146 save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
146 save1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
147 save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
147 save2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
148
148
149 sprintf(temp,"%d\t%d\n\r",save1,save2);
149 sprintf(temp,"%d\t%d\n\r",save1,save2);
150 uartputs(uart0,temp);
150 uartputs(uart0,temp);
151 }
151 }
152 printf("\nFin Main\n\n");
152 printf("\nFin Main\n\n");
153 return 0;
153 return 0;
154 }
154 }
155
155
156
156
157
157
158
158
159 /////////////////// Test R/W Fifo OKAI ///////////////////////////////////
159 /////////////////// Test R/W Fifo OKAI ///////////////////////////////////
160
160
161 /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11;
161 /*fifoX->FIFOreg[(2*0)+FIFO_RWdata] = 0x11;
162 Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata];
162 Table[1] = fifoX->FIFOreg[(2*0)+FIFO_RWdata];
163 printf("data: %x\n",Table[1]);
163 printf("data: %x\n",Table[1]);
164
164
165 FillFifo(fifoX,0,TblX);
165 FillFifo(fifoX,0,TblX);
166 for (i = 1 ; i < 8 ; i++)
166 for (i = 1 ; i < 8 ; i++)
167 {
167 {
168 Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex;
168 Table[i] = fifoX->FIFOreg[(2*0)+FIFO_RWdata] & Mask_2hex;
169 }
169 }
170 printf("data: %x\n",Table[1]);
170 printf("data: %x\n",Table[1]);
171 printf("data: %x\n",Table[2]);
171 printf("data: %x\n",Table[2]);
172 printf("data: %x\n",Table[3]);
172 printf("data: %x\n",Table[3]);
173 printf("data: %x\n",Table[4]);*/
173 printf("data: %x\n",Table[4]);*/
174
174
Show file before | Show file after | Hide comments
@@ -1,76 +1,76
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FIFO_DRIVER_H
22 #ifndef APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
24
24
25 /*! \file apb_fifo_Driver.h
25 /*! \file apb_fifo_Driver.h
26 \brief LPP FIFO driver.
26 \brief LPP FIFO driver.
27
27
28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
29 used in many type of application.
29 used in many type of application.
30
30
31 \todo Check "DEVICE1 => count = 2" function Open
31 \todo Check "DEVICE1 => count = 2" function Open
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
33 */
34 #define FIFO_Ctrl 0
34 #define FIFO_Ctrl 0
35 #define FIFO_RWdata 1
35 #define FIFO_RWdata 1
36
36
37 #define FIFO_Full 0x00010000
37 #define FIFO_Full 0x00010000
38 #define FIFO_Empty 0x00000001
38 #define FIFO_Empty 0x00000001
39 #define FIFO_ReUse 0x00000002
39 #define FIFO_ReUse 0x00000002
40
40
41 #define Mask_2hex 0x000000FF
41 #define Mask_2hex 0x000000FF
42 #define Mask_4hex 0x0000FFFF
42 #define Mask_4hex 0x0000FFFF
43
43
44
44
45 /*===================================================
45 /*===================================================
46 T Y P E S D E F
46 T Y P E S D E F
47 ====================================================*/
47 ====================================================*/
48
48
49 /*! \struct APB_FIFO_REG
49 /*! \struct APB_FIFO_REG
50 \brief Sturcture representing the fifo registers
50 \brief Sturcture representing the fifo registers
51 */
51 */
52 struct APB_FIFO_REG
52 struct APB_FIFO_REG
53 {
53 {
54 int IDreg;
54 volatile int IDreg;
55 int FIFOreg[2*8];
55 volatile int FIFOreg[2*8];
56 };
56 };
57
57
58 typedef volatile struct APB_FIFO_REG FIFO_Device;
58 typedef volatile struct APB_FIFO_REG FIFO_Device;
59
59
60 /*===================================================
60 /*===================================================
61 F U N C T I O N S
61 F U N C T I O N S
62 ====================================================*/
62 ====================================================*/
63
63
64 /*! \fn APB_FIFO_Device* apbfifoOpen(int count);
64 /*! \fn APB_FIFO_Device* apbfifoOpen(int count);
65 \brief Return count FIFO.
65 \brief Return count FIFO.
66
66
67 This Function scans APB devices table and returns count FIFO.
67 This Function scans APB devices table and returns count FIFO.
68
68
69 \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want
69 \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want
70 to use FIFO1 so count = 1.
70 to use FIFO1 so count = 1.
71 \return The pointer to the device.
71 \return The pointer to the device.
72 */
72 */
73 FIFO_Device* openFIFO(int count);
73 FIFO_Device* openFIFO(int count);
74 int FillFifo(FIFO_Device* dev,int ID,int Tbl[]);
74 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count);
75
75
76 #endif
76 #endif
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@@ -1,44 +1,53
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #include "lpp_apb_functions.h"
22 #include "lpp_apb_functions.h"
23 #include "apb_fifo_Driver.h"
23 #include "apb_fifo_Driver.h"
24 #include <stdio.h>
24 #include <stdio.h>
25
25
26
26
27 FIFO_Device* openFIFO(int count)
27 FIFO_Device* openFIFO(int count)
28 {
28 {
29 FIFO_Device* fifo0;
29 FIFO_Device* fifo0;
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
31 return fifo0;
31 return fifo0;
32 }
32 }
33
33
34
34
35 int FillFifo(FIFO_Device* dev,int ID,int Tbl[])
35 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count)
36 {
36 {
37 int i=0;
37 int i=0;
38 while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full) // TANT QUE full a 0 ALORS
38 //int poub;
39 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
40 while(i<count)
41 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS
39 {
42 {
43 //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);
44 //printf("%d\n",i);
40 dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i];
45 dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[i];
41 i++;
46 i++;
42 }
47 }
48 //poub = dev->FIFOreg[(2*ID)+FIFO_RWdata];
49 //dev->FIFOreg[(2*ID)+FIFO_RWdata] = Tbl[0];
50 //printf("END:%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);
51 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full); // TANT QUE full a 0 RIEN
43 return 0;
52 return 0;
44 }
53 }
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@@ -1,76 +1,76
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FIFO_DRIVER_H
22 #ifndef APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
23 #define APB_FIFO_DRIVER_H
24
24
25 /*! \file apb_fifo_Driver.h
25 /*! \file apb_fifo_Driver.h
26 \brief LPP FIFO driver.
26 \brief LPP FIFO driver.
27
27
28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
29 used in many type of application.
29 used in many type of application.
30
30
31 \todo Check "DEVICE1 => count = 2" function Open
31 \todo Check "DEVICE1 => count = 2" function Open
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
33 */
34 #define FIFO_Ctrl 0
34 #define FIFO_Ctrl 0
35 #define FIFO_RWdata 1
35 #define FIFO_RWdata 1
36
36
37 #define FIFO_Full 0x00010000
37 #define FIFO_Full 0x00010000
38 #define FIFO_Empty 0x00000001
38 #define FIFO_Empty 0x00000001
39 #define FIFO_ReUse 0x00000002
39 #define FIFO_ReUse 0x00000002
40
40
41 #define Mask_2hex 0x000000FF
41 #define Mask_2hex 0x000000FF
42 #define Mask_4hex 0x0000FFFF
42 #define Mask_4hex 0x0000FFFF
43
43
44
44
45 /*===================================================
45 /*===================================================
46 T Y P E S D E F
46 T Y P E S D E F
47 ====================================================*/
47 ====================================================*/
48
48
49 /*! \struct APB_FIFO_REG
49 /*! \struct APB_FIFO_REG
50 \brief Sturcture representing the fifo registers
50 \brief Sturcture representing the fifo registers
51 */
51 */
52 struct APB_FIFO_REG
52 struct APB_FIFO_REG
53 {
53 {
54 int IDreg;
54 volatile int IDreg;
55 int FIFOreg[2*8];
55 volatile int FIFOreg[2*8];
56 };
56 };
57
57
58 typedef volatile struct APB_FIFO_REG FIFO_Device;
58 typedef volatile struct APB_FIFO_REG FIFO_Device;
59
59
60 /*===================================================
60 /*===================================================
61 F U N C T I O N S
61 F U N C T I O N S
62 ====================================================*/
62 ====================================================*/
63
63
64 /*! \fn APB_FIFO_Device* apbfifoOpen(int count);
64 /*! \fn APB_FIFO_Device* apbfifoOpen(int count);
65 \brief Return count FIFO.
65 \brief Return count FIFO.
66
66
67 This Function scans APB devices table and returns count FIFO.
67 This Function scans APB devices table and returns count FIFO.
68
68
69 \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want
69 \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want
70 to use FIFO1 so count = 1.
70 to use FIFO1 so count = 1.
71 \return The pointer to the device.
71 \return The pointer to the device.
72 */
72 */
73 FIFO_Device* openFIFO(int count);
73 FIFO_Device* openFIFO(int count);
74 int FillFifo(FIFO_Device* dev,int ID,int Tbl[]);
74 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count);
75
75
76 #endif
76 #endif
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@@ -1,157 +1,121
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity Driver_FFT is
26 entity Driver_FFT is
27 generic(
27 generic(
28 Data_sz : integer range 1 to 32 := 16
28 Data_sz : integer range 1 to 32 := 16;
29 NbData : integer range 1 to 512 := 256
29 );
30 );
30 port(
31 port(
31 clk : in std_logic;
32 clk : in std_logic;
32 rstn : in std_logic;
33 rstn : in std_logic;
33 Load : in std_logic;
34 Load : in std_logic;
34 Empty : in std_logic_vector(4 downto 0);
35 Empty : in std_logic_vector(4 downto 0);
35 Full : in std_logic_vector(4 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
37 Valid : out std_logic;
37 Valid : out std_logic;
38 Read : out std_logic_vector(4 downto 0);
38 Read : out std_logic_vector(4 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
41 );
41 );
42 end entity;
42 end entity;
43
43
44
44
45 architecture ar_Driver of Driver_FFT is
45 architecture ar_Driver of Driver_FFT is
46
46
47 type etat is (eX,e0,e1,e2);
47 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
48 signal ect : etat;
49
49
50 signal FifoCpt : integer;
50 signal DataCount : integer range 0 to 255 := 0;
51 --signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
51 signal FifoCpt : integer range 0 to 4 := 0;
52
52
53 signal sEmpty : std_logic;
53 signal sLoad : std_logic;
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56
54
57 begin
55 begin
58
56
59 process(clk,rstn)
57 process(clk,rstn)
60 begin
58 begin
61 if(rstn='0')then
59 if(rstn='0')then
62 ect <= eX;
60 ect <= e0;
63 Read <= (others => '1');
61 Read <= (others => '1');
64 Valid <= '0';
62 Valid <= '0';
65 FifoCpt <= 1;
66 Data_re <= (others => '0');
63 Data_re <= (others => '0');
67 Data_im <= (others => '0');
64 Data_im <= (others => '0');
65 DataCount <= 0;
66 FifoCpt <= 0;
67 sLoad <= '0';
68
68
69 elsif(clk'event and clk='1')then
69 elsif(clk'event and clk='1')then
70 sLoad <= Load;
70
71
72 if(sLoad='1' and Load='0')then
73 if(FifoCpt=4)then
74 FifoCpt <= 0;
75 else
76 FifoCpt <= FifoCpt + 1;
77 end if;
78 end if;
79
71 case ect is
80 case ect is
72
81
73 when eX =>
74 if(sFull='1')then
75 ect <= e0;
76 end if;
77
78 when e0 =>
82 when e0 =>
79 Valid <= '0';
83 if(Load='1' and Empty(FifoCpt)='0')then
80 if(Load='1' and sEmpty='0')then
84 Read(FifoCpt) <= '0';
81 Read(FifoCpt-1) <= '0';
85 ect <= e1;
82 ect <= e2;
83 -- ect <= e1;
84 elsif(sEmpty='1')then
85 if(FifoCpt=6)then
86 FifoCpt <= 1;
87 else
88 FifoCpt <= FifoCpt+1;
89 end if;
90 ect <= eX;
91 end if;
86 end if;
92
87
93 when e1 =>
88 when e1 =>
94 null;
89 Valid <= '0';
95 -- DataTmp <= sData;
90 Read(FifoCpt) <= '1';
96 -- ect <= e2;
91 ect <= e2;
97
92
98 when e2 =>
93 when e2 =>
99 Read(FifoCpt-1) <= '1';
94 Data_re <= DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz));
100 Data_re <= sData;
101 Data_im <= (others => '0');
95 Data_im <= (others => '0');
102 -- Data_re <= DataTmp;
103 -- Data_im <= sData;
104 Valid <= '1';
96 Valid <= '1';
97 if(DataCount=NbData-1)then
98 DataCount <= 0;
99 ect <= eX;
100 else
101 DataCount <= DataCount + 1;
102 if(Load='1' and Empty(FifoCpt)='0')then
103 Read(FifoCpt) <= '0';
104 ect <= e1;
105 else
106 ect <= eX;
107 end if;
108 end if;
109
110 when eX =>
111 Valid <= '0';
105 ect <= e0;
112 ect <= e0;
106
113
114 when others =>
115 null;
107
116
108 end case;
117 end case;
109 end if;
118 end if;
110 end process;
119 end process;
111
120
112 with FifoCpt select
121 end architecture; No newline at end of file
113 sFull <= Full(0) when 1,
114 Full(1) when 2,
115 Full(2) when 3,
116 Full(3) when 4,
117 Full(4) when 5,
118 '1' when others;
119
120 with FifoCpt select
121 sEmpty <= Empty(0) when 1,
122 Empty(1) when 2,
123 Empty(2) when 3,
124 Empty(3) when 4,
125 Empty(4) when 5,
126 '1' when others;
127
128 with FifoCpt select
129 sData <= DATA(Data_sz-1 downto 0) when 1,
130 DATA((2*Data_sz)-1 downto Data_sz) when 2,
131 DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
132 DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
133 DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
134 (others => '0') when others;
135
136 end architecture;
137
138
139
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142
143
144
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147
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149
150
151
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153
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155
156
157
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@@ -1,95 +1,121
1 -- FFTamont.vhd
1 -- FFTamont.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity FFTamont is
6 entity FFTamont is
7 generic(
7 generic(
8 Data_sz : integer range 1 to 32 := 16
8 Data_sz : integer range 1 to 32 := 16;
9 NbData : integer range 1 to 512 := 256
9 );
10 );
10 port(
11 port(
11 clk : in std_logic;
12 clk : in std_logic;
12 rstn : in std_logic;
13 rstn : in std_logic;
13 Load : in std_logic;
14 Load : in std_logic;
14 Empty : in std_logic;
15 Empty : in std_logic;
15 Full : in std_logic;
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
17 Valid : out std_logic;
17 Valid : out std_logic;
18 Read : out std_logic;
18 Read : out std_logic;
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
21 );
21 );
22 end entity;
22 end entity;
23
23
24
24
25 architecture ar_FFTamont of FFTamont is
25 architecture ar_FFTamont of FFTamont is
26
26
27 type etat is (eX,e0,e1,e2);
27 type etat is (eX,e0,e1,e2);
28 signal ect : etat;
28 signal ect : etat;
29
29
30 signal DataCount : integer;
30
31
31 begin
32 begin
32
33
33 process(clk,rstn)
34 process(clk,rstn)
34 begin
35 begin
35 if(rstn='0')then
36 if(rstn='0')then
36 ect <= eX;
37 ect <= e0;
37 Read <= '1';
38 Read <= '1';
38 Valid <= '0';
39 Valid <= '0';
39 Data_re <= (others => '0');
40 Data_re <= (others => '0');
40 Data_im <= (others => '0');
41 Data_im <= (others => '0');
42 DataCount <= 0;
41
43
42 elsif(clk'event and clk='1')then
44 elsif(clk'event and clk='1')then
43
44 case ect is
45 case ect is
45
46
46 when eX =>
47 if(Full='1')then
48 ect <= e0;
49 end if;
50
51 when e0 =>
47 when e0 =>
52 Valid <= '0';
53 if(Load='1' and Empty='0')then
48 if(Load='1' and Empty='0')then
54 Read <= '0';
49 Read <= '0';
55 ect <= e1;
50 ect <= e1;
56 elsif(Empty='1')then
57 ect <= eX;
58 end if;
51 end if;
59
52
60 when e1 =>
53 when e1 =>
54 Valid <= '0';
61 Read <= '1';
55 Read <= '1';
56 ect <= e2;
57
58 when e2 =>
62 Data_re <= DATA;
59 Data_re <= DATA;
63 Data_im <= (others => '0');
60 Data_im <= (others => '0');
64 Valid <= '1';
61 Valid <= '1';
65 ect <= e0;
62 if(DataCount=NbData-1)then
66
63 DataCount <= 0;
67 when e2 =>
64 ect <= eX;
68 null;
65 else
66 DataCount <= DataCount + 1;
67 if(Load='1' and Empty='0')then
68 Read <= '0';
69 ect <= e1;
70 else
71 ect <= eX;
72 end if;
73 end if;
74
75 when eX =>
76 Valid <= '0';
77 ect <= e0;
78
79 when others =>
80 null;
69
81
70 end case;
82 end case;
83
84 --***********************************************************
85 -- Chargement Rapide (toutes a la suite)
86 --***********************************************************
87 -- case ect is
88 --
89 -- when e0 =>
90 -- if(Load='1' and Empty='0')then
91 -- Read <= '0';
92 -- ect <= eX;
93 -- end if;
94 --
95 -- when eX =>
96 -- ect <= e1;
97 --
98 -- when e1 =>
99 -- Data_re <= DATA;
100 -- Data_im <= (others => '0');
101 -- Valid <= '1';
102 -- if(DataCount=NbData-2)then
103 -- Read <= '1';
104 -- DataCount <= DataCount + 1;
105 -- elsif(DataCount=NbData)then
106 -- Valid <= '0';
107 -- DataCount <= 0;
108 -- ect <= e0;
109 -- else
110 -- DataCount <= DataCount + 1;
111 -- end if;
112 --
113 -- when others =>
114 -- null;
115 --
116 -- end case;
117 --***********************************************************
71 end if;
118 end if;
72 end process;
119 end process;
73
120
74 end architecture;
121 end architecture;
75
76
77
78
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80
81
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83
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@@ -1,90 +1,90
1 -- FFTaval.vhd
1 -- FFTaval.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity FFTaval is
6 entity FFTaval is
7 generic(
7 generic(
8 Data_sz : integer range 1 to 32 := 8
8 Data_sz : integer range 1 to 32 := 8;
9 NbData : integer range 1 to 512 := 256
9 );
10 );
10 port(
11 port(
11 clk : in std_logic;
12 clk : in std_logic;
12 rstn : in std_logic;
13 rstn : in std_logic;
13 Ready : in std_logic;
14 Ready : in std_logic;
14 Valid : in std_logic;
15 Valid : in std_logic;
15 Full : in std_logic;
16 Full : in std_logic;
16 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Read : out std_logic;
19 Read : out std_logic;
19 Write : out std_logic;
20 Write : out std_logic;
20 ReUse : out std_logic;
21 ReUse : out std_logic;
21 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 );
23 );
23 end entity;
24 end entity;
24
25
25
26
26 architecture ar_FFTaval of FFTaval is
27 architecture ar_FFTaval of FFTaval is
27
28
28 type etat is (eX,e0,e1,e2,e3);
29 type etat is (eX,e0,e1,e2,e3);
29 signal ect : etat;
30 signal ect : etat;
30
31
31 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32
33
33 signal sReady : std_logic;
34 signal sRead : std_logic;
35 signal DataCount : integer;
34
36
35 begin
37 begin
36
38
37 process(clk,rstn)
39 process(clk,rstn)
38 begin
40 begin
39 if(rstn='0')then
41 if(rstn='0')then
40 ect <= e0;
42 ect <= e0;
41 Read <= '0';
43 sRead <= '0';
42 Write <= '1';
44 Write <= '1';
43 Reuse <= '0';
45 Reuse <= '0';
46 DataCount <= 0;
44
47
45 elsif(clk'event and clk='1')then
48 elsif(clk'event and clk='1')then
46 sReady <= Ready;
49
50 if(Ready='1')then
51 sRead <= not sRead;
52 else
53 sRead <= '0';
54 end if;
47
55
56 if(DataCount=NbData or Ready='0')then
57 DataCount <= 0;
58 elsif(Valid='1')then
59 DataCount <= DataCount+1;
60 end if;
61
62
48 case ect is
63 case ect is
49
64
50 when e0 =>
65 when e0 =>
51 Write <= '1';
66 Write <= '1';
52 if(sReady='0' and Ready='1' and full='0')then
53 Read <= '1';
54 ect <= e1;
55 end if;
56
57 when e1 =>
58 Read <= '0';
59 if(Valid='1' and full='0')then
67 if(Valid='1' and full='0')then
60 DataTmp <= Data_im;
68 DataTmp <= Data_im;
61 DATA <= Data_re;
69 DATA <= Data_re;
62 Write <= '0';
70 Write <= '0';
63 ect <= e2;
71 ect <= e1;
64 elsif(full='1')then
72 elsif(full='1')then
65 ReUse <= '1';
73 ReUse <= '1';
66 ect <= e0;
67 end if;
74 end if;
68
75
69 when e2 =>
76 when e1 =>
70 DATA <= DataTmp;
77 DATA <= DataTmp;
71 ect <= e3;
78 ect <= e0;
72
73 when e3 =>
74 Write <= '1';
75 if(Ready='1' and full='0')then
76 Read <= '1';
77 ect <= e1;
78 end if;
79
79
80 when eX =>
80 when others =>
81 null;
81 null;
82
82
83 end case;
83 end case;
84 end if;
84 end if;
85 end process;
85 end process;
86
86
87
87 Read <= sRead;
88
88
89 end architecture;
89 end architecture;
90
90
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@@ -1,129 +1,112
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25
25
26 entity Linker_FFT is
26 entity Linker_FFT is
27 generic(
27 generic(
28 Data_sz : integer range 1 to 32 := 8
28 Data_sz : integer range 1 to 32 := 16;
29 NbData : integer range 1 to 512 := 256
29 );
30 );
30 port(
31 port(
31 clk : in std_logic;
32 clk : in std_logic;
32 rstn : in std_logic;
33 rstn : in std_logic;
33 Ready : in std_logic;
34 Ready : in std_logic;
34 Valid : in std_logic;
35 Valid : in std_logic;
35 Full : in std_logic_vector(4 downto 0);
36 Full : in std_logic_vector(4 downto 0);
36 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Read : out std_logic;
39 Read : out std_logic;
39 Write : out std_logic_vector(4 downto 0);
40 Write : out std_logic_vector(4 downto 0);
40 ReUse : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
41 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 );
43 );
43 end entity;
44 end entity;
44
45
45
46
46 architecture ar_Linker of Linker_FFT is
47 architecture ar_Linker of Linker_FFT is
47
48
48 type etat is (eX,e0,e1,e2,e3);
49 type etat is (eX,e0,e1,e2);
49 signal ect : etat;
50 signal ect : etat;
50
51
51 signal FifoCpt : integer;
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53
53
54 signal sFull : std_logic;
54 signal sRead : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
55 signal sReady : std_logic;
56 signal sReady : std_logic;
56
57 signal FifoCpt : integer range 0 to 4 := 0;
57
58
58 begin
59 begin
59
60
60 process(clk,rstn)
61 process(clk,rstn)
61 begin
62 begin
62 if(rstn='0')then
63 if(rstn='0')then
63 ect <= e0;
64 ect <= e0;
64 Read <= '0';
65 sRead <= '0';
66 sReady <= '0';
65 Write <= (others => '1');
67 Write <= (others => '1');
66 Reuse <= (others => '0');
68 Reuse <= (others => '0');
67 FifoCpt <= 1;
69 FifoCpt <= 0;
68 sDATA <= (others => '0');
69
70
70 elsif(clk'event and clk='1')then
71 elsif(clk'event and clk='1')then
71 sReady <= Ready;
72 sReady <= Ready;
72
73
74 if(sReady='1' and Ready='0')then
75 if(FifoCpt=4)then
76 FifoCpt <= 0;
77 else
78 FifoCpt <= FifoCpt + 1;
79 end if;
80 elsif(Ready='1')then
81 sRead <= not sRead;
82 else
83 sRead <= '0';
84 end if;
85
73 case ect is
86 case ect is
74
87
75 when e0 =>
88 when e0 =>
76 Write(FifoCpt-1) <= '1';
89 Write(FifoCpt) <= '1';
77 if(sReady='0' and Ready='1' and sfull='0')then
90 if(Valid='1' and Full(FifoCpt)='0')then
78 Read <= '1';
91 DataTmp <= Data_im;
92 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= Data_re;
93 Write(FifoCpt) <= '0';
79 ect <= e1;
94 ect <= e1;
80 end if;
95 elsif(Full(FifoCpt)='1')then
81
96 ReUse(FifoCpt) <= '1';
82 when e1 =>
83 Read <= '0';
84 if(Valid='1' and sfull='0')then
85 DataTmp <= Data_im;
86 sDATA <= Data_re;
87 Write(FifoCpt-1) <= '0';
88 ect <= e2;
89 elsif(sfull='1')then
90 ReUse(FifoCpt-1) <= '1';
91 ect <= eX;
92 end if;
97 end if;
93
98
94 when e2 =>
99 when e1 =>
95 sDATA <= DataTmp;
100 DATA(((FifoCpt+1)*Data_sz)-1 downto (FifoCpt*Data_sz)) <= DataTmp;
96 ect <= e3;
101 ect <= e0;
97
98 when e3 =>
99 Write(FifoCpt-1) <= '1';
100 if(Ready='1' and sfull='0')then
101 Read <= '1';
102 ect <= e1;
103 end if;
104
102
105 when eX =>
103 when others =>
106 if(FifoCpt=5)then
104 null;
107 FifoCpt <= 1;
108 else
109 FifoCpt <= FifoCpt+1;
110 end if;
111 ect <= e0;
112
105
113 end case;
106 end case;
114 end if;
107 end if;
115 end process;
108 end process;
116
109
117 DATA <= sData & sData & sData & sData & sData;
110 Read <= sRead;
118
111
119 with FifoCpt select
112 end architecture; No newline at end of file
120 sFull <= Full(0) when 1,
121 Full(1) when 2,
122 Full(2) when 3,
123 Full(3) when 4,
124 Full(4) when 5,
125 '1' when others;
126
127
128 end architecture;
129
Show file before | Show file after | Hide comments
@@ -1,242 +1,244
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33
33
34 package lpp_fft is
34 package lpp_fft is
35
35
36 component APB_FFT is
36 component APB_FFT is
37 generic (
37 generic (
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 16
43 Data_sz : integer := 16
44 );
44 );
45 port (
45 port (
46 clk : in std_logic;
46 clk : in std_logic;
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
49 apbo : out apb_slv_out_type
49 apbo : out apb_slv_out_type
50 );
50 );
51 end component;
51 end component;
52
52
53
53
54 component APB_FFT_half is
54 component APB_FFT_half is
55 generic (
55 generic (
56 pindex : integer := 0;
56 pindex : integer := 0;
57 paddr : integer := 0;
57 paddr : integer := 0;
58 pmask : integer := 16#fff#;
58 pmask : integer := 16#fff#;
59 pirq : integer := 0;
59 pirq : integer := 0;
60 abits : integer := 8;
60 abits : integer := 8;
61 Data_sz : integer := 16
61 Data_sz : integer := 16
62 );
62 );
63 port (
63 port (
64 clk : in std_logic; --! Horloge du composant
64 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
65 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
66 Ren : in std_logic;
67 ready : out std_logic;
67 ready : out std_logic;
68 valid : out std_logic;
68 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
71 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
72 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
75 );
76 end component;
76 end component;
77
77
78
78
79 component Flag_Extremum is
79 component Flag_Extremum is
80 port(
80 port(
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
82 load : in std_logic; --! Signal en provenance de CoreFFT
82 load : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 );
86 );
87 end component;
87 end component;
88
88
89
89
90 component Linker_FFT is
90 component Linker_FFT is
91 generic(
91 generic(
92 Data_sz : integer range 1 to 32 := 16
92 Data_sz : integer range 1 to 32 := 16;
93 NbData : integer range 1 to 512 := 256
93 );
94 );
94 port(
95 port(
95 clk : in std_logic;
96 clk : in std_logic;
96 rstn : in std_logic;
97 rstn : in std_logic;
97 Ready : in std_logic;
98 Ready : in std_logic;
98 Valid : in std_logic;
99 Valid : in std_logic;
99 Full : in std_logic_vector(4 downto 0);
100 Full : in std_logic_vector(4 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Read : out std_logic;
103 Read : out std_logic;
103 Write : out std_logic_vector(4 downto 0);
104 Write : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
105 ReUse : out std_logic_vector(4 downto 0);
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 );
107 );
107 end component;
108 end component;
108
109
109
110
110 component Driver_FFT is
111 component Driver_FFT is
111 generic(
112 generic(
112 Data_sz : integer range 1 to 32 := 16
113 Data_sz : integer range 1 to 32 := 16;
114 NbData : integer range 1 to 512 := 256
113 );
115 );
114 port(
116 port(
115 clk : in std_logic;
117 clk : in std_logic;
116 rstn : in std_logic;
118 rstn : in std_logic;
117 Load : in std_logic;
119 Load : in std_logic;
118 Empty : in std_logic_vector(4 downto 0);
120 Empty : in std_logic_vector(4 downto 0);
119 Full : in std_logic_vector(4 downto 0);
120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 Valid : out std_logic;
122 Valid : out std_logic;
122 Read : out std_logic_vector(4 downto 0);
123 Read : out std_logic_vector(4 downto 0);
123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 );
126 );
126 end component;
127 end component;
127
128
128 component FFTamont is
129 component FFTamont is
129 generic(
130 generic(
130 Data_sz : integer range 1 to 32 := 16
131 Data_sz : integer range 1 to 32 := 16;
132 NbData : integer range 1 to 512 := 256
131 );
133 );
132 port(
134 port(
133 clk : in std_logic;
135 clk : in std_logic;
134 rstn : in std_logic;
136 rstn : in std_logic;
135 Load : in std_logic;
137 Load : in std_logic;
136 Empty : in std_logic;
138 Empty : in std_logic;
137 Full : in std_logic;
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 Valid : out std_logic;
140 Valid : out std_logic;
140 Read : out std_logic;
141 Read : out std_logic;
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 );
144 );
144 end component;
145 end component;
145
146
146 component FFTaval is
147 component FFTaval is
147 generic(
148 generic(
148 Data_sz : integer range 1 to 32 := 8
149 Data_sz : integer range 1 to 32 := 8;
150 NbData : integer range 1 to 512 := 256
149 );
151 );
150 port(
152 port(
151 clk : in std_logic;
153 clk : in std_logic;
152 rstn : in std_logic;
154 rstn : in std_logic;
153 Ready : in std_logic;
155 Ready : in std_logic;
154 Valid : in std_logic;
156 Valid : in std_logic;
155 Full : in std_logic;
157 Full : in std_logic;
156 Data_re : in std_logic_vector(Data_sz-1 downto 0);
158 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_im : in std_logic_vector(Data_sz-1 downto 0);
159 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Read : out std_logic;
160 Read : out std_logic;
159 Write : out std_logic;
161 Write : out std_logic;
160 ReUse : out std_logic;
162 ReUse : out std_logic;
161 DATA : out std_logic_vector(Data_sz-1 downto 0)
163 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 );
164 );
163 end component;
165 end component;
164 --==============================================================|
166 --==============================================================|
165 --================== IP VHDL de la FFT actel ===================|
167 --================== IP VHDL de la FFT actel ===================|
166 --================ non partag� dans la VHD_Lib =================|
168 --================ non partag� dans la VHD_Lib =================|
167 --==============================================================|
169 --==============================================================|
168
170
169 component CoreFFT IS
171 component CoreFFT IS
170 GENERIC (
172 GENERIC (
171 LOGPTS : integer := gLOGPTS;
173 LOGPTS : integer := gLOGPTS;
172 LOGLOGPTS : integer := gLOGLOGPTS;
174 LOGLOGPTS : integer := gLOGLOGPTS;
173 WSIZE : integer := gWSIZE;
175 WSIZE : integer := gWSIZE;
174 TWIDTH : integer := gTWIDTH;
176 TWIDTH : integer := gTWIDTH;
175 DWIDTH : integer := gDWIDTH;
177 DWIDTH : integer := gDWIDTH;
176 TDWIDTH : integer := gTDWIDTH;
178 TDWIDTH : integer := gTDWIDTH;
177 RND_MODE : integer := gRND_MODE;
179 RND_MODE : integer := gRND_MODE;
178 SCALE_MODE : integer := gSCALE_MODE;
180 SCALE_MODE : integer := gSCALE_MODE;
179 PTS : integer := gPTS;
181 PTS : integer := gPTS;
180 HALFPTS : integer := gHALFPTS;
182 HALFPTS : integer := gHALFPTS;
181 inBuf_RWDLY : integer := gInBuf_RWDLY );
183 inBuf_RWDLY : integer := gInBuf_RWDLY );
182 PORT (
184 PORT (
183 clk,ifiStart,ifiNreset : IN std_logic;
185 clk,ifiStart,ifiNreset : IN std_logic;
184 ifiD_valid, ifiRead_y : IN std_logic;
186 ifiD_valid, ifiRead_y : IN std_logic;
185 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
187 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
186 ifoLoad, ifoPong : OUT std_logic;
188 ifoLoad, ifoPong : OUT std_logic;
187 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
189 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
188 ifoY_valid, ifoY_rdy : OUT std_logic);
190 ifoY_valid, ifoY_rdy : OUT std_logic);
189 END component;
191 END component;
190
192
191
193
192 component actar is
194 component actar is
193 port( DataA : in std_logic_vector(15 downto 0); DataB : in
195 port( DataA : in std_logic_vector(15 downto 0); DataB : in
194 std_logic_vector(15 downto 0); Mult : out
196 std_logic_vector(15 downto 0); Mult : out
195 std_logic_vector(31 downto 0);Clock : in std_logic) ;
197 std_logic_vector(31 downto 0);Clock : in std_logic) ;
196 end component;
198 end component;
197
199
198 component actram is
200 component actram is
199 port( DI : in std_logic_vector(31 downto 0); DO : out
201 port( DI : in std_logic_vector(31 downto 0); DO : out
200 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
202 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
201 WADDR : in std_logic_vector(6 downto 0); RADDR : in
203 WADDR : in std_logic_vector(6 downto 0); RADDR : in
202 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
204 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
203 std_logic) ;
205 std_logic) ;
204 end component;
206 end component;
205
207
206 component switch IS
208 component switch IS
207 GENERIC ( DWIDTH : integer := 32 );
209 GENERIC ( DWIDTH : integer := 32 );
208 PORT (
210 PORT (
209 clk, sel, validIn : IN std_logic;
211 clk, sel, validIn : IN std_logic;
210 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
212 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
211 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
213 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
212 validOut : OUT std_logic);
214 validOut : OUT std_logic);
213 END component;
215 END component;
214
216
215 component twid_rA IS
217 component twid_rA IS
216 GENERIC (LOGPTS : integer := 8;
218 GENERIC (LOGPTS : integer := 8;
217 LOGLOGPTS : integer := 3 );
219 LOGLOGPTS : integer := 3 );
218 PORT (clk : IN std_logic;
220 PORT (clk : IN std_logic;
219 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
221 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
220 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
222 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
221 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
223 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
222 END component;
224 END component;
223
225
224 component counter IS
226 component counter IS
225 GENERIC (
227 GENERIC (
226 WIDTH : integer := 7;
228 WIDTH : integer := 7;
227 TERMCOUNT : integer := 127 );
229 TERMCOUNT : integer := 127 );
228 PORT (
230 PORT (
229 clk, nGrst, rst, cntEn : IN std_logic;
231 clk, nGrst, rst, cntEn : IN std_logic;
230 tc : OUT std_logic;
232 tc : OUT std_logic;
231 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
233 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
232 END component;
234 END component;
233
235
234
236
235 component twiddle IS
237 component twiddle IS
236 PORT (
238 PORT (
237 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
239 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
238 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
240 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
239 END component;
241 END component;
240
242
241
243
242 end; No newline at end of file
244 end;
Show file before | Show file after | Hide comments
@@ -1,354 +1,355
1
1 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 -- (at your option) any later version.
9 --
10 --
10 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
14 --
15 --
15 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -- 1.0 - initial version
24 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
26 LIBRARY ieee;
27 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
29 LIBRARY grlib;
30 LIBRARY grlib;
30 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
31 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 --USE GRLIB.DMA2AHB_TestPackage.ALL;
35 LIBRARY lpp;
36 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_dma_pkg.ALL;
40 LIBRARY techmap;
41 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
42
43
43
44
44 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
45 GENERIC (
46 GENERIC (
46 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
47 hindex : INTEGER := 2;
48 hindex : INTEGER := 2;
48 pindex : INTEGER := 4;
49 pindex : INTEGER := 4;
49 paddr : INTEGER := 4;
50 paddr : INTEGER := 4;
50 pmask : INTEGER := 16#fff#;
51 pmask : INTEGER := 16#fff#;
51 pirq : INTEGER := 0);
52 pirq : INTEGER := 0);
52 PORT (
53 PORT (
53 -- AMBA AHB system signals
54 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
55 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 HRESETn : IN STD_ULOGIC;
56
57
57 -- AMBA AHB Master Interface
58 -- AMBA AHB Master Interface
58 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60
61
61 -- fifo interface
62 -- fifo interface
62 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fifo_empty : IN STD_LOGIC;
64 fifo_empty : IN STD_LOGIC;
64 fifo_ren : OUT STD_LOGIC;
65 fifo_ren : OUT STD_LOGIC;
65
66
66 -- header
67 -- header
67 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 header_val : IN STD_LOGIC;
69 header_val : IN STD_LOGIC;
69 header_ack : OUT STD_LOGIC;
70 header_ack : OUT STD_LOGIC;
70
71
71 -- Reg out
72 -- Reg out
72 ready_matrix_f0_0 : OUT STD_LOGIC;
73 ready_matrix_f0_0 : OUT STD_LOGIC;
73 ready_matrix_f0_1 : OUT STD_LOGIC;
74 ready_matrix_f0_1 : OUT STD_LOGIC;
74 ready_matrix_f1 : OUT STD_LOGIC;
75 ready_matrix_f1 : OUT STD_LOGIC;
75 ready_matrix_f2 : OUT STD_LOGIC;
76 ready_matrix_f2 : OUT STD_LOGIC;
76 error_anticipating_empty_fifo : OUT STD_LOGIC;
77 error_anticipating_empty_fifo : OUT STD_LOGIC;
77 error_bad_component_error : OUT STD_LOGIC;
78 error_bad_component_error : OUT STD_LOGIC;
78 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79
80
80 -- Reg In
81 -- Reg In
81 status_ready_matrix_f0_0 :IN STD_LOGIC;
82 status_ready_matrix_f0_0 :IN STD_LOGIC;
82 status_ready_matrix_f0_1 :IN STD_LOGIC;
83 status_ready_matrix_f0_1 :IN STD_LOGIC;
83 status_ready_matrix_f1 :IN STD_LOGIC;
84 status_ready_matrix_f1 :IN STD_LOGIC;
84 status_ready_matrix_f2 :IN STD_LOGIC;
85 status_ready_matrix_f2 :IN STD_LOGIC;
85 status_error_anticipating_empty_fifo :IN STD_LOGIC;
86 status_error_anticipating_empty_fifo :IN STD_LOGIC;
86 status_error_bad_component_error :IN STD_LOGIC;
87 status_error_bad_component_error :IN STD_LOGIC;
87
88
88 config_active_interruption_onNewMatrix : IN STD_LOGIC;
89 config_active_interruption_onNewMatrix : IN STD_LOGIC;
89 config_active_interruption_onError : IN STD_LOGIC;
90 config_active_interruption_onError : IN STD_LOGIC;
90 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
92 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
94 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
94 );
95 );
95 END;
96 END;
96
97
97 ARCHITECTURE Behavioral OF lpp_dma_ip IS
98 ARCHITECTURE Behavioral OF lpp_dma_ip IS
98 -----------------------------------------------------------------------------
99 -----------------------------------------------------------------------------
99 SIGNAL DMAIn : DMA_In_Type;
100 SIGNAL DMAIn : DMA_In_Type;
100 SIGNAL header_dmai : DMA_In_Type;
101 SIGNAL header_dmai : DMA_In_Type;
101 SIGNAL component_dmai : DMA_In_Type;
102 SIGNAL component_dmai : DMA_In_Type;
102 SIGNAL DMAOut : DMA_OUt_Type;
103 SIGNAL DMAOut : DMA_OUt_Type;
103 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
104
105
105 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 -----------------------------------------------------------------------------
107 TYPE state_DMAWriteBurst IS (IDLE,
108 TYPE state_DMAWriteBurst IS (IDLE,
108 TRASH_FIFO,
109 TRASH_FIFO,
109 WAIT_HEADER_ACK,
110 WAIT_HEADER_ACK,
110 SEND_DATA,
111 SEND_DATA,
111 WAIT_DATA_ACK,
112 WAIT_DATA_ACK,
112 CHECK_LENGTH
113 CHECK_LENGTH
113 );
114 );
114 SIGNAL state : state_DMAWriteBurst := IDLE;
115 SIGNAL state : state_DMAWriteBurst := IDLE;
115
116
116 SIGNAL nbSend : INTEGER;
117 SIGNAL nbSend : INTEGER;
117 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL header_check_ok : STD_LOGIC;
121 SIGNAL header_check_ok : STD_LOGIC;
121 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL send_matrix : STD_LOGIC;
123 SIGNAL send_matrix : STD_LOGIC;
123 SIGNAL request : STD_LOGIC;
124 SIGNAL request : STD_LOGIC;
124 SIGNAL remaining_data_request : INTEGER;
125 SIGNAL remaining_data_request : INTEGER;
125 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
128 SIGNAL header_select : STD_LOGIC;
129 SIGNAL header_select : STD_LOGIC;
129
130
130 SIGNAL header_send : STD_LOGIC;
131 SIGNAL header_send : STD_LOGIC;
131 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
132 SIGNAL header_send_ok : STD_LOGIC;
133 SIGNAL header_send_ok : STD_LOGIC;
133 SIGNAL header_send_ko : STD_LOGIC;
134 SIGNAL header_send_ko : STD_LOGIC;
134
135
135 SIGNAL component_send : STD_LOGIC;
136 SIGNAL component_send : STD_LOGIC;
136 SIGNAL component_send_ok : STD_LOGIC;
137 SIGNAL component_send_ok : STD_LOGIC;
137 SIGNAL component_send_ko : STD_LOGIC;
138 SIGNAL component_send_ko : STD_LOGIC;
138 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
139 SIGNAL fifo_ren_trash : STD_LOGIC;
140 SIGNAL fifo_ren_trash : STD_LOGIC;
140 SIGNAL component_fifo_ren : STD_LOGIC;
141 SIGNAL component_fifo_ren : STD_LOGIC;
141
142
142 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
143 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
144
145
145 BEGIN
146 BEGIN
146
147
147 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
148 -- DMA to AHB interface
149 -- DMA to AHB interface
149 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
150
151
151 DMA2AHB_1 : DMA2AHB
152 DMA2AHB_1 : DMA2AHB
152 GENERIC MAP (
153 GENERIC MAP (
153 hindex => hindex,
154 hindex => hindex,
154 vendorid => VENDOR_LPP,
155 vendorid => VENDOR_LPP,
155 deviceid => 0,
156 deviceid => 0,
156 version => 0,
157 version => 0,
157 syncrst => 1,
158 syncrst => 1,
158 boundary => 1) -- FIX 11/01/2013
159 boundary => 1) -- FIX 11/01/2013
159 PORT MAP (
160 PORT MAP (
160 HCLK => HCLK,
161 HCLK => HCLK,
161 HRESETn => HRESETn,
162 HRESETn => HRESETn,
162 DMAIn => DMAIn,
163 DMAIn => DMAIn,
163 DMAOut => DMAOut,
164 DMAOut => DMAOut,
164 AHBIn => AHB_Master_In,
165 AHBIn => AHB_Master_In,
165 AHBOut => AHB_Master_Out);
166 AHBOut => AHB_Master_Out);
166
167
167 debug_reg <= debug_reg_s;
168 debug_reg <= debug_reg_s;
168
169
169 debug_info: PROCESS (HCLK, HRESETn)
170 debug_info: PROCESS (HCLK, HRESETn)
170 BEGIN -- PROCESS debug_info
171 BEGIN -- PROCESS debug_info
171 IF HRESETn = '0' THEN -- asynchronous reset (active low)
172 IF HRESETn = '0' THEN -- asynchronous reset (active low)
172 debug_reg <= (OTHERS => '0');
173 debug_reg <= (OTHERS => '0');
173 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
174 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
174 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
175 debug_reg_s(0) <= debug_reg_s(0) OR (DMAOut.Retry );
175 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
176 debug_reg_s(1) <= debug_reg_s(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
176 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
177 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
177 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
178 debug_reg_s(3) <= debug_reg_s(3) OR (header_send_ko);
178 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
179 debug_reg_s(4) <= debug_reg_s(4) OR (header_send_ok);
179 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
180 debug_reg_s(5) <= debug_reg_s(5) OR (component_send_ko);
180 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
181 debug_reg_s(6) <= debug_reg_s(6) OR (component_send_ok);
181
182
182 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
183 debug_reg_s(31 DOWNTO 7) <= (OTHERS => '1');
183 END IF;
184 END IF;
184 END PROCESS debug_info;
185 END PROCESS debug_info;
185
186
186
187
187 matrix_type <= header(1 DOWNTO 0);
188 matrix_type <= header(1 DOWNTO 0);
188 component_type <= header(5 DOWNTO 2);
189 component_type <= header(5 DOWNTO 2);
189
190
190 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
191 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
191 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
192 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
192 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
193 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
193 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
194 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
194 '0';
195 '0';
195
196
196 header_check_ok <= '0' WHEN component_type = "1111" ELSE
197 header_check_ok <= '0' WHEN component_type = "1111" ELSE
197 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
198 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
198 '1' WHEN component_type = component_type_pre + "0001" ELSE
199 '1' WHEN component_type = component_type_pre + "0001" ELSE
199 '0';
200 '0';
200
201
201 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
202 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
202 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
203 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
203 addr_matrix_f1 WHEN matrix_type = "10" ELSE
204 addr_matrix_f1 WHEN matrix_type = "10" ELSE
204 addr_matrix_f2 WHEN matrix_type = "11" ELSE
205 addr_matrix_f2 WHEN matrix_type = "11" ELSE
205 (OTHERS => '0');
206 (OTHERS => '0');
206
207
207 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
208 -- DMA control
209 -- DMA control
209 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
210 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
211 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
211 BEGIN -- PROCESS DMAWriteBurst_p
212 BEGIN -- PROCESS DMAWriteBurst_p
212 IF HRESETn = '0' THEN -- asynchronous reset (active low)
213 IF HRESETn = '0' THEN -- asynchronous reset (active low)
213 state <= IDLE;
214 state <= IDLE;
214 header_ack <= '0';
215 header_ack <= '0';
215 ready_matrix_f0_0 <= '0';
216 ready_matrix_f0_0 <= '0';
216 ready_matrix_f0_1 <= '0';
217 ready_matrix_f0_1 <= '0';
217 ready_matrix_f1 <= '0';
218 ready_matrix_f1 <= '0';
218 ready_matrix_f2 <= '0';
219 ready_matrix_f2 <= '0';
219 error_anticipating_empty_fifo <= '0';
220 error_anticipating_empty_fifo <= '0';
220 error_bad_component_error <= '0';
221 error_bad_component_error <= '0';
221 component_type_pre <= "1110";
222 component_type_pre <= "1110";
222 fifo_ren_trash <= '1';
223 fifo_ren_trash <= '1';
223 component_send <= '0';
224 component_send <= '0';
224 address <= (OTHERS => '0');
225 address <= (OTHERS => '0');
225 header_select <= '0';
226 header_select <= '0';
226 header_send <= '0';
227 header_send <= '0';
227 header_data <= (OTHERS => '0');
228 header_data <= (OTHERS => '0');
228 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
229 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
229
230
230 CASE state IS
231 CASE state IS
231 WHEN IDLE =>
232 WHEN IDLE =>
232 ready_matrix_f0_0 <= '0';
233 ready_matrix_f0_0 <= '0';
233 ready_matrix_f0_1 <= '0';
234 ready_matrix_f0_1 <= '0';
234 ready_matrix_f1 <= '0';
235 ready_matrix_f1 <= '0';
235 ready_matrix_f2 <= '0';
236 ready_matrix_f2 <= '0';
236 error_bad_component_error <= '0';
237 error_bad_component_error <= '0';
237 header_select <= '1';
238 header_select <= '1';
238 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
239 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
239 IF header_check_ok = '1' THEN
240 IF header_check_ok = '1' THEN
240 header_data <= header;
241 header_data <= header;
241 component_type_pre <= header(5 DOWNTO 2);
242 component_type_pre <= header(5 DOWNTO 2);
242 header_ack <= '1';
243 header_ack <= '1';
243 --
244 --
244 header_send <= '1';
245 header_send <= '1';
245 IF component_type = "0000" THEN
246 IF component_type = "0000" THEN
246 address <= address_matrix;
247 address <= address_matrix;
247 END IF;
248 END IF;
248 header_data <= header;
249 header_data <= header;
249 --
250 --
250 state <= WAIT_HEADER_ACK;
251 state <= WAIT_HEADER_ACK;
251 ELSE
252 ELSE
252 error_bad_component_error <= '1';
253 error_bad_component_error <= '1';
253 component_type_pre <= "1110";
254 component_type_pre <= "1110";
254 header_ack <= '1';
255 header_ack <= '1';
255 state <= TRASH_FIFO;
256 state <= TRASH_FIFO;
256 END IF;
257 END IF;
257 END IF;
258 END IF;
258
259
259 WHEN TRASH_FIFO =>
260 WHEN TRASH_FIFO =>
260 error_bad_component_error <= '0';
261 error_bad_component_error <= '0';
261 error_anticipating_empty_fifo <= '0';
262 error_anticipating_empty_fifo <= '0';
262 IF fifo_empty = '1' THEN
263 IF fifo_empty = '1' THEN
263 state <= IDLE;
264 state <= IDLE;
264 fifo_ren_trash <= '1';
265 fifo_ren_trash <= '1';
265 ELSE
266 ELSE
266 fifo_ren_trash <= '0';
267 fifo_ren_trash <= '0';
267 END IF;
268 END IF;
268
269
269 WHEN WAIT_HEADER_ACK =>
270 WHEN WAIT_HEADER_ACK =>
270 header_send <= '0';
271 header_send <= '0';
271 IF header_send_ko = '1' THEN
272 IF header_send_ko = '1' THEN
272 state <= TRASH_FIFO;
273 state <= TRASH_FIFO;
273 error_anticipating_empty_fifo <= '1';
274 error_anticipating_empty_fifo <= '1';
274 -- TODO : error sending header
275 -- TODO : error sending header
275 ELSIF header_send_ok = '1' THEN
276 ELSIF header_send_ok = '1' THEN
276 header_select <= '0';
277 header_select <= '0';
277 state <= SEND_DATA;
278 state <= SEND_DATA;
278 address <= address + 4;
279 address <= address + 4;
279 END IF;
280 END IF;
280
281
281 WHEN SEND_DATA =>
282 WHEN SEND_DATA =>
282 IF fifo_empty = '1' THEN
283 IF fifo_empty = '1' THEN
283 state <= IDLE;
284 state <= IDLE;
284 IF component_type = "1110" THEN
285 IF component_type = "1110" THEN
285 CASE matrix_type IS
286 CASE matrix_type IS
286 WHEN "00" => ready_matrix_f0_0 <= '1';
287 WHEN "00" => ready_matrix_f0_0 <= '1';
287 WHEN "01" => ready_matrix_f0_1 <= '1';
288 WHEN "01" => ready_matrix_f0_1 <= '1';
288 WHEN "10" => ready_matrix_f1 <= '1';
289 WHEN "10" => ready_matrix_f1 <= '1';
289 WHEN "11" => ready_matrix_f2 <= '1';
290 WHEN "11" => ready_matrix_f2 <= '1';
290 WHEN OTHERS => NULL;
291 WHEN OTHERS => NULL;
291 END CASE;
292 END CASE;
292 END IF;
293 END IF;
293 ELSE
294 ELSE
294 component_send <= '1';
295 component_send <= '1';
295 address <= address;
296 address <= address;
296 state <= WAIT_DATA_ACK;
297 state <= WAIT_DATA_ACK;
297 END IF;
298 END IF;
298
299
299 WHEN WAIT_DATA_ACK =>
300 WHEN WAIT_DATA_ACK =>
300 component_send <= '0';
301 component_send <= '0';
301 IF component_send_ok = '1' THEN
302 IF component_send_ok = '1' THEN
302 address <= address + 64;
303 address <= address + 64;
303 state <= SEND_DATA;
304 state <= SEND_DATA;
304 ELSIF component_send_ko = '1' THEN
305 ELSIF component_send_ko = '1' THEN
305 error_anticipating_empty_fifo <= '0';
306 error_anticipating_empty_fifo <= '0';
306 state <= TRASH_FIFO;
307 state <= TRASH_FIFO;
307 END IF;
308 END IF;
308
309
309 WHEN CHECK_LENGTH =>
310 WHEN CHECK_LENGTH =>
310 state <= IDLE;
311 state <= IDLE;
311 WHEN OTHERS => NULL;
312 WHEN OTHERS => NULL;
312 END CASE;
313 END CASE;
313
314
314 END IF;
315 END IF;
315 END PROCESS DMAWriteFSM_p;
316 END PROCESS DMAWriteFSM_p;
316
317
317 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
318 -- SEND 1 word by DMA
319 -- SEND 1 word by DMA
319 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
320 lpp_dma_send_1word_1 : lpp_dma_send_1word
321 lpp_dma_send_1word_1 : lpp_dma_send_1word
321 PORT MAP (
322 PORT MAP (
322 HCLK => HCLK,
323 HCLK => HCLK,
323 HRESETn => HRESETn,
324 HRESETn => HRESETn,
324 DMAIn => header_dmai,
325 DMAIn => header_dmai,
325 DMAOut => DMAOut,
326 DMAOut => DMAOut,
326
327
327 send => header_send,
328 send => header_send,
328 address => address,
329 address => address,
329 data => header_data,
330 data => header_data,
330 send_ok => header_send_ok,
331 send_ok => header_send_ok,
331 send_ko => header_send_ko
332 send_ko => header_send_ko
332 );
333 );
333
334
334 -----------------------------------------------------------------------------
335 -----------------------------------------------------------------------------
335 -- SEND 16 word by DMA (in burst mode)
336 -- SEND 16 word by DMA (in burst mode)
336 -----------------------------------------------------------------------------
337 -----------------------------------------------------------------------------
337 lpp_dma_send_16word_1 : lpp_dma_send_16word
338 lpp_dma_send_16word_1 : lpp_dma_send_16word
338 PORT MAP (
339 PORT MAP (
339 HCLK => HCLK,
340 HCLK => HCLK,
340 HRESETn => HRESETn,
341 HRESETn => HRESETn,
341 DMAIn => component_dmai,
342 DMAIn => component_dmai,
342 DMAOut => DMAOut,
343 DMAOut => DMAOut,
343
344
344 send => component_send,
345 send => component_send,
345 address => address,
346 address => address,
346 data => fifo_data,
347 data => fifo_data,
347 ren => component_fifo_ren,
348 ren => component_fifo_ren,
348 send_ok => component_send_ok,
349 send_ok => component_send_ok,
349 send_ko => component_send_ko);
350 send_ko => component_send_ko);
350
351
351 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
352 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
352 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
353 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
353
354
354 END Behavioral;
355 END Behavioral;
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@@ -1,109 +1,95
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
25
27 entity Dispatch is
26 entity Dispatch is
28 generic(
27 generic(
29 Data_SZ : integer := 32);
28 Data_SZ : integer := 32);
30 port(
29 port(
31 clk : in std_logic;
30 clk : in std_logic;
32 reset : in std_logic;
31 reset : in std_logic;
33 Acq : in std_logic;
32 Acq : in std_logic;
34 Data : in std_logic_vector(Data_SZ-1 downto 0);
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
35 Write : in std_logic;
34 Write : in std_logic;
36 Full : in std_logic_vector(1 downto 0);
35 Full : in std_logic_vector(1 downto 0);
37 -- Empty : in std_logic_vector(1 downto 0);
38 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
36 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
39 FifoWrite : out std_logic_vector(1 downto 0);
37 FifoWrite : out std_logic_vector(1 downto 0);
40 -- FifoFull : out std_logic;
41 Pong : out std_logic;
38 Pong : out std_logic;
42 Error : out std_logic
39 Error : out std_logic
43
44 );
40 );
45 end entity;
41 end entity;
46
42
47
43
48 architecture ar_Dispatch of Dispatch is
44 architecture ar_Dispatch of Dispatch is
49
45
50 type etat is (e0,e1,e2,e3);
46 type etat is (eX,e0,e1,e2);
51 signal ect : etat;
47 signal ect : etat;
52
48
49 signal Pong_int : std_logic;
50 signal FifoCpt : integer range 0 to 1 := 0;
51
53 begin
52 begin
54
53
55 process (clk,reset)
54 process (clk,reset)
56 begin
55 begin
57 if(reset='0')then
56 if(reset='0')then
58 Pong <= '0';
57 Pong_int <= '0';
59 Error <= '0';
58 Error <= '0';
59 ect <= e0;
60
60
61 elsif(clk' event and clk='1')then
61 elsif(clk' event and clk='1')then
62
62
63 case ect is
63 case ect is
64
64
65 when e0 =>
65 when e0 =>
66 if(Full(0) = '1')then
66 if(Full(FifoCpt) = '1')then
67 pong <= '1';
67 Pong_int <= not Pong_int;
68 ect <= e1;
68 ect <= e1;
69 end if;
69 end if;
70
70
71 when e1 =>
71 when e1 =>
72 if(Acq <= '1')then
72 if(Acq = '0')then
73 Error <= '0';
74 pong <= '0';
75 ect <= e2;
76 else
77 Error <= '1';
73 Error <= '1';
78 ect <= e1;
74 ect <= e1;
79 end if;
75 else
80
81 when e2 =>
82 if(Full(1) = '1')then
83 pong <= '1';
84 ect <= e3;
85 end if;
86
87 when e3 =>
88 if(Acq <= '1')then
89 Error <= '0';
76 Error <= '0';
90 pong <= '0';
91 ect <= e0;
77 ect <= e0;
92 else
78 end if;
93 Error <= '1';
79
94 ect <= e3;
80 when others =>
95 end if;
81 null;
96
82
97 end case;
83 end case;
98
84
99 end if;
85 end if;
100 end process;
86 end process;
101
87
102 FifoData <= Data & Data;
88 FifoData <= Data & Data;
89 Pong <= Pong_int;
103
90
104 with ect select
91 FifoCpt <= 0 when Pong_int='0' else 1;
105 FifoWrite <= '1' & not Write when e0,
92
106 not Write & '1' when e2,
93 FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
107 "11" when others;
108
94
109 end architecture; No newline at end of file
95 end architecture;
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@@ -1,259 +1,278
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 Input_SZ : integer := 16;
41 Input_SZ : integer := 16;
42 Result_SZ : integer := 32);
42 Result_SZ : integer := 32);
43 port (
43 port (
44 clk : in std_logic;
44 clk : in std_logic;
45 rst : in std_logic;
45 rst : in std_logic;
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
48 Full : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
49 Empty : in std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
50 ReadFIFO : out std_logic_vector(1 downto 0);
51 FullFIFO : in std_logic;
51 FullFIFO : in std_logic;
52 WriteFIFO : out std_logic;
52 WriteFIFO : out std_logic;
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
56 );
57 end component;
57 end component;
58
58
59 component TopSpecMatrix is
60 generic(
61 Input_SZ : integer := 16);
62 port(
63 clk : in std_logic;
64 rstn : in std_logic;
65 Write : in std_logic;
66 ReadIn : in std_logic_vector(1 downto 0);
67 Full : in std_logic_vector(4 downto 0);
68 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
69 Start : out std_logic;
70 ReadOut : out std_logic_vector(4 downto 0);
71 Statu : out std_logic_vector(3 downto 0);
72 DATA1 : out std_logic_vector(Input_SZ-1 downto 0);
73 DATA2 : out std_logic_vector(Input_SZ-1 downto 0)
74 );
75 end component;
76
77
59 component Top_MatrixSpec is
78 component Top_MatrixSpec is
60 generic(
79 generic(
61 Input_SZ : integer := 16;
80 Input_SZ : integer := 16;
62 Result_SZ : integer := 32);
81 Result_SZ : integer := 32);
63 port(
82 port(
64 clk : in std_logic;
83 clk : in std_logic;
65 reset : in std_logic;
84 reset : in std_logic;
66 Statu : in std_logic_vector(3 downto 0);
85 Statu : in std_logic_vector(3 downto 0);
67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 Full : in std_logic_vector(1 downto 0);
88 Full : in std_logic_vector(1 downto 0);
70 Empty : in std_logic_vector(1 downto 0);
89 Empty : in std_logic_vector(1 downto 0);
71 ReadFIFO : out std_logic_vector(1 downto 0);
90 ReadFIFO : out std_logic_vector(1 downto 0);
72 FullFIFO : in std_logic;
91 FullFIFO : in std_logic;
73 WriteFIFO : out std_logic;
92 WriteFIFO : out std_logic;
74 Result : out std_logic_vector(Result_SZ-1 downto 0)
93 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 );
94 );
76 end component;
95 end component;
77
96
78 component SpectralMatrix is
97 component SpectralMatrix is
79 generic(
98 generic(
80 Input_SZ : integer := 16;
99 Input_SZ : integer := 16;
81 Result_SZ : integer := 32);
100 Result_SZ : integer := 32);
82 port(
101 port(
83 clk : in std_logic;
102 clk : in std_logic;
84 reset : in std_logic;
103 reset : in std_logic;
85 Start : in std_logic;
104 Start : in std_logic;
86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
105 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
106 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 Statu : in std_logic_vector(3 downto 0);
107 Statu : in std_logic_vector(3 downto 0);
89 -- FullFIFO : in std_logic;
108 -- FullFIFO : in std_logic;
90 ReadFIFO : out std_logic_vector(1 downto 0);
109 ReadFIFO : out std_logic_vector(1 downto 0);
91 WriteFIFO : out std_logic;
110 WriteFIFO : out std_logic;
92 Result : out std_logic_vector(Result_SZ-1 downto 0)
111 Result : out std_logic_vector(Result_SZ-1 downto 0)
93 );
112 );
94 end component;
113 end component;
95
114
96
115
97 component Matrix is
116 component Matrix is
98 generic(
117 generic(
99 Input_SZ : integer := 16);
118 Input_SZ : integer := 16);
100 port(
119 port(
101 clk : in std_logic;
120 clk : in std_logic;
102 raz : in std_logic;
121 raz : in std_logic;
103 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
122 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
104 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
123 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
105 Take : in std_logic;
124 Take : in std_logic;
106 Received : in std_logic;
125 Received : in std_logic;
107 Conjugate : in std_logic;
126 Conjugate : in std_logic;
108 Valid : out std_logic;
127 Valid : out std_logic;
109 Read : out std_logic;
128 Read : out std_logic;
110 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
129 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
111 );
130 );
112 end component;
131 end component;
113
132
114 component GetResult is
133 component GetResult is
115 generic(
134 generic(
116 Result_SZ : integer := 32);
135 Result_SZ : integer := 32);
117 port(
136 port(
118 clk : in std_logic;
137 clk : in std_logic;
119 raz : in std_logic;
138 raz : in std_logic;
120 Valid : in std_logic;
139 Valid : in std_logic;
121 Conjugate : in std_logic;
140 Conjugate : in std_logic;
122 Res : in std_logic_vector(Result_SZ-1 downto 0);
141 Res : in std_logic_vector(Result_SZ-1 downto 0);
123 -- Full : in std_logic;
142 -- Full : in std_logic;
124 WriteFIFO : out std_logic;
143 WriteFIFO : out std_logic;
125 Received : out std_logic;
144 Received : out std_logic;
126 Result : out std_logic_vector(Result_SZ-1 downto 0)
145 Result : out std_logic_vector(Result_SZ-1 downto 0)
127 );
146 );
128 end component;
147 end component;
129
148
130
149
131 component TopMatrix_PDR is
150 component TopMatrix_PDR is
132 generic(
151 generic(
133 Input_SZ : integer := 16;
152 Input_SZ : integer := 16;
134 Result_SZ : integer := 32);
153 Result_SZ : integer := 32);
135 port(
154 port(
136 clk : in std_logic;
155 clk : in std_logic;
137 reset : in std_logic;
156 reset : in std_logic;
138 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
157 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
139 FULLin : in std_logic_vector(4 downto 0);
158 FULLin : in std_logic_vector(4 downto 0);
140 READin : in std_logic_vector(1 downto 0);
159 READin : in std_logic_vector(1 downto 0);
141 WRITEin : in std_logic;
160 WRITEin : in std_logic;
142 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
161 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
143 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
162 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
144 Start : out std_logic;
163 Start : out std_logic;
145 Read : out std_logic_vector(4 downto 0);
164 Read : out std_logic_vector(4 downto 0);
146 Statu : out std_logic_vector(3 downto 0)
165 Statu : out std_logic_vector(3 downto 0)
147 );
166 );
148 end component;
167 end component;
149
168
150
169
151 component Dispatch is
170 component Dispatch is
152 generic(
171 generic(
153 Data_SZ : integer := 32);
172 Data_SZ : integer := 32);
154 port(
173 port(
155 clk : in std_logic;
174 clk : in std_logic;
156 reset : in std_logic;
175 reset : in std_logic;
157 Acq : in std_logic;
176 Acq : in std_logic;
158 Data : in std_logic_vector(Data_SZ-1 downto 0);
177 Data : in std_logic_vector(Data_SZ-1 downto 0);
159 Write : in std_logic;
178 Write : in std_logic;
160 Full : in std_logic_vector(1 downto 0);
179 Full : in std_logic_vector(1 downto 0);
161 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
180 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
162 FifoWrite : out std_logic_vector(1 downto 0);
181 FifoWrite : out std_logic_vector(1 downto 0);
163 Pong : out std_logic;
182 Pong : out std_logic;
164 Error : out std_logic
183 Error : out std_logic
165 );
184 );
166 end component;
185 end component;
167
186
168
187
169 component DriveInputs is
188 component DriveInputs is
170 port(
189 port(
171 clk : in std_logic;
190 clk : in std_logic;
172 raz : in std_logic;
191 raz : in std_logic;
173 Read : in std_logic;
192 Read : in std_logic;
174 Conjugate : in std_logic;
193 Conjugate : in std_logic;
175 Take : out std_logic;
194 Take : out std_logic;
176 ReadFIFO : out std_logic_vector(1 downto 0)
195 ReadFIFO : out std_logic_vector(1 downto 0)
177 );
196 );
178 end component;
197 end component;
179
198
180 component Starter is
199 component Starter is
181 port(
200 port(
182 clk : in std_logic;
201 clk : in std_logic;
183 raz : in std_logic;
202 raz : in std_logic;
184 Full : in std_logic_vector(1 downto 0);
203 Full : in std_logic_vector(1 downto 0);
185 Empty : in std_logic_vector(1 downto 0);
204 Empty : in std_logic_vector(1 downto 0);
186 Statu : in std_logic_vector(3 downto 0);
205 Statu : in std_logic_vector(3 downto 0);
187 Write : in std_logic;
206 Write : in std_logic;
188 Start : out std_logic
207 Start : out std_logic
189 );
208 );
190 end component;
209 end component;
191
210
192 component ALU_Driver is
211 component ALU_Driver is
193 generic(
212 generic(
194 Input_SZ_1 : integer := 16;
213 Input_SZ_1 : integer := 16;
195 Input_SZ_2 : integer := 16);
214 Input_SZ_2 : integer := 16);
196 port(
215 port(
197 clk : in std_logic;
216 clk : in std_logic;
198 reset : in std_logic;
217 reset : in std_logic;
199 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
218 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
200 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
219 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
201 Take : in std_logic;
220 Take : in std_logic;
202 Received : in std_logic;
221 Received : in std_logic;
203 Conjugate : in std_logic;
222 Conjugate : in std_logic;
204 Valid : out std_logic;
223 Valid : out std_logic;
205 Read : out std_logic;
224 Read : out std_logic;
206 CTRL : out std_logic_vector(4 downto 0);
225 CTRL : out std_logic_vector(4 downto 0);
207 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
226 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
208 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
227 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
209 );
228 );
210 end component;
229 end component;
211
230
212
231
213 component ALU_v2 is
232 component ALU_v2 is
214 generic(
233 generic(
215 Arith_en : integer := 1;
234 Arith_en : integer := 1;
216 Logic_en : integer := 1;
235 Logic_en : integer := 1;
217 Input_SZ_1 : integer := 16;
236 Input_SZ_1 : integer := 16;
218 Input_SZ_2 : integer := 9);
237 Input_SZ_2 : integer := 9);
219 port(
238 port(
220 clk : in std_logic;
239 clk : in std_logic;
221 reset : in std_logic;
240 reset : in std_logic;
222 ctrl : in std_logic_vector(4 downto 0);
241 ctrl : in std_logic_vector(4 downto 0);
223 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
242 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
224 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
243 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
225 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
244 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
226 );
245 );
227 end component;
246 end component;
228
247
229
248
230 component MAC_v2 is
249 component MAC_v2 is
231 generic(
250 generic(
232 Input_SZ_A : integer := 8;
251 Input_SZ_A : integer := 8;
233 Input_SZ_B : integer := 8);
252 Input_SZ_B : integer := 8);
234 port(
253 port(
235 clk : in std_logic;
254 clk : in std_logic;
236 reset : in std_logic;
255 reset : in std_logic;
237 clr_MAC : in std_logic;
256 clr_MAC : in std_logic;
238 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
257 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
239 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
258 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
240 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
259 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
241 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
260 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
242 );
261 );
243 end component;
262 end component;
244
263
245
264
246 component TwoComplementer is
265 component TwoComplementer is
247 generic(
266 generic(
248 Input_SZ : integer := 16);
267 Input_SZ : integer := 16);
249 port(
268 port(
250 clk : in std_logic;
269 clk : in std_logic;
251 reset : in std_logic;
270 reset : in std_logic;
252 clr : in std_logic;
271 clr : in std_logic;
253 TwoComp : in std_logic;
272 TwoComp : in std_logic;
254 OP : in std_logic_vector(Input_SZ-1 downto 0);
273 OP : in std_logic_vector(Input_SZ-1 downto 0);
255 RES : out std_logic_vector(Input_SZ-1 downto 0)
274 RES : out std_logic_vector(Input_SZ-1 downto 0)
256 );
275 );
257 end component;
276 end component;
258
277
259 end; No newline at end of file
278 end;
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@@ -1,78 +1,53
1 -- Bridge.vhd
1 -- Bridge.vhd
2 library IEEE;
2 library IEEE;
3 use IEEE.std_logic_1164.all;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
4 use IEEE.numeric_std.all;
5
5
6 entity Bridge is
6 entity Bridge is
7 generic(
7 port(
8 Data_sz : integer range 1 to 32 := 16
8 clk : in std_logic;
9 );
9 raz : in std_logic;
10 port(
10 EmptyUp : in std_logic;
11 clk : in std_logic;
11 FullDwn : in std_logic;
12 raz : in std_logic;
12 WriteDwn : out std_logic;
13 Start : in std_logic;
13 ReadUp : out std_logic
14 FullUp : in std_logic;
14 );
15 EmptyUp : in std_logic;
16 FullDown : in std_logic;
17 EmptyDown : in std_logic;
18 Write : out std_logic;
19 Read : out std_logic
20 );
21 end entity;
15 end entity;
22
16
23
17
24 architecture ar_Bridge of Bridge is
18 architecture ar_Bridge of Bridge is
25
19
26 type etat is (eX,e1,e2,e3);
20 type etat is (e0,e1);
27 signal ect : etat;
21 signal ect : etat;
28
22
29 signal i : integer;
30
31 begin
23 begin
32
24
33 process(clk,raz)
25 process(clk,raz)
34 begin
26 begin
35 if(raz='0')then
27 if(raz='0')then
36 Write <= '1';
28 WriteDwn <= '1';
37 Read <= '1';
29 ReadUp <= '1';
38 i <= 0;
30 ect <= e0;
39 ect <= eX;
31
40
41 elsif(clk'event and clk='1')then
32 elsif(clk'event and clk='1')then
42
33
43 case ect is
34 case ect is
44
35
45 when eX =>
36 when e0 =>
46 if(FullUp='1' and EmptyDown='1' and start='0')then
37 WriteDwn <= '1';
47 ect <= e1;
38 if(EmptyUp='0' and FullDwn='0')then
48 end if;
39 ReadUp <= '0';
40 ect <= e1;
41 end if;
49
42
50 when e1 =>
43 when e1 =>
51 Write <= '1';
44 ReadUp <= '1';
52 if(EmptyUp='0')then
45 WriteDwn <= '0';
53 Read <= '0';
46 ect <= e0;
54 ect <= e2;
47
55 else
48 end case;
56 Read <= '1';
49
57 ect <= e3;
58 end if;
59
60 when e2 =>
61 Read <= '1';
62 if(FullDown='0')then
63 Write <= '0';
64 ect <= e1;
65 else
66 Write <= '1';
67 ect <= e3;
68 end if;
69
70 when e3 =>
71 null;
72
73 end case;
74 end if;
50 end if;
75 end process;
51 end process;
76
52
77
78 end architecture; No newline at end of file
53 end architecture;
Show file before | Show file after | Hide comments
@@ -1,182 +1,176
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 library gaisler;
29 library gaisler;
30 use gaisler.misc.all;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
31 use gaisler.memctrl.all;
32 library techmap;
32 library techmap;
33 use techmap.gencomp.all;
33 use techmap.gencomp.all;
34
34
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36
36
37 package lpp_memory is
37 package lpp_memory is
38
38
39 component APB_FIFO is
39 component APB_FIFO is
40 generic (
40 generic (
41 tech : integer := apa3;
41 tech : integer := apa3;
42 pindex : integer := 0;
42 pindex : integer := 0;
43 paddr : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
45 pirq : integer := 0;
46 abits : integer := 8;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
51 R : integer := 1;
52 W : integer := 1
52 W : integer := 1
53 );
53 );
54 port (
54 port (
55 clk : in std_logic; --! Horloge du composant
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
57 rclk : in std_logic;
58 wclk : in std_logic;
58 wclk : in std_logic;
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 );
70 );
71 end component;
71 end component;
72
72
73
73
74 component lpp_fifo is
74 component lpp_fifo is
75 generic(
75 generic(
76 tech : integer := 0;
76 tech : integer := 0;
77 Enable_ReUse : std_logic := '0';
77 Enable_ReUse : std_logic := '0';
78 DataSz : integer range 1 to 32 := 8;
78 DataSz : integer range 1 to 32 := 8;
79 abits : integer range 2 to 12 := 8
79 abits : integer range 2 to 12 := 8
80 );
80 );
81 port(
81 port(
82 rstn : in std_logic;
82 rstn : in std_logic;
83 ReUse : in std_logic; --27/01/12
83 ReUse : in std_logic; --27/01/12
84 rclk : in std_logic;
84 rclk : in std_logic;
85 ren : in std_logic;
85 ren : in std_logic;
86 rdata : out std_logic_vector(DataSz-1 downto 0);
86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 empty : out std_logic;
87 empty : out std_logic;
88 raddr : out std_logic_vector(abits-1 downto 0);
88 raddr : out std_logic_vector(abits-1 downto 0);
89 wclk : in std_logic;
89 wclk : in std_logic;
90 wen : in std_logic;
90 wen : in std_logic;
91 wdata : in std_logic_vector(DataSz-1 downto 0);
91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 full : out std_logic;
92 full : out std_logic;
93 waddr : out std_logic_vector(abits-1 downto 0)
93 waddr : out std_logic_vector(abits-1 downto 0)
94 );
94 );
95 end component;
95 end component;
96
96
97
97
98 component lppFIFOxN is
98 component lppFIFOxN is
99 generic(
99 generic(
100 tech : integer := 0;
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
101 Data_sz : integer range 1 to 32 := 8;
102 FifoCnt : integer := 1;
102 FifoCnt : integer := 1;
103 Enable_ReUse : std_logic := '0'
103 Enable_ReUse : std_logic := '0'
104 );
104 );
105 port(
105 port(
106 rst : in std_logic;
106 rst : in std_logic;
107 wclk : in std_logic;
107 wclk : in std_logic;
108 rclk : in std_logic;
108 rclk : in std_logic;
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
110 wen : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
111 ren : in std_logic_vector(FifoCnt-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
114 full : out std_logic_vector(FifoCnt-1 downto 0);
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
115 empty : out std_logic_vector(FifoCnt-1 downto 0)
116 );
116 );
117 end component;
117 end component;
118
118
119 component lppFIFOx5 is
119 component lppFIFOx5 is
120 generic(
120 generic(
121 tech : integer := 0;
121 tech : integer := 0;
122 Data_sz : integer range 1 to 32 := 16;
122 Data_sz : integer range 1 to 32 := 16;
123 Addr_sz : integer range 2 to 12 := 8;
123 Addr_sz : integer range 2 to 12 := 8;
124 Enable_ReUse : std_logic := '0'
124 Enable_ReUse : std_logic := '0'
125 );
125 );
126 port(
126 port(
127 rst : in std_logic;
127 rst : in std_logic;
128 wclk : in std_logic;
128 wclk : in std_logic;
129 rclk : in std_logic;
129 rclk : in std_logic;
130 ReUse : in std_logic_vector(4 downto 0);
130 ReUse : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 full : out std_logic_vector(4 downto 0);
135 full : out std_logic_vector(4 downto 0);
136 empty : out std_logic_vector(4 downto 0)
136 empty : out std_logic_vector(4 downto 0)
137 );
137 );
138 end component;
138 end component;
139
139
140 component Bridge is
140 component Bridge is
141 generic(
141 port(
142 Data_sz : integer range 1 to 32 := 16
142 clk : in std_logic;
143 );
143 raz : in std_logic;
144 port(
144 EmptyUp : in std_logic;
145 clk : in std_logic;
145 FullDwn : in std_logic;
146 raz : in std_logic;
146 WriteDwn : out std_logic;
147 Start : in std_logic;
147 ReadUp : out std_logic
148 FullUp : in std_logic;
148 );
149 EmptyUp : in std_logic;
150 FullDown : in std_logic;
151 EmptyDown : in std_logic;
152 Write : out std_logic;
153 Read : out std_logic
154 );
155 end component;
149 end component;
156
150
157 component ssram_plugin is
151 component ssram_plugin is
158 generic (tech : integer := 0);
152 generic (tech : integer := 0);
159 port
153 port
160 (
154 (
161 clk : in std_logic;
155 clk : in std_logic;
162 mem_ctrlr_o : in memory_out_type;
156 mem_ctrlr_o : in memory_out_type;
163 SSRAM_CLK : out std_logic;
157 SSRAM_CLK : out std_logic;
164 nBWa : out std_logic;
158 nBWa : out std_logic;
165 nBWb : out std_logic;
159 nBWb : out std_logic;
166 nBWc : out std_logic;
160 nBWc : out std_logic;
167 nBWd : out std_logic;
161 nBWd : out std_logic;
168 nBWE : out std_logic;
162 nBWE : out std_logic;
169 nADSC : out std_logic;
163 nADSC : out std_logic;
170 nADSP : out std_logic;
164 nADSP : out std_logic;
171 nADV : out std_logic;
165 nADV : out std_logic;
172 nGW : out std_logic;
166 nGW : out std_logic;
173 nCE1 : out std_logic;
167 nCE1 : out std_logic;
174 CE2 : out std_logic;
168 CE2 : out std_logic;
175 nCE3 : out std_logic;
169 nCE3 : out std_logic;
176 nOE : out std_logic;
170 nOE : out std_logic;
177 MODE : out std_logic;
171 MODE : out std_logic;
178 ZZ : out std_logic
172 ZZ : out std_logic
179 );
173 );
180 end component;
174 end component;
181
175
182 end;
176 end;
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