@@ -1,124 +1,124 | |||||
1 | set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout |
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1 | set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout | |
2 | set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout |
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2 | set_io clk50MHz -pinname B3 -fixed yes -DIRECTION Inout | |
3 | set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On |
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3 | set_io reset -pinname R4 -fixed yes -DIRECTION Inout -SCHMITT_TRIGGER On | |
4 |
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4 | |||
5 | set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout |
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5 | set_io {address[0]} -pinname U3 -fixed yes -DIRECTION Inout | |
6 | set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout |
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6 | set_io {address[1]} -pinname V14 -fixed yes -DIRECTION Inout | |
7 | set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout |
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7 | set_io {address[2]} -pinname V13 -fixed yes -DIRECTION Inout | |
8 | set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout |
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8 | set_io {address[3]} -pinname V16 -fixed yes -DIRECTION Inout | |
9 | set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout |
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9 | set_io {address[4]} -pinname N9 -fixed yes -DIRECTION Inout | |
10 | set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout |
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10 | set_io {address[5]} -pinname T11 -fixed yes -DIRECTION Inout | |
11 | set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout |
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11 | set_io {address[6]} -pinname U13 -fixed yes -DIRECTION Inout | |
12 | set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout |
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12 | set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout | |
13 | set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout |
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13 | set_io {address[8]} -pinname U2 -fixed yes -DIRECTION Inout | |
14 | set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout |
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14 | set_io {address[9]} -pinname N11 -fixed yes -DIRECTION Inout | |
15 | set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout |
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15 | set_io {address[10]} -pinname R13 -fixed yes -DIRECTION Inout | |
16 | set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout |
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16 | set_io {address[11]} -pinname R12 -fixed yes -DIRECTION Inout | |
17 | set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout |
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17 | set_io {address[12]} -pinname M15 -fixed yes -DIRECTION Inout | |
18 | set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout |
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18 | set_io {address[13]} -pinname T12 -fixed yes -DIRECTION Inout | |
19 | set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout |
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19 | set_io {address[14]} -pinname M13 -fixed yes -DIRECTION Inout | |
20 | set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout |
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20 | set_io {address[15]} -pinname T13 -fixed yes -DIRECTION Inout | |
21 | set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout |
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21 | set_io {address[16]} -pinname L13 -fixed yes -DIRECTION Inout | |
22 | set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout |
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22 | set_io {address[17]} -pinname V17 -fixed yes -DIRECTION Inout | |
23 | set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout |
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23 | set_io {address[18]} -pinname V15 -fixed yes -DIRECTION Inout | |
24 |
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24 | |||
25 | set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout |
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25 | set_io {data[0]} -pinname V4 -fixed yes -DIRECTION Inout | |
26 | set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout |
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26 | set_io {data[1]} -pinname V3 -fixed yes -DIRECTION Inout | |
27 | set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout |
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27 | set_io {data[2]} -pinname V2 -fixed yes -DIRECTION Inout | |
28 | set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout |
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28 | set_io {data[3]} -pinname T3 -fixed yes -DIRECTION Inout | |
29 | set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout |
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29 | set_io {data[4]} -pinname N6 -fixed yes -DIRECTION Inout | |
30 | set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout |
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30 | set_io {data[5]} -pinname P6 -fixed yes -DIRECTION Inout | |
31 | set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout |
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31 | set_io {data[6]} -pinname R6 -fixed yes -DIRECTION Inout | |
32 | set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout |
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32 | set_io {data[7]} -pinname T4 -fixed yes -DIRECTION Inout | |
33 | set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout |
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33 | set_io {data[8]} -pinname T1 -fixed yes -DIRECTION Inout | |
34 | set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout |
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34 | set_io {data[9]} -pinname R1 -fixed yes -DIRECTION Inout | |
35 | set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout |
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35 | set_io {data[10]} -pinname P1 -fixed yes -DIRECTION Inout | |
36 | set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout |
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36 | set_io {data[11]} -pinname N2 -fixed yes -DIRECTION Inout | |
37 | set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout |
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37 | set_io {data[12]} -pinname R3 -fixed yes -DIRECTION Inout | |
38 | set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout |
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38 | set_io {data[13]} -pinname P4 -fixed yes -DIRECTION Inout | |
39 | set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout |
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39 | set_io {data[14]} -pinname N4 -fixed yes -DIRECTION Inout | |
40 | set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout |
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40 | set_io {data[15]} -pinname N3 -fixed yes -DIRECTION Inout | |
41 | set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout |
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41 | set_io {data[16]} -pinname G12 -fixed yes -DIRECTION Inout | |
42 | set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout |
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42 | set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout | |
43 | set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout |
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43 | set_io {data[18]} -pinname H15 -fixed yes -DIRECTION Inout | |
44 | set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout |
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44 | set_io {data[19]} -pinname F17 -fixed yes -DIRECTION Inout | |
45 | set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout |
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45 | set_io {data[20]} -pinname F18 -fixed yes -DIRECTION Inout | |
46 | set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout |
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46 | set_io {data[21]} -pinname G17 -fixed yes -DIRECTION Inout | |
47 | set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout |
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47 | set_io {data[22]} -pinname H18 -fixed yes -DIRECTION Inout | |
48 | set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout |
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48 | set_io {data[23]} -pinname J18 -fixed yes -DIRECTION Inout | |
49 | set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout |
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49 | set_io {data[24]} -pinname R18 -fixed yes -DIRECTION Inout | |
50 | set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout |
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50 | set_io {data[25]} -pinname N18 -fixed yes -DIRECTION Inout | |
51 | set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout |
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51 | set_io {data[26]} -pinname P17 -fixed yes -DIRECTION Inout | |
52 | set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout |
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52 | set_io {data[27]} -pinname N17 -fixed yes -DIRECTION Inout | |
53 | set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout |
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53 | set_io {data[28]} -pinname T18 -fixed yes -DIRECTION Inout | |
54 | set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout |
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54 | set_io {data[29]} -pinname M17 -fixed yes -DIRECTION Inout | |
55 | set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout |
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55 | set_io {data[30]} -pinname U18 -fixed yes -DIRECTION Inout | |
56 | set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout |
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56 | set_io {data[31]} -pinname L18 -fixed yes -DIRECTION Inout | |
57 |
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57 | |||
58 | set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout |
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58 | set_io nSRAM_MBE -pinname E4 -fixed yes -DIRECTION Inout | |
59 | set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout |
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59 | set_io nSRAM_E1 -pinname D1 -fixed yes -DIRECTION Inout | |
60 | set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout |
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60 | set_io nSRAM_E2 -pinname C1 -fixed yes -DIRECTION Inout | |
61 | #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout |
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61 | #set_io nSRAM_SCRUB -pinname C2 -fixed yes -DIRECTION Inout | |
62 | set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout |
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62 | set_io nSRAM_W -pinname D4 -fixed yes -DIRECTION Inout | |
63 | set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout |
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63 | set_io nSRAM_G -pinname E1 -fixed yes -DIRECTION Inout | |
64 | set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout |
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64 | set_io nSRAM_BUSY -pinname F4 -fixed yes -DIRECTION Inout | |
65 |
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65 | |||
66 | set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout |
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66 | set_io spw1_en -pinname G4 -fixed yes -DIRECTION Inout | |
67 | set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout |
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67 | set_io spw1_din -pinname D13 -fixed yes -DIRECTION Inout | |
68 | set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout |
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68 | set_io spw1_sin -pinname D14 -fixed yes -DIRECTION Inout | |
69 | set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout |
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69 | set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout | |
70 | set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout |
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70 | set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout | |
71 |
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71 | |||
72 | set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout |
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72 | set_io spw2_en -pinname G3 -fixed yes -DIRECTION Inout | |
73 | set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout |
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73 | set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout | |
74 | set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout |
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74 | set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout | |
75 | set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout |
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75 | set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout | |
76 | set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout |
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76 | set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout | |
77 |
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77 | |||
78 | set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout |
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78 | set_io {TAG[1]} -pinname J12 -fixed yes -DIRECTION Inout | |
79 |
set_io |
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79 | set_io {TAG[2]} -pinname K12 -fixed yes -DIRECTION Inout | |
80 |
set_io |
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80 | set_io {TAG[3]} -pinname K13 -fixed yes -DIRECTION Inout | |
81 |
set_io |
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81 | set_io {TAG[4]} -pinname L16 -fixed yes -DIRECTION Inout | |
82 |
#set_io |
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82 | #set_io {TAG[5]} -pinname L15 -fixed yes -DIRECTION Inout | |
83 |
#set_io |
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83 | #set_io {TAG[6]} -pinname M16 -fixed yes -DIRECTION Inout | |
84 |
#set_io |
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84 | #set_io {TAG[7]} -pinname J14 -fixed yes -DIRECTION Inout | |
85 |
set_io |
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85 | set_io {TAG[8]} -pinname K15 -fixed yes -DIRECTION Inout | |
86 |
#set_io |
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86 | #set_io {TAG[9]} -pinname J17 -fixed yes -DIRECTION Inout | |
87 |
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87 | |||
88 | set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout |
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88 | set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout | |
89 |
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89 | |||
90 | set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout |
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90 | set_io {ADC_OEB_bar_CH[0]} -pinname A10 -fixed yes -DIRECTION Inout | |
91 | set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout |
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91 | set_io {ADC_OEB_bar_CH[1]} -pinname B10 -fixed yes -DIRECTION Inout | |
92 | set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout |
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92 | set_io {ADC_OEB_bar_CH[2]} -pinname B12 -fixed yes -DIRECTION Inout | |
93 | set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout |
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93 | set_io {ADC_OEB_bar_CH[3]} -pinname A11 -fixed yes -DIRECTION Inout | |
94 | set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout |
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94 | set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout | |
95 | set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout |
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95 | set_io {ADC_OEB_bar_CH[5]} -pinname C6 -fixed yes -DIRECTION Inout | |
96 | set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout |
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96 | set_io {ADC_OEB_bar_CH[6]} -pinname A13 -fixed yes -DIRECTION Inout | |
97 | set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout |
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97 | set_io {ADC_OEB_bar_CH[7]} -pinname A14 -fixed yes -DIRECTION Inout | |
98 |
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98 | |||
99 | set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout |
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99 | set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout | |
100 |
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100 | |||
101 | set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout |
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101 | set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout | |
102 | set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout |
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102 | set_io ADC_OEB_bar_HK -pinname D6 -fixed yes -DIRECTION Inout | |
103 | set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout |
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103 | set_io {HK_SEL[0]} -pinname C3 -fixed yes -DIRECTION Inout | |
104 | set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout |
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104 | set_io {HK_SEL[1]} -pinname A2 -fixed yes -DIRECTION Inout | |
105 |
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105 | |||
106 | set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout |
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106 | set_io {ADC_data[0]} -pinname G13 -fixed yes -DIRECTION Inout | |
107 | set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout |
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107 | set_io {ADC_data[1]} -pinname G16 -fixed yes -DIRECTION Inout | |
108 | set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout |
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108 | set_io {ADC_data[2]} -pinname F16 -fixed yes -DIRECTION Inout | |
109 | set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout |
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109 | set_io {ADC_data[3]} -pinname E15 -fixed yes -DIRECTION Inout | |
110 | set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout |
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110 | set_io {ADC_data[4]} -pinname F13 -fixed yes -DIRECTION Inout | |
111 | set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout |
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111 | set_io {ADC_data[5]} -pinname F15 -fixed yes -DIRECTION Inout | |
112 | set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout |
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112 | set_io {ADC_data[6]} -pinname D16 -fixed yes -DIRECTION Inout | |
113 | set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout |
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113 | set_io {ADC_data[7]} -pinname D15 -fixed yes -DIRECTION Inout | |
114 | set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout |
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114 | set_io {ADC_data[8]} -pinname B17 -fixed yes -DIRECTION Inout | |
115 | set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout |
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115 | set_io {ADC_data[9]} -pinname A17 -fixed yes -DIRECTION Inout | |
116 | set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout |
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116 | set_io {ADC_data[10]} -pinname A16 -fixed yes -DIRECTION Inout | |
117 | set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout |
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117 | set_io {ADC_data[11]} -pinname B16 -fixed yes -DIRECTION Inout | |
118 | set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout |
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118 | set_io {ADC_data[12]} -pinname C12 -fixed yes -DIRECTION Inout | |
119 | set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout |
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119 | set_io {ADC_data[13]} -pinname C13 -fixed yes -DIRECTION Inout | |
120 |
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120 | |||
121 | set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout |
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121 | set_io DAC_SDO -pinname A4 -fixed yes -DIRECTION Inout | |
122 | set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout |
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122 | set_io DAC_SCK -pinname A5 -fixed yes -DIRECTION Inout | |
123 | set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout |
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123 | set_io DAC_SYNC -pinname B6 -fixed yes -DIRECTION Inout | |
124 | set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout |
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124 | set_io DAC_CAL_EN -pinname A6 -fixed yes -DIRECTION Inout |
@@ -1,39 +1,128 | |||||
1 | # Top Level Design Parameters |
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1 | ################################################################################ | |
2 |
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2 | # SDC WRITER VERSION "3.1"; | ||
3 | # Clocks |
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3 | # DESIGN "LFR_EQM"; | |
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4 | # Timing constraints scenario: "Primary"; | |||
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5 | # DATE "Fri Apr 24 16:02:16 2015"; | |||
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6 | # VENDOR "Actel"; | |||
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7 | # PROGRAM "Actel Designer Software Release v9.1 SP5"; | |||
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8 | # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. | |||
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9 | ################################################################################ | |||
4 |
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10 | |||
5 | create_clock -period 20.000000 -waveform {0.000000 10.000000} clk50MHz |
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|||
6 | create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q |
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|||
7 |
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11 | |||
8 | #create_generated_clock -name{clk_domain_25} -divide_by 2 -source{clk_25_int:CLK}{clk_25_int:Q} |
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12 | set sdc_version 1.7 | |
9 |
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||||
10 | create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz |
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|||
11 | create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q |
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|||
12 | #create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} |
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|||
13 |
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13 | |||
14 |
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14 | |||
15 | # False Paths Between Clocks |
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15 | ######## Clock Constraints ######## | |
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16 | ||||
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17 | create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz } | |||
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18 | ||||
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19 | create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } | |||
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20 | ||||
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21 | create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } | |||
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22 | ||||
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23 | #create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } | |||
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24 | ||||
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25 | create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } | |||
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26 | ||||
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27 | create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } | |||
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28 | ||||
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29 | ||||
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30 | ||||
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31 | ######## Generated Clock Constraints ######## | |||
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32 | ||||
16 |
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33 | |||
17 |
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34 | |||
18 | # False Path Constraints |
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35 | ######## Clock Source Latency Constraints ######### | |
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36 | ||||
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37 | ||||
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38 | ||||
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39 | ######## Input Delay Constraints ######## | |||
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40 | ||||
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41 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |||
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42 | set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |||
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43 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |||
|
44 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |||
|
45 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |||
|
46 | set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \ | |||
|
47 | data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \ | |||
|
48 | data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \ | |||
|
49 | data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}] | |||
|
50 | ||||
|
51 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] | |||
|
52 | set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |||
|
53 | set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |||
|
54 | ||||
19 |
|
55 | |||
20 |
|
56 | |||
21 |
# |
|
57 | ######## Output Delay Constraints ######## | |
|
58 | ||||
|
59 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |||
|
60 | set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |||
|
61 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |||
|
62 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |||
|
63 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |||
|
64 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \ | |||
|
65 | data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \ | |||
|
66 | data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \ | |||
|
67 | data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }] | |||
22 |
|
68 | |||
23 | # Multicycle Constraints |
|
69 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }] | |
|
70 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |||
|
71 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |||
|
72 | address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ | |||
|
73 | address[7] address[8] address[9] }] | |||
|
74 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \ | |||
|
75 | address[11] address[12] address[13] address[14] address[15] address[16] address[17] \ | |||
|
76 | address[18] address[1] address[2] address[3] address[4] address[5] address[6] \ | |||
|
77 | address[7] address[8] address[9] }] | |||
|
78 | ||||
|
79 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |||
|
80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |||
|
81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }] | |||
|
82 | ||||
|
83 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }] | |||
|
84 | set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] | |||
|
85 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }] | |||
|
86 | ||||
|
87 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }] | |||
|
88 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] | |||
|
89 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }] | |||
|
90 | ||||
24 |
|
91 | |||
25 |
|
92 | |||
26 | # Virtual Clocks |
|
93 | ######## Delay Constraints ######## | |
27 | # Output Load Constraints |
|
94 | ||
28 | # Driving Cell Constraints |
|
95 | set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ | |
29 | # Wire Loads |
|
96 | nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ | |
30 | # set_wire_load_mode top |
|
97 | {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}] | |
31 |
|
98 | |||
32 | # Other Constraints |
|
99 | set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \ | |
|
100 | nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \ | |||
|
101 | {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}] | |||
|
102 | ||||
|
103 | ||||
|
104 | ||||
|
105 | ######## Delay Constraints ######## | |||
|
106 | ||||
33 |
|
107 | |||
34 |
|
108 | |||
35 | ## GRSPW constraints |
|
109 | ######## Multicycle Constraints ######## | |
36 | create_clock -period 100.00 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y} |
|
110 | ||
37 | create_clock -period 100.00 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y} |
|
111 | ||
38 | set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.0.spw_phy0/rxclki_RNO:Y] |
|
112 | ||
39 | set_max_delay 4.00 -from [all_inputs] -to [get_clocks spw_inputloop.1.spw_phy0/rxclki_RNO:Y] |
|
113 | ######## False Path Constraints ######## | |
|
114 | ||||
|
115 | ||||
|
116 | ||||
|
117 | ######## Output load Constraints ######## | |||
|
118 | ||||
|
119 | ||||
|
120 | ||||
|
121 | ######## Disable Timing Constraints ######### | |||
|
122 | ||||
|
123 | ||||
|
124 | ||||
|
125 | ######## Clock Uncertainty Constraints ######### | |||
|
126 | ||||
|
127 | ||||
|
128 |
@@ -1,602 +1,603 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
|
19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
|
21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
|
22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
|
23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
|
24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
|
25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
|
26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
|
27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
|
28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
|
29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
|
30 | LIBRARY gaisler; | |
31 | USE gaisler.sim.ALL; |
|
31 | USE gaisler.sim.ALL; | |
32 | USE gaisler.memctrl.ALL; |
|
32 | USE gaisler.memctrl.ALL; | |
33 | USE gaisler.leon3.ALL; |
|
33 | USE gaisler.leon3.ALL; | |
34 | USE gaisler.uart.ALL; |
|
34 | USE gaisler.uart.ALL; | |
35 | USE gaisler.misc.ALL; |
|
35 | USE gaisler.misc.ALL; | |
36 | USE gaisler.spacewire.ALL; |
|
36 | USE gaisler.spacewire.ALL; | |
37 | LIBRARY esa; |
|
37 | LIBRARY esa; | |
38 | USE esa.memoryctrl.ALL; |
|
38 | USE esa.memoryctrl.ALL; | |
39 | LIBRARY lpp; |
|
39 | LIBRARY lpp; | |
40 | USE lpp.lpp_memory.ALL; |
|
40 | USE lpp.lpp_memory.ALL; | |
41 | USE lpp.lpp_ad_conv.ALL; |
|
41 | USE lpp.lpp_ad_conv.ALL; | |
42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
44 | USE lpp.iir_filter.ALL; |
|
44 | USE lpp.iir_filter.ALL; | |
45 | USE lpp.general_purpose.ALL; |
|
45 | USE lpp.general_purpose.ALL; | |
46 | USE lpp.lpp_lfr_management.ALL; |
|
46 | USE lpp.lpp_lfr_management.ALL; | |
47 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
48 | USE lpp.lpp_bootloader_pkg.ALL; |
|
48 | USE lpp.lpp_bootloader_pkg.ALL; | |
49 |
|
49 | |||
50 | --library proasic3l; |
|
50 | --library proasic3l; | |
51 | --use proasic3l.all; |
|
51 | --use proasic3l.all; | |
52 |
|
52 | |||
53 | ENTITY LFR_EQM IS |
|
53 | ENTITY LFR_EQM IS | |
54 | GENERIC ( |
|
54 | GENERIC ( | |
55 | Mem_use : INTEGER := use_RAM; |
|
55 | Mem_use : INTEGER := use_RAM; | |
56 | USE_BOOTLOADER : INTEGER := 0; |
|
56 | USE_BOOTLOADER : INTEGER := 0; | |
57 | USE_ADCDRIVER : INTEGER := 1; |
|
57 | USE_ADCDRIVER : INTEGER := 1; | |
58 | tech : INTEGER := apa3e; |
|
58 | tech : INTEGER := apa3e; | |
59 | tech_leon : INTEGER := apa3e; |
|
59 | tech_leon : INTEGER := apa3e; | |
60 |
DEBUG_FORCE_DATA_DMA : INTEGER := |
|
60 | DEBUG_FORCE_DATA_DMA : INTEGER := 0; | |
61 |
USE_DEBUG_VECTOR : INTEGER := |
|
61 | USE_DEBUG_VECTOR : INTEGER := 0 | |
62 | ); |
|
62 | ); | |
63 |
|
63 | |||
64 | PORT ( |
|
64 | PORT ( | |
65 | clk50MHz : IN STD_ULOGIC; |
|
65 | clk50MHz : IN STD_ULOGIC; | |
66 | clk49_152MHz : IN STD_ULOGIC; |
|
66 | clk49_152MHz : IN STD_ULOGIC; | |
67 | reset : IN STD_ULOGIC; |
|
67 | reset : IN STD_ULOGIC; | |
68 |
|
68 | |||
69 | TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); |
|
69 | TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1); | |
70 |
|
70 | |||
71 | -- TAG -------------------------------------------------------------------- |
|
71 | -- TAG -------------------------------------------------------------------- | |
72 | --TAG1 : IN STD_ULOGIC; -- DSU rx data |
|
72 | --TAG1 : IN STD_ULOGIC; -- DSU rx data | |
73 | --TAG3 : OUT STD_ULOGIC; -- DSU tx data |
|
73 | --TAG3 : OUT STD_ULOGIC; -- DSU tx data | |
74 | -- UART APB --------------------------------------------------------------- |
|
74 | -- UART APB --------------------------------------------------------------- | |
75 | --TAG2 : IN STD_ULOGIC; -- UART1 rx data |
|
75 | --TAG2 : IN STD_ULOGIC; -- UART1 rx data | |
76 | --TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
|
76 | --TAG4 : OUT STD_ULOGIC; -- UART1 tx data | |
77 | -- RAM -------------------------------------------------------------------- |
|
77 | -- RAM -------------------------------------------------------------------- | |
78 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); |
|
78 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); | |
79 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
79 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
80 |
|
80 | |||
81 | nSRAM_MBE : INOUT STD_LOGIC; -- new |
|
81 | nSRAM_MBE : INOUT STD_LOGIC; -- new | |
82 | nSRAM_E1 : OUT STD_LOGIC; -- new |
|
82 | nSRAM_E1 : OUT STD_LOGIC; -- new | |
83 | nSRAM_E2 : OUT STD_LOGIC; -- new |
|
83 | nSRAM_E2 : OUT STD_LOGIC; -- new | |
84 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new |
|
84 | -- nSRAM_SCRUB : OUT STD_LOGIC; -- new | |
85 | nSRAM_W : OUT STD_LOGIC; -- new |
|
85 | nSRAM_W : OUT STD_LOGIC; -- new | |
86 | nSRAM_G : OUT STD_LOGIC; -- new |
|
86 | nSRAM_G : OUT STD_LOGIC; -- new | |
87 | nSRAM_BUSY : IN STD_LOGIC; -- new |
|
87 | nSRAM_BUSY : IN STD_LOGIC; -- new | |
88 | -- SPW -------------------------------------------------------------------- |
|
88 | -- SPW -------------------------------------------------------------------- | |
89 | spw1_en : OUT STD_LOGIC; -- new |
|
89 | spw1_en : OUT STD_LOGIC; -- new | |
90 | spw1_din : IN STD_LOGIC; |
|
90 | spw1_din : IN STD_LOGIC; | |
91 | spw1_sin : IN STD_LOGIC; |
|
91 | spw1_sin : IN STD_LOGIC; | |
92 | spw1_dout : OUT STD_LOGIC; |
|
92 | spw1_dout : OUT STD_LOGIC; | |
93 | spw1_sout : OUT STD_LOGIC; |
|
93 | spw1_sout : OUT STD_LOGIC; | |
94 | spw2_en : OUT STD_LOGIC; -- new |
|
94 | spw2_en : OUT STD_LOGIC; -- new | |
95 | spw2_din : IN STD_LOGIC; |
|
95 | spw2_din : IN STD_LOGIC; | |
96 | spw2_sin : IN STD_LOGIC; |
|
96 | spw2_sin : IN STD_LOGIC; | |
97 | spw2_dout : OUT STD_LOGIC; |
|
97 | spw2_dout : OUT STD_LOGIC; | |
98 | spw2_sout : OUT STD_LOGIC; |
|
98 | spw2_sout : OUT STD_LOGIC; | |
99 | -- ADC -------------------------------------------------------------------- |
|
99 | -- ADC -------------------------------------------------------------------- | |
100 | bias_fail_sw : OUT STD_LOGIC; |
|
100 | bias_fail_sw : OUT STD_LOGIC; | |
101 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
101 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 | ADC_smpclk : OUT STD_LOGIC; |
|
102 | ADC_smpclk : OUT STD_LOGIC; | |
103 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
|
103 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |
104 | -- DAC -------------------------------------------------------------------- |
|
104 | -- DAC -------------------------------------------------------------------- | |
105 | DAC_SDO : OUT STD_LOGIC; |
|
105 | DAC_SDO : OUT STD_LOGIC; | |
106 | DAC_SCK : OUT STD_LOGIC; |
|
106 | DAC_SCK : OUT STD_LOGIC; | |
107 | DAC_SYNC : OUT STD_LOGIC; |
|
107 | DAC_SYNC : OUT STD_LOGIC; | |
108 | DAC_CAL_EN : OUT STD_LOGIC; |
|
108 | DAC_CAL_EN : OUT STD_LOGIC; | |
109 | -- HK --------------------------------------------------------------------- |
|
109 | -- HK --------------------------------------------------------------------- | |
110 | HK_smpclk : OUT STD_LOGIC; |
|
110 | HK_smpclk : OUT STD_LOGIC; | |
111 | ADC_OEB_bar_HK : OUT STD_LOGIC; |
|
111 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |
112 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; |
|
112 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--; | |
113 | --------------------------------------------------------------------------- |
|
113 | --------------------------------------------------------------------------- | |
114 | -- TAG8 : OUT STD_LOGIC |
|
114 | -- TAG8 : OUT STD_LOGIC | |
115 | ); |
|
115 | ); | |
116 |
|
116 | |||
117 | END LFR_EQM; |
|
117 | END LFR_EQM; | |
118 |
|
118 | |||
119 |
|
119 | |||
120 | ARCHITECTURE beh OF LFR_EQM IS |
|
120 | ARCHITECTURE beh OF LFR_EQM IS | |
121 |
|
121 | |||
122 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
122 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
123 |
SIGNAL clk_ |
|
123 | SIGNAL clk_49 : STD_LOGIC := '0'; | |
124 | ----------------------------------------------------------------------------- |
|
124 | ----------------------------------------------------------------------------- | |
125 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
125 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
126 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
126 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
127 |
|
127 | |||
128 | -- CONSTANTS |
|
128 | -- CONSTANTS | |
129 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
129 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
130 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
130 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
131 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
131 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
132 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
132 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
133 |
|
133 | |||
134 | SIGNAL apbi_ext : apb_slv_in_type; |
|
134 | SIGNAL apbi_ext : apb_slv_in_type; | |
135 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
135 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
136 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
136 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
137 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
137 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
138 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
138 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
139 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
139 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
140 |
|
140 | |||
141 | -- Spacewire signals |
|
141 | -- Spacewire signals | |
142 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
142 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
143 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
143 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
144 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
144 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
145 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
145 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
146 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
146 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
147 | SIGNAL spw_clk : STD_LOGIC; |
|
147 | SIGNAL spw_clk : STD_LOGIC; | |
148 | SIGNAL swni : grspw_in_type; |
|
148 | SIGNAL swni : grspw_in_type; | |
149 | SIGNAL swno : grspw_out_type; |
|
149 | SIGNAL swno : grspw_out_type; | |
150 |
|
150 | |||
151 | --GPIO |
|
151 | --GPIO | |
152 | SIGNAL gpioi : gpio_in_type; |
|
152 | SIGNAL gpioi : gpio_in_type; | |
153 | SIGNAL gpioo : gpio_out_type; |
|
153 | SIGNAL gpioo : gpio_out_type; | |
154 |
|
154 | |||
155 | -- AD Converter ADS7886 |
|
155 | -- AD Converter ADS7886 | |
156 | SIGNAL sample : Samples14v(8 DOWNTO 0); |
|
156 | SIGNAL sample : Samples14v(8 DOWNTO 0); | |
157 | SIGNAL sample_s : Samples(8 DOWNTO 0); |
|
157 | SIGNAL sample_s : Samples(8 DOWNTO 0); | |
158 | SIGNAL sample_val : STD_LOGIC; |
|
158 | SIGNAL sample_val : STD_LOGIC; | |
159 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); |
|
159 | SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0); | |
160 |
|
160 | |||
161 | ----------------------------------------------------------------------------- |
|
161 | ----------------------------------------------------------------------------- | |
162 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
162 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
163 |
|
163 | |||
164 | ----------------------------------------------------------------------------- |
|
164 | ----------------------------------------------------------------------------- | |
165 | SIGNAL rstn_25 : STD_LOGIC; |
|
165 | SIGNAL rstn_25 : STD_LOGIC; | |
166 |
SIGNAL rstn_ |
|
166 | SIGNAL rstn_49 : STD_LOGIC; | |
167 |
|
167 | |||
168 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
|
168 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
169 | SIGNAL LFR_rstn : STD_LOGIC; |
|
169 | SIGNAL LFR_rstn : STD_LOGIC; | |
170 |
|
170 | |||
171 | SIGNAL ADC_smpclk_s : STD_LOGIC; |
|
171 | SIGNAL ADC_smpclk_s : STD_LOGIC; | |
172 |
|
172 | |||
173 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
173 | SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
174 |
|
174 | |||
175 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; |
|
175 | SIGNAL clk50MHz_int : STD_LOGIC := '0'; | |
176 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
|
176 | SIGNAL clk_25_int : STD_LOGIC := '0'; | |
177 |
|
177 | |||
178 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
|
178 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; | |
179 |
|
179 | |||
180 | SIGNAL rstn_50 : STD_LOGIC; |
|
180 | SIGNAL rstn_50 : STD_LOGIC; | |
181 | SIGNAL clk_lock : STD_LOGIC; |
|
181 | SIGNAL clk_lock : STD_LOGIC; | |
182 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
182 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
183 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; |
|
183 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; | |
184 |
|
184 | |||
185 | SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
185 | SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
186 | SIGNAL ahbrxd: STD_LOGIC; |
|
186 | SIGNAL ahbrxd: STD_LOGIC; | |
187 | SIGNAL ahbtxd: STD_LOGIC; |
|
187 | SIGNAL ahbtxd: STD_LOGIC; | |
188 | SIGNAL urxd1 : STD_LOGIC; |
|
188 | SIGNAL urxd1 : STD_LOGIC; | |
189 | SIGNAL utxd1 : STD_LOGIC; |
|
189 | SIGNAL utxd1 : STD_LOGIC; | |
190 | BEGIN -- beh |
|
190 | BEGIN -- beh | |
191 |
|
191 | |||
192 | ----------------------------------------------------------------------------- |
|
192 | ----------------------------------------------------------------------------- | |
193 | -- CLK_LOCK |
|
193 | -- CLK_LOCK | |
194 | ----------------------------------------------------------------------------- |
|
194 | ----------------------------------------------------------------------------- | |
195 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); |
|
195 | rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN); | |
196 |
|
196 | |||
197 | PROCESS (clk50MHz_int, rstn_50) |
|
197 | PROCESS (clk50MHz_int, rstn_50) | |
198 | BEGIN -- PROCESS |
|
198 | BEGIN -- PROCESS | |
199 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
199 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
200 | clk_lock <= '0'; |
|
200 | clk_lock <= '0'; | |
201 | clk_busy_counter <= (OTHERS => '0'); |
|
201 | clk_busy_counter <= (OTHERS => '0'); | |
202 | nSRAM_BUSY_reg <= '0'; |
|
202 | nSRAM_BUSY_reg <= '0'; | |
203 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge |
|
203 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge | |
204 | nSRAM_BUSY_reg <= nSRAM_BUSY; |
|
204 | nSRAM_BUSY_reg <= nSRAM_BUSY; | |
205 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN |
|
205 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN | |
206 | IF clk_busy_counter = "1111" THEN |
|
206 | IF clk_busy_counter = "1111" THEN | |
207 | clk_lock <= '1'; |
|
207 | clk_lock <= '1'; | |
208 | ELSE |
|
208 | ELSE | |
209 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); |
|
209 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); | |
210 | END IF; |
|
210 | END IF; | |
211 | END IF; |
|
211 | END IF; | |
212 | END IF; |
|
212 | END IF; | |
213 | END PROCESS; |
|
213 | END PROCESS; | |
214 |
|
214 | |||
215 | ----------------------------------------------------------------------------- |
|
215 | ----------------------------------------------------------------------------- | |
216 | -- CLK |
|
216 | -- CLK | |
217 | ----------------------------------------------------------------------------- |
|
217 | ----------------------------------------------------------------------------- | |
218 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); |
|
218 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); | |
219 |
rst_domain24 : rstgen PORT MAP (reset, clk_ |
|
219 | rst_domain24 : rstgen PORT MAP (reset, clk_49, clk_lock, rstn_49, OPEN); | |
220 |
|
220 | |||
221 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
|
221 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); | |
222 | clk50MHz_int <= clk50MHz; |
|
222 | clk50MHz_int <= clk50MHz; | |
223 |
|
223 | |||
224 | PROCESS(clk50MHz_int) |
|
224 | PROCESS(clk50MHz_int) | |
225 | BEGIN |
|
225 | BEGIN | |
226 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN |
|
226 | IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN | |
227 | --clk_25_int <= NOT clk_25_int; |
|
227 | --clk_25_int <= NOT clk_25_int; | |
228 | clk_25 <= NOT clk_25; |
|
228 | clk_25 <= NOT clk_25; | |
229 | END IF; |
|
229 | END IF; | |
230 | END PROCESS; |
|
230 | END PROCESS; | |
231 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); |
|
231 | --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 ); | |
232 |
|
232 | |||
233 | PROCESS(clk49_152MHz) |
|
233 | --PROCESS(clk49_152MHz) | |
234 | BEGIN |
|
234 | --BEGIN | |
235 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
|
235 | -- IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN | |
236 | clk_24 <= NOT clk_24; |
|
236 | -- clk_24 <= NOT clk_24; | |
237 | END IF; |
|
237 | -- END IF; | |
238 | END PROCESS; |
|
238 | --END PROCESS; | |
|
239 | clk_49 <= clk49_152MHz; | |||
239 |
|
240 | |||
240 | ----------------------------------------------------------------------------- |
|
241 | ----------------------------------------------------------------------------- | |
241 | -- |
|
242 | -- | |
242 | leon3_soc_1 : leon3_soc |
|
243 | leon3_soc_1 : leon3_soc | |
243 | GENERIC MAP ( |
|
244 | GENERIC MAP ( | |
244 | fabtech => tech_leon, |
|
245 | fabtech => tech_leon, | |
245 | memtech => tech_leon, |
|
246 | memtech => tech_leon, | |
246 | padtech => inferred, |
|
247 | padtech => inferred, | |
247 | clktech => inferred, |
|
248 | clktech => inferred, | |
248 | disas => 0, |
|
249 | disas => 0, | |
249 | dbguart => 0, |
|
250 | dbguart => 0, | |
250 | pclow => 2, |
|
251 | pclow => 2, | |
251 | clk_freq => 25000, |
|
252 | clk_freq => 25000, | |
252 | IS_RADHARD => 0, |
|
253 | IS_RADHARD => 0, | |
253 | NB_CPU => 1, |
|
254 | NB_CPU => 1, | |
254 | ENABLE_FPU => 1, |
|
255 | ENABLE_FPU => 1, | |
255 | FPU_NETLIST => 0, |
|
256 | FPU_NETLIST => 0, | |
256 | ENABLE_DSU => 1, |
|
257 | ENABLE_DSU => 1, | |
257 | ENABLE_AHB_UART => 1, |
|
258 | ENABLE_AHB_UART => 1, | |
258 | ENABLE_APB_UART => 1, |
|
259 | ENABLE_APB_UART => 1, | |
259 | ENABLE_IRQMP => 1, |
|
260 | ENABLE_IRQMP => 1, | |
260 | ENABLE_GPT => 1, |
|
261 | ENABLE_GPT => 1, | |
261 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
262 | NB_AHB_MASTER => NB_AHB_MASTER, | |
262 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
263 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
263 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
264 | NB_APB_SLAVE => NB_APB_SLAVE, | |
264 | ADDRESS_SIZE => 19, |
|
265 | ADDRESS_SIZE => 19, | |
265 | USES_IAP_MEMCTRLR => 1, |
|
266 | USES_IAP_MEMCTRLR => 1, | |
266 | BYPASS_EDAC_MEMCTRLR => '0', |
|
267 | BYPASS_EDAC_MEMCTRLR => '0', | |
267 | SRBANKSZ => 8) |
|
268 | SRBANKSZ => 8) | |
268 | PORT MAP ( |
|
269 | PORT MAP ( | |
269 | clk => clk_25, |
|
270 | clk => clk_25, | |
270 | reset => rstn_25, |
|
271 | reset => rstn_25, | |
271 | errorn => OPEN, |
|
272 | errorn => OPEN, | |
272 |
|
273 | |||
273 | ahbrxd => ahbrxd, -- INPUT |
|
274 | ahbrxd => ahbrxd, -- INPUT | |
274 | ahbtxd => ahbtxd, -- OUTPUT |
|
275 | ahbtxd => ahbtxd, -- OUTPUT | |
275 | urxd1 => urxd1, -- INPUT |
|
276 | urxd1 => urxd1, -- INPUT | |
276 | utxd1 => utxd1, -- OUTPUT |
|
277 | utxd1 => utxd1, -- OUTPUT | |
277 |
|
278 | |||
278 | address => address, |
|
279 | address => address, | |
279 | data => data, |
|
280 | data => data, | |
280 | nSRAM_BE0 => OPEN, |
|
281 | nSRAM_BE0 => OPEN, | |
281 | nSRAM_BE1 => OPEN, |
|
282 | nSRAM_BE1 => OPEN, | |
282 | nSRAM_BE2 => OPEN, |
|
283 | nSRAM_BE2 => OPEN, | |
283 | nSRAM_BE3 => OPEN, |
|
284 | nSRAM_BE3 => OPEN, | |
284 | nSRAM_WE => nSRAM_W, |
|
285 | nSRAM_WE => nSRAM_W, | |
285 | nSRAM_CE => nSRAM_CE, |
|
286 | nSRAM_CE => nSRAM_CE, | |
286 | nSRAM_OE => nSRAM_G, |
|
287 | nSRAM_OE => nSRAM_G, | |
287 | nSRAM_READY => nSRAM_BUSY, |
|
288 | nSRAM_READY => nSRAM_BUSY, | |
288 | SRAM_MBE => nSRAM_MBE, |
|
289 | SRAM_MBE => nSRAM_MBE, | |
289 |
|
290 | |||
290 | apbi_ext => apbi_ext, |
|
291 | apbi_ext => apbi_ext, | |
291 | apbo_ext => apbo_ext, |
|
292 | apbo_ext => apbo_ext, | |
292 | ahbi_s_ext => ahbi_s_ext, |
|
293 | ahbi_s_ext => ahbi_s_ext, | |
293 | ahbo_s_ext => ahbo_s_ext, |
|
294 | ahbo_s_ext => ahbo_s_ext, | |
294 | ahbi_m_ext => ahbi_m_ext, |
|
295 | ahbi_m_ext => ahbi_m_ext, | |
295 | ahbo_m_ext => ahbo_m_ext); |
|
296 | ahbo_m_ext => ahbo_m_ext); | |
296 |
|
297 | |||
297 |
|
298 | |||
298 | nSRAM_E1 <= nSRAM_CE(0); |
|
299 | nSRAM_E1 <= nSRAM_CE(0); | |
299 | nSRAM_E2 <= nSRAM_CE(1); |
|
300 | nSRAM_E2 <= nSRAM_CE(1); | |
300 |
|
301 | |||
301 | ------------------------------------------------------------------------------- |
|
302 | ------------------------------------------------------------------------------- | |
302 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
303 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
303 | ------------------------------------------------------------------------------- |
|
304 | ------------------------------------------------------------------------------- | |
304 | apb_lfr_management_1 : apb_lfr_management |
|
305 | apb_lfr_management_1 : apb_lfr_management | |
305 | GENERIC MAP ( |
|
306 | GENERIC MAP ( | |
306 | tech => tech, |
|
307 | tech => tech, | |
307 | pindex => 6, |
|
308 | pindex => 6, | |
308 | paddr => 6, |
|
309 | paddr => 6, | |
309 | pmask => 16#fff#, |
|
310 | pmask => 16#fff#, | |
310 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
311 | --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
311 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
312 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
312 | PORT MAP ( |
|
313 | PORT MAP ( | |
313 | clk25MHz => clk_25, |
|
314 | clk25MHz => clk_25, | |
314 | resetn_25MHz => rstn_25, -- TODO |
|
315 | resetn_25MHz => rstn_25, -- TODO | |
315 | --clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
316 | --clk24_576MHz => clk_24, -- 49.152MHz/2 | |
316 | --resetn_24_576MHz => rstn_24, -- TODO |
|
317 | --resetn_24_576MHz => rstn_24, -- TODO | |
317 |
|
318 | |||
318 | grspw_tick => swno.tickout, |
|
319 | grspw_tick => swno.tickout, | |
319 | apbi => apbi_ext, |
|
320 | apbi => apbi_ext, | |
320 | apbo => apbo_ext(6), |
|
321 | apbo => apbo_ext(6), | |
321 |
|
322 | |||
322 | HK_sample => sample_s(8), |
|
323 | HK_sample => sample_s(8), | |
323 | HK_val => sample_val, |
|
324 | HK_val => sample_val, | |
324 | HK_sel => HK_SEL, |
|
325 | HK_sel => HK_SEL, | |
325 |
|
326 | |||
326 | DAC_SDO => DAC_SDO, |
|
327 | DAC_SDO => DAC_SDO, | |
327 | DAC_SCK => DAC_SCK, |
|
328 | DAC_SCK => DAC_SCK, | |
328 | DAC_SYNC => DAC_SYNC, |
|
329 | DAC_SYNC => DAC_SYNC, | |
329 | DAC_CAL_EN => DAC_CAL_EN, |
|
330 | DAC_CAL_EN => DAC_CAL_EN, | |
330 |
|
331 | |||
331 | coarse_time => coarse_time, |
|
332 | coarse_time => coarse_time, | |
332 | fine_time => fine_time, |
|
333 | fine_time => fine_time, | |
333 | LFR_soft_rstn => LFR_soft_rstn |
|
334 | LFR_soft_rstn => LFR_soft_rstn | |
334 | ); |
|
335 | ); | |
335 |
|
336 | |||
336 | ----------------------------------------------------------------------- |
|
337 | ----------------------------------------------------------------------- | |
337 | --- SpaceWire -------------------------------------------------------- |
|
338 | --- SpaceWire -------------------------------------------------------- | |
338 | ----------------------------------------------------------------------- |
|
339 | ----------------------------------------------------------------------- | |
339 |
|
340 | |||
340 | ------------------------------------------------------------------------------ |
|
341 | ------------------------------------------------------------------------------ | |
341 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ |
|
342 | -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/ | |
342 | ------------------------------------------------------------------------------ |
|
343 | ------------------------------------------------------------------------------ | |
343 | spw1_en <= '1'; |
|
344 | spw1_en <= '1'; | |
344 | spw2_en <= '1'; |
|
345 | spw2_en <= '1'; | |
345 | ------------------------------------------------------------------------------ |
|
346 | ------------------------------------------------------------------------------ | |
346 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ |
|
347 | -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\ | |
347 | ------------------------------------------------------------------------------ |
|
348 | ------------------------------------------------------------------------------ | |
348 |
|
349 | |||
349 | --spw_clk <= clk50MHz; |
|
350 | --spw_clk <= clk50MHz; | |
350 | --spw_rxtxclk <= spw_clk; |
|
351 | --spw_rxtxclk <= spw_clk; | |
351 | --spw_rxclkn <= NOT spw_rxtxclk; |
|
352 | --spw_rxclkn <= NOT spw_rxtxclk; | |
352 |
|
353 | |||
353 | -- PADS for SPW1 |
|
354 | -- PADS for SPW1 | |
354 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
355 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
355 | PORT MAP (spw1_din, dtmp(0)); |
|
356 | PORT MAP (spw1_din, dtmp(0)); | |
356 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
357 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
357 | PORT MAP (spw1_sin, stmp(0)); |
|
358 | PORT MAP (spw1_sin, stmp(0)); | |
358 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
359 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
359 | PORT MAP (spw1_dout, swno.d(0)); |
|
360 | PORT MAP (spw1_dout, swno.d(0)); | |
360 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
361 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
361 | PORT MAP (spw1_sout, swno.s(0)); |
|
362 | PORT MAP (spw1_sout, swno.s(0)); | |
362 | -- PADS FOR SPW2 |
|
363 | -- PADS FOR SPW2 | |
363 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
364 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
364 | PORT MAP (spw2_din, dtmp(1)); |
|
365 | PORT MAP (spw2_din, dtmp(1)); | |
365 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
366 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
366 | PORT MAP (spw2_sin, stmp(1)); |
|
367 | PORT MAP (spw2_sin, stmp(1)); | |
367 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
368 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
368 | PORT MAP (spw2_dout, swno.d(1)); |
|
369 | PORT MAP (spw2_dout, swno.d(1)); | |
369 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
370 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
370 | PORT MAP (spw2_sout, swno.s(1)); |
|
371 | PORT MAP (spw2_sout, swno.s(1)); | |
371 |
|
372 | |||
372 | -- GRSPW PHY |
|
373 | -- GRSPW PHY | |
373 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
374 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
374 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
375 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
375 | spw_phy0 : grspw_phy |
|
376 | spw_phy0 : grspw_phy | |
376 | GENERIC MAP( |
|
377 | GENERIC MAP( | |
377 | tech => tech_leon, |
|
378 | tech => tech_leon, | |
378 | rxclkbuftype => 1, |
|
379 | rxclkbuftype => 1, | |
379 | scantest => 0) |
|
380 | scantest => 0) | |
380 | PORT MAP( |
|
381 | PORT MAP( | |
381 | rxrst => swno.rxrst, |
|
382 | rxrst => swno.rxrst, | |
382 | di => dtmp(j), |
|
383 | di => dtmp(j), | |
383 | si => stmp(j), |
|
384 | si => stmp(j), | |
384 | rxclko => spw_rxclk(j), |
|
385 | rxclko => spw_rxclk(j), | |
385 | do => swni.d(j), |
|
386 | do => swni.d(j), | |
386 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
387 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
387 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
388 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
388 | END GENERATE spw_inputloop; |
|
389 | END GENERATE spw_inputloop; | |
389 |
|
390 | |||
390 | -- SPW core |
|
391 | -- SPW core | |
391 | sw0 : grspwm GENERIC MAP( |
|
392 | sw0 : grspwm GENERIC MAP( | |
392 | tech => tech_leon, |
|
393 | tech => tech_leon, | |
393 | hindex => 1, |
|
394 | hindex => 1, | |
394 | pindex => 5, |
|
395 | pindex => 5, | |
395 | paddr => 5, |
|
396 | paddr => 5, | |
396 | pirq => 11, |
|
397 | pirq => 11, | |
397 | sysfreq => 25000, -- CPU_FREQ |
|
398 | sysfreq => 25000, -- CPU_FREQ | |
398 | rmap => 1, |
|
399 | rmap => 1, | |
399 | rmapcrc => 1, |
|
400 | rmapcrc => 1, | |
400 | fifosize1 => 16, |
|
401 | fifosize1 => 16, | |
401 | fifosize2 => 16, |
|
402 | fifosize2 => 16, | |
402 | rxclkbuftype => 1, |
|
403 | rxclkbuftype => 1, | |
403 | rxunaligned => 0, |
|
404 | rxunaligned => 0, | |
404 | rmapbufs => 4, |
|
405 | rmapbufs => 4, | |
405 | ft => 0, |
|
406 | ft => 0, | |
406 | netlist => 0, |
|
407 | netlist => 0, | |
407 | ports => 2, |
|
408 | ports => 2, | |
408 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
409 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
409 | memtech => tech_leon, |
|
410 | memtech => tech_leon, | |
410 | destkey => 2, |
|
411 | destkey => 2, | |
411 | spwcore => 1 |
|
412 | spwcore => 1 | |
412 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
413 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
413 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
414 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
414 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
415 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
415 | ) |
|
416 | ) | |
416 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
417 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
417 | spw_rxclk(1), |
|
418 | spw_rxclk(1), | |
418 | clk50MHz_int, |
|
419 | clk50MHz_int, | |
419 | clk50MHz_int, |
|
420 | clk50MHz_int, | |
420 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, |
|
421 | -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, | |
421 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
422 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
422 | swni, swno); |
|
423 | swni, swno); | |
423 |
|
424 | |||
424 | swni.tickin <= '0'; |
|
425 | swni.tickin <= '0'; | |
425 | swni.rmapen <= '1'; |
|
426 | swni.rmapen <= '1'; | |
426 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz |
|
427 | swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz | |
427 | swni.tickinraw <= '0'; |
|
428 | swni.tickinraw <= '0'; | |
428 | swni.timein <= (OTHERS => '0'); |
|
429 | swni.timein <= (OTHERS => '0'); | |
429 | swni.dcrstval <= (OTHERS => '0'); |
|
430 | swni.dcrstval <= (OTHERS => '0'); | |
430 | swni.timerrstval <= (OTHERS => '0'); |
|
431 | swni.timerrstval <= (OTHERS => '0'); | |
431 |
|
432 | |||
432 | ------------------------------------------------------------------------------- |
|
433 | ------------------------------------------------------------------------------- | |
433 | -- LFR ------------------------------------------------------------------------ |
|
434 | -- LFR ------------------------------------------------------------------------ | |
434 | ------------------------------------------------------------------------------- |
|
435 | ------------------------------------------------------------------------------- | |
435 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
436 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
436 |
|
437 | |||
437 | lpp_lfr_1 : lpp_lfr |
|
438 | lpp_lfr_1 : lpp_lfr | |
438 | GENERIC MAP ( |
|
439 | GENERIC MAP ( | |
439 | Mem_use => Mem_use, |
|
440 | Mem_use => Mem_use, | |
440 | tech => tech, |
|
441 | tech => tech, | |
441 | nb_data_by_buffer_size => 32, |
|
442 | nb_data_by_buffer_size => 32, | |
442 | --nb_word_by_buffer_size => 30, |
|
443 | --nb_word_by_buffer_size => 30, | |
443 | nb_snapshot_param_size => 32, |
|
444 | nb_snapshot_param_size => 32, | |
444 | delta_vector_size => 32, |
|
445 | delta_vector_size => 32, | |
445 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
446 | delta_vector_size_f0_2 => 7, -- log2(96) | |
446 | pindex => 15, |
|
447 | pindex => 15, | |
447 | paddr => 15, |
|
448 | paddr => 15, | |
448 | pmask => 16#fff#, |
|
449 | pmask => 16#fff#, | |
449 | pirq_ms => 6, |
|
450 | pirq_ms => 6, | |
450 | pirq_wfp => 14, |
|
451 | pirq_wfp => 14, | |
451 | hindex => 2, |
|
452 | hindex => 2, | |
452 |
top_lfr_version => X"0201 |
|
453 | top_lfr_version => X"020150", -- aa.bb.cc version | |
453 | -- AA : BOARD NUMBER |
|
454 | -- AA : BOARD NUMBER | |
454 | -- 0 => MINI_LFR |
|
455 | -- 0 => MINI_LFR | |
455 | -- 1 => EM |
|
456 | -- 1 => EM | |
456 | -- 2 => EQM (with A3PE3000) |
|
457 | -- 2 => EQM (with A3PE3000) | |
457 | DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) |
|
458 | DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA) | |
458 | PORT MAP ( |
|
459 | PORT MAP ( | |
459 | clk => clk_25, |
|
460 | clk => clk_25, | |
460 | rstn => LFR_rstn, |
|
461 | rstn => LFR_rstn, | |
461 | sample_B => sample_s(2 DOWNTO 0), |
|
462 | sample_B => sample_s(2 DOWNTO 0), | |
462 | sample_E => sample_s(7 DOWNTO 3), |
|
463 | sample_E => sample_s(7 DOWNTO 3), | |
463 | sample_val => sample_val, |
|
464 | sample_val => sample_val, | |
464 | apbi => apbi_ext, |
|
465 | apbi => apbi_ext, | |
465 | apbo => apbo_ext(15), |
|
466 | apbo => apbo_ext(15), | |
466 | ahbi => ahbi_m_ext, |
|
467 | ahbi => ahbi_m_ext, | |
467 | ahbo => ahbo_m_ext(2), |
|
468 | ahbo => ahbo_m_ext(2), | |
468 | coarse_time => coarse_time, |
|
469 | coarse_time => coarse_time, | |
469 | fine_time => fine_time, |
|
470 | fine_time => fine_time, | |
470 | data_shaping_BW => bias_fail_sw, |
|
471 | data_shaping_BW => bias_fail_sw, | |
471 | debug_vector => debug_vector, |
|
472 | debug_vector => debug_vector, | |
472 | debug_vector_ms => OPEN); --, |
|
473 | debug_vector_ms => OPEN); --, | |
473 | --observation_vector_0 => OPEN, |
|
474 | --observation_vector_0 => OPEN, | |
474 | --observation_vector_1 => OPEN, |
|
475 | --observation_vector_1 => OPEN, | |
475 | --observation_reg => observation_reg); |
|
476 | --observation_reg => observation_reg); | |
476 |
|
477 | |||
477 |
|
478 | |||
478 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
479 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
479 | sample_s(I) <= sample(I) & '0' & '0'; |
|
480 | sample_s(I) <= sample(I) & '0' & '0'; | |
480 | END GENERATE all_sample; |
|
481 | END GENERATE all_sample; | |
481 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); |
|
482 | sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8); | |
482 |
|
483 | |||
483 | ----------------------------------------------------------------------------- |
|
484 | ----------------------------------------------------------------------------- | |
484 | -- |
|
485 | -- | |
485 | ----------------------------------------------------------------------------- |
|
486 | ----------------------------------------------------------------------------- | |
486 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE |
|
487 | USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE | |
487 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
488 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
488 | GENERIC MAP ( |
|
489 | GENERIC MAP ( | |
489 | ChanelCount => 9, |
|
490 | ChanelCount => 9, | |
490 |
ncycle_cnv_high => |
|
491 | ncycle_cnv_high => 50, | |
491 |
ncycle_cnv => |
|
492 | ncycle_cnv => 100, | |
492 | FILTER_ENABLED => 16#FF#) |
|
493 | FILTER_ENABLED => 16#FF#) | |
493 | PORT MAP ( |
|
494 | PORT MAP ( | |
494 |
cnv_clk => clk_ |
|
495 | cnv_clk => clk_49, | |
495 |
cnv_rstn => rstn_ |
|
496 | cnv_rstn => rstn_49, | |
496 | cnv => ADC_smpclk_s, |
|
497 | cnv => ADC_smpclk_s, | |
497 | clk => clk_25, |
|
498 | clk => clk_25, | |
498 | rstn => rstn_25, |
|
499 | rstn => rstn_25, | |
499 | ADC_data => ADC_data, |
|
500 | ADC_data => ADC_data, | |
500 | ADC_nOE => ADC_OEB_bar_CH_s, |
|
501 | ADC_nOE => ADC_OEB_bar_CH_s, | |
501 | sample => sample, |
|
502 | sample => sample, | |
502 | sample_val => sample_val); |
|
503 | sample_val => sample_val); | |
503 |
|
504 | |||
504 | END GENERATE USE_ADCDRIVER_true; |
|
505 | END GENERATE USE_ADCDRIVER_true; | |
505 |
|
506 | |||
506 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE |
|
507 | USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE | |
507 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter |
|
508 | top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter | |
508 | GENERIC MAP ( |
|
509 | GENERIC MAP ( | |
509 | ChanelCount => 9, |
|
510 | ChanelCount => 9, | |
510 |
ncycle_cnv_high => |
|
511 | ncycle_cnv_high => 25, | |
511 |
ncycle_cnv => |
|
512 | ncycle_cnv => 50, | |
512 | FILTER_ENABLED => 16#FF#) |
|
513 | FILTER_ENABLED => 16#FF#) | |
513 | PORT MAP ( |
|
514 | PORT MAP ( | |
514 |
cnv_clk => clk_ |
|
515 | cnv_clk => clk_49, | |
515 |
cnv_rstn => rstn_ |
|
516 | cnv_rstn => rstn_49, | |
516 | cnv => ADC_smpclk_s, |
|
517 | cnv => ADC_smpclk_s, | |
517 | clk => clk_25, |
|
518 | clk => clk_25, | |
518 | rstn => rstn_25, |
|
519 | rstn => rstn_25, | |
519 | ADC_data => ADC_data, |
|
520 | ADC_data => ADC_data, | |
520 | ADC_nOE => OPEN, |
|
521 | ADC_nOE => OPEN, | |
521 | sample => OPEN, |
|
522 | sample => OPEN, | |
522 | sample_val => sample_val); |
|
523 | sample_val => sample_val); | |
523 |
|
524 | |||
524 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); |
|
525 | ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1'); | |
525 |
|
526 | |||
526 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE |
|
527 | all_sample: FOR I IN 8 DOWNTO 0 GENERATE | |
527 | ramp_generator_1: ramp_generator |
|
528 | ramp_generator_1: ramp_generator | |
528 | GENERIC MAP ( |
|
529 | GENERIC MAP ( | |
529 | DATA_SIZE => 14, |
|
530 | DATA_SIZE => 14, | |
530 | VALUE_UNSIGNED_INIT => 2**I, |
|
531 | VALUE_UNSIGNED_INIT => 2**I, | |
531 | VALUE_UNSIGNED_INCR => 0, |
|
532 | VALUE_UNSIGNED_INCR => 0, | |
532 | VALUE_UNSIGNED_MASK => 16#3FFF#) |
|
533 | VALUE_UNSIGNED_MASK => 16#3FFF#) | |
533 | PORT MAP ( |
|
534 | PORT MAP ( | |
534 | clk => clk_25, |
|
535 | clk => clk_25, | |
535 | rstn => rstn_25, |
|
536 | rstn => rstn_25, | |
536 | new_data => sample_val, |
|
537 | new_data => sample_val, | |
537 | output_data => sample(I) ); |
|
538 | output_data => sample(I) ); | |
538 | END GENERATE all_sample; |
|
539 | END GENERATE all_sample; | |
539 |
|
540 | |||
540 |
|
541 | |||
541 | END GENERATE USE_ADCDRIVER_false; |
|
542 | END GENERATE USE_ADCDRIVER_false; | |
542 |
|
543 | |||
543 |
|
544 | |||
544 |
|
545 | |||
545 |
|
546 | |||
546 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); |
|
547 | ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0); | |
547 |
|
548 | |||
548 | ADC_smpclk <= ADC_smpclk_s; |
|
549 | ADC_smpclk <= ADC_smpclk_s; | |
549 | HK_smpclk <= ADC_smpclk_s; |
|
550 | HK_smpclk <= ADC_smpclk_s; | |
550 |
|
551 | |||
551 |
|
552 | |||
552 | ----------------------------------------------------------------------------- |
|
553 | ----------------------------------------------------------------------------- | |
553 | -- HK |
|
554 | -- HK | |
554 | ----------------------------------------------------------------------------- |
|
555 | ----------------------------------------------------------------------------- | |
555 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); |
|
556 | ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8); | |
556 |
|
557 | |||
557 | ----------------------------------------------------------------------------- |
|
558 | ----------------------------------------------------------------------------- | |
558 | -- |
|
559 | -- | |
559 | ----------------------------------------------------------------------------- |
|
560 | ----------------------------------------------------------------------------- | |
560 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE |
|
561 | inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE | |
561 | lpp_bootloader_1: lpp_bootloader |
|
562 | lpp_bootloader_1: lpp_bootloader | |
562 | GENERIC MAP ( |
|
563 | GENERIC MAP ( | |
563 | pindex => 13, |
|
564 | pindex => 13, | |
564 | paddr => 13, |
|
565 | paddr => 13, | |
565 | pmask => 16#fff#, |
|
566 | pmask => 16#fff#, | |
566 | hindex => 3, |
|
567 | hindex => 3, | |
567 | haddr => 0, |
|
568 | haddr => 0, | |
568 | hmask => 16#fff#) |
|
569 | hmask => 16#fff#) | |
569 | PORT MAP ( |
|
570 | PORT MAP ( | |
570 | HCLK => clk_25, |
|
571 | HCLK => clk_25, | |
571 | HRESETn => rstn_25, |
|
572 | HRESETn => rstn_25, | |
572 | apbi => apbi_ext, |
|
573 | apbi => apbi_ext, | |
573 | apbo => apbo_ext(13), |
|
574 | apbo => apbo_ext(13), | |
574 | ahbsi => ahbi_s_ext, |
|
575 | ahbsi => ahbi_s_ext, | |
575 | ahbso => ahbo_s_ext(3)); |
|
576 | ahbso => ahbo_s_ext(3)); | |
576 | END GENERATE inst_bootloader; |
|
577 | END GENERATE inst_bootloader; | |
577 |
|
578 | |||
578 | ----------------------------------------------------------------------------- |
|
579 | ----------------------------------------------------------------------------- | |
579 | -- |
|
580 | -- | |
580 | ----------------------------------------------------------------------------- |
|
581 | ----------------------------------------------------------------------------- | |
581 | USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE |
|
582 | USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE | |
582 | PROCESS (clk_25, rstn_25) |
|
583 | PROCESS (clk_25, rstn_25) | |
583 | BEGIN -- PROCESS |
|
584 | BEGIN -- PROCESS | |
584 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
585 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
585 | TAG <= (OTHERS => '0'); |
|
586 | TAG <= (OTHERS => '0'); | |
586 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
587 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
587 | TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); |
|
588 | TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0); | |
588 | END IF; |
|
589 | END IF; | |
589 | END PROCESS; |
|
590 | END PROCESS; | |
590 |
|
591 | |||
591 |
|
592 | |||
592 | END GENERATE USE_DEBUG_VECTOR_IF; |
|
593 | END GENERATE USE_DEBUG_VECTOR_IF; | |
593 |
|
594 | |||
594 | USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE |
|
595 | USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE | |
595 | ahbrxd <= TAG(1); |
|
596 | ahbrxd <= TAG(1); | |
596 | TAG(3) <= ahbtxd; |
|
597 | TAG(3) <= ahbtxd; | |
597 | urxd1 <= TAG(2); |
|
598 | urxd1 <= TAG(2); | |
598 | TAG(4) <= utxd1; |
|
599 | TAG(4) <= utxd1; | |
599 | TAG(8) <= nSRAM_BUSY; |
|
600 | TAG(8) <= nSRAM_BUSY; | |
600 | END GENERATE USE_DEBUG_VECTOR_IF2; |
|
601 | END GENERATE USE_DEBUG_VECTOR_IF2; | |
601 |
|
602 | |||
602 | END beh; |
|
603 | END beh; |
@@ -1,54 +1,54 | |||||
1 | #GRLIB=../.. |
|
1 | #GRLIB=../.. | |
2 | VHDLIB=../.. |
|
2 | VHDLIB=../.. | |
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | SCRIPTSDIR=$(VHDLIB)/scripts/ | |
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) | |
5 | TOP=LFR_EQM |
|
5 | TOP=LFR_EQM | |
6 | BOARD=LFR-EQM |
|
6 | BOARD=LFR-EQM | |
7 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc |
|
7 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc | |
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) | |
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf |
|
9 | UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf | |
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf |
|
10 | QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf | |
11 | EFFORT=high |
|
11 | EFFORT=high | |
12 | XSTOPT= |
|
12 | XSTOPT= | |
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" | |
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd |
|
14 | #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd | |
15 | #VHDLSYNFILES=config.vhd leon3mp.vhd |
|
15 | #VHDLSYNFILES=config.vhd leon3mp.vhd | |
16 | VHDLSYNFILES=LFR-EQM.vhd |
|
16 | VHDLSYNFILES=LFR-EQM.vhd | |
17 | VHDLSIMFILES=testbench.vhd |
|
17 | VHDLSIMFILES=testbench.vhd | |
18 | #SIMTOP=testbench |
|
18 | #SIMTOP=testbench | |
19 |
PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000 |
|
19 | PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc | |
20 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc |
|
20 | #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc | |
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc |
|
21 | SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc | |
22 |
|
22 | |||
23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
23 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut | |
24 | CLEAN=soft-clean |
|
24 | CLEAN=soft-clean | |
25 |
|
25 | |||
26 | TECHLIBS = proasic3e |
|
26 | TECHLIBS = proasic3e | |
27 |
|
27 | |||
28 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
28 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ | |
29 | tmtc openchip hynix ihp gleichmann micron usbhc |
|
29 | tmtc openchip hynix ihp gleichmann micron usbhc | |
30 |
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30 | |||
31 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
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31 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ | |
32 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
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32 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ | |
33 | ./amba_lcd_16x2_ctrlr \ |
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33 | ./amba_lcd_16x2_ctrlr \ | |
34 | ./general_purpose/lpp_AMR \ |
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34 | ./general_purpose/lpp_AMR \ | |
35 | ./general_purpose/lpp_balise \ |
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35 | ./general_purpose/lpp_balise \ | |
36 | ./general_purpose/lpp_delay \ |
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36 | ./general_purpose/lpp_delay \ | |
37 | ./dsp/lpp_fft_rtax \ |
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37 | ./dsp/lpp_fft_rtax \ | |
38 | ./lpp_uart \ |
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38 | ./lpp_uart \ | |
39 | ./lpp_usb \ |
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39 | ./lpp_usb \ | |
40 | ./lpp_sim/CY7C1061DV33 \ |
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40 | ./lpp_sim/CY7C1061DV33 \ | |
41 |
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41 | |||
42 | FILESKIP = i2cmst.vhd \ |
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42 | FILESKIP = i2cmst.vhd \ | |
43 | APB_MULTI_DIODE.vhd \ |
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43 | APB_MULTI_DIODE.vhd \ | |
44 | APB_MULTI_DIODE.vhd \ |
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44 | APB_MULTI_DIODE.vhd \ | |
45 | Top_MatrixSpec.vhd \ |
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45 | Top_MatrixSpec.vhd \ | |
46 | APB_FFT.vhd\ |
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46 | APB_FFT.vhd\ | |
47 | CoreFFT_simu.vhd \ |
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47 | CoreFFT_simu.vhd \ | |
48 | lpp_lfr_apbreg_simu.vhd |
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48 | lpp_lfr_apbreg_simu.vhd | |
49 |
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49 | |||
50 | include $(GRLIB)/bin/Makefile |
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50 | include $(GRLIB)/bin/Makefile | |
51 | include $(GRLIB)/software/leon3/Makefile |
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51 | include $(GRLIB)/software/leon3/Makefile | |
52 |
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52 | |||
53 | ################## project specific targets ########################## |
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53 | ################## project specific targets ########################## | |
54 |
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54 |
@@ -1,125 +1,146 | |||||
1 | onerror {resume} |
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1 | onerror {resume} | |
2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc |
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2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc | |
3 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA |
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3 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA | |
4 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA |
|
4 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA | |
5 | quietly WaveActivateNextPane {} 0 |
|
5 | quietly WaveActivateNextPane {} 0 | |
6 | add wave -noupdate -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1) |
|
6 | add wave -noupdate -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1) | |
7 | add wave -noupdate -height 74 -max 326.0 -min 256.0 /tb/sample_counter |
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7 | add wave -noupdate -height 74 -max 326.0 -min 256.0 /tb/sample_counter | |
8 |
add wave -noupdate |
|
8 | add wave -noupdate -group ALL /tb/data_message | |
9 |
add wave -noupdate |
|
9 | add wave -noupdate -group ALL /tb/message_simu | |
10 |
add wave -noupdate |
|
10 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 | |
11 |
add wave -noupdate |
|
11 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 | |
12 |
add wave -noupdate |
|
12 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G | |
13 |
add wave -noupdate |
|
13 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W | |
14 |
add wave -noupdate |
|
14 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data | |
15 |
add wave -noupdate - |
|
15 | add wave -noupdate -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc | |
16 |
add wave -noupdate - |
|
16 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address | |
17 |
add wave -noupdate |
|
17 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
18 |
add wave -noupdate |
|
18 | add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE | |
19 |
add wave -noupdate - |
|
19 | add wave -noupdate -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data | |
20 |
add wave -noupdate |
|
20 | add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk | |
21 |
add wave -noupdate |
|
21 | add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH | |
22 |
add wave -noupdate |
|
22 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |
23 |
add wave -noupdate |
|
23 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |
24 |
add wave -noupdate |
|
24 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |
25 |
add wave -noupdate |
|
25 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |
26 |
add wave -noupdate |
|
26 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |
27 |
add wave -noupdate |
|
27 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |
28 |
add wave -noupdate |
|
28 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |
29 |
add wave -noupdate |
|
29 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |
30 |
add wave -noupdate |
|
30 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |
31 |
add wave -noupdate |
|
31 | add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |
32 |
add wave -noupdate |
|
32 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
33 |
add wave -noupdate |
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33 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
34 |
add wave -noupdate |
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34 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
35 |
add wave -noupdate |
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35 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
36 |
add wave -noupdate |
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36 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
37 |
add wave -noupdate |
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37 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
38 |
add wave -noupdate |
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38 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
39 |
add wave -noupdate |
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39 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
40 |
add wave -noupdate |
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40 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
41 |
add wave -noupdate |
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41 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
42 |
add wave -noupdate |
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42 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
43 |
add wave -noupdate |
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43 | add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
44 |
add wave -noupdate - |
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44 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
45 |
add wave -noupdate |
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45 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
46 |
add wave -noupdate |
|
46 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk | |
47 |
add wave -noupdate |
|
47 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
48 |
add wave -noupdate |
|
48 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid | |
49 |
add wave -noupdate |
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49 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex | |
50 |
add wave -noupdate |
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50 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn | |
51 |
add wave -noupdate |
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51 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
52 |
add wave -noupdate |
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52 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
53 |
add wave -noupdate |
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53 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid | |
54 |
add wave -noupdate |
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54 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version | |
55 |
add wave -noupdate |
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55 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
56 |
add wave -noupdate |
|
56 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
57 |
add wave -noupdate |
|
57 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
58 |
add wave -noupdate |
|
58 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
59 |
add wave -noupdate |
|
59 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |
60 |
add wave -noupdate |
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60 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
61 |
add wave -noupdate |
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61 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
62 |
add wave -noupdate |
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62 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
63 |
add wave -noupdate |
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63 | add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
64 |
add wave -noupdate |
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64 | add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
65 |
add wave -noupdate |
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65 | add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
66 |
add wave -noupdate |
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66 | add wave -noupdate -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |
67 |
add wave -noupdate |
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67 | add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1 | |
68 |
add wave -noupdate |
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68 | add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2 | |
69 |
add wave -noupdate |
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69 | add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0 | |
70 |
add wave -noupdate |
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70 | add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1 | |
71 |
add wave -noupdate |
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71 | add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2 | |
72 |
add wave -noupdate |
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72 | add wave -noupdate -group ALL /tb/error_wfp | |
73 |
add wave -noupdate |
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73 | add wave -noupdate -group ALL /tb/error_wfp_addr | |
74 |
add wave -noupdate |
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74 | add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a | |
75 |
add wave -noupdate |
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75 | add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 | |
76 |
add wave -noupdate |
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76 | add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe | |
77 |
add wave -noupdate |
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77 | add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we | |
78 |
add wave -noupdate |
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78 | add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a | |
79 |
add wave -noupdate |
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79 | add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 | |
80 |
add wave -noupdate |
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80 | add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe | |
81 |
add wave -noupdate |
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81 | add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we | |
82 |
add wave -noupdate |
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82 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi | |
83 |
add wave -noupdate |
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83 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo | |
84 |
add wave -noupdate |
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84 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi | |
85 |
add wave -noupdate |
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85 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso | |
86 |
add wave -noupdate - |
|
86 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi | |
87 |
add wave -noupdate - |
|
87 | add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo | |
88 |
add wave -noupdate |
|
88 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |
89 |
add wave -noupdate |
|
89 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |
90 |
add wave -noupdate |
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90 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |
91 |
add wave -noupdate |
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91 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |
92 |
add wave -noupdate |
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92 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |
93 |
add wave -noupdate |
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93 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |
94 |
add wave -noupdate |
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94 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
95 |
add wave -noupdate |
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95 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |
96 |
add wave -noupdate |
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96 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |
97 |
add wave -noupdate |
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97 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |
98 |
add wave -noupdate |
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98 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |
99 |
add wave -noupdate |
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99 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |
100 |
add wave -noupdate |
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100 | add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |
101 |
add wave -noupdate |
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101 | add wave -noupdate /tb/LFR_EQM_1/debug_vector | |
102 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state |
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102 | add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |
103 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/HWDATA |
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103 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/HWDATA | |
104 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY |
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104 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |
105 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/DMA_DATA |
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105 | add wave -noupdate -radix unsigned /tb/LFR_EQM_1/DMA_DATA | |
106 | add wave -noupdate -label DMA_REN /tb/LFR_EQM_1/debug_vector(8) |
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106 | add wave -noupdate -label DMA_REN /tb/LFR_EQM_1/debug_vector(8) | |
107 | add wave -noupdate -label HREADY /tb/LFR_EQM_1/debug_vector(5) |
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107 | add wave -noupdate -label HREADY /tb/LFR_EQM_1/debug_vector(5) | |
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108 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk | |||
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109 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn | |||
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110 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn | |||
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111 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk | |||
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112 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data | |||
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113 | add wave -noupdate -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE | |||
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114 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv | |||
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115 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample | |||
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116 | add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val | |||
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117 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high | |||
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118 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv | |||
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119 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current | |||
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120 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled | |||
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121 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result | |||
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122 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled | |||
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123 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid | |||
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124 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data | |||
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125 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg | |||
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126 | add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected | |||
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127 | add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg | |||
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128 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample | |||
108 | TreeUpdate [SetDefaultTree] |
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129 | TreeUpdate [SetDefaultTree] | |
109 |
WaveRestoreCursors {{Cursor 1} {1 |
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130 | WaveRestoreCursors {{Cursor 1} {12871601883 ps} 0} {{Cursor 2} {32570000 ps} 0} {{Cursor 3} {14130170000 ps} 0} | |
110 | quietly wave cursor active 2 |
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131 | quietly wave cursor active 2 | |
111 |
configure wave -namecolwidth 5 |
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132 | configure wave -namecolwidth 571 | |
112 | configure wave -valuecolwidth 347 |
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133 | configure wave -valuecolwidth 347 | |
113 | configure wave -justifyvalue left |
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134 | configure wave -justifyvalue left | |
114 | configure wave -signalnamewidth 0 |
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135 | configure wave -signalnamewidth 0 | |
115 | configure wave -snapdistance 10 |
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136 | configure wave -snapdistance 10 | |
116 | configure wave -datasetprefix 0 |
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137 | configure wave -datasetprefix 0 | |
117 | configure wave -rowmargin 4 |
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138 | configure wave -rowmargin 4 | |
118 | configure wave -childrowmargin 2 |
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139 | configure wave -childrowmargin 2 | |
119 | configure wave -gridoffset 0 |
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140 | configure wave -gridoffset 0 | |
120 | configure wave -gridperiod 1 |
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141 | configure wave -gridperiod 1 | |
121 | configure wave -griddelta 40 |
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142 | configure wave -griddelta 40 | |
122 | configure wave -timeline 0 |
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143 | configure wave -timeline 0 | |
123 | configure wave -timelineunits ns |
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144 | configure wave -timelineunits ns | |
124 | update |
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145 | update | |
125 |
WaveRestoreZoom { |
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146 | WaveRestoreZoom {32208206 ps} {33843459 ps} |
@@ -1,228 +1,248 | |||||
1 |
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1 | |||
2 | LIBRARY IEEE; |
|
2 | LIBRARY IEEE; | |
3 | USE IEEE.STD_LOGIC_1164.ALL; |
|
3 | USE IEEE.STD_LOGIC_1164.ALL; | |
4 | USE IEEE.numeric_std.ALL; |
|
4 | USE IEEE.numeric_std.ALL; | |
5 | LIBRARY lpp; |
|
5 | LIBRARY lpp; | |
6 | USE lpp.lpp_ad_conv.ALL; |
|
6 | USE lpp.lpp_ad_conv.ALL; | |
7 | USE lpp.general_purpose.SYNC_FF; |
|
7 | USE lpp.general_purpose.SYNC_FF; | |
8 |
|
8 | |||
9 | ENTITY top_ad_conv_RHF1401_withFilter IS |
|
9 | ENTITY top_ad_conv_RHF1401_withFilter IS | |
10 | GENERIC( |
|
10 | GENERIC( | |
11 | ChanelCount : INTEGER := 8; |
|
11 | ChanelCount : INTEGER := 8; | |
12 |
ncycle_cnv_high : INTEGER := |
|
12 | ncycle_cnv_high : INTEGER := 25; | |
13 |
ncycle_cnv : INTEGER := |
|
13 | ncycle_cnv : INTEGER := 50; | |
14 | FILTER_ENABLED : INTEGER := 16#FF# |
|
14 | FILTER_ENABLED : INTEGER := 16#FF# | |
15 | ); |
|
15 | ); | |
16 | PORT ( |
|
16 | PORT ( | |
17 | cnv_clk : IN STD_LOGIC; -- 24Mhz |
|
17 | cnv_clk : IN STD_LOGIC; -- 24Mhz | |
18 | cnv_rstn : IN STD_LOGIC; |
|
18 | cnv_rstn : IN STD_LOGIC; | |
19 |
|
19 | |||
20 | cnv : OUT STD_LOGIC; |
|
20 | cnv : OUT STD_LOGIC; | |
21 |
|
21 | |||
22 | clk : IN STD_LOGIC; -- 25MHz |
|
22 | clk : IN STD_LOGIC; -- 25MHz | |
23 | rstn : IN STD_LOGIC; |
|
23 | rstn : IN STD_LOGIC; | |
24 | ADC_data : IN Samples14; |
|
24 | ADC_data : IN Samples14; | |
25 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
25 | ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
26 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); |
|
26 | sample : OUT Samples14v(ChanelCount-1 DOWNTO 0); | |
27 | sample_val : OUT STD_LOGIC |
|
27 | sample_val : OUT STD_LOGIC | |
28 | ); |
|
28 | ); | |
29 | END top_ad_conv_RHF1401_withFilter; |
|
29 | END top_ad_conv_RHF1401_withFilter; | |
30 |
|
30 | |||
31 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS |
|
31 | ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS | |
32 |
|
32 | |||
33 | SIGNAL cnv_cycle_counter : INTEGER; |
|
33 | SIGNAL cnv_cycle_counter : INTEGER; | |
34 | SIGNAL cnv_s : STD_LOGIC; |
|
34 | SIGNAL cnv_s : STD_LOGIC; | |
35 | SIGNAL cnv_s_reg : STD_LOGIC; |
|
35 | SIGNAL cnv_s_reg : STD_LOGIC; | |
36 | SIGNAL cnv_sync : STD_LOGIC; |
|
36 | SIGNAL cnv_sync : STD_LOGIC; | |
37 |
SIGNAL cnv_sync_ |
|
37 | SIGNAL cnv_sync_reg : STD_LOGIC; | |
|
38 | SIGNAL cnv_sync_rising : STD_LOGIC; | |||
38 |
|
39 | |||
39 | SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); |
|
40 | SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); | |
40 | SIGNAL enable_ADC : STD_LOGIC; |
|
41 | SIGNAL enable_ADC : STD_LOGIC; | |
41 |
|
42 | |||
42 |
|
43 | |||
43 | SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); |
|
44 | SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0); | |
44 |
|
45 | |||
45 | SIGNAL channel_counter : INTEGER; |
|
46 | SIGNAL channel_counter : INTEGER; | |
46 | CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; |
|
47 | CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1; | |
47 |
|
48 | |||
48 | SIGNAL ADC_data_selected : Samples14; |
|
49 | SIGNAL ADC_data_selected : Samples14; | |
49 | SIGNAL ADC_data_result : Samples15; |
|
50 | SIGNAL ADC_data_result : Samples15; | |
50 |
|
51 | |||
51 | SIGNAL sample_counter : INTEGER; |
|
52 | SIGNAL sample_counter : INTEGER; | |
52 | CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; |
|
53 | CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9; | |
53 |
|
54 | |||
54 | CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount)); |
|
55 | CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount)); | |
|
56 | ||||
|
57 | ----------------------------------------------------------------------------- | |||
|
58 | CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 2; | |||
|
59 | CONSTANT DATA_CYCLE_VALID : INTEGER := 3; | |||
55 |
|
60 | |||
|
61 | -- GEN OutPut Enable | |||
|
62 | TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE); | |||
|
63 | SIGNAL state_GEN_OEn : FSM_GEN_OEn_state; | |||
|
64 | SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1; | |||
|
65 | SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1; | |||
|
66 | SIGNAL ADC_data_valid : STD_LOGIC; | |||
|
67 | SIGNAL ADC_data_reg : Samples14; | |||
|
68 | ----------------------------------------------------------------------------- | |||
|
69 | CONSTANT SAMPLE_DIVISION : INTEGER := 2; | |||
|
70 | SIGNAL sample_val_s : STD_LOGIC; | |||
|
71 | SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION; | |||
56 | BEGIN |
|
72 | BEGIN | |
57 |
|
73 | |||
58 |
|
74 | |||
59 | ----------------------------------------------------------------------------- |
|
75 | ----------------------------------------------------------------------------- | |
60 | -- CNV GEN |
|
76 | -- CNV GEN | |
61 | ----------------------------------------------------------------------------- |
|
77 | ----------------------------------------------------------------------------- | |
62 | PROCESS (cnv_clk, cnv_rstn) |
|
78 | PROCESS (cnv_clk, cnv_rstn) | |
63 | BEGIN -- PROCESS |
|
79 | BEGIN -- PROCESS | |
64 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
80 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
65 | cnv_cycle_counter <= 0; |
|
81 | cnv_cycle_counter <= 0; | |
66 | cnv_s <= '0'; |
|
82 | cnv_s <= '0'; | |
67 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
83 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
68 | IF cnv_cycle_counter < ncycle_cnv-1 THEN |
|
84 | IF cnv_cycle_counter < ncycle_cnv-1 THEN | |
69 | cnv_cycle_counter <= cnv_cycle_counter + 1; |
|
85 | cnv_cycle_counter <= cnv_cycle_counter + 1; | |
70 | IF cnv_cycle_counter < ncycle_cnv_high THEN |
|
86 | IF cnv_cycle_counter < ncycle_cnv_high-1 THEN | |
71 | cnv_s <= '1'; |
|
87 | cnv_s <= '1'; | |
72 | ELSE |
|
88 | ELSE | |
73 | cnv_s <= '0'; |
|
89 | cnv_s <= '0'; | |
74 | END IF; |
|
90 | END IF; | |
75 | ELSE |
|
91 | ELSE | |
76 | cnv_s <= '1'; |
|
92 | cnv_s <= '1'; | |
77 | cnv_cycle_counter <= 0; |
|
93 | cnv_cycle_counter <= 0; | |
78 | END IF; |
|
94 | END IF; | |
79 | END IF; |
|
95 | END IF; | |
80 | END PROCESS; |
|
96 | END PROCESS; | |
81 |
|
97 | |||
82 | cnv <= cnv_s; |
|
98 | cnv <= cnv_s; | |
83 |
|
99 | |||
84 | PROCESS (cnv_clk, cnv_rstn) |
|
100 | PROCESS (cnv_clk, cnv_rstn) | |
85 | BEGIN -- PROCESS |
|
101 | BEGIN -- PROCESS | |
86 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
102 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) | |
87 | cnv_s_reg <= '0'; |
|
103 | cnv_s_reg <= '0'; | |
88 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
104 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge | |
89 | cnv_s_reg <= cnv_s; |
|
105 | cnv_s_reg <= cnv_s; | |
90 | END IF; |
|
106 | END IF; | |
91 | END PROCESS; |
|
107 | END PROCESS; | |
92 |
|
108 | |||
93 |
|
109 | |||
94 | ----------------------------------------------------------------------------- |
|
110 | ----------------------------------------------------------------------------- | |
95 | -- SYNC CNV |
|
111 | -- SYNC CNV | |
96 | ----------------------------------------------------------------------------- |
|
112 | ----------------------------------------------------------------------------- | |
97 |
|
113 | |||
98 | SYNC_FF_cnv : SYNC_FF |
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114 | SYNC_FF_cnv : SYNC_FF | |
99 | GENERIC MAP ( |
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115 | GENERIC MAP ( | |
100 | NB_FF_OF_SYNC => 2) |
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116 | NB_FF_OF_SYNC => 2) | |
101 | PORT MAP ( |
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117 | PORT MAP ( | |
102 | clk => clk, |
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118 | clk => clk, | |
103 | rstn => rstn, |
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119 | rstn => rstn, | |
104 | A => cnv_s_reg, |
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120 | A => cnv_s_reg, | |
105 | A_sync => cnv_sync); |
|
121 | A_sync => cnv_sync); | |
106 |
|
122 | |||
107 |
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||||
108 | ----------------------------------------------------------------------------- |
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123 | ----------------------------------------------------------------------------- | |
109 | -- DATA GEN Output Enable |
|
124 | -- | |
110 | ----------------------------------------------------------------------------- |
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|||
111 | PROCESS (clk, rstn) |
|
|||
112 | BEGIN -- PROCESS |
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|||
113 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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|||
114 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1'); |
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115 | cnv_sync_pre <= '0'; |
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|||
116 | enable_ADC <= '0'; |
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|||
117 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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|||
118 | cnv_sync_pre <= cnv_sync; |
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|||
119 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN |
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|||
120 | enable_ADC <= '1'; |
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121 | ADC_nOE_reg(0) <= '0'; |
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122 | ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1'); |
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|||
123 | ELSE |
|
|||
124 | enable_ADC <= NOT enable_ADC; |
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|||
125 | IF enable_ADC = '0' THEN |
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|||
126 | ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1'; |
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|||
127 | END IF; |
|
|||
128 | END IF; |
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129 |
|
||||
130 | END IF; |
|
|||
131 | END PROCESS; |
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132 |
|
||||
133 | ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg; |
|
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134 |
|
||||
135 | ----------------------------------------------------------------------------- |
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136 | -- ADC READ DATA |
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137 | ----------------------------------------------------------------------------- |
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125 | ----------------------------------------------------------------------------- | |
138 | PROCESS (clk, rstn) |
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126 | PROCESS (clk, rstn) | |
139 | BEGIN -- PROCESS |
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127 | BEGIN -- PROCESS | |
140 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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128 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
141 | channel_counter <= MAX_COUNTER; |
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129 | cnv_sync_reg <= '0'; | |
142 |
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130 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | ||
143 | all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
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131 | cnv_sync_reg <= cnv_sync; | |
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132 | END IF; | |||
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133 | END PROCESS; | |||
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134 | ||||
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135 | cnv_sync_rising <= '1' WHEN cnv_sync = '1' AND cnv_sync_reg = '0' ELSE '0'; | |||
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136 | ||||
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137 | ----------------------------------------------------------------------------- | |||
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138 | -- GEN OutPut Enable | |||
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139 | ----------------------------------------------------------------------------- | |||
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140 | PROCESS (clk, rstn) | |||
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141 | BEGIN -- PROCESS | |||
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142 | IF rstn = '0' THEN | |||
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143 | ------------------------------------------------------------------------- | |||
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144 | ADC_nOE <= (OTHERS => '1'); | |||
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145 | ADC_current <= 0; | |||
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146 | ADC_current_cycle_enabled <= 0; | |||
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147 | state_GEN_OEn <= IDLE; | |||
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148 | ------------------------------------------------------------------------- | |||
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149 | ADC_data_reg <= (OTHERS => '0'); | |||
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150 | all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP | |||
144 | sample_reg(I) <= (OTHERS => '0'); |
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151 | sample_reg(I) <= (OTHERS => '0'); | |
145 | END LOOP all_sample_reg_init; |
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152 | END LOOP all_channel_sample_reg_init; | |
146 |
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147 | sample_val <= '0'; |
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148 | sample_counter <= 0; |
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149 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
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150 | IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN |
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151 | channel_counter <= 0; |
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152 | ELSE |
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153 | IF channel_counter < MAX_COUNTER THEN |
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154 | channel_counter <= channel_counter + 1; |
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155 | END IF; |
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156 | END IF; |
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157 | sample_val <= '0'; |
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153 | sample_val <= '0'; | |
158 |
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154 | sample_val_s <= '0'; | ||
159 | all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP |
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155 | sample_val_counter <= 0; | |
160 | IF channel_counter = I*2 THEN |
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156 | ------------------------------------------------------------------------- | |
161 | IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN |
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157 | ELSIF clk'event AND clk = '1' THEN | |
162 | sample_reg(I) <= ADC_data_result(14 DOWNTO 1); |
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158 | ------------------------------------------------------------------------- | |
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159 | sample_val_s <= '0'; | |||
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160 | ADC_nOE <= (OTHERS => '1'); | |||
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161 | CASE state_GEN_OEn IS | |||
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162 | WHEN IDLE => | |||
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163 | IF cnv_sync_rising = '1' THEN | |||
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164 | ADC_nOE(0) <= '0'; | |||
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165 | state_GEN_OEn <= GEN_OE; | |||
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166 | ADC_current <= 0; | |||
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167 | ADC_current_cycle_enabled <= 1; | |||
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168 | END IF; | |||
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169 | ||||
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170 | WHEN GEN_OE => | |||
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171 | ADC_nOE(ADC_current) <= '0'; | |||
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172 | ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1; | |||
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173 | IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN | |||
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174 | state_GEN_OEn <= WAIT_CYCLE; | |||
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175 | END IF; | |||
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176 | ||||
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177 | WHEN WAIT_CYCLE => | |||
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178 | ADC_current_cycle_enabled <= 0; | |||
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179 | IF ADC_current = ChanelCount-1 THEN | |||
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180 | state_GEN_OEn <= IDLE; | |||
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181 | sample_val_s <= '1'; | |||
163 | ELSE |
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182 | ELSE | |
164 |
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183 | ADC_current <= ADC_current + 1; | |
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184 | state_GEN_OEn <= GEN_OE; | |||
165 | END IF; |
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185 | END IF; | |
166 | END IF; |
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186 | WHEN OTHERS => NULL; | |
167 | END LOOP all_sample_reg; |
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187 | END CASE; | |
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188 | ------------------------------------------------------------------------- | |||
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189 | ADC_data_reg <= ADC_data; | |||
168 |
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190 | |||
169 | IF channel_counter = (ChanelCount-1)*2 THEN |
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191 | all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP | |
170 |
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192 | IF ADC_data_valid = '1' AND ADC_current = I THEN | ||
171 | IF sample_counter = MAX_SAMPLE_COUNTER THEN |
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193 | sample_reg(I) <= ADC_data_result(14 DOWNTO 1); | |
172 | sample_counter <= 0 ; |
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173 | sample_val <= '1'; |
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174 | ELSE |
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194 | ELSE | |
175 |
sample_ |
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195 | sample_reg(I) <= sample_reg(I); | |
176 | END IF; |
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196 | END IF; | |
177 |
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197 | END LOOP all_channel_sample_reg; | ||
178 | END IF; |
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198 | ------------------------------------------------------------------------- | |
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199 | sample_val <= '0'; | |||
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200 | IF sample_val_s = '1' THEN | |||
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201 | IF sample_val_counter = SAMPLE_DIVISION-1 THEN | |||
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202 | sample_val_counter <= 0; | |||
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203 | sample_val <= '1'; -- TODO | |||
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204 | ELSE | |||
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205 | sample_val_counter <= sample_val_counter + 1; | |||
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206 | sample_val <= '0'; | |||
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207 | END IF; | |||
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208 | END IF; | |||
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209 | ||||
179 | END IF; |
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210 | END IF; | |
180 | END PROCESS; |
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211 | END PROCESS; | |
181 |
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212 | |||
182 | -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg) |
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213 | ADC_data_valid <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID ELSE '0'; | |
183 | -- BEGIN -- PROCESS mux_adc |
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184 | -- CASE channel_counter IS |
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185 | -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2); |
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186 | -- END CASE; |
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187 | -- END PROCESS mux_adc; |
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188 |
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214 | |||
189 |
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215 | WITH ADC_current SELECT | ||
190 | ----------------------------------------------------------------------------- |
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216 | ADC_data_selected <= sample_reg(0) WHEN 0, | |
191 | -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/ |
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217 | sample_reg(1) WHEN 1, | |
192 | ----------------------------------------------------------------------------- |
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218 | sample_reg(2) WHEN 2, | |
193 |
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219 | sample_reg(3) WHEN 3, | ||
194 | WITH channel_counter SELECT |
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220 | sample_reg(4) WHEN 4, | |
195 | ADC_data_selected <= sample_reg(0) WHEN 0*2, |
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221 | sample_reg(5) WHEN 5, | |
196 |
sample_reg( |
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222 | sample_reg(6) WHEN 6, | |
197 |
sample_reg( |
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223 | sample_reg(7) WHEN 7, | |
198 | sample_reg(3) WHEN 3*2, |
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199 | sample_reg(4) WHEN 4*2, |
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200 | sample_reg(5) WHEN 5*2, |
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201 | sample_reg(6) WHEN 6*2, |
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202 | sample_reg(7) WHEN 7*2, |
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203 | sample_reg(8) WHEN OTHERS ; |
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224 | sample_reg(8) WHEN OTHERS ; | |
204 |
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225 | |||
205 | ----------------------------------------------------------------------------- |
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226 | ADC_data_result <= std_logic_vector(( | |
206 | -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\ |
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227 | signed( ADC_data_selected(13) & ADC_data_selected) + | |
207 | ----------------------------------------------------------------------------- |
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228 | signed( ADC_data_reg(13) & ADC_data_reg) | |
|
229 | )); | |||
208 |
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230 | |||
209 | ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) ); |
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210 |
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211 |
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231 | sample <= sample_reg; | |
212 |
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232 | |||
213 | END ar_top_ad_conv_RHF1401; |
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233 | END ar_top_ad_conv_RHF1401; | |
214 |
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234 | |||
215 |
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235 | |||
216 |
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236 | |||
217 |
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237 | |||
218 |
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238 | |||
219 |
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239 | |||
220 |
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240 | |||
221 |
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241 | |||
222 |
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242 | |||
223 |
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243 | |||
224 |
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244 | |||
225 |
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245 | |||
226 |
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246 | |||
227 |
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247 | |||
228 |
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248 |
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