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1 | SOLO\_LFR\_MINI-LFR is the implementation of Solar Orbiter LFR analyser for the board MINI-LFR. | |
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2 | ||
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3 | You can find information about : | |
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4 | ||
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5 | - MINI-LFR board in the redmine here : | |
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6 | [Mini_LFR](https://hephaistos.lpp.polytechnique.fr/redmine/projects/mini-lfr/wiki) | |
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7 | - the bistream Generation : | |
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8 | [Bitstream_Generation](https://hephaistos.lpp.polytechnique.fr/redmine/projects/vhdlib/wiki/Mini_LFR_-_Bitstream_Generation) | |
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9 | ||
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10 |
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1 | NO CONTENT: file renamed from boards/MINI-LFR/MINI-LFR.sdc to boards/MINI-LFR/MINI-LFR_PlaceAndRoute.sdc |
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1 | ------------------------------------------------------------------------------ | |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
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8 | -- (at your option) any later version. | |
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9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
|
14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------- | |
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19 | -- Author : Jean-christophe Pellion | |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
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21 | ------------------------------------------------------------------------------- | |
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22 | LIBRARY IEEE; | |
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23 | USE IEEE.numeric_std.ALL; | |
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24 | USE IEEE.std_logic_1164.ALL; | |
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25 | LIBRARY grlib; | |
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26 | USE grlib.amba.ALL; | |
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27 | USE grlib.stdlib.ALL; | |
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28 | LIBRARY techmap; | |
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29 | USE techmap.gencomp.ALL; | |
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30 | LIBRARY gaisler; | |
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31 | USE gaisler.memctrl.ALL; | |
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32 | USE gaisler.leon3.ALL; | |
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33 | USE gaisler.uart.ALL; | |
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34 | USE gaisler.misc.ALL; | |
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35 | USE gaisler.spacewire.ALL; | |
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36 | LIBRARY esa; | |
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37 | USE esa.memoryctrl.ALL; | |
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38 | LIBRARY lpp; | |
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39 | USE lpp.lpp_memory.ALL; | |
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40 | USE lpp.lpp_ad_conv.ALL; | |
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41 | USE lpp.lpp_lfr_pkg.ALL; | |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; | |
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43 | USE lpp.iir_filter.ALL; | |
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44 | USE lpp.general_purpose.ALL; | |
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45 | USE lpp.lpp_lfr_management.ALL; | |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
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47 | ||
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48 | ENTITY MINI_LFR_top IS | |
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49 | ||
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50 | PORT ( | |
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51 | clk100MHz : IN STD_LOGIC; | |
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52 | clk49_152MHz : IN STD_LOGIC; | |
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53 | reset : IN STD_LOGIC; | |
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54 | --BPs | |
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55 | BP0 : IN STD_LOGIC; | |
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56 | BP1 : IN STD_LOGIC; | |
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57 | --LEDs | |
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58 | LED0 : OUT STD_LOGIC; | |
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59 | LED1 : OUT STD_LOGIC; | |
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60 | LED2 : OUT STD_LOGIC; | |
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61 | --UARTs | |
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62 | TXD1 : IN STD_LOGIC; | |
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63 | RXD1 : OUT STD_LOGIC; | |
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64 | nCTS1 : OUT STD_LOGIC; | |
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65 | nRTS1 : IN STD_LOGIC; | |
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66 | ||
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67 | TXD2 : IN STD_LOGIC; | |
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68 | RXD2 : OUT STD_LOGIC; | |
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69 | nCTS2 : OUT STD_LOGIC; | |
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70 | nDTR2 : IN STD_LOGIC; | |
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71 | nRTS2 : IN STD_LOGIC; | |
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72 | nDCD2 : OUT STD_LOGIC; | |
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73 | ||
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74 | --EXT CONNECTOR | |
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75 | IO0 : INOUT STD_LOGIC; | |
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76 | IO1 : INOUT STD_LOGIC; | |
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77 | IO2 : INOUT STD_LOGIC; | |
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78 | IO3 : INOUT STD_LOGIC; | |
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79 | IO4 : INOUT STD_LOGIC; | |
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80 | IO5 : INOUT STD_LOGIC; | |
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81 | IO6 : INOUT STD_LOGIC; | |
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82 | IO7 : INOUT STD_LOGIC; | |
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83 | IO8 : INOUT STD_LOGIC; | |
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84 | IO9 : INOUT STD_LOGIC; | |
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85 | IO10 : INOUT STD_LOGIC; | |
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86 | IO11 : INOUT STD_LOGIC; | |
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87 | ||
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88 | --SPACE WIRE | |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
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95 | SPW_RED_SIN : IN STD_LOGIC; | |
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
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98 | -- MINI LFR ADC INPUTS | |
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99 | ADC_nCS : OUT STD_LOGIC; | |
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100 | ADC_CLK : OUT STD_LOGIC; | |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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102 | ||
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103 | -- SRAM | |
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104 | SRAM_nWE : OUT STD_LOGIC; | |
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105 | SRAM_CE : OUT STD_LOGIC; | |
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106 | SRAM_nOE : OUT STD_LOGIC; | |
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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110 | ); | |
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111 | ||
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112 | END MINI_LFR_top; | |
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113 | ||
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114 | ||
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
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116 | ||
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117 | --========================================================================== | |
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118 | -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board | |
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119 | -- when enabled, chip enable polarity should be reversed and bank size also | |
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120 | -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 | |
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121 | -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 | |
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122 | --========================================================================== | |
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123 | CONSTANT USE_IAP_MEMCTRL : integer := 1; | |
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124 | --========================================================================== | |
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125 | ||
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126 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
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127 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
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128 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
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129 | ----------------------------------------------------------------------------- | |
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130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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132 | -- | |
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133 | SIGNAL errorn : STD_LOGIC; | |
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134 | -- | |
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135 | SIGNAL I00_s : STD_LOGIC; | |
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136 | ||
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137 | -- CONSTANTS | |
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138 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
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139 | -- | |
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140 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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141 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
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142 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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143 | ||
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144 | SIGNAL apbi_ext : apb_slv_in_type; | |
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145 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
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146 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
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147 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
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148 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
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149 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
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150 | ||
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151 | -- Spacewire signals | |
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152 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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153 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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154 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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155 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
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156 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
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157 | SIGNAL spw_clk : STD_LOGIC; | |
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158 | SIGNAL swni : grspw_in_type; | |
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159 | SIGNAL swno : grspw_out_type; | |
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160 | ||
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161 | --GPIO | |
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162 | SIGNAL gpioi : gpio_in_type; | |
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163 | SIGNAL gpioo : gpio_out_type; | |
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164 | ||
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165 | -- AD Converter ADS7886 | |
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166 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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167 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
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168 | SIGNAL sample_val : STD_LOGIC; | |
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169 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
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170 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
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171 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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172 | ||
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173 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
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174 | ||
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175 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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176 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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177 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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178 | ----------------------------------------------------------------------------- | |
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179 | ||
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180 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
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181 | SIGNAL LFR_rstn : STD_LOGIC; | |
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182 | ||
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183 | ||
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184 | SIGNAL rstn_25 : STD_LOGIC; | |
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185 | SIGNAL rstn_25_d1 : STD_LOGIC; | |
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186 | SIGNAL rstn_25_d2 : STD_LOGIC; | |
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187 | SIGNAL rstn_25_d3 : STD_LOGIC; | |
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188 | ||
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189 | SIGNAL rstn_24 : STD_LOGIC; | |
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190 | SIGNAL rstn_24_d1 : STD_LOGIC; | |
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191 | SIGNAL rstn_24_d2 : STD_LOGIC; | |
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192 | SIGNAL rstn_24_d3 : STD_LOGIC; | |
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193 | ||
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194 | SIGNAL rstn_50 : STD_LOGIC; | |
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195 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
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196 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
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197 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
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198 | ||
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199 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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200 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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201 | ||
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202 | -- | |
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203 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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204 | ||
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205 | -- | |
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206 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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207 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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208 | ||
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209 | SIGNAL nSRAM_READY : STD_LOGIC; | |
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210 | ||
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211 | BEGIN -- beh | |
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212 | ||
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213 | ----------------------------------------------------------------------------- | |
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214 | PROCESS (clk100MHz, reset) | |
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215 | BEGIN -- PROCESS | |
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216 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge | |
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217 | clk_50_s <= NOT clk_50_s; | |
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218 | END IF; | |
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219 | END PROCESS; | |
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220 | ----------------------------------------------------------------------------- | |
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221 | ||
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222 | PROCESS (clk_50_s, reset) | |
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223 | BEGIN -- PROCESS | |
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224 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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225 | clk_25 <= '0'; | |
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226 | rstn_25 <= '0'; | |
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227 | rstn_25_d1 <= '0'; | |
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228 | rstn_25_d2 <= '0'; | |
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229 | rstn_25_d3 <= '0'; | |
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230 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
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231 | clk_25 <= NOT clk_25; | |
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232 | rstn_25_d1 <= '1'; | |
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233 | rstn_25_d2 <= rstn_25_d1; | |
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234 | rstn_25_d3 <= rstn_25_d2; | |
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235 | rstn_25 <= rstn_25_d3; | |
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236 | END IF; | |
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237 | END PROCESS; | |
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238 | ||
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239 | PROCESS (clk49_152MHz, reset) | |
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240 | BEGIN -- PROCESS | |
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241 | IF reset = '0' THEN -- asynchronous reset (active low) | |
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242 | clk_24 <= '0'; | |
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243 | rstn_24_d1 <= '0'; | |
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244 | rstn_24_d2 <= '0'; | |
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245 | rstn_24_d3 <= '0'; | |
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246 | rstn_24 <= '0'; | |
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247 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
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248 | clk_24 <= NOT clk_24; | |
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249 | rstn_24_d1 <= '1'; | |
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250 | rstn_24_d2 <= rstn_24_d1; | |
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251 | rstn_24_d3 <= rstn_24_d2; | |
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252 | rstn_24 <= rstn_24_d3; | |
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253 | END IF; | |
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254 | END PROCESS; | |
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255 | ||
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256 | ----------------------------------------------------------------------------- | |
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257 | ||
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258 | PROCESS (clk_25, rstn_25) | |
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259 | BEGIN -- PROCESS | |
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260 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
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261 | LED0 <= '0'; | |
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262 | LED1 <= '0'; | |
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263 | LED2 <= '0'; | |
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264 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
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265 | LED0 <= '0'; | |
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266 | LED1 <= '1'; | |
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267 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
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268 | END IF; | |
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269 | END PROCESS; | |
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270 | ||
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271 | PROCESS (clk49_152MHz, rstn_24) | |
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272 | BEGIN -- PROCESS | |
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273 | IF rstn_24 = '0' THEN -- asynchronous reset (active low) | |
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274 | I00_s <= '0'; | |
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275 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
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276 | I00_s <= NOT I00_s; | |
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277 | END IF; | |
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278 | END PROCESS; | |
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279 | ||
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280 | --UARTs | |
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281 | nCTS1 <= '1'; | |
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282 | nCTS2 <= '1'; | |
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283 | nDCD2 <= '1'; | |
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284 | -- No AHB UART | |
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285 | RXD1 <= TXD1; | |
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286 | ||
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287 | -- | |
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288 | ||
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289 | leon3_soc_1 : leon3_soc | |
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290 | GENERIC MAP ( | |
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291 | fabtech => apa3e, | |
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292 | memtech => apa3e, | |
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293 | padtech => inferred, | |
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294 | clktech => inferred, | |
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295 | disas => 0, | |
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296 | dbguart => 0, | |
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297 | pclow => 2, | |
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298 | clk_freq => 25000, | |
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299 | IS_RADHARD => 0, | |
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300 | NB_CPU => 1, | |
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301 | ENABLE_FPU => 1, | |
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302 | FPU_NETLIST => 0, | |
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303 | ENABLE_DSU => 1, | |
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304 | ENABLE_AHB_UART => 0, | |
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305 | ENABLE_APB_UART => 1, | |
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306 | ENABLE_IRQMP => 1, | |
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307 | ENABLE_GPT => 1, | |
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308 | NB_AHB_MASTER => NB_AHB_MASTER, | |
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309 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
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310 | NB_APB_SLAVE => NB_APB_SLAVE, | |
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311 | ADDRESS_SIZE => 20, | |
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312 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, | |
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313 | BYPASS_EDAC_MEMCTRLR => '0', | |
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314 | SRBANKSZ => 9) | |
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315 | PORT MAP ( | |
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316 | clk => clk_25, | |
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317 | reset => rstn_25, | |
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318 | errorn => errorn, | |
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319 | ahbrxd => OPEN,--TXD1, | |
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320 | ahbtxd => OPEN,--RXD1, | |
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321 | urxd1 => TXD2, | |
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322 | utxd1 => RXD2, | |
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323 | address => SRAM_A, | |
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324 | data => SRAM_DQ, | |
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325 | nSRAM_BE0 => SRAM_nBE(0), | |
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326 | nSRAM_BE1 => SRAM_nBE(1), | |
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327 | nSRAM_BE2 => SRAM_nBE(2), | |
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328 | nSRAM_BE3 => SRAM_nBE(3), | |
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329 | nSRAM_WE => SRAM_nWE, | |
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330 | nSRAM_CE => SRAM_CE_s, | |
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331 | nSRAM_OE => SRAM_nOE, | |
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332 | nSRAM_READY => nSRAM_READY, | |
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333 | SRAM_MBE => OPEN, | |
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334 | apbi_ext => apbi_ext, | |
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335 | apbo_ext => apbo_ext, | |
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336 | ahbi_s_ext => ahbi_s_ext, | |
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337 | ahbo_s_ext => ahbo_s_ext, | |
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338 | ahbi_m_ext => ahbi_m_ext, | |
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339 | ahbo_m_ext => ahbo_m_ext); | |
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340 | ||
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341 | PROCESS (clk_25, rstn_25) | |
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342 | BEGIN -- PROCESS | |
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343 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
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344 | nSRAM_READY <= '1'; | |
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345 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
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346 | nSRAM_READY <= '1'; | |
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347 | IF IO0 = '1' THEN | |
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348 | nSRAM_READY <= '0'; | |
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349 | END IF; | |
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350 | END IF; | |
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351 | END PROCESS; | |
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352 | ||
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353 | ||
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354 | ||
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355 | IAP:if USE_IAP_MEMCTRL = 1 GENERATE | |
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356 | SRAM_CE <= not SRAM_CE_s(0); | |
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357 | END GENERATE; | |
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358 | ||
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359 | NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE | |
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360 | SRAM_CE <= SRAM_CE_s(0); | |
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361 | END GENERATE; | |
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362 | ------------------------------------------------------------------------------- | |
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363 | -- APB_LFR_MANAGEMENT --------------------------------------------------------- | |
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364 | ------------------------------------------------------------------------------- | |
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365 | apb_lfr_management_1 : apb_lfr_management | |
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366 | GENERIC MAP ( | |
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367 | tech => apa3e, | |
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368 | pindex => 6, | |
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369 | paddr => 6, | |
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370 | pmask => 16#fff#, | |
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371 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
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372 | PORT MAP ( | |
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373 | clk25MHz => clk_25, | |
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374 | resetn_25MHz => rstn_25, | |
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375 | grspw_tick => swno.tickout, | |
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376 | apbi => apbi_ext, | |
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377 | apbo => apbo_ext(6), | |
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378 | HK_sample => sample_hk, | |
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379 | HK_val => sample_val, | |
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380 | HK_sel => HK_SEL, | |
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381 | DAC_SDO => OPEN, | |
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382 | DAC_SCK => OPEN, | |
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383 | DAC_SYNC => OPEN, | |
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384 | DAC_CAL_EN => OPEN, | |
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385 | coarse_time => coarse_time, | |
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386 | fine_time => fine_time, | |
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387 | LFR_soft_rstn => LFR_soft_rstn | |
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388 | ); | |
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389 | ||
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390 | ----------------------------------------------------------------------- | |
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391 | --- SpaceWire -------------------------------------------------------- | |
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392 | ----------------------------------------------------------------------- | |
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393 | ||
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394 | SPW_EN <= '1'; | |
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395 | ||
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396 | spw_clk <= clk_50_s; | |
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397 | spw_rxtxclk <= spw_clk; | |
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398 | spw_rxclkn <= NOT spw_rxtxclk; | |
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399 | ||
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400 | -- PADS for SPW1 | |
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401 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
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402 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
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403 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
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404 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
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405 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
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406 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
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407 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
|
408 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
|
409 | -- PADS FOR SPW2 | |
|
410 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
|
411 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
|
412 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
|
413 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
|
414 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
|
415 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
|
416 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
|
417 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
|
418 | ||
|
419 | -- GRSPW PHY | |
|
420 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
|
421 | spw_phy0 : grspw_phy | |
|
422 | GENERIC MAP( | |
|
423 | tech => apa3e, | |
|
424 | rxclkbuftype => 1, | |
|
425 | scantest => 0) | |
|
426 | PORT MAP( | |
|
427 | rxrst => swno.rxrst, | |
|
428 | di => dtmp(j), | |
|
429 | si => stmp(j), | |
|
430 | rxclko => spw_rxclk(j), | |
|
431 | do => swni.d(j), | |
|
432 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
|
433 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
|
434 | END GENERATE spw_inputloop; | |
|
435 | ||
|
436 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
|
437 | ||
|
438 | -- SPW core | |
|
439 | sw0 : grspwm GENERIC MAP( | |
|
440 | tech => apa3e, | |
|
441 | hindex => 1, | |
|
442 | pindex => 5, | |
|
443 | paddr => 5, | |
|
444 | pirq => 11, | |
|
445 | sysfreq => 25000, -- CPU_FREQ | |
|
446 | rmap => 1, | |
|
447 | rmapcrc => 1, | |
|
448 | fifosize1 => 16, | |
|
449 | fifosize2 => 16, | |
|
450 | rxclkbuftype => 1, | |
|
451 | rxunaligned => 0, | |
|
452 | rmapbufs => 4, | |
|
453 | ft => 0, | |
|
454 | netlist => 0, | |
|
455 | ports => 2, | |
|
456 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
|
457 | memtech => apa3e, | |
|
458 | destkey => 2, | |
|
459 | spwcore => 1 | |
|
460 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
|
461 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
|
462 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
|
463 | ) | |
|
464 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
|
465 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
|
466 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
|
467 | swni, swno); | |
|
468 | ||
|
469 | swni.tickin <= '0'; | |
|
470 | swni.rmapen <= '1'; | |
|
471 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
|
472 | swni.tickinraw <= '0'; | |
|
473 | swni.timein <= (OTHERS => '0'); | |
|
474 | swni.dcrstval <= (OTHERS => '0'); | |
|
475 | swni.timerrstval <= (OTHERS => '0'); | |
|
476 | ||
|
477 | ------------------------------------------------------------------------------- | |
|
478 | -- LFR ------------------------------------------------------------------------ | |
|
479 | ------------------------------------------------------------------------------- | |
|
480 | ||
|
481 | ||
|
482 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
|
483 | ||
|
484 | lpp_lfr_1 : lpp_lfr | |
|
485 | GENERIC MAP ( | |
|
486 | Mem_use => use_RAM, | |
|
487 | nb_data_by_buffer_size => 32, | |
|
488 | nb_snapshot_param_size => 32, | |
|
489 | delta_vector_size => 32, | |
|
490 | delta_vector_size_f0_2 => 7, -- log2(96) | |
|
491 | pindex => 15, | |
|
492 | paddr => 15, | |
|
493 | pmask => 16#fff#, | |
|
494 | pirq_ms => 6, | |
|
495 | pirq_wfp => 14, | |
|
496 | hindex => 2, | |
|
497 |
top_lfr_version => |
|
|
498 | PORT MAP ( | |
|
499 | clk => clk_25, | |
|
500 | rstn => LFR_rstn, | |
|
501 | sample_B => sample_s(2 DOWNTO 0), | |
|
502 | sample_E => sample_s(7 DOWNTO 3), | |
|
503 | sample_val => sample_val, | |
|
504 | apbi => apbi_ext, | |
|
505 | apbo => apbo_ext(15), | |
|
506 | ahbi => ahbi_m_ext, | |
|
507 | ahbo => ahbo_m_ext(2), | |
|
508 | coarse_time => coarse_time, | |
|
509 | fine_time => fine_time, | |
|
510 | data_shaping_BW => bias_fail_sw_sig, | |
|
511 | debug_vector => lfr_debug_vector, | |
|
512 | debug_vector_ms => lfr_debug_vector_ms | |
|
513 | ); | |
|
514 | ||
|
515 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
|
516 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
|
517 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
|
518 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
|
519 | ||
|
520 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
|
521 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
|
522 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
|
523 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
|
524 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
|
525 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
|
526 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
|
527 | ||
|
528 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
|
529 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
|
530 | END GENERATE all_sample; | |
|
531 | ||
|
532 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
|
533 | GENERIC MAP( | |
|
534 | ChannelCount => 8, | |
|
535 | SampleNbBits => 14, | |
|
536 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
|
537 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
|
538 | PORT MAP ( | |
|
539 | -- CONV | |
|
540 | cnv_clk => clk_24, | |
|
541 | cnv_rstn => rstn_24, | |
|
542 | cnv => ADC_nCS_sig, | |
|
543 | -- DATA | |
|
544 | clk => clk_25, | |
|
545 | rstn => rstn_25, | |
|
546 | sck => ADC_CLK_sig, | |
|
547 | sdo => ADC_SDO_sig, | |
|
548 | -- SAMPLE | |
|
549 | sample => sample, | |
|
550 | sample_val => sample_val); | |
|
551 | ||
|
552 | ADC_nCS <= ADC_nCS_sig; | |
|
553 | ADC_CLK <= ADC_CLK_sig; | |
|
554 | ADC_SDO_sig <= ADC_SDO; | |
|
555 | ||
|
556 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE | |
|
557 | "0010001000100010" WHEN HK_SEL = "01" ELSE | |
|
558 | "0100010001000100" WHEN HK_SEL = "10" ELSE | |
|
559 | (OTHERS => '0'); | |
|
560 | ||
|
561 | ||
|
562 | ---------------------------------------------------------------------- | |
|
563 | --- GPIO ----------------------------------------------------------- | |
|
564 | ---------------------------------------------------------------------- | |
|
565 | ||
|
566 | grgpio0 : grgpio | |
|
567 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
|
568 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
|
569 | ||
|
570 | gpioi.sig_en <= (OTHERS => '0'); | |
|
571 | gpioi.sig_in <= (OTHERS => '0'); | |
|
572 | gpioi.din <= (OTHERS => '0'); | |
|
573 | PROCESS (clk_25, rstn_25) | |
|
574 | BEGIN -- PROCESS | |
|
575 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
576 | IO8 <= '0'; | |
|
577 | IO9 <= '0'; | |
|
578 | IO10 <= '0'; | |
|
579 | IO11 <= '0'; | |
|
580 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
|
581 | CASE gpioo.dout(2 DOWNTO 0) IS | |
|
582 | WHEN "011" => | |
|
583 | IO8 <= observation_reg(8); | |
|
584 | IO9 <= observation_reg(9); | |
|
585 | IO10 <= observation_reg(10); | |
|
586 | IO11 <= observation_reg(11); | |
|
587 | WHEN "001" => | |
|
588 | IO8 <= observation_reg(8 + 12); | |
|
589 | IO9 <= observation_reg(9 + 12); | |
|
590 | IO10 <= observation_reg(10 + 12); | |
|
591 | IO11 <= observation_reg(11 + 12); | |
|
592 | WHEN "010" => | |
|
593 | IO8 <= '0'; | |
|
594 | IO9 <= '0'; | |
|
595 | IO10 <= '0'; | |
|
596 | IO11 <= '0'; | |
|
597 | WHEN "000" => | |
|
598 | IO8 <= observation_vector_0(8); | |
|
599 | IO9 <= observation_vector_0(9); | |
|
600 | IO10 <= observation_vector_0(10); | |
|
601 | IO11 <= observation_vector_0(11); | |
|
602 | WHEN "100" => | |
|
603 | IO8 <= observation_vector_1(8); | |
|
604 | IO9 <= observation_vector_1(9); | |
|
605 | IO10 <= observation_vector_1(10); | |
|
606 | IO11 <= observation_vector_1(11); | |
|
607 | WHEN OTHERS => NULL; | |
|
608 | END CASE; | |
|
609 | ||
|
610 | END IF; | |
|
611 | END PROCESS; | |
|
612 | ----------------------------------------------------------------------------- | |
|
613 | -- | |
|
614 | ----------------------------------------------------------------------------- | |
|
615 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
|
616 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
|
617 | apbo_ext(I) <= apb_none; | |
|
618 | END GENERATE apbo_ext_not_used; | |
|
619 | END GENERATE all_apbo_ext; | |
|
620 | ||
|
621 | ||
|
622 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
|
623 | ahbo_s_ext(I) <= ahbs_none; | |
|
624 | END GENERATE all_ahbo_ext; | |
|
625 | ||
|
626 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
|
627 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
|
628 | ahbo_m_ext(I) <= ahbm_none; | |
|
629 | END GENERATE ahbo_m_ext_not_used; | |
|
630 | END GENERATE all_ahbo_m_ext; | |
|
631 | ||
|
632 |
END beh; |
|
|
1 | ------------------------------------------------------------------------------ | |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
|
4 | -- | |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
|
6 | -- it under the terms of the GNU General Public License as published by | |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
|
8 | -- (at your option) any later version. | |
|
9 | -- | |
|
10 | -- This program is distributed in the hope that it will be useful, | |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
|
13 | -- GNU General Public License for more details. | |
|
14 | -- | |
|
15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
|
18 | ------------------------------------------------------------------------------- | |
|
19 | -- Author : Jean-christophe Pellion | |
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
|
21 | ------------------------------------------------------------------------------- | |
|
22 | LIBRARY IEEE; | |
|
23 | USE IEEE.numeric_std.ALL; | |
|
24 | USE IEEE.std_logic_1164.ALL; | |
|
25 | LIBRARY grlib; | |
|
26 | USE grlib.amba.ALL; | |
|
27 | USE grlib.stdlib.ALL; | |
|
28 | LIBRARY techmap; | |
|
29 | USE techmap.gencomp.ALL; | |
|
30 | LIBRARY gaisler; | |
|
31 | USE gaisler.memctrl.ALL; | |
|
32 | USE gaisler.leon3.ALL; | |
|
33 | USE gaisler.uart.ALL; | |
|
34 | USE gaisler.misc.ALL; | |
|
35 | USE gaisler.spacewire.ALL; | |
|
36 | LIBRARY esa; | |
|
37 | USE esa.memoryctrl.ALL; | |
|
38 | LIBRARY lpp; | |
|
39 | USE lpp.lpp_memory.ALL; | |
|
40 | USE lpp.lpp_ad_conv.ALL; | |
|
41 | USE lpp.lpp_lfr_pkg.ALL; | |
|
42 | USE lpp.lpp_top_lfr_pkg.ALL; | |
|
43 | USE lpp.iir_filter.ALL; | |
|
44 | USE lpp.general_purpose.ALL; | |
|
45 | USE lpp.lpp_lfr_management.ALL; | |
|
46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
|
47 | ||
|
48 | ENTITY MINI_LFR_top IS | |
|
49 | ||
|
50 | PORT ( | |
|
51 | clk100MHz : IN STD_LOGIC; | |
|
52 | clk49_152MHz : IN STD_LOGIC; | |
|
53 | reset : IN STD_LOGIC; | |
|
54 | --BPs | |
|
55 | BP0 : IN STD_LOGIC; | |
|
56 | BP1 : IN STD_LOGIC; | |
|
57 | --LEDs | |
|
58 | LED0 : OUT STD_LOGIC; | |
|
59 | LED1 : OUT STD_LOGIC; | |
|
60 | LED2 : OUT STD_LOGIC; | |
|
61 | --UARTs | |
|
62 | TXD1 : IN STD_LOGIC; | |
|
63 | RXD1 : OUT STD_LOGIC; | |
|
64 | nCTS1 : OUT STD_LOGIC; | |
|
65 | nRTS1 : IN STD_LOGIC; | |
|
66 | ||
|
67 | TXD2 : IN STD_LOGIC; | |
|
68 | RXD2 : OUT STD_LOGIC; | |
|
69 | nCTS2 : OUT STD_LOGIC; | |
|
70 | nDTR2 : IN STD_LOGIC; | |
|
71 | nRTS2 : IN STD_LOGIC; | |
|
72 | nDCD2 : OUT STD_LOGIC; | |
|
73 | ||
|
74 | --EXT CONNECTOR | |
|
75 | IO0 : INOUT STD_LOGIC; | |
|
76 | IO1 : INOUT STD_LOGIC; | |
|
77 | IO2 : INOUT STD_LOGIC; | |
|
78 | IO3 : INOUT STD_LOGIC; | |
|
79 | IO4 : INOUT STD_LOGIC; | |
|
80 | IO5 : INOUT STD_LOGIC; | |
|
81 | IO6 : INOUT STD_LOGIC; | |
|
82 | IO7 : INOUT STD_LOGIC; | |
|
83 | IO8 : INOUT STD_LOGIC; | |
|
84 | IO9 : INOUT STD_LOGIC; | |
|
85 | IO10 : INOUT STD_LOGIC; | |
|
86 | IO11 : INOUT STD_LOGIC; | |
|
87 | ||
|
88 | --SPACE WIRE | |
|
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
|
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
|
91 | SPW_NOM_SIN : IN STD_LOGIC; | |
|
92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
|
93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
|
95 | SPW_RED_SIN : IN STD_LOGIC; | |
|
96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
|
97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
|
98 | -- MINI LFR ADC INPUTS | |
|
99 | ADC_nCS : OUT STD_LOGIC; | |
|
100 | ADC_CLK : OUT STD_LOGIC; | |
|
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
102 | ||
|
103 | -- SRAM | |
|
104 | SRAM_nWE : OUT STD_LOGIC; | |
|
105 | SRAM_CE : OUT STD_LOGIC; | |
|
106 | SRAM_nOE : OUT STD_LOGIC; | |
|
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
|
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
110 | ); | |
|
111 | ||
|
112 | END MINI_LFR_top; | |
|
113 | ||
|
114 | ||
|
115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
|
116 | ||
|
117 | --========================================================================== | |
|
118 | -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board | |
|
119 | -- when enabled, chip enable polarity should be reversed and bank size also | |
|
120 | -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9 | |
|
121 | -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8 | |
|
122 | --========================================================================== | |
|
123 | CONSTANT USE_IAP_MEMCTRL : integer := 1; | |
|
124 | --========================================================================== | |
|
125 | ||
|
126 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
|
127 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
|
128 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
|
129 | ----------------------------------------------------------------------------- | |
|
130 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
131 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
132 | -- | |
|
133 | SIGNAL errorn : STD_LOGIC; | |
|
134 | -- | |
|
135 | SIGNAL I00_s : STD_LOGIC; | |
|
136 | ||
|
137 | -- CONSTANTS | |
|
138 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
|
139 | -- | |
|
140 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
|
141 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
|
142 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
|
143 | ||
|
144 | SIGNAL apbi_ext : apb_slv_in_type; | |
|
145 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
|
146 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
|
147 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
|
148 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
|
149 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
|
150 | ||
|
151 | -- Spacewire signals | |
|
152 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
153 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
154 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
155 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
|
156 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
|
157 | SIGNAL spw_clk : STD_LOGIC; | |
|
158 | SIGNAL swni : grspw_in_type; | |
|
159 | SIGNAL swno : grspw_out_type; | |
|
160 | ||
|
161 | --GPIO | |
|
162 | SIGNAL gpioi : gpio_in_type; | |
|
163 | SIGNAL gpioo : gpio_out_type; | |
|
164 | ||
|
165 | -- AD Converter ADS7886 | |
|
166 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
|
167 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
|
168 | SIGNAL sample_val : STD_LOGIC; | |
|
169 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
|
170 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
|
171 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
|
172 | ||
|
173 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
|
174 | ||
|
175 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
176 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
177 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
178 | ----------------------------------------------------------------------------- | |
|
179 | ||
|
180 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
|
181 | SIGNAL LFR_rstn : STD_LOGIC; | |
|
182 | ||
|
183 | ||
|
184 | SIGNAL rstn_25 : STD_LOGIC; | |
|
185 | SIGNAL rstn_25_d1 : STD_LOGIC; | |
|
186 | SIGNAL rstn_25_d2 : STD_LOGIC; | |
|
187 | SIGNAL rstn_25_d3 : STD_LOGIC; | |
|
188 | ||
|
189 | SIGNAL rstn_24 : STD_LOGIC; | |
|
190 | SIGNAL rstn_24_d1 : STD_LOGIC; | |
|
191 | SIGNAL rstn_24_d2 : STD_LOGIC; | |
|
192 | SIGNAL rstn_24_d3 : STD_LOGIC; | |
|
193 | ||
|
194 | SIGNAL rstn_50 : STD_LOGIC; | |
|
195 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
|
196 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
|
197 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
|
198 | ||
|
199 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
200 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
201 | ||
|
202 | -- | |
|
203 | SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
204 | ||
|
205 | -- | |
|
206 | SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
|
207 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
208 | ||
|
209 | SIGNAL nSRAM_READY : STD_LOGIC; | |
|
210 | ||
|
211 | BEGIN -- beh | |
|
212 | ||
|
213 | ----------------------------------------------------------------------------- | |
|
214 | PROCESS (clk100MHz, reset) | |
|
215 | BEGIN -- PROCESS | |
|
216 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge | |
|
217 | clk_50_s <= NOT clk_50_s; | |
|
218 | END IF; | |
|
219 | END PROCESS; | |
|
220 | ----------------------------------------------------------------------------- | |
|
221 | ||
|
222 | PROCESS (clk_50_s, reset) | |
|
223 | BEGIN -- PROCESS | |
|
224 | IF reset = '0' THEN -- asynchronous reset (active low) | |
|
225 | clk_25 <= '0'; | |
|
226 | rstn_25 <= '0'; | |
|
227 | rstn_25_d1 <= '0'; | |
|
228 | rstn_25_d2 <= '0'; | |
|
229 | rstn_25_d3 <= '0'; | |
|
230 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
|
231 | clk_25 <= NOT clk_25; | |
|
232 | rstn_25_d1 <= '1'; | |
|
233 | rstn_25_d2 <= rstn_25_d1; | |
|
234 | rstn_25_d3 <= rstn_25_d2; | |
|
235 | rstn_25 <= rstn_25_d3; | |
|
236 | END IF; | |
|
237 | END PROCESS; | |
|
238 | ||
|
239 | PROCESS (clk49_152MHz, reset) | |
|
240 | BEGIN -- PROCESS | |
|
241 | IF reset = '0' THEN -- asynchronous reset (active low) | |
|
242 | clk_24 <= '0'; | |
|
243 | rstn_24_d1 <= '0'; | |
|
244 | rstn_24_d2 <= '0'; | |
|
245 | rstn_24_d3 <= '0'; | |
|
246 | rstn_24 <= '0'; | |
|
247 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
|
248 | clk_24 <= NOT clk_24; | |
|
249 | rstn_24_d1 <= '1'; | |
|
250 | rstn_24_d2 <= rstn_24_d1; | |
|
251 | rstn_24_d3 <= rstn_24_d2; | |
|
252 | rstn_24 <= rstn_24_d3; | |
|
253 | END IF; | |
|
254 | END PROCESS; | |
|
255 | ||
|
256 | ----------------------------------------------------------------------------- | |
|
257 | ||
|
258 | PROCESS (clk_25, rstn_25) | |
|
259 | BEGIN -- PROCESS | |
|
260 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
261 | LED0 <= '0'; | |
|
262 | LED1 <= '0'; | |
|
263 | LED2 <= '0'; | |
|
264 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
|
265 | LED0 <= '0'; | |
|
266 | LED1 <= '1'; | |
|
267 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
|
268 | END IF; | |
|
269 | END PROCESS; | |
|
270 | ||
|
271 | PROCESS (clk49_152MHz, rstn_24) | |
|
272 | BEGIN -- PROCESS | |
|
273 | IF rstn_24 = '0' THEN -- asynchronous reset (active low) | |
|
274 | I00_s <= '0'; | |
|
275 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
|
276 | I00_s <= NOT I00_s; | |
|
277 | END IF; | |
|
278 | END PROCESS; | |
|
279 | ||
|
280 | --UARTs | |
|
281 | nCTS1 <= '1'; | |
|
282 | nCTS2 <= '1'; | |
|
283 | nDCD2 <= '1'; | |
|
284 | -- No AHB UART | |
|
285 | RXD1 <= TXD1; | |
|
286 | ||
|
287 | -- | |
|
288 | ||
|
289 | leon3_soc_1 : leon3_soc | |
|
290 | GENERIC MAP ( | |
|
291 | fabtech => apa3e, | |
|
292 | memtech => apa3e, | |
|
293 | padtech => inferred, | |
|
294 | clktech => inferred, | |
|
295 | disas => 0, | |
|
296 | dbguart => 0, | |
|
297 | pclow => 2, | |
|
298 | clk_freq => 25000, | |
|
299 | IS_RADHARD => 0, | |
|
300 | NB_CPU => 1, | |
|
301 | ENABLE_FPU => 1, | |
|
302 | FPU_NETLIST => 0, | |
|
303 | ENABLE_DSU => 1, | |
|
304 | ENABLE_AHB_UART => 0, | |
|
305 | ENABLE_APB_UART => 1, | |
|
306 | ENABLE_IRQMP => 1, | |
|
307 | ENABLE_GPT => 1, | |
|
308 | NB_AHB_MASTER => NB_AHB_MASTER, | |
|
309 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
|
310 | NB_APB_SLAVE => NB_APB_SLAVE, | |
|
311 | ADDRESS_SIZE => 20, | |
|
312 | USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL, | |
|
313 | BYPASS_EDAC_MEMCTRLR => '0', | |
|
314 | SRBANKSZ => 9) | |
|
315 | PORT MAP ( | |
|
316 | clk => clk_25, | |
|
317 | reset => rstn_25, | |
|
318 | errorn => errorn, | |
|
319 | ahbrxd => OPEN,--TXD1, | |
|
320 | ahbtxd => OPEN,--RXD1, | |
|
321 | urxd1 => TXD2, | |
|
322 | utxd1 => RXD2, | |
|
323 | address => SRAM_A, | |
|
324 | data => SRAM_DQ, | |
|
325 | nSRAM_BE0 => SRAM_nBE(0), | |
|
326 | nSRAM_BE1 => SRAM_nBE(1), | |
|
327 | nSRAM_BE2 => SRAM_nBE(2), | |
|
328 | nSRAM_BE3 => SRAM_nBE(3), | |
|
329 | nSRAM_WE => SRAM_nWE, | |
|
330 | nSRAM_CE => SRAM_CE_s, | |
|
331 | nSRAM_OE => SRAM_nOE, | |
|
332 | nSRAM_READY => nSRAM_READY, | |
|
333 | SRAM_MBE => OPEN, | |
|
334 | apbi_ext => apbi_ext, | |
|
335 | apbo_ext => apbo_ext, | |
|
336 | ahbi_s_ext => ahbi_s_ext, | |
|
337 | ahbo_s_ext => ahbo_s_ext, | |
|
338 | ahbi_m_ext => ahbi_m_ext, | |
|
339 | ahbo_m_ext => ahbo_m_ext); | |
|
340 | ||
|
341 | PROCESS (clk_25, rstn_25) | |
|
342 | BEGIN -- PROCESS | |
|
343 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
344 | nSRAM_READY <= '1'; | |
|
345 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge | |
|
346 | nSRAM_READY <= '1'; | |
|
347 | IF IO0 = '1' THEN | |
|
348 | nSRAM_READY <= '0'; | |
|
349 | END IF; | |
|
350 | END IF; | |
|
351 | END PROCESS; | |
|
352 | ||
|
353 | ||
|
354 | ||
|
355 | IAP:if USE_IAP_MEMCTRL = 1 GENERATE | |
|
356 | SRAM_CE <= not SRAM_CE_s(0); | |
|
357 | END GENERATE; | |
|
358 | ||
|
359 | NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE | |
|
360 | SRAM_CE <= SRAM_CE_s(0); | |
|
361 | END GENERATE; | |
|
362 | ------------------------------------------------------------------------------- | |
|
363 | -- APB_LFR_MANAGEMENT --------------------------------------------------------- | |
|
364 | ------------------------------------------------------------------------------- | |
|
365 | apb_lfr_management_1 : apb_lfr_management | |
|
366 | GENERIC MAP ( | |
|
367 | tech => apa3e, | |
|
368 | pindex => 6, | |
|
369 | paddr => 6, | |
|
370 | pmask => 16#fff#, | |
|
371 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
|
372 | PORT MAP ( | |
|
373 | clk25MHz => clk_25, | |
|
374 | resetn_25MHz => rstn_25, | |
|
375 | grspw_tick => swno.tickout, | |
|
376 | apbi => apbi_ext, | |
|
377 | apbo => apbo_ext(6), | |
|
378 | HK_sample => sample_hk, | |
|
379 | HK_val => sample_val, | |
|
380 | HK_sel => HK_SEL, | |
|
381 | DAC_SDO => OPEN, | |
|
382 | DAC_SCK => OPEN, | |
|
383 | DAC_SYNC => OPEN, | |
|
384 | DAC_CAL_EN => OPEN, | |
|
385 | coarse_time => coarse_time, | |
|
386 | fine_time => fine_time, | |
|
387 | LFR_soft_rstn => LFR_soft_rstn | |
|
388 | ); | |
|
389 | ||
|
390 | ----------------------------------------------------------------------- | |
|
391 | --- SpaceWire -------------------------------------------------------- | |
|
392 | ----------------------------------------------------------------------- | |
|
393 | ||
|
394 | SPW_EN <= '1'; | |
|
395 | ||
|
396 | spw_clk <= clk_50_s; | |
|
397 | spw_rxtxclk <= spw_clk; | |
|
398 | spw_rxclkn <= NOT spw_rxtxclk; | |
|
399 | ||
|
400 | -- PADS for SPW1 | |
|
401 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
|
402 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
|
403 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
|
404 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
|
405 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
|
406 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
|
407 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
|
408 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
|
409 | -- PADS FOR SPW2 | |
|
410 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
|
411 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
|
412 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
|
413 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
|
414 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
|
415 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
|
416 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
|
417 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
|
418 | ||
|
419 | -- GRSPW PHY | |
|
420 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
|
421 | spw_phy0 : grspw_phy | |
|
422 | GENERIC MAP( | |
|
423 | tech => apa3e, | |
|
424 | rxclkbuftype => 1, | |
|
425 | scantest => 0) | |
|
426 | PORT MAP( | |
|
427 | rxrst => swno.rxrst, | |
|
428 | di => dtmp(j), | |
|
429 | si => stmp(j), | |
|
430 | rxclko => spw_rxclk(j), | |
|
431 | do => swni.d(j), | |
|
432 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
|
433 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
|
434 | END GENERATE spw_inputloop; | |
|
435 | ||
|
436 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
|
437 | ||
|
438 | -- SPW core | |
|
439 | sw0 : grspwm GENERIC MAP( | |
|
440 | tech => apa3e, | |
|
441 | hindex => 1, | |
|
442 | pindex => 5, | |
|
443 | paddr => 5, | |
|
444 | pirq => 11, | |
|
445 | sysfreq => 25000, -- CPU_FREQ | |
|
446 | rmap => 1, | |
|
447 | rmapcrc => 1, | |
|
448 | fifosize1 => 16, | |
|
449 | fifosize2 => 16, | |
|
450 | rxclkbuftype => 1, | |
|
451 | rxunaligned => 0, | |
|
452 | rmapbufs => 4, | |
|
453 | ft => 0, | |
|
454 | netlist => 0, | |
|
455 | ports => 2, | |
|
456 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
|
457 | memtech => apa3e, | |
|
458 | destkey => 2, | |
|
459 | spwcore => 1 | |
|
460 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
|
461 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
|
462 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
|
463 | ) | |
|
464 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
|
465 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
|
466 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
|
467 | swni, swno); | |
|
468 | ||
|
469 | swni.tickin <= '0'; | |
|
470 | swni.rmapen <= '1'; | |
|
471 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
|
472 | swni.tickinraw <= '0'; | |
|
473 | swni.timein <= (OTHERS => '0'); | |
|
474 | swni.dcrstval <= (OTHERS => '0'); | |
|
475 | swni.timerrstval <= (OTHERS => '0'); | |
|
476 | ||
|
477 | ------------------------------------------------------------------------------- | |
|
478 | -- LFR ------------------------------------------------------------------------ | |
|
479 | ------------------------------------------------------------------------------- | |
|
480 | ||
|
481 | ||
|
482 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
|
483 | ||
|
484 | lpp_lfr_1 : lpp_lfr | |
|
485 | GENERIC MAP ( | |
|
486 | Mem_use => use_RAM, | |
|
487 | nb_data_by_buffer_size => 32, | |
|
488 | nb_snapshot_param_size => 32, | |
|
489 | delta_vector_size => 32, | |
|
490 | delta_vector_size_f0_2 => 7, -- log2(96) | |
|
491 | pindex => 15, | |
|
492 | paddr => 15, | |
|
493 | pmask => 16#fff#, | |
|
494 | pirq_ms => 6, | |
|
495 | pirq_wfp => 14, | |
|
496 | hindex => 2, | |
|
497 | top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015A") -- aa.bb.cc version | |
|
498 | PORT MAP ( | |
|
499 | clk => clk_25, | |
|
500 | rstn => LFR_rstn, | |
|
501 | sample_B => sample_s(2 DOWNTO 0), | |
|
502 | sample_E => sample_s(7 DOWNTO 3), | |
|
503 | sample_val => sample_val, | |
|
504 | apbi => apbi_ext, | |
|
505 | apbo => apbo_ext(15), | |
|
506 | ahbi => ahbi_m_ext, | |
|
507 | ahbo => ahbo_m_ext(2), | |
|
508 | coarse_time => coarse_time, | |
|
509 | fine_time => fine_time, | |
|
510 | data_shaping_BW => bias_fail_sw_sig, | |
|
511 | debug_vector => lfr_debug_vector, | |
|
512 | debug_vector_ms => lfr_debug_vector_ms | |
|
513 | ); | |
|
514 | ||
|
515 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
|
516 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
|
517 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
|
518 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
|
519 | ||
|
520 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
|
521 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
|
522 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
|
523 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
|
524 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
|
525 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
|
526 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
|
527 | ||
|
528 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
|
529 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
|
530 | END GENERATE all_sample; | |
|
531 | ||
|
532 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
|
533 | GENERIC MAP( | |
|
534 | ChannelCount => 8, | |
|
535 | SampleNbBits => 14, | |
|
536 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
|
537 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
|
538 | PORT MAP ( | |
|
539 | -- CONV | |
|
540 | cnv_clk => clk_24, | |
|
541 | cnv_rstn => rstn_24, | |
|
542 | cnv => ADC_nCS_sig, | |
|
543 | -- DATA | |
|
544 | clk => clk_25, | |
|
545 | rstn => rstn_25, | |
|
546 | sck => ADC_CLK_sig, | |
|
547 | sdo => ADC_SDO_sig, | |
|
548 | -- SAMPLE | |
|
549 | sample => sample, | |
|
550 | sample_val => sample_val); | |
|
551 | ||
|
552 | ADC_nCS <= ADC_nCS_sig; | |
|
553 | ADC_CLK <= ADC_CLK_sig; | |
|
554 | ADC_SDO_sig <= ADC_SDO; | |
|
555 | ||
|
556 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE | |
|
557 | "0010001000100010" WHEN HK_SEL = "01" ELSE | |
|
558 | "0100010001000100" WHEN HK_SEL = "10" ELSE | |
|
559 | (OTHERS => '0'); | |
|
560 | ||
|
561 | ||
|
562 | ---------------------------------------------------------------------- | |
|
563 | --- GPIO ----------------------------------------------------------- | |
|
564 | ---------------------------------------------------------------------- | |
|
565 | ||
|
566 | grgpio0 : grgpio | |
|
567 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
|
568 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
|
569 | ||
|
570 | gpioi.sig_en <= (OTHERS => '0'); | |
|
571 | gpioi.sig_in <= (OTHERS => '0'); | |
|
572 | gpioi.din <= (OTHERS => '0'); | |
|
573 | PROCESS (clk_25, rstn_25) | |
|
574 | BEGIN -- PROCESS | |
|
575 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
|
576 | IO8 <= '0'; | |
|
577 | IO9 <= '0'; | |
|
578 | IO10 <= '0'; | |
|
579 | IO11 <= '0'; | |
|
580 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
|
581 | CASE gpioo.dout(2 DOWNTO 0) IS | |
|
582 | WHEN "011" => | |
|
583 | IO8 <= observation_reg(8); | |
|
584 | IO9 <= observation_reg(9); | |
|
585 | IO10 <= observation_reg(10); | |
|
586 | IO11 <= observation_reg(11); | |
|
587 | WHEN "001" => | |
|
588 | IO8 <= observation_reg(8 + 12); | |
|
589 | IO9 <= observation_reg(9 + 12); | |
|
590 | IO10 <= observation_reg(10 + 12); | |
|
591 | IO11 <= observation_reg(11 + 12); | |
|
592 | WHEN "010" => | |
|
593 | IO8 <= '0'; | |
|
594 | IO9 <= '0'; | |
|
595 | IO10 <= '0'; | |
|
596 | IO11 <= '0'; | |
|
597 | WHEN "000" => | |
|
598 | IO8 <= observation_vector_0(8); | |
|
599 | IO9 <= observation_vector_0(9); | |
|
600 | IO10 <= observation_vector_0(10); | |
|
601 | IO11 <= observation_vector_0(11); | |
|
602 | WHEN "100" => | |
|
603 | IO8 <= observation_vector_1(8); | |
|
604 | IO9 <= observation_vector_1(9); | |
|
605 | IO10 <= observation_vector_1(10); | |
|
606 | IO11 <= observation_vector_1(11); | |
|
607 | WHEN OTHERS => NULL; | |
|
608 | END CASE; | |
|
609 | ||
|
610 | END IF; | |
|
611 | END PROCESS; | |
|
612 | ----------------------------------------------------------------------------- | |
|
613 | -- | |
|
614 | ----------------------------------------------------------------------------- | |
|
615 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
|
616 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
|
617 | apbo_ext(I) <= apb_none; | |
|
618 | END GENERATE apbo_ext_not_used; | |
|
619 | END GENERATE all_apbo_ext; | |
|
620 | ||
|
621 | ||
|
622 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
|
623 | ahbo_s_ext(I) <= ahbs_none; | |
|
624 | END GENERATE all_ahbo_ext; | |
|
625 | ||
|
626 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
|
627 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
|
628 | ahbo_m_ext(I) <= ahbm_none; | |
|
629 | END GENERATE ahbo_m_ext_not_used; | |
|
630 | END GENERATE all_ahbo_m_ext; | |
|
631 | ||
|
632 | END beh; No newline at end of file |
@@ -1,52 +1,52 | |||
|
1 | 1 | VHDLIB=../.. |
|
2 | 2 | SCRIPTSDIR=$(VHDLIB)/scripts/ |
|
3 | 3 | GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) |
|
4 | 4 | TOP=MINI_LFR_top |
|
5 | 5 | BOARD=MINI-LFR |
|
6 | 6 | include $(VHDLIB)/boards/$(BOARD)/Makefile.inc |
|
7 | 7 | DEVICE=$(PART)-$(PACKAGE)$(SPEED) |
|
8 | 8 | UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf |
|
9 | 9 | QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf |
|
10 | 10 | EFFORT=high |
|
11 | 11 | XSTOPT= |
|
12 | 12 | SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0" |
|
13 | 13 | VHDLSYNFILES= MINI_LFR_top.vhd |
|
14 | 14 | VHDLSIMFILES= testbench.vhd |
|
15 | 15 | SIMTOP=testbench |
|
16 | 16 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc |
|
17 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc | |
|
18 | SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc | |
|
17 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR_PlaceAndRoute.sdc | |
|
18 | SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR_PlaceAndRoute.sdc | |
|
19 | 19 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
20 | 20 | CLEAN=soft-clean |
|
21 | 21 | |
|
22 | 22 | TECHLIBS = proasic3e |
|
23 | 23 | |
|
24 | 24 | LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \ |
|
25 | 25 | tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX |
|
26 | 26 | |
|
27 | 27 | DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \ |
|
28 | 28 | pci grusbhc haps slink ascs pwm coremp7 spi ac97 \ |
|
29 | 29 | ./amba_lcd_16x2_ctrlr \ |
|
30 | 30 | ./general_purpose/lpp_AMR \ |
|
31 | 31 | ./general_purpose/lpp_balise \ |
|
32 | 32 | ./general_purpose/lpp_delay \ |
|
33 | 33 | ./lpp_bootloader \ |
|
34 | 34 | ./lpp_uart \ |
|
35 | 35 | ./lpp_usb \ |
|
36 | 36 | ./dsp/lpp_fft_rtax \ |
|
37 | 37 | ./lpp_sim/CY7C1061DV33 \ |
|
38 | 38 | |
|
39 | 39 | FILESKIP =i2cmst.vhd \ |
|
40 | 40 | APB_MULTI_DIODE.vhd \ |
|
41 | 41 | APB_SIMPLE_DIODE.vhd \ |
|
42 | 42 | Top_MatrixSpec.vhd \ |
|
43 | 43 | APB_FFT.vhd \ |
|
44 | 44 | CoreFFT_simu.vhd \ |
|
45 | 45 | lpp_lfr_apbreg_simu.vhd \ |
|
46 | 46 | sgmii.vhd |
|
47 | 47 | |
|
48 | 48 | include $(GRLIB)/bin/Makefile |
|
49 | 49 | include $(GRLIB)/software/leon3/Makefile |
|
50 | 50 | |
|
51 | 51 | ################## project specific targets ########################## |
|
52 | 52 |
|
1 | NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/run.do to designs/SOLO_LFR_MINI-LFR/run.do |
|
1 | NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/testbench.vhd to designs/SOLO_LFR_MINI-LFR/testbench.vhd |
|
1 | NO CONTENT: file renamed from designs/MINI-LFR_WFP_MS/wave.do to designs/SOLO_LFR_MINI-LFR/wave.do |
@@ -1,413 +1,420 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | ||
|
17 | constant LPP_LFR_BOARD_MINI_LFR : std_logic_vector(7 downto 0) := X"00"; -- with fpga A3PE3000 | |
|
18 | constant LPP_LFR_BOARD_LFR_EM : std_logic_vector(7 downto 0) := X"01"; -- with fpga A3PE3000 | |
|
19 | constant LPP_LFR_BOARD_LFR_EQM : std_logic_vector(7 downto 0) := X"02"; -- with fpga A3PE3000 | |
|
20 | constant LPP_LFR_BOARD_LFR_FM : std_logic_vector(7 downto 0) := X"03"; -- with fpga RTAX4000D | |
|
21 | constant LPP_LFR_BOARD_DISCOSPACE : std_logic_vector(7 downto 0) := X"04"; -- with fpga A3PE3000 | |
|
22 | ||
|
16 | 23 |
|
|
17 | 24 | -- TEMP |
|
18 | 25 | ----------------------------------------------------------------------------- |
|
19 | 26 | COMPONENT lpp_lfr_ms_test |
|
20 | 27 | GENERIC ( |
|
21 | 28 | Mem_use : INTEGER); |
|
22 | 29 | PORT ( |
|
23 | 30 | clk : IN STD_LOGIC; |
|
24 | 31 | rstn : IN STD_LOGIC; |
|
25 | 32 | |
|
26 | 33 | -- TIME |
|
27 | 34 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
28 | 35 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
29 | 36 | -- |
|
30 | 37 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 38 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 39 | -- |
|
33 | 40 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | 41 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | 42 | -- |
|
36 | 43 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | 44 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | 45 | |
|
39 | 46 | |
|
40 | 47 | |
|
41 | 48 | --------------------------------------------------------------------------- |
|
42 | 49 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
43 | 50 | |
|
44 | 51 | -- |
|
45 | 52 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | 53 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | 54 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 55 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 56 | |
|
50 | 57 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
51 | 58 | |
|
52 | 59 | -- IN |
|
53 | 60 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | 61 | |
|
55 | 62 | ----------------------------------------------------------------------------- |
|
56 | 63 | |
|
57 | 64 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
58 | 65 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
59 | 66 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | 67 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 68 | |
|
62 | 69 | SM_correlation_start : OUT STD_LOGIC; |
|
63 | 70 | SM_correlation_auto : OUT STD_LOGIC; |
|
64 | 71 | SM_correlation_done : IN STD_LOGIC |
|
65 | 72 | ); |
|
66 | 73 | END COMPONENT; |
|
67 | 74 | |
|
68 | 75 | |
|
69 | 76 | ----------------------------------------------------------------------------- |
|
70 | 77 | COMPONENT lpp_lfr_ms |
|
71 | 78 | GENERIC ( |
|
72 | 79 | Mem_use : INTEGER; |
|
73 | 80 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); |
|
74 | 81 | PORT ( |
|
75 | 82 | clk : IN STD_LOGIC; |
|
76 | 83 | rstn : IN STD_LOGIC; |
|
77 | 84 | run : IN STD_LOGIC; |
|
78 | 85 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
79 | 86 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
80 | 87 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
81 | 88 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | 89 | sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
83 | 90 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | 91 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
85 | 92 | sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
86 | 93 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
87 | 94 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | 95 | sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | 96 | dma_fifo_burst_valid : OUT STD_LOGIC; |
|
90 | 97 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 98 | dma_fifo_ren : IN STD_LOGIC; |
|
92 | 99 | dma_buffer_new : OUT STD_LOGIC; |
|
93 | 100 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
94 | 101 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
95 | 102 | dma_buffer_full : IN STD_LOGIC; |
|
96 | 103 | dma_buffer_full_err : IN STD_LOGIC; |
|
97 | 104 | ready_matrix_f0 : OUT STD_LOGIC; |
|
98 | 105 | ready_matrix_f1 : OUT STD_LOGIC; |
|
99 | 106 | ready_matrix_f2 : OUT STD_LOGIC; |
|
100 | 107 | error_buffer_full : OUT STD_LOGIC; |
|
101 | 108 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
102 | 109 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
103 | 110 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
104 | 111 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
105 | 112 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | 113 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
107 | 114 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
108 | 115 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
109 | 116 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
110 | 117 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
111 | 118 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
112 | 119 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
113 | 120 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
114 | 121 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
|
115 | 122 | END COMPONENT; |
|
116 | 123 | |
|
117 | 124 | COMPONENT lpp_lfr_ms_fsmdma |
|
118 | 125 | PORT ( |
|
119 | 126 | clk : IN STD_ULOGIC; |
|
120 | 127 | rstn : IN STD_ULOGIC; |
|
121 | 128 | run : IN STD_LOGIC; |
|
122 | 129 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
123 | 130 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
124 | 131 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
125 | 132 | fifo_empty : IN STD_LOGIC; |
|
126 | 133 | fifo_empty_threshold : IN STD_LOGIC; |
|
127 | 134 | fifo_ren : OUT STD_LOGIC; |
|
128 | 135 | dma_fifo_valid_burst : OUT STD_LOGIC; |
|
129 | 136 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | 137 | dma_fifo_ren : IN STD_LOGIC; |
|
131 | 138 | dma_buffer_new : OUT STD_LOGIC; |
|
132 | 139 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 140 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
134 | 141 | dma_buffer_full : IN STD_LOGIC; |
|
135 | 142 | dma_buffer_full_err : IN STD_LOGIC; |
|
136 | 143 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
137 | 144 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
138 | 145 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
139 | 146 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | 147 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
141 | 148 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
142 | 149 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
143 | 150 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
144 | 151 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
145 | 152 | ready_matrix_f0 : OUT STD_LOGIC; |
|
146 | 153 | ready_matrix_f1 : OUT STD_LOGIC; |
|
147 | 154 | ready_matrix_f2 : OUT STD_LOGIC; |
|
148 | 155 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
149 | 156 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
150 | 157 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
151 | 158 | error_buffer_full : OUT STD_LOGIC); |
|
152 | 159 | END COMPONENT; |
|
153 | 160 | |
|
154 | 161 | COMPONENT lpp_lfr_ms_FFT |
|
155 | 162 | GENERIC ( |
|
156 | 163 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER); |
|
157 | 164 | PORT ( |
|
158 | 165 | clk : IN STD_LOGIC; |
|
159 | 166 | rstn : IN STD_LOGIC; |
|
160 | 167 | sample_valid : IN STD_LOGIC; |
|
161 | 168 | fft_read : IN STD_LOGIC; |
|
162 | 169 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
163 | 170 | sample_load : OUT STD_LOGIC; |
|
164 | 171 | fft_pong : OUT STD_LOGIC; |
|
165 | 172 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
166 | 173 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
167 | 174 | fft_data_valid : OUT STD_LOGIC; |
|
168 | 175 | fft_ready : OUT STD_LOGIC); |
|
169 | 176 | END COMPONENT; |
|
170 | 177 | |
|
171 | 178 | COMPONENT lpp_lfr_filter |
|
172 | 179 | GENERIC ( |
|
173 | 180 | tech : INTEGER; |
|
174 | 181 | Mem_use : INTEGER; |
|
175 | 182 | RTL_DESIGN_LIGHT : INTEGER |
|
176 | 183 | ); |
|
177 | 184 | PORT ( |
|
178 | 185 | sample : IN Samples(7 DOWNTO 0); |
|
179 | 186 | sample_val : IN STD_LOGIC; |
|
180 | 187 | sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
181 | 188 | clk : IN STD_LOGIC; |
|
182 | 189 | rstn : IN STD_LOGIC; |
|
183 | 190 | data_shaping_SP0 : IN STD_LOGIC; |
|
184 | 191 | data_shaping_SP1 : IN STD_LOGIC; |
|
185 | 192 | data_shaping_R0 : IN STD_LOGIC; |
|
186 | 193 | data_shaping_R1 : IN STD_LOGIC; |
|
187 | 194 | data_shaping_R2 : IN STD_LOGIC; |
|
188 | 195 | sample_f0_val : OUT STD_LOGIC; |
|
189 | 196 | sample_f1_val : OUT STD_LOGIC; |
|
190 | 197 | sample_f2_val : OUT STD_LOGIC; |
|
191 | 198 | sample_f3_val : OUT STD_LOGIC; |
|
192 | 199 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
193 | 200 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
194 | 201 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
195 | 202 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
196 | 203 | sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
197 | 204 | sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
198 | 205 | sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
199 | 206 | sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
200 | 207 | ); |
|
201 | 208 | END COMPONENT; |
|
202 | 209 | |
|
203 | 210 | COMPONENT lpp_lfr |
|
204 | 211 | GENERIC ( |
|
205 | 212 | Mem_use : INTEGER; |
|
206 | 213 | tech : INTEGER; |
|
207 | 214 | nb_data_by_buffer_size : INTEGER; |
|
208 | 215 | -- nb_word_by_buffer_size : INTEGER; |
|
209 | 216 | nb_snapshot_param_size : INTEGER; |
|
210 | 217 | delta_vector_size : INTEGER; |
|
211 | 218 | delta_vector_size_f0_2 : INTEGER; |
|
212 | 219 | pindex : INTEGER; |
|
213 | 220 | paddr : INTEGER; |
|
214 | 221 | pmask : INTEGER; |
|
215 | 222 | pirq_ms : INTEGER; |
|
216 | 223 | pirq_wfp : INTEGER; |
|
217 | 224 | hindex : INTEGER; |
|
218 | 225 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0); |
|
219 | 226 | DEBUG_FORCE_DATA_DMA : INTEGER; |
|
220 | 227 | RTL_DESIGN_LIGHT : INTEGER; |
|
221 | 228 | WINDOWS_HAANNING_PARAM_SIZE : INTEGER |
|
222 | 229 | ); |
|
223 | 230 | PORT ( |
|
224 | 231 | clk : IN STD_LOGIC; |
|
225 | 232 | rstn : IN STD_LOGIC; |
|
226 | 233 | sample_B : IN Samples(2 DOWNTO 0); |
|
227 | 234 | sample_E : IN Samples(4 DOWNTO 0); |
|
228 | 235 | sample_val : IN STD_LOGIC; |
|
229 | 236 | apbi : IN apb_slv_in_type; |
|
230 | 237 | apbo : OUT apb_slv_out_type; |
|
231 | 238 | ahbi : IN AHB_Mst_In_Type; |
|
232 | 239 | ahbo : OUT AHB_Mst_Out_Type; |
|
233 | 240 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
234 | 241 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
235 | 242 | data_shaping_BW : OUT STD_LOGIC; |
|
236 | 243 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); |
|
237 | 244 | debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
238 | 245 | ); |
|
239 | 246 | END COMPONENT; |
|
240 | 247 | |
|
241 | 248 | ----------------------------------------------------------------------------- |
|
242 | 249 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
243 | 250 | ----------------------------------------------------------------------------- |
|
244 | 251 | COMPONENT lpp_lfr_WFP_nMS |
|
245 | 252 | GENERIC ( |
|
246 | 253 | Mem_use : INTEGER; |
|
247 | 254 | nb_data_by_buffer_size : INTEGER; |
|
248 | 255 | nb_word_by_buffer_size : INTEGER; |
|
249 | 256 | nb_snapshot_param_size : INTEGER; |
|
250 | 257 | delta_vector_size : INTEGER; |
|
251 | 258 | delta_vector_size_f0_2 : INTEGER; |
|
252 | 259 | pindex : INTEGER; |
|
253 | 260 | paddr : INTEGER; |
|
254 | 261 | pmask : INTEGER; |
|
255 | 262 | pirq_ms : INTEGER; |
|
256 | 263 | pirq_wfp : INTEGER; |
|
257 | 264 | hindex : INTEGER; |
|
258 | 265 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
259 | 266 | PORT ( |
|
260 | 267 | clk : IN STD_LOGIC; |
|
261 | 268 | rstn : IN STD_LOGIC; |
|
262 | 269 | sample_B : IN Samples(2 DOWNTO 0); |
|
263 | 270 | sample_E : IN Samples(4 DOWNTO 0); |
|
264 | 271 | sample_val : IN STD_LOGIC; |
|
265 | 272 | apbi : IN apb_slv_in_type; |
|
266 | 273 | apbo : OUT apb_slv_out_type; |
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267 | 274 | ahbi : IN AHB_Mst_In_Type; |
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268 | 275 | ahbo : OUT AHB_Mst_Out_Type; |
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269 | 276 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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270 | 277 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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271 | 278 | data_shaping_BW : OUT STD_LOGIC; |
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272 | 279 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
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273 | 280 | END COMPONENT; |
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274 | 281 | ----------------------------------------------------------------------------- |
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275 | 282 | |
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276 | 283 | COMPONENT lpp_lfr_apbreg |
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277 | 284 | GENERIC ( |
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278 | 285 | nb_data_by_buffer_size : INTEGER; |
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279 | 286 | nb_snapshot_param_size : INTEGER; |
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280 | 287 | delta_vector_size : INTEGER; |
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281 | 288 | delta_vector_size_f0_2 : INTEGER; |
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282 | 289 | pindex : INTEGER; |
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283 | 290 | paddr : INTEGER; |
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284 | 291 | pmask : INTEGER; |
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285 | 292 | pirq_ms : INTEGER; |
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286 | 293 | pirq_wfp : INTEGER; |
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287 | 294 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
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288 | 295 | PORT ( |
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289 | 296 | HCLK : IN STD_ULOGIC; |
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290 | 297 | HRESETn : IN STD_ULOGIC; |
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291 | 298 | apbi : IN apb_slv_in_type; |
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292 | 299 | apbo : OUT apb_slv_out_type; |
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293 | 300 | -- run_ms : OUT STD_LOGIC; |
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294 | 301 | ready_matrix_f0 : IN STD_LOGIC; |
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295 | 302 | ready_matrix_f1 : IN STD_LOGIC; |
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296 | 303 | ready_matrix_f2 : IN STD_LOGIC; |
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297 | 304 | error_buffer_full : IN STD_LOGIC; |
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298 | 305 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
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299 | 306 | status_ready_matrix_f0 : OUT STD_LOGIC; |
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300 | 307 | status_ready_matrix_f1 : OUT STD_LOGIC; |
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301 | 308 | status_ready_matrix_f2 : OUT STD_LOGIC; |
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302 | 309 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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303 | 310 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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304 | 311 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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305 | 312 | length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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306 | 313 | length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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307 | 314 | length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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308 | 315 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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309 | 316 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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310 | 317 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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311 | 318 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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312 | 319 | data_shaping_BW : OUT STD_LOGIC; |
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313 | 320 | data_shaping_SP0 : OUT STD_LOGIC; |
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314 | 321 | data_shaping_SP1 : OUT STD_LOGIC; |
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315 | 322 | data_shaping_R0 : OUT STD_LOGIC; |
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316 | 323 | data_shaping_R1 : OUT STD_LOGIC; |
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317 | 324 | data_shaping_R2 : OUT STD_LOGIC; |
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318 | 325 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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319 | 326 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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320 | 327 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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321 | 328 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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322 | 329 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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323 | 330 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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324 | 331 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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325 | 332 | enable_f0 : OUT STD_LOGIC; |
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326 | 333 | enable_f1 : OUT STD_LOGIC; |
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327 | 334 | enable_f2 : OUT STD_LOGIC; |
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328 | 335 | enable_f3 : OUT STD_LOGIC; |
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329 | 336 | burst_f0 : OUT STD_LOGIC; |
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330 | 337 | burst_f1 : OUT STD_LOGIC; |
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331 | 338 | burst_f2 : OUT STD_LOGIC; |
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332 | 339 | run : OUT STD_LOGIC; |
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333 | 340 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); |
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334 | 341 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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335 | 342 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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336 | 343 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
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337 | 344 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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338 | 345 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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339 | 346 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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340 | 347 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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341 | 348 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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342 | 349 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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343 | 350 | sample_f3_valid : IN STD_LOGIC; |
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344 | 351 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)); |
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345 | 352 | END COMPONENT; |
|
346 | 353 | |
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347 | 354 | COMPONENT lpp_top_ms |
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348 | 355 | GENERIC ( |
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349 | 356 | Mem_use : INTEGER; |
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350 | 357 | nb_burst_available_size : INTEGER; |
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351 | 358 | nb_snapshot_param_size : INTEGER; |
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352 | 359 | delta_snapshot_size : INTEGER; |
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353 | 360 | delta_f2_f0_size : INTEGER; |
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354 | 361 | delta_f2_f1_size : INTEGER; |
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355 | 362 | pindex : INTEGER; |
|
356 | 363 | paddr : INTEGER; |
|
357 | 364 | pmask : INTEGER; |
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358 | 365 | pirq_ms : INTEGER; |
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359 | 366 | pirq_wfp : INTEGER; |
|
360 | 367 | hindex_wfp : INTEGER; |
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361 | 368 | hindex_ms : INTEGER); |
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362 | 369 | PORT ( |
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363 | 370 | clk : IN STD_LOGIC; |
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364 | 371 | rstn : IN STD_LOGIC; |
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365 | 372 | sample_B : IN Samples14v(2 DOWNTO 0); |
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366 | 373 | sample_E : IN Samples14v(4 DOWNTO 0); |
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367 | 374 | sample_val : IN STD_LOGIC; |
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368 | 375 | apbi : IN apb_slv_in_type; |
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369 | 376 | apbo : OUT apb_slv_out_type; |
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370 | 377 | ahbi_ms : IN AHB_Mst_In_Type; |
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371 | 378 | ahbo_ms : OUT AHB_Mst_Out_Type; |
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372 | 379 | data_shaping_BW : OUT STD_LOGIC; |
|
373 | 380 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
374 | 381 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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375 | 382 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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376 | 383 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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377 | 384 | ); |
|
378 | 385 | END COMPONENT; |
|
379 | 386 | |
|
380 | 387 | COMPONENT lpp_apbreg_ms_pointer |
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381 | 388 | PORT ( |
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382 | 389 | clk : IN STD_LOGIC; |
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383 | 390 | rstn : IN STD_LOGIC; |
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384 | 391 | run : IN STD_LOGIC; |
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385 | 392 | reg0_status_ready_matrix : IN STD_LOGIC; |
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386 | 393 | reg0_ready_matrix : OUT STD_LOGIC; |
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387 | 394 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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388 | 395 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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389 | 396 | reg1_status_ready_matrix : IN STD_LOGIC; |
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390 | 397 | reg1_ready_matrix : OUT STD_LOGIC; |
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391 | 398 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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392 | 399 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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393 | 400 | ready_matrix : IN STD_LOGIC; |
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394 | 401 | status_ready_matrix : OUT STD_LOGIC; |
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395 | 402 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
396 | 403 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
397 | 404 | END COMPONENT; |
|
398 | 405 | |
|
399 | 406 | COMPONENT lpp_lfr_ms_reg_head |
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400 | 407 | PORT ( |
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401 | 408 | clk : IN STD_LOGIC; |
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402 | 409 | rstn : IN STD_LOGIC; |
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403 | 410 | in_wen : IN STD_LOGIC; |
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404 | 411 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
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405 | 412 | in_full : IN STD_LOGIC; |
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406 | 413 | in_empty : IN STD_LOGIC; |
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407 | 414 | out_write_error : OUT STD_LOGIC; |
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408 | 415 | out_wen : OUT STD_LOGIC; |
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409 | 416 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
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410 | 417 | out_full : OUT STD_LOGIC); |
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411 | 418 | END COMPONENT; |
|
412 | 419 | |
|
413 | 420 | END lpp_lfr_pkg; |
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1 | NO CONTENT: file was removed |
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1 | NO CONTENT: file was removed |
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