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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Alexis Jeandet |
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20 | 20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
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21 | 21 | ---------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY lpp; |
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26 | 26 | USE lpp.iir_filter.ALL; |
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27 | 27 | USE lpp.FILTERcfg.ALL; |
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28 | 28 | USE lpp.general_purpose.ALL; |
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29 | 29 | LIBRARY techmap; |
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30 | 30 | USE techmap.gencomp.ALL; |
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31 | 31 | |
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32 | 32 | ENTITY RAM_CTRLR_v2 IS |
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33 | 33 | GENERIC( |
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34 | 34 | tech : INTEGER := 0; |
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35 | 35 | Input_SZ_1 : INTEGER := 16; |
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36 | 36 | Mem_use : INTEGER := use_RAM; |
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37 | 37 | FILENAME : STRING:= "" |
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38 | 38 | ); |
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39 | 39 | PORT( |
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40 | 40 | rstn : IN STD_LOGIC; |
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41 | 41 | clk : IN STD_LOGIC; |
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42 | 42 | -- ram init done |
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43 | 43 | init_mem_done: out STD_LOGIC; |
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44 | 44 | -- R/W Ctrl |
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45 | 45 | ram_write : IN STD_LOGIC; |
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46 | 46 | ram_read : IN STD_LOGIC; |
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47 | 47 | -- ADDR Ctrl |
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48 | 48 | raddr_rst : IN STD_LOGIC; |
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49 | 49 | raddr_add1 : IN STD_LOGIC; |
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50 | 50 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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51 | 51 | -- Data |
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52 | 52 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
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53 | 53 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) |
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54 | 54 | ); |
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55 | 55 | END RAM_CTRLR_v2; |
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56 | 56 | |
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57 | 57 | |
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58 | 58 | ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS |
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59 | 59 | |
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60 | 60 | SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
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61 | 61 | SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); |
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62 | 62 | SIGNAL WEN, REN : STD_LOGIC; |
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63 | 63 | SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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64 | 64 | SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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65 | 65 | SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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66 | 66 | |
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67 | 67 | signal rst_mem_done_s : std_logic; |
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68 | 68 | signal ram_write_s : std_logic; |
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69 | 69 | |
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70 | 70 | BEGIN |
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71 | 71 | |
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72 | 72 | init_mem_done <= rst_mem_done_s; |
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73 | 73 | |
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74 | 74 | sample_out <= RD(Input_SZ_1-1 DOWNTO 0) when rst_mem_done_s = '1' else (others => '0'); |
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75 | 75 | WD(Input_SZ_1-1 DOWNTO 0) <= sample_in when rst_mem_done_s = '1' else (others => '0'); |
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76 | 76 | ram_write_s <= ram_write when rst_mem_done_s = '1' else '1'; |
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77 | 77 | ----------------------------------------------------------------------------- |
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78 | 78 | -- RAM |
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79 | 79 | ----------------------------------------------------------------------------- |
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80 | 80 | |
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81 | 81 | memCEL : IF Mem_use = use_CEL GENERATE |
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82 | 82 | WEN <= NOT ram_write_s; |
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83 | 83 | REN <= NOT ram_read; |
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84 | 84 | RAMblk : RAM_CEL |
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85 | 85 | GENERIC MAP(Input_SZ_1, 8,FILENAME) |
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86 | 86 | PORT MAP( |
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87 | 87 | WD => WD, |
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88 | 88 | RD => RD, |
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89 | 89 | WEN => WEN, |
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90 | 90 | REN => REN, |
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91 | 91 | WADDR => WADDR, |
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92 | 92 | RADDR => RADDR, |
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93 | 93 | RWCLK => clk, |
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94 | 94 | RESET => rstn |
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95 | 95 | ) ; |
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96 | 96 | END GENERATE; |
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97 | 97 | |
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98 | 98 | memRAM : IF Mem_use = use_RAM GENERATE |
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99 | 99 | SRAM : syncram_2p |
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100 | 100 | GENERIC MAP(tech, 8, Input_SZ_1) |
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101 | 101 | PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write_s, WADDR, WD); |
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102 | 102 | END GENERATE; |
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103 | 103 | |
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104 | 104 | ----------------------------------------------------------------------------- |
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105 | 105 | -- RADDR |
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106 | 106 | ----------------------------------------------------------------------------- |
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107 | 107 | PROCESS (clk, rstn) |
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108 | 108 | BEGIN -- PROCESS |
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109 | 109 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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110 | 110 | counter <= (OTHERS => '0'); |
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111 |
rst_mem_done_s <= ' |
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111 | rst_mem_done_s <= '1'; | |
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112 | 112 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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113 | if rst_mem_done_s = '0' then | |
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113 | IF raddr_rst = '1' THEN | |
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114 | counter <= (OTHERS => '0'); | |
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115 | ELSIF raddr_add1 = '1' THEN | |
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114 | 116 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); |
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115 | else | |
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116 | IF raddr_rst = '1' THEN | |
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117 | counter <= (OTHERS => '0'); | |
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118 | ELSIF raddr_add1 = '1' THEN | |
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119 | counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); | |
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120 | END IF; | |
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121 | end if; | |
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122 | if counter = x"FF" then | |
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123 | rst_mem_done_s <= '1'; | |
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124 | end if; | |
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125 | ||
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117 | END IF; | |
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126 | 118 | END IF; |
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127 | 119 | END PROCESS; |
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128 | 120 | RADDR <= counter; |
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129 | 121 | |
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130 | 122 | ----------------------------------------------------------------------------- |
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131 | 123 | -- WADDR |
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132 | 124 | ----------------------------------------------------------------------------- |
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133 | 125 | WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)) when rst_mem_done_s = '0' else |
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134 | 126 | STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE |
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135 | 127 | STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE |
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136 | 128 | STD_LOGIC_VECTOR(UNSIGNED(counter)); |
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137 | 129 | |
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138 | 130 | |
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139 | 131 | END ar_RAM_CTRLR_v2; |
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