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1 | 1 | ----------------------------------------------------------------------------- |
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2 | 2 | -- LEON3 Demonstration design |
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3 | 3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 2 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | 19 | |
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20 | 20 | |
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21 | 21 | library ieee; |
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22 | 22 | use ieee.std_logic_1164.all; |
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23 | 23 | library grlib; |
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24 | 24 | use grlib.amba.all; |
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25 | 25 | use grlib.stdlib.all; |
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26 | 26 | library techmap; |
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27 | 27 | use techmap.gencomp.all; |
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28 | 28 | library gaisler; |
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29 | 29 | use gaisler.memctrl.all; |
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30 | 30 | use gaisler.leon3.all; |
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31 | 31 | use gaisler.uart.all; |
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32 | 32 | use gaisler.misc.all; |
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33 | 33 | library esa; |
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34 | 34 | use esa.memoryctrl.all; |
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35 | 35 | use work.config.all; |
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36 | 36 | library lpp; |
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37 | 37 | use lpp.lpp_amba.all; |
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38 | 38 | use lpp.lpp_memory.all; |
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39 | 39 | use lpp.lpp_uart.all; |
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40 | 40 | use lpp.lpp_matrix.all; |
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41 | 41 | use lpp.lpp_delay.all; |
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42 | 42 | use lpp.lpp_fft.all; |
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43 | 43 | use lpp.fft_components.all; |
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44 | 44 | use lpp.lpp_ad_conv.all; |
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45 | 45 | use lpp.iir_filter.all; |
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46 | 46 | use lpp.general_purpose.all; |
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47 | 47 | use lpp.Filtercfg.all; |
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48 | 48 | use lpp.lpp_cna.all; |
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49 | 49 | |
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50 | 50 | entity leon3mp is |
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51 | 51 | generic ( |
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52 | 52 | fabtech : integer := CFG_FABTECH; |
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53 | 53 | memtech : integer := CFG_MEMTECH; |
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54 | 54 | padtech : integer := CFG_PADTECH; |
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55 | 55 | clktech : integer := CFG_CLKTECH; |
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56 | 56 | disas : integer := CFG_DISAS; -- Enable disassembly to console |
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57 | 57 | dbguart : integer := CFG_DUART; -- Print UART on console |
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58 | 58 | pclow : integer := CFG_PCLOW |
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59 | 59 | ); |
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60 | 60 | port ( |
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61 | 61 | clk50MHz : in std_ulogic; |
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62 | 62 | reset : in std_ulogic; |
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63 | 63 | ramclk : out std_logic; |
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64 | 64 | |
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65 | 65 | ahbrxd : in std_ulogic; -- DSU rx data |
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66 | 66 | ahbtxd : out std_ulogic; -- DSU tx data |
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67 | 67 | dsubre : in std_ulogic; |
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68 | 68 | dsuact : out std_ulogic; |
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69 | 69 | urxd1 : in std_ulogic; -- UART1 rx data |
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70 | 70 | utxd1 : out std_ulogic; -- UART1 tx data |
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71 | 71 | errorn : out std_ulogic; |
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72 | 72 | |
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73 | 73 | address : out std_logic_vector(18 downto 0); |
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74 | 74 | data : inout std_logic_vector(31 downto 0); |
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75 | 75 | gpio : inout std_logic_vector(6 downto 0); -- I/O port |
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76 | 76 | |
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77 | 77 | nBWa : out std_logic; |
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78 | 78 | nBWb : out std_logic; |
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79 | 79 | nBWc : out std_logic; |
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80 | 80 | nBWd : out std_logic; |
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81 | 81 | nBWE : out std_logic; |
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82 | 82 | nADSC : out std_logic; |
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83 | 83 | nADSP : out std_logic; |
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84 | 84 | nADV : out std_logic; |
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85 | 85 | nGW : out std_logic; |
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86 | 86 | nCE1 : out std_logic; |
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87 | 87 | CE2 : out std_logic; |
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88 | 88 | nCE3 : out std_logic; |
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89 | 89 | nOE : out std_logic; |
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90 | 90 | MODE : out std_logic; |
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91 | 91 | SSRAM_CLK : out std_logic; |
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92 | 92 | ZZ : out std_logic; |
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93 | 93 | --------------------------------------------------------------------- |
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94 | 94 | --- AJOUT TEST ------------------------In/Out----------------------- |
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95 | 95 | --------------------------------------------------------------------- |
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96 | 96 | -- DAC |
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97 | DAC_EN : out std_logic; | |
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97 | 98 | DAC_SYNC : out std_logic; |
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98 | 99 | DAC_SCLK : out std_logic; |
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99 | 100 | DAC_DATA : out std_logic; |
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100 | 101 | -- UART |
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101 | 102 | UART_RXD : in std_logic; |
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102 | 103 | UART_TXD : out std_logic; |
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103 | 104 | --------------------------------------------------------------------- |
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104 | 105 | led : out std_logic_vector(1 downto 0) |
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105 | 106 | ); |
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106 | 107 | end; |
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107 | 108 | |
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108 | 109 | architecture Behavioral of leon3mp is |
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109 | 110 | |
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110 | 111 | constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+ |
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111 | 112 | CFG_GRETH+CFG_AHB_JTAG; |
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112 | 113 | constant maxahbm : integer := maxahbmsp; |
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113 | 114 | |
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114 | 115 | --Clk & Rst gοΏ½nοΏ½ |
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115 | 116 | signal vcc : std_logic_vector(4 downto 0); |
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116 | 117 | signal gnd : std_logic_vector(4 downto 0); |
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117 | 118 | signal resetnl : std_ulogic; |
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118 | 119 | signal clk2x : std_ulogic; |
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119 | 120 | signal lclk : std_ulogic; |
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120 | 121 | signal lclk2x : std_ulogic; |
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121 | 122 | signal clkm : std_ulogic; |
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122 | 123 | signal rstn : std_ulogic; |
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123 | 124 | signal rstraw : std_ulogic; |
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124 | 125 | signal pciclk : std_ulogic; |
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125 | 126 | signal sdclkl : std_ulogic; |
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126 | 127 | signal cgi : clkgen_in_type; |
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127 | 128 | signal cgo : clkgen_out_type; |
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128 | 129 | --- AHB / APB |
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129 | 130 | signal apbi : apb_slv_in_type; |
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130 | 131 | signal apbo : apb_slv_out_vector := (others => apb_none); |
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131 | 132 | signal ahbsi : ahb_slv_in_type; |
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132 | 133 | signal ahbso : ahb_slv_out_vector := (others => ahbs_none); |
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133 | 134 | signal ahbmi : ahb_mst_in_type; |
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134 | 135 | signal ahbmo : ahb_mst_out_vector := (others => ahbm_none); |
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135 | 136 | --UART |
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136 | 137 | signal ahbuarti : uart_in_type; |
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137 | 138 | signal ahbuarto : uart_out_type; |
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138 | 139 | signal apbuarti : uart_in_type; |
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139 | 140 | signal apbuarto : uart_out_type; |
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140 | 141 | --MEM CTRLR |
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141 | 142 | signal memi : memory_in_type; |
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142 | 143 | signal memo : memory_out_type; |
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143 | 144 | signal wpo : wprot_out_type; |
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144 | 145 | signal sdo : sdram_out_type; |
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145 | 146 | --IRQ |
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146 | 147 | signal irqi : irq_in_vector(0 to CFG_NCPU-1); |
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147 | 148 | signal irqo : irq_out_vector(0 to CFG_NCPU-1); |
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148 | 149 | --Timer |
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149 | 150 | signal gpti : gptimer_in_type; |
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150 | 151 | signal gpto : gptimer_out_type; |
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151 | 152 | --GPIO |
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152 | 153 | signal gpioi : gpio_in_type; |
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153 | 154 | signal gpioo : gpio_out_type; |
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154 | 155 | --DSU |
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155 | 156 | signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1); |
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156 | 157 | signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1); |
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157 | 158 | signal dsui : dsu_in_type; |
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158 | 159 | signal dsuo : dsu_out_type; |
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159 | 160 | |
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160 | 161 | --------------------------------------------------------------------- |
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161 | 162 | --- AJOUT TEST ------------------------Signaux---------------------- |
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162 | 163 | --------------------------------------------------------------------- |
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163 | 164 | |
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164 | 165 | --------------------------------------------------------------------- |
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165 | 166 | constant IOAEN : integer := CFG_CAN; |
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166 | 167 | constant boardfreq : integer := 50000; |
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167 | 168 | |
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168 | 169 | begin |
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169 | 170 | |
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170 | 171 | --------------------------------------------------------------------- |
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171 | 172 | --- AJOUT TEST -------------------------------------IPs------------- |
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172 | 173 | --------------------------------------------------------------------- |
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173 | 174 | |
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174 | 175 | -- apbo not free : 0 1 2 3 7 11 |
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175 | 176 | |
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176 | 177 | --- DAC ------------------------------------------------------------- |
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177 | 178 | |
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178 | 179 | CAL0 : APB_CNA |
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179 | 180 | generic map (pindex => 4, paddr => 4) |
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180 | port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA); | |
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181 | port map(clkm,rstn,apbi,apbo(4),DAC_EN,DAC_SYNC,DAC_SCLK,DAC_DATA); | |
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181 | 182 | |
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182 | 183 | |
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183 | 184 | --- UART ------------------------------------------------------------- |
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184 | 185 | |
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185 | 186 | COM0 : APB_UART |
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186 | 187 | generic map (pindex => 5, paddr => 5) |
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187 | 188 | port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD); |
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188 | 189 | |
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189 | 190 | |
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190 | 191 | --- FIFO ------------------------------------------------------------- |
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191 | 192 | |
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192 | 193 | Memtest : APB_FIFO |
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193 | 194 | generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1) |
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194 | 195 | port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6)); |
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195 | 196 | |
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196 | 197 | |
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197 | 198 | ---------------------------------------------------------------------- |
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198 | 199 | --- Reset and Clock generation ------------------------------------- |
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199 | 200 | ---------------------------------------------------------------------- |
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200 | 201 | |
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201 | 202 | vcc <= (others => '1'); gnd <= (others => '0'); |
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202 | 203 | cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; |
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203 | 204 | |
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204 | 205 | rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw); |
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205 | 206 | |
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206 | 207 | |
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207 | 208 | clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x); |
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208 | 209 | |
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209 | 210 | clkgen0 : clkgen -- clock generator |
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210 | 211 | generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, |
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211 | 212 | CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV) |
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212 | 213 | port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo); |
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213 | 214 | |
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214 | 215 | ramclk <= clkm; |
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215 | 216 | process(lclk2x) |
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216 | 217 | begin |
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217 | 218 | if lclk2x'event and lclk2x = '1' then |
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218 | 219 | lclk <= not lclk; |
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219 | 220 | end if; |
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220 | 221 | end process; |
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221 | 222 | |
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222 | 223 | ---------------------------------------------------------------------- |
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223 | 224 | --- LEON3 processor / DSU / IRQ ------------------------------------ |
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224 | 225 | ---------------------------------------------------------------------- |
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225 | 226 | |
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226 | 227 | l3 : if CFG_LEON3 = 1 generate |
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227 | 228 | cpu : for i in 0 to CFG_NCPU-1 generate |
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228 | 229 | u0 : leon3s -- LEON3 processor |
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229 | 230 | generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8, |
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230 | 231 | 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE, |
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231 | 232 | CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ, |
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232 | 233 | CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN, |
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233 | 234 | CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP, |
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234 | 235 | CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1) |
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235 | 236 | port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, |
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236 | 237 | irqi(i), irqo(i), dbgi(i), dbgo(i)); |
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237 | 238 | end generate; |
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238 | 239 | errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error); |
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239 | 240 | |
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240 | 241 | dsugen : if CFG_DSU = 1 generate |
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241 | 242 | dsu0 : dsu3 -- LEON3 Debug Support Unit |
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242 | 243 | generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#, |
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243 | 244 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) |
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244 | 245 | port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); |
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245 | 246 | -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable); |
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246 | 247 | dsui.enable <= '1'; |
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247 | 248 | dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break); |
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248 | 249 | dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active); |
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249 | 250 | end generate; |
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250 | 251 | end generate; |
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251 | 252 | |
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252 | 253 | nodsu : if CFG_DSU = 0 generate |
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253 | 254 | ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0'; |
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254 | 255 | end generate; |
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255 | 256 | |
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256 | 257 | irqctrl : if CFG_IRQ3_ENABLE /= 0 generate |
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257 | 258 | irqctrl0 : irqmp -- interrupt controller |
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258 | 259 | generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU) |
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259 | 260 | port map (rstn, clkm, apbi, apbo(2), irqo, irqi); |
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260 | 261 | end generate; |
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261 | 262 | irq3 : if CFG_IRQ3_ENABLE = 0 generate |
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262 | 263 | x : for i in 0 to CFG_NCPU-1 generate |
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263 | 264 | irqi(i).irl <= "0000"; |
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264 | 265 | end generate; |
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265 | 266 | apbo(2) <= apb_none; |
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266 | 267 | end generate; |
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267 | 268 | |
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268 | 269 | ---------------------------------------------------------------------- |
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269 | 270 | --- Memory controllers --------------------------------------------- |
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270 | 271 | ---------------------------------------------------------------------- |
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271 | 272 | |
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272 | 273 | memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0) |
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273 | 274 | port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo); |
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274 | 275 | |
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275 | 276 | memi.brdyn <= '1'; memi.bexcn <= '1'; |
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276 | 277 | memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10"; |
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277 | 278 | |
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278 | 279 | bdr : for i in 0 to 3 generate |
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279 | 280 | data_pad : iopadv generic map (tech => padtech, width => 8) |
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280 | 281 | port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8), |
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281 | 282 | memo.bdrive(i), memi.data(31-i*8 downto 24-i*8)); |
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282 | 283 | end generate; |
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283 | 284 | |
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284 | 285 | |
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285 | 286 | addr_pad : outpadv generic map (width => 19, tech => padtech) |
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286 | 287 | port map (address, memo.address(20 downto 2)); |
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287 | 288 | |
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288 | 289 | |
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289 | 290 | SSRAM_0:entity ssram_plugin |
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290 | 291 | generic map (tech => padtech) |
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291 | 292 | port map |
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292 | 293 | (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ); |
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293 | 294 | |
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294 | 295 | ---------------------------------------------------------------------- |
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295 | 296 | --- AHB CONTROLLER ------------------------------------------------- |
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296 | 297 | ---------------------------------------------------------------------- |
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297 | 298 | |
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298 | 299 | ahb0 : ahbctrl -- AHB arbiter/multiplexer |
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299 | 300 | generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, |
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300 | 301 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, |
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301 | 302 | ioen => IOAEN, nahbm => maxahbm, nahbs => 8) |
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302 | 303 | port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); |
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303 | 304 | |
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304 | 305 | ---------------------------------------------------------------------- |
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305 | 306 | --- AHB UART ------------------------------------------------------- |
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306 | 307 | ---------------------------------------------------------------------- |
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307 | 308 | |
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308 | 309 | dcomgen : if CFG_AHB_UART = 1 generate |
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309 | 310 | dcom0: ahbuart -- Debug UART |
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310 | 311 | generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7) |
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311 | 312 | port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU)); |
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312 | 313 | dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd); |
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313 | 314 | dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd); |
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314 | 315 | -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd; |
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315 | 316 | end generate; |
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316 | 317 | nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate; |
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317 | 318 | |
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318 | 319 | ---------------------------------------------------------------------- |
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319 | 320 | --- APB Bridge ----------------------------------------------------- |
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320 | 321 | ---------------------------------------------------------------------- |
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321 | 322 | |
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322 | 323 | apb0 : apbctrl -- AHB/APB bridge |
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323 | 324 | generic map (hindex => 1, haddr => CFG_APBADDR) |
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324 | 325 | port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo ); |
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325 | 326 | |
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326 | 327 | ---------------------------------------------------------------------- |
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327 | 328 | --- GPT Timer ------------------------------------------------------ |
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328 | 329 | ---------------------------------------------------------------------- |
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329 | 330 | |
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330 | 331 | gpt : if CFG_GPT_ENABLE /= 0 generate |
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331 | 332 | timer0 : gptimer -- timer unit |
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332 | 333 | generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, |
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333 | 334 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, |
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334 | 335 | nbits => CFG_GPT_TW) |
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335 | 336 | port map (rstn, clkm, apbi, apbo(3), gpti, gpto); |
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336 | 337 | gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0'; |
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337 | 338 | -- led(4) <= gpto.wdog; |
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338 | 339 | end generate; |
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339 | 340 | notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate; |
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340 | 341 | |
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341 | 342 | |
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342 | 343 | ---------------------------------------------------------------------- |
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343 | 344 | --- APB UART ------------------------------------------------------- |
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344 | 345 | ---------------------------------------------------------------------- |
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345 | 346 | |
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346 | 347 | ua1 : if CFG_UART1_ENABLE /= 0 generate |
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347 | 348 | uart1 : apbuart -- UART 1 |
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348 | 349 | generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, |
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349 | 350 | fifosize => CFG_UART1_FIFO) |
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350 | 351 | port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto); |
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351 | 352 | apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd; |
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352 | 353 | apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn; |
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353 | 354 | -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd; |
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354 | 355 | end generate; |
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355 | 356 | noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate; |
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356 | 357 | |
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357 | 358 | ---------------------------------------------------------------------- |
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358 | 359 | --- GPIO ----------------------------------------------------------- |
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359 | 360 | ---------------------------------------------------------------------- |
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360 | 361 | led(0) <= gpio(0); led(1) <= gpio(1); |
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361 | 362 | |
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362 | 363 | gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit |
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363 | 364 | grgpio0: grgpio |
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364 | 365 | generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7) |
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365 | 366 | port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo); |
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366 | 367 | |
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367 | 368 | pio_pads : for i in 0 to 6 generate |
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368 | 369 | pio_pad : iopad generic map (tech => padtech) |
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369 | 370 | port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i)); |
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370 | 371 | end generate; |
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371 | 372 | end generate; |
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372 | 373 | |
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373 | 374 | |
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374 | 375 | end Behavioral; No newline at end of file |
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