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1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 library ieee;
22 22 use ieee.std_logic_1164.all;
23 23 library grlib;
24 24 use grlib.amba.all;
25 25 use grlib.stdlib.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library gaisler;
29 29 use gaisler.memctrl.all;
30 30 use gaisler.leon3.all;
31 31 use gaisler.uart.all;
32 32 use gaisler.misc.all;
33 33 library esa;
34 34 use esa.memoryctrl.all;
35 35 use work.config.all;
36 36 library lpp;
37 37 use lpp.lpp_amba.all;
38 38 use lpp.lpp_memory.all;
39 39 use lpp.lpp_uart.all;
40 40 use lpp.lpp_matrix.all;
41 41 use lpp.lpp_delay.all;
42 42 use lpp.lpp_fft.all;
43 43 use lpp.fft_components.all;
44 44 use lpp.lpp_ad_conv.all;
45 45 use lpp.iir_filter.all;
46 46 use lpp.general_purpose.all;
47 47 use lpp.Filtercfg.all;
48 48 use lpp.lpp_cna.all;
49 49
50 50 entity leon3mp is
51 51 generic (
52 52 fabtech : integer := CFG_FABTECH;
53 53 memtech : integer := CFG_MEMTECH;
54 54 padtech : integer := CFG_PADTECH;
55 55 clktech : integer := CFG_CLKTECH;
56 56 disas : integer := CFG_DISAS; -- Enable disassembly to console
57 57 dbguart : integer := CFG_DUART; -- Print UART on console
58 58 pclow : integer := CFG_PCLOW
59 59 );
60 60 port (
61 61 clk50MHz : in std_ulogic;
62 62 reset : in std_ulogic;
63 63 ramclk : out std_logic;
64 64
65 65 ahbrxd : in std_ulogic; -- DSU rx data
66 66 ahbtxd : out std_ulogic; -- DSU tx data
67 67 dsubre : in std_ulogic;
68 68 dsuact : out std_ulogic;
69 69 urxd1 : in std_ulogic; -- UART1 rx data
70 70 utxd1 : out std_ulogic; -- UART1 tx data
71 71 errorn : out std_ulogic;
72 72
73 73 address : out std_logic_vector(18 downto 0);
74 74 data : inout std_logic_vector(31 downto 0);
75 75 gpio : inout std_logic_vector(6 downto 0); -- I/O port
76 76
77 77 nBWa : out std_logic;
78 78 nBWb : out std_logic;
79 79 nBWc : out std_logic;
80 80 nBWd : out std_logic;
81 81 nBWE : out std_logic;
82 82 nADSC : out std_logic;
83 83 nADSP : out std_logic;
84 84 nADV : out std_logic;
85 85 nGW : out std_logic;
86 86 nCE1 : out std_logic;
87 87 CE2 : out std_logic;
88 88 nCE3 : out std_logic;
89 89 nOE : out std_logic;
90 90 MODE : out std_logic;
91 91 SSRAM_CLK : out std_logic;
92 92 ZZ : out std_logic;
93 93 ---------------------------------------------------------------------
94 94 --- AJOUT TEST ------------------------In/Out-----------------------
95 95 ---------------------------------------------------------------------
96 96 -- DAC
97 DAC_EN : out std_logic;
97 98 DAC_SYNC : out std_logic;
98 99 DAC_SCLK : out std_logic;
99 100 DAC_DATA : out std_logic;
100 101 -- UART
101 102 UART_RXD : in std_logic;
102 103 UART_TXD : out std_logic;
103 104 ---------------------------------------------------------------------
104 105 led : out std_logic_vector(1 downto 0)
105 106 );
106 107 end;
107 108
108 109 architecture Behavioral of leon3mp is
109 110
110 111 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
111 112 CFG_GRETH+CFG_AHB_JTAG;
112 113 constant maxahbm : integer := maxahbmsp;
113 114
114 115 --Clk & Rst gοΏ½nοΏ½
115 116 signal vcc : std_logic_vector(4 downto 0);
116 117 signal gnd : std_logic_vector(4 downto 0);
117 118 signal resetnl : std_ulogic;
118 119 signal clk2x : std_ulogic;
119 120 signal lclk : std_ulogic;
120 121 signal lclk2x : std_ulogic;
121 122 signal clkm : std_ulogic;
122 123 signal rstn : std_ulogic;
123 124 signal rstraw : std_ulogic;
124 125 signal pciclk : std_ulogic;
125 126 signal sdclkl : std_ulogic;
126 127 signal cgi : clkgen_in_type;
127 128 signal cgo : clkgen_out_type;
128 129 --- AHB / APB
129 130 signal apbi : apb_slv_in_type;
130 131 signal apbo : apb_slv_out_vector := (others => apb_none);
131 132 signal ahbsi : ahb_slv_in_type;
132 133 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
133 134 signal ahbmi : ahb_mst_in_type;
134 135 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
135 136 --UART
136 137 signal ahbuarti : uart_in_type;
137 138 signal ahbuarto : uart_out_type;
138 139 signal apbuarti : uart_in_type;
139 140 signal apbuarto : uart_out_type;
140 141 --MEM CTRLR
141 142 signal memi : memory_in_type;
142 143 signal memo : memory_out_type;
143 144 signal wpo : wprot_out_type;
144 145 signal sdo : sdram_out_type;
145 146 --IRQ
146 147 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
147 148 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
148 149 --Timer
149 150 signal gpti : gptimer_in_type;
150 151 signal gpto : gptimer_out_type;
151 152 --GPIO
152 153 signal gpioi : gpio_in_type;
153 154 signal gpioo : gpio_out_type;
154 155 --DSU
155 156 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
156 157 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
157 158 signal dsui : dsu_in_type;
158 159 signal dsuo : dsu_out_type;
159 160
160 161 ---------------------------------------------------------------------
161 162 --- AJOUT TEST ------------------------Signaux----------------------
162 163 ---------------------------------------------------------------------
163 164
164 165 ---------------------------------------------------------------------
165 166 constant IOAEN : integer := CFG_CAN;
166 167 constant boardfreq : integer := 50000;
167 168
168 169 begin
169 170
170 171 ---------------------------------------------------------------------
171 172 --- AJOUT TEST -------------------------------------IPs-------------
172 173 ---------------------------------------------------------------------
173 174
174 175 -- apbo not free : 0 1 2 3 7 11
175 176
176 177 --- DAC -------------------------------------------------------------
177 178
178 179 CAL0 : APB_CNA
179 180 generic map (pindex => 4, paddr => 4)
180 port map(clkm,rstn,apbi,apbo(4),DAC_SYNC,DAC_SCLK,DAC_DATA);
181 port map(clkm,rstn,apbi,apbo(4),DAC_EN,DAC_SYNC,DAC_SCLK,DAC_DATA);
181 182
182 183
183 184 --- UART -------------------------------------------------------------
184 185
185 186 COM0 : APB_UART
186 187 generic map (pindex => 5, paddr => 5)
187 188 port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD);
188 189
189 190
190 191 --- FIFO -------------------------------------------------------------
191 192
192 193 Memtest : APB_FIFO
193 194 generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
194 195 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6));
195 196
196 197
197 198 ----------------------------------------------------------------------
198 199 --- Reset and Clock generation -------------------------------------
199 200 ----------------------------------------------------------------------
200 201
201 202 vcc <= (others => '1'); gnd <= (others => '0');
202 203 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203 204
204 205 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
205 206
206 207
207 208 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
208 209
209 210 clkgen0 : clkgen -- clock generator
210 211 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 212 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 213 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
213 214
214 215 ramclk <= clkm;
215 216 process(lclk2x)
216 217 begin
217 218 if lclk2x'event and lclk2x = '1' then
218 219 lclk <= not lclk;
219 220 end if;
220 221 end process;
221 222
222 223 ----------------------------------------------------------------------
223 224 --- LEON3 processor / DSU / IRQ ------------------------------------
224 225 ----------------------------------------------------------------------
225 226
226 227 l3 : if CFG_LEON3 = 1 generate
227 228 cpu : for i in 0 to CFG_NCPU-1 generate
228 229 u0 : leon3s -- LEON3 processor
229 230 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
230 231 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
231 232 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
232 233 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
233 234 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
234 235 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
235 236 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
236 237 irqi(i), irqo(i), dbgi(i), dbgo(i));
237 238 end generate;
238 239 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
239 240
240 241 dsugen : if CFG_DSU = 1 generate
241 242 dsu0 : dsu3 -- LEON3 Debug Support Unit
242 243 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
243 244 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
244 245 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
245 246 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
246 247 dsui.enable <= '1';
247 248 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
248 249 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
249 250 end generate;
250 251 end generate;
251 252
252 253 nodsu : if CFG_DSU = 0 generate
253 254 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
254 255 end generate;
255 256
256 257 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
257 258 irqctrl0 : irqmp -- interrupt controller
258 259 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
259 260 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
260 261 end generate;
261 262 irq3 : if CFG_IRQ3_ENABLE = 0 generate
262 263 x : for i in 0 to CFG_NCPU-1 generate
263 264 irqi(i).irl <= "0000";
264 265 end generate;
265 266 apbo(2) <= apb_none;
266 267 end generate;
267 268
268 269 ----------------------------------------------------------------------
269 270 --- Memory controllers ---------------------------------------------
270 271 ----------------------------------------------------------------------
271 272
272 273 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
273 274 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
274 275
275 276 memi.brdyn <= '1'; memi.bexcn <= '1';
276 277 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
277 278
278 279 bdr : for i in 0 to 3 generate
279 280 data_pad : iopadv generic map (tech => padtech, width => 8)
280 281 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
281 282 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
282 283 end generate;
283 284
284 285
285 286 addr_pad : outpadv generic map (width => 19, tech => padtech)
286 287 port map (address, memo.address(20 downto 2));
287 288
288 289
289 290 SSRAM_0:entity ssram_plugin
290 291 generic map (tech => padtech)
291 292 port map
292 293 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
293 294
294 295 ----------------------------------------------------------------------
295 296 --- AHB CONTROLLER -------------------------------------------------
296 297 ----------------------------------------------------------------------
297 298
298 299 ahb0 : ahbctrl -- AHB arbiter/multiplexer
299 300 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
300 301 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
301 302 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
302 303 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
303 304
304 305 ----------------------------------------------------------------------
305 306 --- AHB UART -------------------------------------------------------
306 307 ----------------------------------------------------------------------
307 308
308 309 dcomgen : if CFG_AHB_UART = 1 generate
309 310 dcom0: ahbuart -- Debug UART
310 311 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
311 312 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
312 313 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
313 314 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
314 315 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
315 316 end generate;
316 317 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
317 318
318 319 ----------------------------------------------------------------------
319 320 --- APB Bridge -----------------------------------------------------
320 321 ----------------------------------------------------------------------
321 322
322 323 apb0 : apbctrl -- AHB/APB bridge
323 324 generic map (hindex => 1, haddr => CFG_APBADDR)
324 325 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
325 326
326 327 ----------------------------------------------------------------------
327 328 --- GPT Timer ------------------------------------------------------
328 329 ----------------------------------------------------------------------
329 330
330 331 gpt : if CFG_GPT_ENABLE /= 0 generate
331 332 timer0 : gptimer -- timer unit
332 333 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
333 334 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
334 335 nbits => CFG_GPT_TW)
335 336 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
336 337 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
337 338 -- led(4) <= gpto.wdog;
338 339 end generate;
339 340 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
340 341
341 342
342 343 ----------------------------------------------------------------------
343 344 --- APB UART -------------------------------------------------------
344 345 ----------------------------------------------------------------------
345 346
346 347 ua1 : if CFG_UART1_ENABLE /= 0 generate
347 348 uart1 : apbuart -- UART 1
348 349 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
349 350 fifosize => CFG_UART1_FIFO)
350 351 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
351 352 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
352 353 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
353 354 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
354 355 end generate;
355 356 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
356 357
357 358 ----------------------------------------------------------------------
358 359 --- GPIO -----------------------------------------------------------
359 360 ----------------------------------------------------------------------
360 361 led(0) <= gpio(0); led(1) <= gpio(1);
361 362
362 363 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
363 364 grgpio0: grgpio
364 365 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
365 366 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
366 367
367 368 pio_pads : for i in 0 to 6 generate
368 369 pio_pad : iopad generic map (tech => padtech)
369 370 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
370 371 end generate;
371 372 end generate;
372 373
373 374
374 375 end Behavioral; No newline at end of file
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