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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2013, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
23 USE IEEE.STD_LOGIC_1164.ALL;
24 LIBRARY lpp;
24 LIBRARY lpp;
25 USE lpp.lpp_ad_conv.ALL;
25 USE lpp.lpp_ad_conv.ALL;
26
26
27 ENTITY RHF1401_drvr IS
27 ENTITY RHF1401_drvr IS
28 GENERIC(
28 GENERIC(
29 ChanelCount : INTEGER := 8);
29 ChanelCount : INTEGER := 8);
30 PORT (
30 PORT (
31 cnv_clk : IN STD_LOGIC;
31 cnv_clk : IN STD_LOGIC;
32 clk : IN STD_LOGIC;
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 ADC_data : IN Samples14;
34 ADC_data : IN Samples14;
35 --ADC_smpclk : OUT STD_LOGIC;
35 --ADC_smpclk : OUT STD_LOGIC;
36 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
36 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
37 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
37 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
38 sample_val : OUT STD_LOGIC
38 sample_val : OUT STD_LOGIC
39 );
39 );
40 END RHF1401_drvr;
40 END RHF1401_drvr;
41
41
42 ARCHITECTURE ar_RHF1401_drvr OF RHF1401_drvr IS
42 ARCHITECTURE ar_RHF1401_drvr OF RHF1401_drvr IS
43
43
44 TYPE RHF1401_FSM_STATE IS (idle, output_en, latch, data_valid);
44 TYPE RHF1401_FSM_STATE IS (idle, output_en, latch, data_valid);
45
45
46 SIGNAL cnv_clk_reg : STD_LOGIC_VECTOR(1 DOWNTO 0) ;--:= (OTHERS => '0');
46 SIGNAL cnv_clk_reg : STD_LOGIC_VECTOR(1 DOWNTO 0) ;--:= (OTHERS => '0');
47 SIGNAL start_readout : STD_LOGIC ;--:= '0';
47 SIGNAL start_readout : STD_LOGIC ;--:= '0';
48 SIGNAL state : RHF1401_FSM_STATE ;--:= idle;
48 SIGNAL state : RHF1401_FSM_STATE ;--:= idle;
49 SIGNAL adc_index : INTEGER RANGE 0 TO ChanelCount; -- ChanelCount-1
49 SIGNAL adc_index : INTEGER RANGE 0 TO ChanelCount; -- ChanelCount-1
50 SIGNAL ADC_nOE_Reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
50 SIGNAL ADC_nOE_Reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
51 SIGNAL ADC_nOE_Reg_Shift : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
51 SIGNAL ADC_nOE_Reg_Shift : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
52 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
52 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
53
53
54 BEGIN
54 BEGIN
55
55
56 --ADC_smpclk <= cnv_clk;
56 --ADC_smpclk <= cnv_clk;
57
57
58 ADC_nOE <= ADC_nOE_Reg;
58 ADC_nOE <= ADC_nOE_Reg;
59 ADC_nOE_Reg <= ADC_nOE_Reg_Shift WHEN state = output_en ELSE (OTHERS => '1');
59 ADC_nOE_Reg <= ADC_nOE_Reg_Shift WHEN state = output_en ELSE (OTHERS => '1');
60
60
61 PROCESS(rstn, clk)
61 PROCESS(rstn, clk)
62 BEGIN
62 BEGIN
63 IF rstn = '0' THEN
63 IF rstn = '0' THEN
64 cnv_clk_reg(1 DOWNTO 0) <= (OTHERS => '0');
64 cnv_clk_reg(1 DOWNTO 0) <= (OTHERS => '0');
65 start_readout <= '0';
65 start_readout <= '0';
66 ELSIF clk'EVENT AND clk = '1' THEN
66 ELSIF clk'EVENT AND clk = '1' THEN
67 cnv_clk_reg(1 DOWNTO 0) <= cnv_clk_reg(0) & cnv_clk;
67 cnv_clk_reg(1 DOWNTO 0) <= cnv_clk_reg(0) & cnv_clk;
68 IF cnv_clk_reg = "10" AND cnv_clk = '0' THEN
68 IF cnv_clk_reg = "10" AND cnv_clk = '0' THEN
69 start_readout <= '1';
69 start_readout <= '1';
70 ELSE
70 ELSE
71 start_readout <= '0';
71 start_readout <= '0';
72 END IF;
72 END IF;
73 END IF;
73 END IF;
74 END PROCESS;
74 END PROCESS;
75
75
76
76
77 PROCESS(rstn, clk)
77 PROCESS(rstn, clk)
78 BEGIN
78 BEGIN
79 IF rstn = '0' THEN
79 IF rstn = '0' THEN
80 state <= idle;
80 state <= idle;
81 ADC_nOE_Reg_Shift <= (OTHERS => '1');
81 ADC_nOE_Reg_Shift <= (OTHERS => '1');
82 adc_index <= 0;
82 adc_index <= 0;
83 sample_val <= '0';
83 sample_val <= '0';
84 ELSIF clk'EVENT AND clk = '1' THEN
84 ELSIF clk'EVENT AND clk = '1' THEN
85 CASE state IS
85 CASE state IS
86 WHEN idle =>
86 WHEN idle =>
87 adc_index <= 0;
87 adc_index <= 0;
88 IF start_readout = '1' THEN
88 IF start_readout = '1' THEN
89 state <= output_en;
89 state <= output_en;
90 ADC_nOE_Reg_Shift(0) <= '0';
90 ADC_nOE_Reg_Shift(0) <= '0';
91 ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
91 ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
92 END IF;
92 END IF;
93 sample_val <= '0';
93 sample_val <= '0';
94 WHEN output_en =>
94 WHEN output_en =>
95 sample_reg(0) <= ADC_data; --JC
95 sample_reg(ChanelCount-1) <= ADC_data;
96 sample_reg(ChanelCount-1 DOWNTO 1) <= sample_reg(ChanelCount-2 DOWNTO 0); --JC
96 sample_reg(ChanelCount-2 DOWNTO 0) <= sample_reg(ChanelCount-1 DOWNTO 1);
97 ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 0) <= ADC_nOE_Reg_Shift(ChanelCount-2 DOWNTO 0) & '1';
97 ADC_nOE_Reg_Shift(ChanelCount-1 DOWNTO 0) <= ADC_nOE_Reg_Shift(ChanelCount-2 DOWNTO 0) & '1';
98 adc_index <= adc_index + 1;
98 adc_index <= adc_index + 1;
99 sample_val <= '0';
99 sample_val <= '0';
100 state <= latch;
100 state <= latch;
101 WHEN latch =>
101 WHEN latch =>
102 --sample_reg(0) <= ADC_data; --JC
103 --sample_reg(ChanelCount-1 DOWNTO 1) <= sample_reg(ChanelCount-2 DOWNTO 0); --JC
104 IF(adc_index = ChanelCount) THEN
102 IF(adc_index = ChanelCount) THEN
105 state <= data_valid;
103 state <= data_valid;
106 ELSE
104 ELSE
107 state <= output_en;
105 state <= output_en;
108 END IF;
106 END IF;
109 sample_val <= '0';
107 sample_val <= '0';
110 WHEN data_valid =>
108 WHEN data_valid =>
111 sample_val <= '1';
109 sample_val <= '1';
112 sample <= sample_reg;
110 sample <= sample_reg;
113 state <= idle;
111 state <= idle;
114 END CASE;
112 END CASE;
115 END IF;
113 END IF;
116 END PROCESS;
114 END PROCESS;
117
115
118
116
119 END ar_RHF1401_drvr;
117 END ar_RHF1401_drvr;
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