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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY LFR_em IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk100MHz : IN STD_ULOGIC; |
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52 | 52 | clk49_152MHz : IN STD_ULOGIC; |
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53 | 53 | reset : IN STD_ULOGIC; |
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54 | 54 | |
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55 | 55 | -- TAG -------------------------------------------------------------------- |
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56 | 56 | TAG1 : IN STD_ULOGIC; -- DSU rx data |
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57 | 57 | TAG3 : OUT STD_ULOGIC; -- DSU tx data |
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58 | 58 | -- UART APB --------------------------------------------------------------- |
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59 | 59 | TAG2 : IN STD_ULOGIC; -- UART1 rx data |
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60 | 60 | TAG4 : OUT STD_ULOGIC; -- UART1 tx data |
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61 | 61 | -- RAM -------------------------------------------------------------------- |
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62 | 62 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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63 | 63 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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64 | 64 | nSRAM_BE0 : OUT STD_LOGIC; |
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65 | 65 | nSRAM_BE1 : OUT STD_LOGIC; |
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66 | 66 | nSRAM_BE2 : OUT STD_LOGIC; |
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67 | 67 | nSRAM_BE3 : OUT STD_LOGIC; |
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68 | 68 | nSRAM_WE : OUT STD_LOGIC; |
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69 | 69 | nSRAM_CE : OUT STD_LOGIC; |
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70 | 70 | nSRAM_OE : OUT STD_LOGIC; |
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71 | 71 | -- SPW -------------------------------------------------------------------- |
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72 | 72 | spw1_din : IN STD_LOGIC; |
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73 | 73 | spw1_sin : IN STD_LOGIC; |
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74 | 74 | spw1_dout : OUT STD_LOGIC; |
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75 | 75 | spw1_sout : OUT STD_LOGIC; |
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76 | 76 | spw2_din : IN STD_LOGIC; |
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77 | 77 | spw2_sin : IN STD_LOGIC; |
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78 | 78 | spw2_dout : OUT STD_LOGIC; |
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79 | 79 | spw2_sout : OUT STD_LOGIC; |
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80 | 80 | -- ADC -------------------------------------------------------------------- |
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81 | 81 | bias_fail_sw : OUT STD_LOGIC; |
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82 | 82 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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83 | 83 | ADC_smpclk : OUT STD_LOGIC; |
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84 | 84 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); |
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85 | 85 | --------------------------------------------------------------------------- |
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86 | 86 | TAG8 : OUT STD_LOGIC; |
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87 | 87 | led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) |
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88 | 88 | ); |
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89 | 89 | |
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90 | 90 | END LFR_em; |
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91 | 91 | |
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92 | 92 | |
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93 | 93 | ARCHITECTURE beh OF LFR_em IS |
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94 | 94 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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95 | 95 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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96 | 96 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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97 | 97 | ----------------------------------------------------------------------------- |
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98 | 98 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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99 | 99 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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100 | 100 | |
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101 | 101 | -- CONSTANTS |
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102 | 102 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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103 | 103 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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104 | 104 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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105 | 105 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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106 | 106 | |
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107 | 107 | SIGNAL apbi_ext : apb_slv_in_type; |
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108 | 108 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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109 | 109 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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110 | 110 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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111 | 111 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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112 | 112 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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113 | 113 | |
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114 | 114 | -- Spacewire signals |
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115 | 115 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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116 | 116 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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117 | 117 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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118 | 118 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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119 | 119 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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120 | 120 | SIGNAL spw_clk : STD_LOGIC; |
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121 | 121 | SIGNAL swni : grspw_in_type; |
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122 | 122 | SIGNAL swno : grspw_out_type; |
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123 | 123 | |
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124 | 124 | --GPIO |
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125 | 125 | SIGNAL gpioi : gpio_in_type; |
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126 | 126 | SIGNAL gpioo : gpio_out_type; |
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127 | 127 | |
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128 | 128 | -- AD Converter ADS7886 |
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129 | 129 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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130 | 130 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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131 | 131 | SIGNAL sample_val : STD_LOGIC; |
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132 | 132 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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133 | 133 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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134 | 134 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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135 | 135 | |
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136 | 136 | ----------------------------------------------------------------------------- |
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137 | 137 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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138 | 138 | |
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139 | 139 | ----------------------------------------------------------------------------- |
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140 | 140 | SIGNAL rstn : STD_LOGIC; |
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141 | 141 | BEGIN -- beh |
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142 | 142 | |
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143 | 143 | ----------------------------------------------------------------------------- |
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144 | 144 | -- CLK |
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145 | 145 | ----------------------------------------------------------------------------- |
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146 | 146 | rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN); |
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147 | 147 | |
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148 | 148 | PROCESS(clk100MHz) |
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149 | 149 | BEGIN |
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150 | 150 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN |
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151 | 151 | clk_50_s <= NOT clk_50_s; |
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152 | 152 | END IF; |
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153 | 153 | END PROCESS; |
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154 | 154 | |
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155 | 155 | PROCESS(clk_50_s) |
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156 | 156 | BEGIN |
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157 | 157 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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158 | 158 | clk_25 <= NOT clk_25; |
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159 | 159 | END IF; |
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160 | 160 | END PROCESS; |
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161 | 161 | |
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162 | 162 | PROCESS(clk49_152MHz) |
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163 | 163 | BEGIN |
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164 | 164 | IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN |
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165 | 165 | clk_24 <= NOT clk_24; |
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166 | 166 | END IF; |
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167 | 167 | END PROCESS; |
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168 | 168 | |
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169 | 169 | ----------------------------------------------------------------------------- |
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170 | 170 | |
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171 | 171 | PROCESS (clk_25, rstn) |
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172 | 172 | BEGIN -- PROCESS |
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173 | 173 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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174 | 174 | led(0) <= '0'; |
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175 | 175 | led(1) <= '0'; |
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176 | 176 | led(2) <= '0'; |
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177 | 177 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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178 | 178 | led(0) <= '0'; |
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179 | 179 | led(1) <= '1'; |
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180 | 180 | led(2) <= '1'; |
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181 | 181 | END IF; |
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182 | 182 | END PROCESS; |
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183 | 183 | |
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184 | 184 | -- |
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185 | 185 | leon3_soc_1 : leon3_soc |
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186 | 186 | GENERIC MAP ( |
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187 | 187 | fabtech => apa3e, |
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188 | 188 | memtech => apa3e, |
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189 | 189 | padtech => inferred, |
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190 | 190 | clktech => inferred, |
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191 | 191 | disas => 0, |
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192 | 192 | dbguart => 0, |
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193 | 193 | pclow => 2, |
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194 | 194 | clk_freq => 25000, |
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195 | 195 | NB_CPU => 1, |
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196 | 196 | ENABLE_FPU => 1, |
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197 | 197 | FPU_NETLIST => 0, |
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198 | 198 | ENABLE_DSU => 1, |
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199 | 199 | ENABLE_AHB_UART => 1, |
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200 | 200 | ENABLE_APB_UART => 1, |
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201 | 201 | ENABLE_IRQMP => 1, |
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202 | 202 | ENABLE_GPT => 1, |
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203 | 203 | NB_AHB_MASTER => NB_AHB_MASTER, |
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204 | 204 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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205 | 205 | NB_APB_SLAVE => NB_APB_SLAVE) |
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206 | 206 | PORT MAP ( |
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207 | 207 | clk => clk_25, |
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208 | 208 | reset => rstn, |
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209 | 209 | errorn => OPEN, |
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210 | 210 | |
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211 | 211 | ahbrxd => TAG1, |
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212 | 212 | ahbtxd => TAG3, |
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213 | 213 | urxd1 => TAG2, |
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214 | 214 | utxd1 => TAG4, |
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215 | 215 | |
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216 | 216 | address => address, |
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217 | 217 | data => data, |
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218 | 218 | nSRAM_BE0 => nSRAM_BE0, |
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219 | 219 | nSRAM_BE1 => nSRAM_BE1, |
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220 | 220 | nSRAM_BE2 => nSRAM_BE2, |
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221 | 221 | nSRAM_BE3 => nSRAM_BE3, |
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222 | 222 | nSRAM_WE => nSRAM_WE, |
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223 | 223 | nSRAM_CE => nSRAM_CE, |
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224 | 224 | nSRAM_OE => nSRAM_OE, |
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225 | 225 | |
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226 | 226 | apbi_ext => apbi_ext, |
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227 | 227 | apbo_ext => apbo_ext, |
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228 | 228 | ahbi_s_ext => ahbi_s_ext, |
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229 | 229 | ahbo_s_ext => ahbo_s_ext, |
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230 | 230 | ahbi_m_ext => ahbi_m_ext, |
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231 | 231 | ahbo_m_ext => ahbo_m_ext); |
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232 | 232 | |
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233 | 233 | |
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234 | 234 | ------------------------------------------------------------------------------- |
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235 | 235 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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236 | 236 | ------------------------------------------------------------------------------- |
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237 | 237 | apb_lfr_time_management_1 : apb_lfr_time_management |
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238 | 238 | GENERIC MAP ( |
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239 | 239 | pindex => 6, |
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240 | 240 | paddr => 6, |
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241 | 241 | pmask => 16#fff#, |
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242 | 242 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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243 | 243 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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244 | 244 | PORT MAP ( |
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245 | 245 | clk25MHz => clk_25, |
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246 | 246 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
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247 | 247 | resetn => rstn, |
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248 | 248 | grspw_tick => swno.tickout, |
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249 | 249 | apbi => apbi_ext, |
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250 | 250 | apbo => apbo_ext(6), |
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251 | 251 | coarse_time => coarse_time, |
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252 | 252 | fine_time => fine_time); |
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253 | 253 | |
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254 | 254 | ----------------------------------------------------------------------- |
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255 | 255 | --- SpaceWire -------------------------------------------------------- |
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256 | 256 | ----------------------------------------------------------------------- |
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257 | 257 | |
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258 | 258 | -- SPW_EN <= '1'; |
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259 | 259 | |
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260 | 260 | spw_clk <= clk_50_s; |
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261 | 261 | spw_rxtxclk <= spw_clk; |
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262 | 262 | spw_rxclkn <= NOT spw_rxtxclk; |
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263 | 263 | |
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264 | 264 | -- PADS for SPW1 |
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265 | 265 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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266 | 266 | PORT MAP (spw1_din, dtmp(0)); |
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267 | 267 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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268 | 268 | PORT MAP (spw1_sin, stmp(0)); |
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269 | 269 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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270 | 270 | PORT MAP (spw1_dout, swno.d(0)); |
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271 | 271 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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272 | 272 | PORT MAP (spw1_sout, swno.s(0)); |
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273 | 273 | -- PADS FOR SPW2 |
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274 | 274 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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275 | 275 | PORT MAP (spw2_sin, dtmp(1)); |
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276 | 276 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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277 | 277 | PORT MAP (spw2_din, stmp(1)); |
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278 | 278 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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279 | 279 | PORT MAP (spw2_dout, swno.d(1)); |
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280 | 280 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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281 | 281 | PORT MAP (spw2_sout, swno.s(1)); |
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282 | 282 | |
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283 | 283 | -- GRSPW PHY |
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284 | 284 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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285 | 285 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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286 | 286 | spw_phy0 : grspw_phy |
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287 | 287 | GENERIC MAP( |
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288 | 288 | tech => apa3e, |
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289 | 289 | rxclkbuftype => 1, |
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290 | 290 | scantest => 0) |
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291 | 291 | PORT MAP( |
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292 | 292 | rxrst => swno.rxrst, |
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293 | 293 | di => dtmp(j), |
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294 | 294 | si => stmp(j), |
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295 | 295 | rxclko => spw_rxclk(j), |
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296 | 296 | do => swni.d(j), |
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297 | 297 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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298 | 298 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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299 | 299 | END GENERATE spw_inputloop; |
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300 | 300 | |
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301 | 301 | -- SPW core |
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302 | 302 | sw0 : grspwm GENERIC MAP( |
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303 | 303 | tech => apa3e, |
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304 | 304 | hindex => 1, |
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305 | 305 | pindex => 5, |
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306 | 306 | paddr => 5, |
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307 | 307 | pirq => 11, |
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308 | 308 | sysfreq => 25000, -- CPU_FREQ |
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309 | 309 | rmap => 1, |
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310 | 310 | rmapcrc => 1, |
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311 | 311 | fifosize1 => 16, |
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312 | 312 | fifosize2 => 16, |
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313 | 313 | rxclkbuftype => 1, |
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314 | 314 | rxunaligned => 0, |
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315 | 315 | rmapbufs => 4, |
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316 | 316 | ft => 0, |
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317 | 317 | netlist => 0, |
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318 | 318 | ports => 2, |
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319 | 319 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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320 | 320 | memtech => apa3e, |
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321 | 321 | destkey => 2, |
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322 | 322 | spwcore => 1 |
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323 | 323 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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324 | 324 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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325 | 325 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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326 | 326 | ) |
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327 | 327 | PORT MAP(rstn, clk_25, spw_rxclk(0), |
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328 | 328 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
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329 | 329 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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330 | 330 | swni, swno); |
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331 | 331 | |
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332 | 332 | swni.tickin <= '0'; |
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333 | 333 | swni.rmapen <= '1'; |
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334 | 334 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
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335 | 335 | swni.tickinraw <= '0'; |
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336 | 336 | swni.timein <= (OTHERS => '0'); |
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337 | 337 | swni.dcrstval <= (OTHERS => '0'); |
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338 | 338 | swni.timerrstval <= (OTHERS => '0'); |
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339 | 339 | |
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340 | 340 | ------------------------------------------------------------------------------- |
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341 | 341 | -- LFR ------------------------------------------------------------------------ |
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342 | 342 | ------------------------------------------------------------------------------- |
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343 |
lpp_lfr_1 : lpp_lfr |
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343 | lpp_lfr_1 : lpp_lfr | |
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344 | 344 | GENERIC MAP ( |
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345 | 345 | Mem_use => use_RAM, |
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346 | 346 | nb_data_by_buffer_size => 32, |
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347 | 347 | nb_word_by_buffer_size => 30, |
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348 | 348 | nb_snapshot_param_size => 32, |
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349 | 349 | delta_vector_size => 32, |
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350 | 350 | delta_vector_size_f0_2 => 7, -- log2(96) |
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351 | 351 | pindex => 15, |
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352 | 352 | paddr => 15, |
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353 | 353 | pmask => 16#fff#, |
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354 | 354 | pirq_ms => 6, |
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355 | 355 | pirq_wfp => 14, |
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356 | 356 | hindex => 2, |
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357 |
top_lfr_version => X"0 |
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357 | top_lfr_version => X"010110") -- aa.bb.cc version | |
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358 | 358 | -- AA : BOARD NUMBER |
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359 | 359 | -- 0 => MINI_LFR |
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360 | 360 | -- 1 => EM |
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361 | 361 | PORT MAP ( |
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362 | 362 | clk => clk_25, |
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363 | 363 | rstn => rstn, |
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364 | 364 | sample_B => sample_s(2 DOWNTO 0), |
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365 | 365 | sample_E => sample_s(7 DOWNTO 3), |
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366 | 366 | sample_val => sample_val, |
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367 | 367 | apbi => apbi_ext, |
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368 | 368 | apbo => apbo_ext(15), |
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369 | 369 | ahbi => ahbi_m_ext, |
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370 | 370 | ahbo => ahbo_m_ext(2), |
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371 | 371 | coarse_time => coarse_time, |
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372 | 372 | fine_time => fine_time, |
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373 | 373 | data_shaping_BW => bias_fail_sw, |
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374 | 374 | observation_reg => observation_reg); |
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375 | 375 | |
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376 | 376 | |
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377 | 377 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
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378 | 378 | sample_s(I) <= sample(I) & '0' & '0'; |
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379 | 379 | END GENERATE all_sample; |
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380 | 380 | |
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381 | 381 | ----------------------------------------------------------------------------- |
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382 | 382 | -- |
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383 | 383 | ----------------------------------------------------------------------------- |
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384 | 384 | top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 |
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385 | 385 | GENERIC MAP ( |
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386 | 386 | ChanelCount => 8, |
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387 | 387 | ncycle_cnv_high => 40, -- TODO : 79 |
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388 | 388 | ncycle_cnv => 250) -- TODO : 500 |
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389 | 389 | PORT MAP ( |
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390 | 390 | cnv_clk => clk_24, -- TODO : 49.152 |
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391 | 391 | cnv_rstn => rstn, -- ok |
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392 | 392 | cnv => ADC_smpclk, -- ok |
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393 | 393 | clk => clk_25, -- ok |
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394 | 394 | rstn => rstn, -- ok |
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395 | 395 | ADC_data => ADC_data, -- ok |
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396 | 396 | ADC_nOE => ADC_OEB_bar_CH, -- ok |
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397 | 397 | sample => sample, -- ok |
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398 | 398 | sample_val => sample_val); -- ok |
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399 | 399 | |
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400 | 400 | TAG8 <= ADC_smpclk; |
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401 | 401 | |
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402 | 402 | END beh; |
@@ -1,587 +1,587 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY MINI_LFR_top IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk_50 : IN STD_LOGIC; |
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52 | 52 | clk_49 : IN STD_LOGIC; |
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53 | 53 | reset : IN STD_LOGIC; |
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54 | 54 | --BPs |
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55 | 55 | BP0 : IN STD_LOGIC; |
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56 | 56 | BP1 : IN STD_LOGIC; |
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57 | 57 | --LEDs |
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58 | 58 | LED0 : OUT STD_LOGIC; |
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59 | 59 | LED1 : OUT STD_LOGIC; |
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60 | 60 | LED2 : OUT STD_LOGIC; |
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61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
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64 | 64 | nCTS1 : OUT STD_LOGIC; |
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65 | 65 | nRTS1 : IN STD_LOGIC; |
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66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
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68 | 68 | RXD2 : OUT STD_LOGIC; |
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69 | 69 | nCTS2 : OUT STD_LOGIC; |
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70 | 70 | nDTR2 : IN STD_LOGIC; |
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71 | 71 | nRTS2 : IN STD_LOGIC; |
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72 | 72 | nDCD2 : OUT STD_LOGIC; |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
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75 | 75 | IO0 : INOUT STD_LOGIC; |
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76 | 76 | IO1 : INOUT STD_LOGIC; |
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77 | 77 | IO2 : INOUT STD_LOGIC; |
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78 | 78 | IO3 : INOUT STD_LOGIC; |
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79 | 79 | IO4 : INOUT STD_LOGIC; |
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80 | 80 | IO5 : INOUT STD_LOGIC; |
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81 | 81 | IO6 : INOUT STD_LOGIC; |
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82 | 82 | IO7 : INOUT STD_LOGIC; |
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83 | 83 | IO8 : INOUT STD_LOGIC; |
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84 | 84 | IO9 : INOUT STD_LOGIC; |
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85 | 85 | IO10 : INOUT STD_LOGIC; |
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
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105 | 105 | SRAM_CE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
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107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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110 | 110 | ); |
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111 | 111 | |
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112 | 112 | END MINI_LFR_top; |
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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118 | 118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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119 | 119 | ----------------------------------------------------------------------------- |
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120 | 120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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121 | 121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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122 | 122 | -- |
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123 | 123 | SIGNAL errorn : STD_LOGIC; |
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124 | 124 | -- UART AHB --------------------------------------------------------------- |
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125 | 125 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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126 | 126 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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127 | 127 | |
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128 | 128 | -- UART APB --------------------------------------------------------------- |
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129 | 129 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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130 | 130 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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131 | 131 | -- |
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132 | 132 | SIGNAL I00_s : STD_LOGIC; |
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133 | 133 | |
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134 | 134 | -- CONSTANTS |
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135 | 135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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136 | 136 | -- |
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137 | 137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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138 | 138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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139 | 139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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140 | 140 | |
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141 | 141 | SIGNAL apbi_ext : apb_slv_in_type; |
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142 | 142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
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143 | 143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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144 | 144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
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145 | 145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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146 | 146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
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147 | 147 | |
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148 | 148 | -- Spacewire signals |
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149 | 149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | 150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | 151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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152 | 152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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153 | 153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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154 | 154 | SIGNAL spw_clk : STD_LOGIC; |
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155 | 155 | SIGNAL swni : grspw_in_type; |
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156 | 156 | SIGNAL swno : grspw_out_type; |
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157 | 157 | -- SIGNAL clkmn : STD_ULOGIC; |
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158 | 158 | -- SIGNAL txclk : STD_ULOGIC; |
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159 | 159 | |
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160 | 160 | --GPIO |
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161 | 161 | SIGNAL gpioi : gpio_in_type; |
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162 | 162 | SIGNAL gpioo : gpio_out_type; |
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163 | 163 | |
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164 | 164 | -- AD Converter ADS7886 |
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165 | 165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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166 | 166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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167 | 167 | SIGNAL sample_val : STD_LOGIC; |
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168 | 168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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169 | 169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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170 | 170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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171 | 171 | |
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172 | 172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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173 | 173 | |
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174 | 174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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175 | 175 | ----------------------------------------------------------------------------- |
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176 | 176 | |
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177 | 177 | BEGIN -- beh |
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178 | 178 | |
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179 | 179 | ----------------------------------------------------------------------------- |
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180 | 180 | -- CLK |
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181 | 181 | ----------------------------------------------------------------------------- |
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182 | 182 | |
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183 | 183 | PROCESS(clk_50) |
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184 | 184 | BEGIN |
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185 | 185 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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186 | 186 | clk_50_s <= NOT clk_50_s; |
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187 | 187 | END IF; |
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188 | 188 | END PROCESS; |
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189 | 189 | |
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190 | 190 | PROCESS(clk_50_s) |
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191 | 191 | BEGIN |
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192 | 192 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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193 | 193 | clk_25 <= NOT clk_25; |
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194 | 194 | END IF; |
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195 | 195 | END PROCESS; |
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196 | 196 | |
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197 | 197 | PROCESS(clk_49) |
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198 | 198 | BEGIN |
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199 | 199 | IF clk_49'EVENT AND clk_49 = '1' THEN |
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200 | 200 | clk_24 <= NOT clk_24; |
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201 | 201 | END IF; |
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202 | 202 | END PROCESS; |
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203 | 203 | |
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204 | 204 | ----------------------------------------------------------------------------- |
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205 | 205 | |
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206 | 206 | PROCESS (clk_25, reset) |
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207 | 207 | BEGIN -- PROCESS |
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208 | 208 | IF reset = '0' THEN -- asynchronous reset (active low) |
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209 | 209 | LED0 <= '0'; |
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210 | 210 | LED1 <= '0'; |
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211 | 211 | LED2 <= '0'; |
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212 | 212 | --IO1 <= '0'; |
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213 | 213 | --IO2 <= '1'; |
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214 | 214 | --IO3 <= '0'; |
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215 | 215 | --IO4 <= '0'; |
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216 | 216 | --IO5 <= '0'; |
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217 | 217 | --IO6 <= '0'; |
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218 | 218 | --IO7 <= '0'; |
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219 | 219 | --IO8 <= '0'; |
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220 | 220 | --IO9 <= '0'; |
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221 | 221 | --IO10 <= '0'; |
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222 | 222 | --IO11 <= '0'; |
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223 | 223 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
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224 | 224 | LED0 <= '0'; |
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225 | 225 | LED1 <= '1'; |
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226 | 226 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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227 | 227 | --IO1 <= '1'; |
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228 | 228 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
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229 | 229 | --IO3 <= ADC_SDO(0); |
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230 | 230 | --IO4 <= ADC_SDO(1); |
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231 | 231 | --IO5 <= ADC_SDO(2); |
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232 | 232 | --IO6 <= ADC_SDO(3); |
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233 | 233 | --IO7 <= ADC_SDO(4); |
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234 | 234 | --IO8 <= ADC_SDO(5); |
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235 | 235 | --IO9 <= ADC_SDO(6); |
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236 | 236 | --IO10 <= ADC_SDO(7); |
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237 | 237 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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238 | 238 | END IF; |
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239 | 239 | END PROCESS; |
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240 | 240 | |
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241 | 241 | PROCESS (clk_24, reset) |
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242 | 242 | BEGIN -- PROCESS |
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243 | 243 | IF reset = '0' THEN -- asynchronous reset (active low) |
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244 | 244 | I00_s <= '0'; |
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245 | 245 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
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246 | 246 | I00_s <= NOT I00_s ; |
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247 | 247 | END IF; |
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248 | 248 | END PROCESS; |
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249 | 249 | -- IO0 <= I00_s; |
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250 | 250 | |
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251 | 251 | --UARTs |
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252 | 252 | nCTS1 <= '1'; |
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253 | 253 | nCTS2 <= '1'; |
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254 | 254 | nDCD2 <= '1'; |
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255 | 255 | |
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256 | 256 | --EXT CONNECTOR |
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257 | 257 | |
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258 | 258 | --SPACE WIRE |
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259 | 259 | |
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260 | 260 | leon3_soc_1 : leon3_soc |
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261 | 261 | GENERIC MAP ( |
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262 | 262 | fabtech => apa3e, |
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263 | 263 | memtech => apa3e, |
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264 | 264 | padtech => inferred, |
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265 | 265 | clktech => inferred, |
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266 | 266 | disas => 0, |
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267 | 267 | dbguart => 0, |
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268 | 268 | pclow => 2, |
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269 | 269 | clk_freq => 25000, |
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270 | 270 | NB_CPU => 1, |
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271 | 271 | ENABLE_FPU => 1, |
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272 | 272 | FPU_NETLIST => 0, |
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273 | 273 | ENABLE_DSU => 1, |
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274 | 274 | ENABLE_AHB_UART => 1, |
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275 | 275 | ENABLE_APB_UART => 1, |
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276 | 276 | ENABLE_IRQMP => 1, |
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277 | 277 | ENABLE_GPT => 1, |
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278 | 278 | NB_AHB_MASTER => NB_AHB_MASTER, |
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279 | 279 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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280 | 280 | NB_APB_SLAVE => NB_APB_SLAVE) |
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281 | 281 | PORT MAP ( |
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282 | 282 | clk => clk_25, |
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283 | 283 | reset => reset, |
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284 | 284 | errorn => errorn, |
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285 | 285 | ahbrxd => TXD1, |
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286 | 286 | ahbtxd => RXD1, |
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287 | 287 | urxd1 => TXD2, |
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288 | 288 | utxd1 => RXD2, |
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289 | 289 | address => SRAM_A, |
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290 | 290 | data => SRAM_DQ, |
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291 | 291 | nSRAM_BE0 => SRAM_nBE(0), |
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292 | 292 | nSRAM_BE1 => SRAM_nBE(1), |
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293 | 293 | nSRAM_BE2 => SRAM_nBE(2), |
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294 | 294 | nSRAM_BE3 => SRAM_nBE(3), |
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295 | 295 | nSRAM_WE => SRAM_nWE, |
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296 | 296 | nSRAM_CE => SRAM_CE, |
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297 | 297 | nSRAM_OE => SRAM_nOE, |
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298 | 298 | |
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299 | 299 | apbi_ext => apbi_ext, |
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300 | 300 | apbo_ext => apbo_ext, |
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301 | 301 | ahbi_s_ext => ahbi_s_ext, |
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302 | 302 | ahbo_s_ext => ahbo_s_ext, |
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303 | 303 | ahbi_m_ext => ahbi_m_ext, |
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304 | 304 | ahbo_m_ext => ahbo_m_ext); |
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305 | 305 | |
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306 | 306 | ------------------------------------------------------------------------------- |
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307 | 307 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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308 | 308 | ------------------------------------------------------------------------------- |
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309 | 309 | apb_lfr_time_management_1 : apb_lfr_time_management |
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310 | 310 | GENERIC MAP ( |
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311 | 311 | pindex => 6, |
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312 | 312 | paddr => 6, |
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313 | 313 | pmask => 16#fff#, |
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314 | 314 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
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315 | 315 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
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316 | 316 | PORT MAP ( |
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317 | 317 | clk25MHz => clk_25, |
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318 | 318 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
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319 | 319 | resetn => reset, |
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320 | 320 | grspw_tick => swno.tickout, |
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321 | 321 | apbi => apbi_ext, |
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322 | 322 | apbo => apbo_ext(6), |
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323 | 323 | coarse_time => coarse_time, |
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324 | 324 | fine_time => fine_time); |
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325 | 325 | |
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326 | 326 | ----------------------------------------------------------------------- |
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327 | 327 | --- SpaceWire -------------------------------------------------------- |
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328 | 328 | ----------------------------------------------------------------------- |
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329 | 329 | |
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330 | 330 | SPW_EN <= '1'; |
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331 | 331 | |
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332 | 332 | spw_clk <= clk_50_s; |
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333 | 333 | spw_rxtxclk <= spw_clk; |
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334 | 334 | spw_rxclkn <= NOT spw_rxtxclk; |
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335 | 335 | |
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336 | 336 | -- PADS for SPW1 |
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337 | 337 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
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338 | 338 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
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339 | 339 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
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340 | 340 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
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341 | 341 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
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342 | 342 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
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343 | 343 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
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344 | 344 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
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345 | 345 | -- PADS FOR SPW2 |
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346 | 346 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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347 | 347 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
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348 | 348 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
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349 | 349 | PORT MAP (SPW_RED_DIN, stmp(1)); |
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350 | 350 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
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351 | 351 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
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352 | 352 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
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353 | 353 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
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354 | 354 | |
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355 | 355 | -- GRSPW PHY |
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356 | 356 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
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357 | 357 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
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358 | 358 | spw_phy0 : grspw_phy |
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359 | 359 | GENERIC MAP( |
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360 | 360 | tech => apa3e, |
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361 | 361 | rxclkbuftype => 1, |
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362 | 362 | scantest => 0) |
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363 | 363 | PORT MAP( |
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364 | 364 | rxrst => swno.rxrst, |
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365 | 365 | di => dtmp(j), |
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366 | 366 | si => stmp(j), |
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367 | 367 | rxclko => spw_rxclk(j), |
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368 | 368 | do => swni.d(j), |
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369 | 369 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
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370 | 370 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
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371 | 371 | END GENERATE spw_inputloop; |
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372 | 372 | |
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373 | 373 | -- SPW core |
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374 | 374 | sw0 : grspwm GENERIC MAP( |
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375 | 375 | tech => apa3e, |
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376 | 376 | hindex => 1, |
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377 | 377 | pindex => 5, |
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378 | 378 | paddr => 5, |
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379 | 379 | pirq => 11, |
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380 | 380 | sysfreq => 25000, -- CPU_FREQ |
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381 | 381 | rmap => 1, |
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382 | 382 | rmapcrc => 1, |
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383 | 383 | fifosize1 => 16, |
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384 | 384 | fifosize2 => 16, |
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385 | 385 | rxclkbuftype => 1, |
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386 | 386 | rxunaligned => 0, |
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387 | 387 | rmapbufs => 4, |
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388 | 388 | ft => 0, |
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389 | 389 | netlist => 0, |
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390 | 390 | ports => 2, |
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391 | 391 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
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392 | 392 | memtech => apa3e, |
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393 | 393 | destkey => 2, |
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394 | 394 | spwcore => 1 |
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395 | 395 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
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396 | 396 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
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397 | 397 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
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398 | 398 | ) |
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399 | 399 | PORT MAP(reset, clk_25, spw_rxclk(0), |
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400 | 400 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
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401 | 401 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
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402 | 402 | swni, swno); |
|
403 | 403 | |
|
404 | 404 | swni.tickin <= '0'; |
|
405 | 405 | swni.rmapen <= '1'; |
|
406 | 406 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
407 | 407 | swni.tickinraw <= '0'; |
|
408 | 408 | swni.timein <= (OTHERS => '0'); |
|
409 | 409 | swni.dcrstval <= (OTHERS => '0'); |
|
410 | 410 | swni.timerrstval <= (OTHERS => '0'); |
|
411 | 411 | |
|
412 | 412 | ------------------------------------------------------------------------------- |
|
413 | 413 | -- LFR ------------------------------------------------------------------------ |
|
414 | 414 | ------------------------------------------------------------------------------- |
|
415 | 415 | lpp_lfr_1 : lpp_lfr |
|
416 | 416 | GENERIC MAP ( |
|
417 | 417 | Mem_use => use_RAM, |
|
418 | 418 | nb_data_by_buffer_size => 32, |
|
419 | 419 | nb_word_by_buffer_size => 30, |
|
420 | 420 | nb_snapshot_param_size => 32, |
|
421 | 421 | delta_vector_size => 32, |
|
422 | 422 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
423 | 423 | pindex => 15, |
|
424 | 424 | paddr => 15, |
|
425 | 425 | pmask => 16#fff#, |
|
426 | 426 | pirq_ms => 6, |
|
427 | 427 | pirq_wfp => 14, |
|
428 | 428 | hindex => 2, |
|
429 |
top_lfr_version => X"00010 |
|
|
429 | top_lfr_version => X"000110") -- aa.bb.cc version | |
|
430 | 430 | PORT MAP ( |
|
431 | 431 | clk => clk_25, |
|
432 | 432 | rstn => reset, |
|
433 | 433 | sample_B => sample_s(2 DOWNTO 0), |
|
434 | 434 | sample_E => sample_s(7 DOWNTO 3), |
|
435 | 435 | sample_val => sample_val, |
|
436 | 436 | apbi => apbi_ext, |
|
437 | 437 | apbo => apbo_ext(15), |
|
438 | 438 | ahbi => ahbi_m_ext, |
|
439 | 439 | ahbo => ahbo_m_ext(2), |
|
440 | 440 | coarse_time => coarse_time, |
|
441 | 441 | fine_time => fine_time, |
|
442 | 442 | data_shaping_BW => bias_fail_sw_sig, |
|
443 | 443 | observation_reg => observation_reg); |
|
444 | 444 | |
|
445 | 445 | all_sample: FOR I IN 7 DOWNTO 0 GENERATE |
|
446 | 446 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
447 | 447 | END GENERATE all_sample; |
|
448 | 448 | |
|
449 | 449 | |
|
450 | 450 | |
|
451 | 451 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
452 | 452 | GENERIC MAP( |
|
453 | 453 | ChannelCount => 8, |
|
454 | 454 | SampleNbBits => 14, |
|
455 | 455 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
456 | 456 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
457 | 457 | PORT MAP ( |
|
458 | 458 | -- CONV |
|
459 | 459 | cnv_clk => clk_24, |
|
460 | 460 | cnv_rstn => reset, |
|
461 | 461 | cnv => ADC_nCS_sig, |
|
462 | 462 | -- DATA |
|
463 | 463 | clk => clk_25, |
|
464 | 464 | rstn => reset, |
|
465 | 465 | sck => ADC_CLK_sig, |
|
466 | 466 | sdo => ADC_SDO_sig, |
|
467 | 467 | -- SAMPLE |
|
468 | 468 | sample => sample, |
|
469 | 469 | sample_val => sample_val); |
|
470 | 470 | |
|
471 | 471 | --IO10 <= ADC_SDO_sig(5); |
|
472 | 472 | --IO9 <= ADC_SDO_sig(4); |
|
473 | 473 | --IO8 <= ADC_SDO_sig(3); |
|
474 | 474 | |
|
475 | 475 | ADC_nCS <= ADC_nCS_sig; |
|
476 | 476 | ADC_CLK <= ADC_CLK_sig; |
|
477 | 477 | ADC_SDO_sig <= ADC_SDO; |
|
478 | 478 | |
|
479 | 479 | ---------------------------------------------------------------------- |
|
480 | 480 | --- GPIO ----------------------------------------------------------- |
|
481 | 481 | ---------------------------------------------------------------------- |
|
482 | 482 | |
|
483 | 483 | grgpio0 : grgpio |
|
484 | 484 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
485 | 485 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
486 | 486 | |
|
487 | 487 | --pio_pad_0 : iopad |
|
488 | 488 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
489 | 489 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
490 | 490 | --pio_pad_1 : iopad |
|
491 | 491 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
492 | 492 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
493 | 493 | --pio_pad_2 : iopad |
|
494 | 494 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
495 | 495 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
496 | 496 | --pio_pad_3 : iopad |
|
497 | 497 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
498 | 498 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
499 | 499 | --pio_pad_4 : iopad |
|
500 | 500 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
501 | 501 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
502 | 502 | --pio_pad_5 : iopad |
|
503 | 503 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
504 | 504 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
505 | 505 | --pio_pad_6 : iopad |
|
506 | 506 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
507 | 507 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
508 | 508 | --pio_pad_7 : iopad |
|
509 | 509 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
510 | 510 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
511 | 511 | |
|
512 | 512 | PROCESS (clk_25, reset) |
|
513 | 513 | BEGIN -- PROCESS |
|
514 | 514 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
515 | 515 | IO0 <= '0'; |
|
516 | 516 | IO1 <= '0'; |
|
517 | 517 | IO2 <= '0'; |
|
518 | 518 | IO3 <= '0'; |
|
519 | 519 | IO4 <= '0'; |
|
520 | 520 | IO5 <= '0'; |
|
521 | 521 | IO6 <= '0'; |
|
522 | 522 | IO7 <= '0'; |
|
523 | 523 | IO8 <= '0'; |
|
524 | 524 | IO9 <= '0'; |
|
525 | 525 | IO10 <= '0'; |
|
526 | 526 | IO11 <= '0'; |
|
527 | 527 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
|
528 | 528 | CASE gpioo.dout(1 DOWNTO 0) IS |
|
529 | 529 | WHEN "00" => |
|
530 | 530 | IO0 <= observation_reg(0 ); |
|
531 | 531 | IO1 <= observation_reg(1 ); |
|
532 | 532 | IO2 <= observation_reg(2 ); |
|
533 | 533 | IO3 <= observation_reg(3 ); |
|
534 | 534 | IO4 <= observation_reg(4 ); |
|
535 | 535 | IO5 <= observation_reg(5 ); |
|
536 | 536 | IO6 <= observation_reg(6 ); |
|
537 | 537 | IO7 <= observation_reg(7 ); |
|
538 | 538 | IO8 <= observation_reg(8 ); |
|
539 | 539 | IO9 <= observation_reg(9 ); |
|
540 | 540 | IO10 <= observation_reg(10); |
|
541 | 541 | IO11 <= observation_reg(11); |
|
542 | 542 | WHEN "01" => |
|
543 | 543 | IO0 <= observation_reg(0 + 12); |
|
544 | 544 | IO1 <= observation_reg(1 + 12); |
|
545 | 545 | IO2 <= observation_reg(2 + 12); |
|
546 | 546 | IO3 <= observation_reg(3 + 12); |
|
547 | 547 | IO4 <= observation_reg(4 + 12); |
|
548 | 548 | IO5 <= observation_reg(5 + 12); |
|
549 | 549 | IO6 <= observation_reg(6 + 12); |
|
550 | 550 | IO7 <= observation_reg(7 + 12); |
|
551 | 551 | IO8 <= observation_reg(8 + 12); |
|
552 | 552 | IO9 <= observation_reg(9 + 12); |
|
553 | 553 | IO10 <= observation_reg(10 + 12); |
|
554 | 554 | IO11 <= observation_reg(11 + 12); |
|
555 | 555 | WHEN "10" => |
|
556 | 556 | IO0 <= observation_reg(0 + 12 + 12); |
|
557 | 557 | IO1 <= observation_reg(1 + 12 + 12); |
|
558 | 558 | IO2 <= observation_reg(2 + 12 + 12); |
|
559 | 559 | IO3 <= observation_reg(3 + 12 + 12); |
|
560 | 560 | IO4 <= observation_reg(4 + 12 + 12); |
|
561 | 561 | IO5 <= observation_reg(5 + 12 + 12); |
|
562 | 562 | IO6 <= observation_reg(6 + 12 + 12); |
|
563 | 563 | IO7 <= observation_reg(7 + 12 + 12); |
|
564 | 564 | IO8 <= '0'; |
|
565 | 565 | IO9 <= '0'; |
|
566 | 566 | IO10 <= '0'; |
|
567 | 567 | IO11 <= '0'; |
|
568 | 568 | WHEN "11" => |
|
569 | 569 | IO0 <= '0'; |
|
570 | 570 | IO1 <= '0'; |
|
571 | 571 | IO2 <= '0'; |
|
572 | 572 | IO3 <= '0'; |
|
573 | 573 | IO4 <= '0'; |
|
574 | 574 | IO5 <= '0'; |
|
575 | 575 | IO6 <= '0'; |
|
576 | 576 | IO7 <= '0'; |
|
577 | 577 | IO8 <= '0'; |
|
578 | 578 | IO9 <= '0'; |
|
579 | 579 | IO10 <= '0'; |
|
580 | 580 | IO11 <= '0'; |
|
581 | 581 | WHEN OTHERS => NULL; |
|
582 | 582 | END CASE; |
|
583 | 583 | |
|
584 | 584 | END IF; |
|
585 | 585 | END PROCESS; |
|
586 | 586 | |
|
587 | 587 | END beh; |
@@ -1,432 +1,480 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | |
|
23 | 23 | LIBRARY IEEE; |
|
24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
|
25 | 25 | USE IEEE.NUMERIC_STD.ALL; |
|
26 | 26 | |
|
27 | 27 | LIBRARY lpp; |
|
28 | 28 | USE lpp.lpp_lfr_pkg.ALL; |
|
29 | 29 | USE lpp.lpp_memory.ALL; |
|
30 | 30 | USE lpp.iir_filter.ALL; |
|
31 | 31 | USE lpp.spectral_matrix_package.ALL; |
|
32 | 32 | use lpp.lpp_fft.all; |
|
33 | 33 | use lpp.fft_components.all; |
|
34 | 34 | |
|
35 | 35 | LIBRARY grlib; |
|
36 | 36 | USE grlib.amba.ALL; |
|
37 | 37 | USE grlib.stdlib.ALL; |
|
38 | 38 | USE grlib.devices.ALL; |
|
39 | 39 | USE GRLIB.DMA2AHB_Package.ALL; |
|
40 | 40 | |
|
41 | 41 | ENTITY TB IS |
|
42 | 42 | |
|
43 | 43 | |
|
44 | 44 | END TB; |
|
45 | 45 | |
|
46 | 46 | |
|
47 | 47 | ARCHITECTURE beh OF TB IS |
|
48 | 48 | |
|
49 | 49 | ----------------------------------------------------------------------------- |
|
50 | 50 | SIGNAL clk25MHz : STD_LOGIC := '0'; |
|
51 | 51 | SIGNAL rstn : STD_LOGIC := '0'; |
|
52 | 52 | |
|
53 | 53 | ----------------------------------------------------------------------------- |
|
54 | 54 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
55 | 55 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
56 | 56 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
57 | 57 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
58 | 58 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
59 | 59 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
60 | 60 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
61 | 61 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
62 | 62 | SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
63 | 63 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
64 | 64 | SIGNAL dma_valid : STD_LOGIC; |
|
65 | 65 | SIGNAL dma_valid_burst : STD_LOGIC; |
|
66 | 66 | SIGNAL dma_ren : STD_LOGIC; |
|
67 | 67 | SIGNAL dma_done : STD_LOGIC; |
|
68 | 68 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
|
69 | 69 | -- SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
|
70 | 70 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
|
71 | 71 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
|
72 | 72 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
|
73 | 73 | SIGNAL error_bad_component_error : STD_LOGIC; |
|
74 | 74 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | 75 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
|
76 | 76 | -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
|
77 | 77 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
|
78 | 78 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
|
79 | 79 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
|
80 | 80 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
|
81 | 81 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
|
82 | 82 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
|
83 | 83 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | 85 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | 86 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
87 | 87 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | 88 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | 89 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | 90 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
91 | 91 | |
|
92 | 92 | ----------------------------------------------------------------------------- |
|
93 | 93 | SIGNAL clk49_152MHz : STD_LOGIC := '0'; |
|
94 | 94 | SIGNAL sample_counter_24k : INTEGER; |
|
95 | 95 | SIGNAL s_24576Hz : STD_LOGIC; |
|
96 | 96 | |
|
97 | 97 | SIGNAL s_24_sync_reg_0 : STD_LOGIC; |
|
98 | 98 | SIGNAL s_24_sync_reg_1 : STD_LOGIC; |
|
99 | 99 | |
|
100 | 100 | SIGNAL s_24576Hz_sync : STD_LOGIC; |
|
101 | 101 | |
|
102 | 102 | SIGNAL sample_counter_f1 : INTEGER; |
|
103 | 103 | SIGNAL sample_counter_f2 : INTEGER; |
|
104 | 104 | -- |
|
105 | 105 | SIGNAL sample_f0_val : STD_LOGIC; |
|
106 | 106 | SIGNAL sample_f1_val : STD_LOGIC; |
|
107 | 107 | SIGNAL sample_f2_val : STD_LOGIC; |
|
108 | 108 | |
|
109 | 109 | ----------------------------------------------------------------------------- |
|
110 | 110 | SIGNAL ren_counter : INTEGER; |
|
111 | 111 | |
|
112 | 112 | SIGNAL error_buffer_full : STD_LOGIC; |
|
113 | 113 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
114 | 114 | ----------------------------------------------------------------------------- |
|
115 | 115 | SIGNAL apbi : apb_slv_in_type; |
|
116 | SIGNAL apbo : apb_slv_out_type; | |
|
116 | 117 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
117 | 118 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
118 | 119 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
119 | 120 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
120 | ||
|
121 | -- | |
|
122 | SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0); | |
|
123 | SIGNAL irq_ongoing : STD_LOGIC; | |
|
124 | -- | |
|
125 | SIGNAL read_status : STD_LOGIC; | |
|
126 | SIGNAL read_status_t : STD_LOGIC; | |
|
127 | ||
|
128 | ||
|
129 | SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
130 | SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
131 | ||
|
121 | 132 | BEGIN -- beh |
|
122 | 133 | |
|
123 | 134 | clk25MHz <= NOT clk25MHz AFTER 20 ns; |
|
124 | 135 | clk25MHz <= NOT clk25MHz AFTER 20 ns; |
|
125 | 136 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz |
|
126 | 137 | |
|
127 | 138 | PROCESS |
|
128 | 139 | BEGIN -- PROCESS |
|
129 | 140 | WAIT UNTIL clk25MHz = '1'; |
|
130 | 141 | WAIT UNTIL clk25MHz = '1'; |
|
131 | 142 | WAIT UNTIL clk25MHz = '1'; |
|
132 | 143 | rstn <= '1'; |
|
133 | 144 | WAIT UNTIL clk25MHz = '1'; |
|
134 | 145 | |
|
135 | 146 | |
|
136 | 147 | WAIT FOR 100 ms; |
|
137 | 148 | |
|
138 | 149 | REPORT "*** END simulation ***" SEVERITY failure; |
|
139 | 150 | WAIT; |
|
140 | 151 | |
|
141 | 152 | END PROCESS; |
|
142 | 153 | |
|
143 | 154 | |
|
144 | 155 | ----------------------------------------------------------------------------- |
|
145 | 156 | PROCESS (clk49_152MHz, rstn) |
|
146 | 157 | BEGIN -- PROCESS |
|
147 | 158 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
148 | 159 | sample_counter_24k <= 0; |
|
149 | 160 | s_24576Hz <= '0'; |
|
150 | 161 | ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge |
|
151 | 162 | IF sample_counter_24k = 0 THEN |
|
152 | 163 | sample_counter_24k <= 2000; |
|
153 | 164 | s_24576Hz <= NOT s_24576Hz; |
|
154 | 165 | ELSE |
|
155 | 166 | sample_counter_24k <= sample_counter_24k - 1; |
|
156 | 167 | END IF; |
|
157 | 168 | END IF; |
|
158 | 169 | END PROCESS; |
|
159 | 170 | |
|
160 | 171 | PROCESS (clk25MHz, rstn) |
|
161 | 172 | BEGIN -- PROCESS |
|
162 | 173 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
163 | 174 | s_24_sync_reg_0 <= '0'; |
|
164 | 175 | s_24_sync_reg_1 <= '0'; |
|
165 | 176 | s_24576Hz_sync <= '0'; |
|
166 | 177 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
167 | 178 | s_24_sync_reg_0 <= s_24576Hz; |
|
168 | 179 | s_24_sync_reg_1 <= s_24_sync_reg_0; |
|
169 | 180 | s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1; |
|
170 | 181 | END IF; |
|
171 | 182 | END PROCESS; |
|
172 | 183 | |
|
173 | 184 | PROCESS (clk25MHz, rstn) |
|
174 | 185 | BEGIN -- PROCESS |
|
175 | 186 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
176 | 187 | sample_f0_val <= '0'; |
|
177 | 188 | sample_f1_val <= '0'; |
|
178 | 189 | sample_f2_val <= '0'; |
|
179 | 190 | |
|
180 | 191 | sample_counter_f1 <= 0; |
|
181 | 192 | sample_counter_f2 <= 0; |
|
182 | 193 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
183 | 194 | IF s_24576Hz_sync = '1' THEN |
|
184 | 195 | sample_f0_val <= '1'; |
|
185 | 196 | IF sample_counter_f1 = 0 THEN |
|
186 | 197 | sample_f1_val <= '1'; |
|
187 | 198 | sample_counter_f1 <= 5; |
|
188 | 199 | ELSE |
|
189 | 200 | sample_f1_val <= '0'; |
|
190 | 201 | sample_counter_f1 <= sample_counter_f1 -1; |
|
191 | 202 | END IF; |
|
192 | 203 | IF sample_counter_f2 = 0 THEN |
|
193 | 204 | sample_f2_val <= '1'; |
|
194 | 205 | sample_counter_f2 <= 95; |
|
195 | 206 | ELSE |
|
196 | 207 | sample_f2_val <= '0'; |
|
197 | 208 | sample_counter_f2 <= sample_counter_f2 -1; |
|
198 | 209 | END IF; |
|
199 | 210 | ELSE |
|
200 | 211 | sample_f0_val <= '0'; |
|
201 | 212 | sample_f1_val <= '0'; |
|
202 | 213 | sample_f2_val <= '0'; |
|
203 | 214 | END IF; |
|
204 | 215 | END IF; |
|
205 | 216 | END PROCESS; |
|
206 | 217 | |
|
207 | 218 | |
|
208 | 219 | |
|
209 | 220 | ----------------------------------------------------------------------------- |
|
210 | 221 | coarse_time <= (OTHERS => '1'); |
|
211 | 222 | |
|
212 | 223 | PROCESS (clk25MHz, rstn) |
|
213 | 224 | BEGIN |
|
214 | 225 | IF rstn = '0' THEN |
|
215 | 226 | fine_time <= (OTHERS => '0'); |
|
216 | 227 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN |
|
217 | 228 | fine_time <= fine_time + 1; |
|
218 | 229 | END IF; |
|
219 | 230 | END PROCESS; |
|
220 | 231 | |
|
221 | 232 | |
|
222 | 233 | sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444"; |
|
223 | 234 | sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444"; |
|
224 | 235 | sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444"; |
|
225 | 236 | |
|
226 | 237 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val); |
|
227 | 238 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val); |
|
228 | 239 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val); |
|
229 | 240 | ----------------------------------------------------------------------------- |
|
230 | 241 | |
|
231 | 242 | lpp_lfr_ms_1: lpp_lfr_ms |
|
232 | 243 | GENERIC MAP ( |
|
233 | 244 | Mem_use => use_CEL) |
|
234 | 245 | PORT MAP ( |
|
235 | 246 | clk => clk25MHz, |
|
236 | 247 | rstn => rstn, |
|
237 | 248 | -- |
|
238 | 249 | coarse_time => coarse_time, |
|
239 | 250 | fine_time => fine_time, |
|
240 | 251 | -- |
|
241 | 252 | sample_f0_wen => sample_f0_wen, |
|
242 | 253 | sample_f0_wdata => sample_f0_wdata, |
|
243 | 254 | sample_f1_wen => sample_f1_wen, |
|
244 | 255 | sample_f1_wdata => sample_f1_wdata, |
|
245 | 256 | sample_f2_wen => sample_f2_wen, |
|
246 | 257 | sample_f2_wdata => sample_f2_wdata, |
|
247 | 258 | -- |
|
248 | 259 | dma_addr => dma_addr, |
|
249 | 260 | dma_data => dma_data, |
|
250 | 261 | dma_valid => dma_valid, |
|
251 | 262 | dma_valid_burst => dma_valid_burst, |
|
252 | 263 | dma_ren => dma_ren, |
|
253 | 264 | dma_done => dma_done, |
|
254 | 265 | |
|
255 | 266 | ready_matrix_f0 => ready_matrix_f0, |
|
256 | 267 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
257 | 268 | ready_matrix_f1 => ready_matrix_f1, |
|
258 | 269 | ready_matrix_f2 => ready_matrix_f2, |
|
259 | 270 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
260 | 271 | error_bad_component_error => error_bad_component_error, |
|
261 | 272 | error_buffer_full => error_buffer_full, |
|
262 | 273 | error_input_fifo_write => error_input_fifo_write, |
|
263 | 274 | |
|
264 | 275 | debug_reg => debug_reg, |
|
276 | ||
|
277 | -- | |
|
278 | observation_vector_0 => observation_vector_0, | |
|
279 | observation_vector_1 => observation_vector_1, | |
|
280 | -- | |
|
265 | 281 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
266 | 282 | -- status_ready_matrix_f0 => status_ready_matrix_f0_1, |
|
267 | 283 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
268 | 284 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
269 | 285 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
270 | 286 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
271 | 287 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
272 | 288 | config_active_interruption_onError => config_active_interruption_onError, |
|
273 | 289 | addr_matrix_f0 => addr_matrix_f0, |
|
274 | 290 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
275 | 291 | addr_matrix_f1 => addr_matrix_f1, |
|
276 | 292 | addr_matrix_f2 => addr_matrix_f2, |
|
277 | 293 | matrix_time_f0 => matrix_time_f0, |
|
278 | 294 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
279 | 295 | matrix_time_f1 => matrix_time_f1, |
|
280 | 296 | matrix_time_f2 => matrix_time_f2); |
|
281 | 297 | |
|
282 | 298 | |
|
283 | 299 | |
|
284 | apbi.psel(4) <= '0'; | |
|
300 | ||
|
285 | 301 |
|
|
286 | 302 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
287 | 303 | GENERIC MAP ( |
|
288 | 304 | nb_data_by_buffer_size => 11, |
|
289 | 305 | nb_word_by_buffer_size => 11, |
|
290 | 306 | nb_snapshot_param_size => 11, |
|
291 | 307 | delta_vector_size => 20, |
|
292 | 308 | delta_vector_size_f0_2 => 7, |
|
293 | 309 | pindex => 4, |
|
294 | 310 | paddr => 4, |
|
295 | 311 | pmask => 16#fff#, |
|
296 | 312 | pirq_ms => 0, |
|
297 | 313 | pirq_wfp => 1, |
|
298 | 314 | top_lfr_version => (OTHERS => '0') |
|
299 | 315 | ) |
|
300 | 316 | PORT MAP ( |
|
301 | 317 | HCLK => clk25MHz, |
|
302 | 318 | HRESETn => rstn, |
|
303 | 319 | apbi => apbi, |
|
304 |
apbo => |
|
|
320 | apbo => apbo, | |
|
305 | 321 | |
|
306 | 322 | run_ms => OPEN, |
|
307 | 323 | |
|
308 | 324 | ready_matrix_f0 => ready_matrix_f0, |
|
309 | 325 | ready_matrix_f1 => ready_matrix_f1, |
|
310 | 326 | ready_matrix_f2 => ready_matrix_f2, |
|
311 | 327 | error_bad_component_error => error_bad_component_error, |
|
312 | 328 | error_buffer_full => error_buffer_full, -- TODO |
|
313 | 329 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
314 | 330 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
315 | 331 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
316 | 332 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
317 | 333 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
318 | 334 | config_active_interruption_onError => config_active_interruption_onError, |
|
319 | 335 | |
|
320 | 336 | matrix_time_f0 => matrix_time_f0, |
|
321 | 337 | matrix_time_f1 => matrix_time_f1, |
|
322 | 338 | matrix_time_f2 => matrix_time_f2, |
|
323 | 339 | |
|
324 | 340 | addr_matrix_f0 => addr_matrix_f0, |
|
325 | 341 | addr_matrix_f1 => addr_matrix_f1, |
|
326 | 342 | addr_matrix_f2 => addr_matrix_f2, |
|
327 | 343 | ------------------------------------------------------------------------- |
|
328 | 344 | status_full => status_full, |
|
329 | 345 | status_full_ack => status_full_ack, |
|
330 | 346 | status_full_err => status_full_err, |
|
331 | 347 | status_new_err => status_new_err, |
|
332 | 348 | data_shaping_BW => OPEN, |
|
333 | 349 | data_shaping_SP0 => OPEN, |
|
334 | 350 | data_shaping_SP1 => OPEN, |
|
335 | 351 | data_shaping_R0 => OPEN, |
|
336 | 352 | data_shaping_R1 => OPEN, |
|
337 | 353 | delta_snapshot => OPEN, |
|
338 | 354 | delta_f0 => OPEN, |
|
339 | 355 | delta_f0_2 => OPEN, |
|
340 | 356 | delta_f1 => OPEN, |
|
341 | 357 | delta_f2 => OPEN, |
|
342 | 358 | nb_data_by_buffer => OPEN, |
|
343 | 359 | nb_word_by_buffer => OPEN, |
|
344 | 360 | nb_snapshot_param => OPEN, |
|
345 | 361 | enable_f0 => OPEN, |
|
346 | 362 | enable_f1 => OPEN, |
|
347 | 363 | enable_f2 => OPEN, |
|
348 | 364 | enable_f3 => OPEN, |
|
349 | 365 | burst_f0 => OPEN, |
|
350 | 366 | burst_f1 => OPEN, |
|
351 | 367 | burst_f2 => OPEN, |
|
352 | 368 | run => OPEN, |
|
353 | 369 | addr_data_f0 => OPEN, |
|
354 | 370 | addr_data_f1 => OPEN, |
|
355 | 371 | addr_data_f2 => OPEN, |
|
356 | 372 | addr_data_f3 => OPEN, |
|
357 | 373 | start_date => OPEN); |
|
358 | 374 | |
|
359 | 375 | |
|
360 | 376 | |
|
361 | 377 | |
|
378 | read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us; | |
|
362 | 379 | |
|
380 | PROCESS (clk25MHz, rstn) | |
|
381 | BEGIN | |
|
382 | IF rstn = '0' THEN | |
|
383 | ready_reg <= (OTHERS => '0'); | |
|
384 | --read_status <= '0'; | |
|
385 | apbi.psel(4) <= '0'; | |
|
386 | apbi.pwrite <= '0'; | |
|
387 | apbi.penable <= '0'; | |
|
388 | apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0'); | |
|
389 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN | |
|
390 | apbi.psel(4) <= '1'; | |
|
391 | apbi.paddr(7 DOWNTO 2) <= "000001"; | |
|
392 | apbi.penable <= '1'; | |
|
393 | read_status <= apbo.pirq(0); | |
|
363 | 394 | |
|
395 | IF read_status = '1' AND irq_ongoing = '0' THEN | |
|
396 | ready_reg <= apbo.prdata(5 DOWNTO 0); | |
|
397 | irq_ongoing <= '1'; | |
|
398 | END IF; | |
|
399 | ||
|
400 | IF read_status_t = '0' THEN | |
|
401 | apbi.pwrite <= '0'; | |
|
402 | ELSE | |
|
403 | irq_ongoing <= '0'; | |
|
404 | apbi.pwrite <= '1'; | |
|
405 | apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0'); | |
|
406 | apbi.pwdata(5 DOWNTO 0) <= ready_reg; | |
|
407 | ready_reg <= (OTHERS => '0'); | |
|
408 | END IF; | |
|
409 | ||
|
410 | END IF; | |
|
411 | END PROCESS; | |
|
364 | 412 | |
|
365 | 413 | |
|
366 | 414 | |
|
367 | 415 | |
|
368 | 416 | |
|
369 | 417 | |
|
370 | 418 | |
|
371 | 419 | |
|
372 | 420 | |
|
373 | 421 | |
|
374 | 422 | -- PROCESS (clk25MHz, rstn) |
|
375 | 423 | -- BEGIN -- PROCESS |
|
376 | 424 | -- IF rstn = '0' THEN -- asynchronous reset (active low) |
|
377 | 425 | -- status_ready_matrix_f0 <= '0'; |
|
378 | 426 | ---- status_ready_matrix_f0_1 <= '0'; |
|
379 | 427 | -- status_ready_matrix_f1 <= '0'; |
|
380 | 428 | -- status_ready_matrix_f2 <= '0'; |
|
381 | 429 | -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
382 | 430 | -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0; |
|
383 | 431 | ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1; |
|
384 | 432 | -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1; |
|
385 | 433 | -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2; |
|
386 | 434 | -- END IF; |
|
387 | 435 | -- END PROCESS; |
|
388 | 436 | |
|
389 | 437 | |
|
390 | 438 | |
|
391 | 439 | -- status_error_anticipating_empty_fifo <= '0'; |
|
392 | 440 | -- status_error_bad_component_error <= '0'; |
|
393 | 441 | |
|
394 | 442 | -- config_active_interruption_onNewMatrix <= '0'; |
|
395 | 443 | -- config_active_interruption_onError <= '0'; |
|
396 | 444 | -- addr_matrix_f0 <= (OTHERS => '0'); |
|
397 | 445 | -- addr_matrix_f0_1 <= (OTHERS => '0'); |
|
398 | 446 | -- addr_matrix_f1 <= (OTHERS => '0'); |
|
399 | 447 | -- addr_matrix_f2 <= (OTHERS => '0'); |
|
400 | 448 | |
|
401 | 449 | |
|
402 | 450 | PROCESS (clk25MHz, rstn) |
|
403 | 451 | BEGIN -- PROCESS |
|
404 | 452 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
405 | 453 | |
|
406 | 454 | dma_ren <= '1'; |
|
407 | 455 | dma_done <= '0'; |
|
408 | 456 | ren_counter <= 0; |
|
409 | 457 | ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge |
|
410 | 458 | dma_ren <= '1'; |
|
411 | 459 | dma_done <= '0'; |
|
412 | 460 | |
|
413 | 461 | IF dma_valid_burst = '1' THEN |
|
414 | 462 | ren_counter <= 17; |
|
415 | 463 | END IF; |
|
416 | 464 | |
|
417 | 465 | IF ren_counter > 1 THEN |
|
418 | 466 | ren_counter <= ren_counter - 1; |
|
419 | 467 | dma_ren <= '0'; |
|
420 | 468 | END IF; |
|
421 | 469 | |
|
422 | 470 | IF ren_counter = 1 THEN |
|
423 | 471 | ren_counter <= 0; |
|
424 | 472 | dma_done <= '1'; |
|
425 | 473 | END IF; |
|
426 | 474 | |
|
427 | 475 | END IF; |
|
428 | 476 | END PROCESS; |
|
429 | 477 | |
|
430 | 478 | |
|
431 | 479 | END beh; |
|
432 | 480 |
@@ -1,212 +1,230 | |||
|
1 | 1 | onerror {resume} |
|
2 | 2 | quietly WaveActivateNextPane {} 0 |
|
3 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0) | |
|
4 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1) | |
|
5 | add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2) | |
|
6 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5) | |
|
7 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4) | |
|
8 | add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3) | |
|
9 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8) | |
|
10 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7) | |
|
11 | add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6) | |
|
12 | add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg | |
|
13 | add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi | |
|
14 | add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo | |
|
15 | add wave -noupdate -expand -group debug /tb/ready_reg | |
|
16 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0) | |
|
17 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1) | |
|
18 | add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2) | |
|
19 | add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal | |
|
20 | add wave -noupdate -divider {New Divider} | |
|
3 | 21 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen |
|
4 | 22 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata |
|
5 | 23 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen |
|
6 | 24 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata |
|
7 | 25 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen |
|
8 | 26 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata |
|
9 | 27 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen |
|
10 | 28 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full |
|
11 | 29 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full |
|
12 | 30 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty |
|
13 | 31 | add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren |
|
14 | 32 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect |
|
15 | 33 | add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect |
|
16 | 34 | add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
17 | 35 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen |
|
18 | 36 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full |
|
19 | 37 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full |
|
20 | 38 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty |
|
21 | 39 | add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren |
|
22 | 40 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen |
|
23 | 41 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk |
|
24 | 42 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full |
|
25 | 43 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full |
|
26 | 44 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty |
|
27 | 45 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren |
|
28 | 46 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull |
|
29 | 47 | add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s |
|
30 | 48 | add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
31 | 49 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen |
|
32 | 50 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full |
|
33 | 51 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full |
|
34 | 52 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty |
|
35 | 53 | add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren |
|
36 | 54 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel |
|
37 | 55 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft |
|
38 | 56 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0 |
|
39 | 57 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1 |
|
40 | 58 | add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2 |
|
41 | 59 | add wave -noupdate /tb/lpp_lfr_ms_1/status_channel |
|
42 | 60 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
43 | 61 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray |
|
44 | 62 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray |
|
45 | 63 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray |
|
46 | 64 | add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray |
|
47 | 65 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load |
|
48 | 66 | add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory |
|
49 | 67 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full |
|
50 | 68 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty |
|
51 | 69 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full |
|
52 | 70 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata |
|
53 | 71 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen |
|
54 | 72 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked |
|
55 | 73 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata |
|
56 | 74 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren |
|
57 | 75 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto |
|
58 | 76 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done |
|
59 | 77 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start |
|
60 | 78 | add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data |
|
61 | 79 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty |
|
62 | 80 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren |
|
63 | 81 | add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data |
|
64 | 82 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full |
|
65 | 83 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen |
|
66 | 84 | add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1 |
|
67 | 85 | add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2 |
|
68 | 86 | add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res |
|
69 | 87 | add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state |
|
70 | 88 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty |
|
71 | 89 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full |
|
72 | 90 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata |
|
73 | 91 | add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen |
|
74 | 92 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect |
|
75 | 93 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s |
|
76 | 94 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect |
|
77 | 95 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s |
|
78 | 96 | add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray |
|
79 | 97 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect |
|
80 | 98 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s |
|
81 | 99 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect |
|
82 | 100 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s |
|
83 | 101 | add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
84 | 102 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 |
|
85 | 103 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end |
|
86 | 104 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 |
|
87 | 105 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end |
|
88 | 106 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready |
|
89 | 107 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready |
|
90 | 108 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing |
|
91 | 109 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data |
|
92 | 110 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty |
|
93 | 111 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren |
|
94 | 112 | add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status |
|
95 | 113 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr |
|
96 | 114 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data |
|
97 | 115 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done |
|
98 | 116 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren |
|
99 | 117 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid |
|
100 | 118 | add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst |
|
101 | 119 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1 |
|
102 | 120 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2 |
|
103 | 121 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1 |
|
104 | 122 | add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2 |
|
105 | 123 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state |
|
106 | 124 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type |
|
107 | 125 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre |
|
108 | 126 | add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type |
|
109 | 127 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok |
|
110 | 128 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty |
|
111 | 129 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo |
|
112 | 130 | add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error |
|
113 | 131 | add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full |
|
114 | 132 | add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write |
|
115 | 133 | add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1 |
|
116 | 134 | add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2 |
|
117 | 135 | add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res |
|
118 | 136 | add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp |
|
119 | 137 | add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl |
|
120 | 138 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse |
|
121 | 139 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen |
|
122 | 140 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata |
|
123 | 141 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren |
|
124 | 142 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata |
|
125 | 143 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty |
|
126 | 144 | add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full |
|
127 | 145 | add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full |
|
128 | 146 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray |
|
129 | 147 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray |
|
130 | 148 | add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult |
|
131 | 149 | add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1 |
|
132 | 150 | add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2 |
|
133 | 151 | add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res |
|
134 | 152 | add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add |
|
135 | 153 | add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr |
|
136 | 154 | add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load |
|
137 | 155 | add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1 |
|
138 | 156 | add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2 |
|
139 | 157 | add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res |
|
140 | 158 | add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp |
|
141 | 159 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk |
|
142 | 160 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn |
|
143 | 161 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix |
|
144 | 162 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix |
|
145 | 163 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix |
|
146 | 164 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time |
|
147 | 165 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix |
|
148 | 166 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix |
|
149 | 167 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix |
|
150 | 168 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time |
|
151 | 169 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix |
|
152 | 170 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix |
|
153 | 171 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix |
|
154 | 172 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time |
|
155 | 173 | add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg |
|
156 | 174 | add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time |
|
157 | 175 | add wave -noupdate /tb/lpp_lfr_ms_1/fine_time |
|
158 | 176 | add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time |
|
159 | 177 | add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status |
|
160 | 178 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component |
|
161 | 179 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0 |
|
162 | 180 | add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1 |
|
163 | 181 | add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms |
|
164 | 182 | add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component |
|
165 | 183 | add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel |
|
166 | 184 | add wave -noupdate /tb/lpp_lfr_ms_1/all_time |
|
167 | 185 | add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a |
|
168 | 186 | add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b |
|
169 | 187 | add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1 |
|
170 | 188 | add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2 |
|
171 | 189 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen |
|
172 | 190 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren |
|
173 | 191 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata |
|
174 | 192 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full |
|
175 | 193 | add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty |
|
176 | 194 | add wave -noupdate /tb/matrix_time_f0 |
|
177 | 195 | add wave -noupdate /tb/matrix_time_f1 |
|
178 | 196 | add wave -noupdate /tb/matrix_time_f2 |
|
179 | 197 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk |
|
180 | 198 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn |
|
181 | 199 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix |
|
182 | 200 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix |
|
183 | 201 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix |
|
184 | 202 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time |
|
185 | 203 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix |
|
186 | 204 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix |
|
187 | 205 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix |
|
188 | 206 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time |
|
189 | 207 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix |
|
190 | 208 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix |
|
191 | 209 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix |
|
192 | 210 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time |
|
193 | 211 | add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg |
|
194 | 212 | TreeUpdate [SetDefaultTree] |
|
195 | WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0} | |
|
213 | WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0} | |
|
196 | 214 | configure wave -namecolwidth 486 |
|
197 | 215 | configure wave -valuecolwidth 112 |
|
198 | 216 | configure wave -justifyvalue left |
|
199 | 217 | configure wave -signalnamewidth 0 |
|
200 | 218 | configure wave -snapdistance 10 |
|
201 | 219 | configure wave -datasetprefix 0 |
|
202 | 220 | configure wave -rowmargin 4 |
|
203 | 221 | configure wave -childrowmargin 2 |
|
204 | 222 | configure wave -gridoffset 0 |
|
205 | 223 | configure wave -gridperiod 1 |
|
206 | 224 | configure wave -griddelta 40 |
|
207 | 225 | configure wave -timeline 0 |
|
208 | 226 | configure wave -timelineunits ps |
|
209 | 227 | update |
|
210 |
WaveRestoreZoom {0 ps} {1 |
|
|
228 | WaveRestoreZoom {124629370639 ps} {125891337681 ps} | |
|
211 | 229 | bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 |
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212 | 230 | bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0 |
@@ -1,735 +1,748 | |||
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1 | 1 | LIBRARY ieee; |
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2 | 2 | USE ieee.std_logic_1164.ALL; |
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3 | 3 | USE ieee.numeric_std.ALL; |
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4 | 4 | |
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5 | 5 | LIBRARY lpp; |
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6 | 6 | USE lpp.lpp_ad_conv.ALL; |
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7 | 7 | USE lpp.iir_filter.ALL; |
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8 | 8 | USE lpp.FILTERcfg.ALL; |
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9 | 9 | USE lpp.lpp_memory.ALL; |
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10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
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11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
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12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
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13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
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14 | 14 | USE lpp.general_purpose.ALL; |
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15 | 15 | |
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16 | 16 | LIBRARY techmap; |
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17 | 17 | USE techmap.gencomp.ALL; |
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18 | 18 | |
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19 | 19 | LIBRARY grlib; |
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20 | 20 | USE grlib.amba.ALL; |
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21 | 21 | USE grlib.stdlib.ALL; |
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22 | 22 | USE grlib.devices.ALL; |
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23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
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24 | 24 | |
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25 | 25 | ENTITY lpp_lfr IS |
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26 | 26 | GENERIC ( |
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27 | 27 | Mem_use : INTEGER := use_RAM; |
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28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
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29 | 29 | nb_word_by_buffer_size : INTEGER := 11; |
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30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
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31 | 31 | delta_vector_size : INTEGER := 20; |
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32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
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33 | 33 | |
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34 | 34 | pindex : INTEGER := 4; |
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35 | 35 | paddr : INTEGER := 4; |
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36 | 36 | pmask : INTEGER := 16#fff#; |
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37 | 37 | pirq_ms : INTEGER := 0; |
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38 | 38 | pirq_wfp : INTEGER := 1; |
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39 | 39 | |
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40 | 40 | hindex : INTEGER := 2; |
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41 | 41 | |
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42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0') |
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43 | 43 | |
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44 | 44 | ); |
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45 | 45 | PORT ( |
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46 | 46 | clk : IN STD_LOGIC; |
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47 | 47 | rstn : IN STD_LOGIC; |
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48 | 48 | -- SAMPLE |
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49 | 49 | sample_B : IN Samples(2 DOWNTO 0); |
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50 | 50 | sample_E : IN Samples(4 DOWNTO 0); |
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51 | 51 | sample_val : IN STD_LOGIC; |
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52 | 52 | -- APB |
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53 | 53 | apbi : IN apb_slv_in_type; |
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54 | 54 | apbo : OUT apb_slv_out_type; |
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55 | 55 | -- AHB |
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56 | 56 | ahbi : IN AHB_Mst_In_Type; |
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57 | 57 | ahbo : OUT AHB_Mst_Out_Type; |
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58 | 58 | -- TIME |
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59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
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60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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61 | 61 | -- |
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62 | 62 | data_shaping_BW : OUT STD_LOGIC; |
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63 | 63 | -- |
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64 | -- | |
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65 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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66 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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67 | ||
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64 | 68 |
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65 | 69 | |
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66 | 70 | --debug |
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67 | 71 | --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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68 | 72 | --debug_f0_data_valid : OUT STD_LOGIC; |
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69 | 73 | --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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70 | 74 | --debug_f1_data_valid : OUT STD_LOGIC; |
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71 | 75 | --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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72 | 76 | --debug_f2_data_valid : OUT STD_LOGIC; |
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73 | 77 | --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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74 | 78 | --debug_f3_data_valid : OUT STD_LOGIC; |
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75 | 79 | |
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76 | 80 | ---- debug FIFO_IN |
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77 | 81 | --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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78 | 82 | --debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
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79 | 83 | --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | 84 | --debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
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81 | 85 | --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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82 | 86 | --debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
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83 | 87 | --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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84 | 88 | --debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
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85 | 89 | |
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86 | 90 | ----debug FIFO OUT |
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87 | 91 | --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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88 | 92 | --debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
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89 | 93 | --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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90 | 94 | --debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
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91 | 95 | --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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92 | 96 | --debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
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93 | 97 | --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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94 | 98 | --debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
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95 | 99 | |
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96 | 100 | ----debug DMA IN |
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97 | 101 | --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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98 | 102 | --debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
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99 | 103 | --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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100 | 104 | --debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
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101 | 105 | --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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102 | 106 | --debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
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103 | 107 | --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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104 | 108 | --debug_f3_data_dma_in_valid : OUT STD_LOGIC |
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105 | 109 | ); |
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106 | 110 | END lpp_lfr; |
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107 | 111 | |
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108 | 112 | ARCHITECTURE beh OF lpp_lfr IS |
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109 | 113 | --SIGNAL sample : Samples14v(7 DOWNTO 0); |
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110 | 114 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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111 | 115 | -- |
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112 | 116 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
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113 | 117 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
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114 | 118 | SIGNAL data_shaping_R0 : STD_LOGIC; |
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115 | 119 | SIGNAL data_shaping_R1 : STD_LOGIC; |
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116 | 120 | -- |
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117 | 121 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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118 | 122 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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119 | 123 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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120 | 124 | -- |
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121 | 125 | SIGNAL sample_f0_val : STD_LOGIC; |
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122 | 126 | SIGNAL sample_f1_val : STD_LOGIC; |
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123 | 127 | SIGNAL sample_f2_val : STD_LOGIC; |
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124 | 128 | SIGNAL sample_f3_val : STD_LOGIC; |
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125 | 129 | -- |
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126 | 130 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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127 | 131 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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128 | 132 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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129 | 133 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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130 | 134 | -- |
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131 | 135 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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132 | 136 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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133 | 137 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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134 | 138 | |
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135 | 139 | -- SM |
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136 | 140 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
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137 | 141 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
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138 | 142 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
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139 | 143 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
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140 | 144 | -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
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141 | 145 | SIGNAL error_bad_component_error : STD_LOGIC; |
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142 | 146 | -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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143 | 147 | SIGNAL status_ready_matrix_f0 : STD_LOGIC; |
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144 | 148 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
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145 | 149 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
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146 | 150 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
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147 | 151 | -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
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148 | 152 | -- SIGNAL status_error_bad_component_error : STD_LOGIC; |
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149 | 153 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
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150 | 154 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
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151 | 155 | SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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152 | 156 | -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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153 | 157 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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154 | 158 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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155 | 159 | |
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156 | 160 | -- WFP |
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157 | 161 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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158 | 162 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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159 | 163 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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160 | 164 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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161 | 165 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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162 | 166 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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163 | 167 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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164 | 168 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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165 | 169 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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166 | 170 | |
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167 | 171 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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168 | 172 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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169 | 173 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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170 | 174 | SIGNAL enable_f0 : STD_LOGIC; |
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171 | 175 | SIGNAL enable_f1 : STD_LOGIC; |
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172 | 176 | SIGNAL enable_f2 : STD_LOGIC; |
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173 | 177 | SIGNAL enable_f3 : STD_LOGIC; |
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174 | 178 | SIGNAL burst_f0 : STD_LOGIC; |
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175 | 179 | SIGNAL burst_f1 : STD_LOGIC; |
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176 | 180 | SIGNAL burst_f2 : STD_LOGIC; |
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177 | 181 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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178 | 182 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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179 | 183 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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180 | 184 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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181 | 185 | |
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182 | 186 | SIGNAL run : STD_LOGIC; |
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183 | 187 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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184 | 188 | |
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185 | 189 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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186 | 190 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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187 | 191 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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188 | 192 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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189 | 193 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
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190 | 194 | --f1 |
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191 | 195 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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192 | 196 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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193 | 197 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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194 | 198 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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195 | 199 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
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196 | 200 | --f2 |
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197 | 201 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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198 | 202 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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199 | 203 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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200 | 204 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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201 | 205 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
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202 | 206 | --f3 |
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203 | 207 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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204 | 208 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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205 | 209 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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206 | 210 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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207 | 211 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
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208 | 212 | |
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209 | 213 | ----------------------------------------------------------------------------- |
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210 | 214 | -- |
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211 | 215 | ----------------------------------------------------------------------------- |
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212 | 216 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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213 | 217 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
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214 | 218 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
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215 | 219 | --f1 |
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216 | 220 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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217 | 221 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
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218 | 222 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
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219 | 223 | --f2 |
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220 | 224 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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221 | 225 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
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222 | 226 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
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223 | 227 | --f3 |
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224 | 228 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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225 | 229 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
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226 | 230 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
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227 | 231 | |
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228 | 232 | ----------------------------------------------------------------------------- |
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229 | 233 | -- DMA RR |
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230 | 234 | ----------------------------------------------------------------------------- |
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231 | 235 | SIGNAL dma_sel_valid : STD_LOGIC; |
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232 | 236 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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233 | 237 | SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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234 | 238 | SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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235 | 239 | SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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236 | 240 | |
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237 | 241 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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238 | 242 | SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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239 | 243 | |
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240 | 244 | ----------------------------------------------------------------------------- |
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241 | 245 | -- DMA_REG |
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242 | 246 | ----------------------------------------------------------------------------- |
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243 | 247 | SIGNAL ongoing_reg : STD_LOGIC; |
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244 | 248 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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245 | 249 | SIGNAL dma_send_reg : STD_LOGIC; |
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246 | 250 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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247 | 251 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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248 | 252 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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249 | 253 | |
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250 | 254 | |
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251 | 255 | ----------------------------------------------------------------------------- |
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252 | 256 | -- DMA |
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253 | 257 | ----------------------------------------------------------------------------- |
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254 | 258 | SIGNAL dma_send : STD_LOGIC; |
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255 | 259 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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256 | 260 | SIGNAL dma_done : STD_LOGIC; |
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257 | 261 | SIGNAL dma_ren : STD_LOGIC; |
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258 | 262 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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259 | 263 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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260 | 264 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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261 | 265 | |
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262 | 266 | ----------------------------------------------------------------------------- |
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263 | 267 | -- MS |
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264 | 268 | ----------------------------------------------------------------------------- |
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265 | 269 | |
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266 | 270 | SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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267 | 271 | SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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268 | 272 | SIGNAL data_ms_valid : STD_LOGIC; |
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269 | 273 | SIGNAL data_ms_valid_burst : STD_LOGIC; |
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270 | 274 | SIGNAL data_ms_ren : STD_LOGIC; |
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271 | 275 | SIGNAL data_ms_done : STD_LOGIC; |
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272 | 276 | SIGNAL dma_ms_ongoing : STD_LOGIC; |
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273 | 277 | |
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274 | 278 | SIGNAL run_ms : STD_LOGIC; |
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275 | 279 | SIGNAL ms_softandhard_rstn : STD_LOGIC; |
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276 | 280 | |
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277 | 281 | SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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278 | 282 | -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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279 | 283 | SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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280 | 284 | SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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281 | 285 | |
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282 | 286 | |
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283 | 287 | SIGNAL error_buffer_full : STD_LOGIC; |
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284 | 288 | SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
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285 | 289 | |
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286 | 290 | SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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291 | SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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287 | 292 | |
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288 | 293 | BEGIN |
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289 | 294 | |
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290 | 295 | sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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291 | 296 | sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
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292 | 297 | |
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293 | 298 | --all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
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294 | 299 | -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
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295 | 300 | --END GENERATE all_channel; |
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296 | 301 | |
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297 | 302 | ----------------------------------------------------------------------------- |
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298 | 303 | lpp_lfr_filter_1 : lpp_lfr_filter |
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299 | 304 | GENERIC MAP ( |
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300 | 305 | Mem_use => Mem_use) |
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301 | 306 | PORT MAP ( |
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302 | 307 | sample => sample_s, |
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303 | 308 | sample_val => sample_val, |
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304 | 309 | clk => clk, |
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305 | 310 | rstn => rstn, |
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306 | 311 | data_shaping_SP0 => data_shaping_SP0, |
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307 | 312 | data_shaping_SP1 => data_shaping_SP1, |
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308 | 313 | data_shaping_R0 => data_shaping_R0, |
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309 | 314 | data_shaping_R1 => data_shaping_R1, |
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310 | 315 | sample_f0_val => sample_f0_val, |
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311 | 316 | sample_f1_val => sample_f1_val, |
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312 | 317 | sample_f2_val => sample_f2_val, |
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313 | 318 | sample_f3_val => sample_f3_val, |
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314 | 319 | sample_f0_wdata => sample_f0_data, |
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315 | 320 | sample_f1_wdata => sample_f1_data, |
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316 | 321 | sample_f2_wdata => sample_f2_data, |
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317 | 322 | sample_f3_wdata => sample_f3_data); |
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318 | 323 | |
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319 | 324 | ----------------------------------------------------------------------------- |
|
320 | 325 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
|
321 | 326 | GENERIC MAP ( |
|
322 | 327 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
323 | 328 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
324 | 329 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
325 | 330 | delta_vector_size => delta_vector_size, |
|
326 | 331 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
|
327 | 332 | pindex => pindex, |
|
328 | 333 | paddr => paddr, |
|
329 | 334 | pmask => pmask, |
|
330 | 335 | pirq_ms => pirq_ms, |
|
331 | 336 | pirq_wfp => pirq_wfp, |
|
332 | 337 | top_lfr_version => top_lfr_version) |
|
333 | 338 | PORT MAP ( |
|
334 | 339 | HCLK => clk, |
|
335 | 340 | HRESETn => rstn, |
|
336 | 341 | apbi => apbi, |
|
337 | 342 | apbo => apbo, |
|
338 | 343 | |
|
339 | 344 | run_ms => run_ms, |
|
340 | 345 | |
|
341 | 346 | ready_matrix_f0 => ready_matrix_f0, |
|
342 | 347 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
|
343 | 348 | ready_matrix_f1 => ready_matrix_f1, |
|
344 | 349 | ready_matrix_f2 => ready_matrix_f2, |
|
345 | 350 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
|
346 | 351 | error_bad_component_error => error_bad_component_error, |
|
347 | 352 | error_buffer_full => error_buffer_full, -- TODO |
|
348 | 353 | error_input_fifo_write => error_input_fifo_write, -- TODO |
|
349 | 354 | -- debug_reg => debug_reg, |
|
350 | 355 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
351 | 356 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
|
352 | 357 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
353 | 358 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
354 | 359 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
|
355 | 360 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
356 | 361 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
357 | 362 | config_active_interruption_onError => config_active_interruption_onError, |
|
358 | 363 | |
|
359 | 364 | matrix_time_f0 => matrix_time_f0, |
|
360 | 365 | -- matrix_time_f0_1 => matrix_time_f0_1, |
|
361 | 366 | matrix_time_f1 => matrix_time_f1, |
|
362 | 367 | matrix_time_f2 => matrix_time_f2, |
|
363 | 368 | |
|
364 | 369 | addr_matrix_f0 => addr_matrix_f0, |
|
365 | 370 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
|
366 | 371 | addr_matrix_f1 => addr_matrix_f1, |
|
367 | 372 | addr_matrix_f2 => addr_matrix_f2, |
|
368 | 373 | ------------------------------------------------------------------------- |
|
369 | 374 | status_full => status_full, |
|
370 | 375 | status_full_ack => status_full_ack, |
|
371 | 376 | status_full_err => status_full_err, |
|
372 | 377 | status_new_err => status_new_err, |
|
373 | 378 | data_shaping_BW => data_shaping_BW, |
|
374 | 379 | data_shaping_SP0 => data_shaping_SP0, |
|
375 | 380 | data_shaping_SP1 => data_shaping_SP1, |
|
376 | 381 | data_shaping_R0 => data_shaping_R0, |
|
377 | 382 | data_shaping_R1 => data_shaping_R1, |
|
378 | 383 | delta_snapshot => delta_snapshot, |
|
379 | 384 | delta_f0 => delta_f0, |
|
380 | 385 | delta_f0_2 => delta_f0_2, |
|
381 | 386 | delta_f1 => delta_f1, |
|
382 | 387 | delta_f2 => delta_f2, |
|
383 | 388 | nb_data_by_buffer => nb_data_by_buffer, |
|
384 | 389 | nb_word_by_buffer => nb_word_by_buffer, |
|
385 | 390 | nb_snapshot_param => nb_snapshot_param, |
|
386 | 391 | enable_f0 => enable_f0, |
|
387 | 392 | enable_f1 => enable_f1, |
|
388 | 393 | enable_f2 => enable_f2, |
|
389 | 394 | enable_f3 => enable_f3, |
|
390 | 395 | burst_f0 => burst_f0, |
|
391 | 396 | burst_f1 => burst_f1, |
|
392 | 397 | burst_f2 => burst_f2, |
|
393 | 398 | run => run, |
|
394 | 399 | addr_data_f0 => addr_data_f0, |
|
395 | 400 | addr_data_f1 => addr_data_f1, |
|
396 | 401 | addr_data_f2 => addr_data_f2, |
|
397 | 402 | addr_data_f3 => addr_data_f3, |
|
398 |
start_date => start_date |
|
|
403 | start_date => start_date, | |
|
404 | debug_signal => debug_signal); | |
|
399 | 405 | |
|
400 | 406 | ----------------------------------------------------------------------------- |
|
401 | 407 | ----------------------------------------------------------------------------- |
|
402 | 408 | lpp_waveform_1 : lpp_waveform |
|
403 | 409 | GENERIC MAP ( |
|
404 | 410 | tech => inferred, |
|
405 | 411 | data_size => 6*16, |
|
406 | 412 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
407 | 413 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
408 | 414 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
409 | 415 | delta_vector_size => delta_vector_size, |
|
410 | 416 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
411 | 417 | ) |
|
412 | 418 | PORT MAP ( |
|
413 | 419 | clk => clk, |
|
414 | 420 | rstn => rstn, |
|
415 | 421 | |
|
416 | 422 | reg_run => run, |
|
417 | 423 | reg_start_date => start_date, |
|
418 | 424 | reg_delta_snapshot => delta_snapshot, |
|
419 | 425 | reg_delta_f0 => delta_f0, |
|
420 | 426 | reg_delta_f0_2 => delta_f0_2, |
|
421 | 427 | reg_delta_f1 => delta_f1, |
|
422 | 428 | reg_delta_f2 => delta_f2, |
|
423 | 429 | |
|
424 | 430 | enable_f0 => enable_f0, |
|
425 | 431 | enable_f1 => enable_f1, |
|
426 | 432 | enable_f2 => enable_f2, |
|
427 | 433 | enable_f3 => enable_f3, |
|
428 | 434 | burst_f0 => burst_f0, |
|
429 | 435 | burst_f1 => burst_f1, |
|
430 | 436 | burst_f2 => burst_f2, |
|
431 | 437 | |
|
432 | 438 | nb_data_by_buffer => nb_data_by_buffer, |
|
433 | 439 | nb_word_by_buffer => nb_word_by_buffer, |
|
434 | 440 | nb_snapshot_param => nb_snapshot_param, |
|
435 | 441 | status_full => status_full, |
|
436 | 442 | status_full_ack => status_full_ack, |
|
437 | 443 | status_full_err => status_full_err, |
|
438 | 444 | status_new_err => status_new_err, |
|
439 | 445 | |
|
440 | 446 | coarse_time => coarse_time, |
|
441 | 447 | fine_time => fine_time, |
|
442 | 448 | |
|
443 | 449 | --f0 |
|
444 | 450 | addr_data_f0 => addr_data_f0, |
|
445 | 451 | data_f0_in_valid => sample_f0_val, |
|
446 | 452 | data_f0_in => sample_f0_data, |
|
447 | 453 | --f1 |
|
448 | 454 | addr_data_f1 => addr_data_f1, |
|
449 | 455 | data_f1_in_valid => sample_f1_val, |
|
450 | 456 | data_f1_in => sample_f1_data, |
|
451 | 457 | --f2 |
|
452 | 458 | addr_data_f2 => addr_data_f2, |
|
453 | 459 | data_f2_in_valid => sample_f2_val, |
|
454 | 460 | data_f2_in => sample_f2_data, |
|
455 | 461 | --f3 |
|
456 | 462 | addr_data_f3 => addr_data_f3, |
|
457 | 463 | data_f3_in_valid => sample_f3_val, |
|
458 | 464 | data_f3_in => sample_f3_data, |
|
459 | 465 | -- OUTPUT -- DMA interface |
|
460 | 466 | --f0 |
|
461 | 467 | data_f0_addr_out => data_f0_addr_out_s, |
|
462 | 468 | data_f0_data_out => data_f0_data_out, |
|
463 | 469 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
464 | 470 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
465 | 471 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
466 | 472 | --f1 |
|
467 | 473 | data_f1_addr_out => data_f1_addr_out_s, |
|
468 | 474 | data_f1_data_out => data_f1_data_out, |
|
469 | 475 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
470 | 476 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
471 | 477 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
472 | 478 | --f2 |
|
473 | 479 | data_f2_addr_out => data_f2_addr_out_s, |
|
474 | 480 | data_f2_data_out => data_f2_data_out, |
|
475 | 481 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
476 | 482 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
477 | 483 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
478 | 484 | --f3 |
|
479 | 485 | data_f3_addr_out => data_f3_addr_out_s, |
|
480 | 486 | data_f3_data_out => data_f3_data_out, |
|
481 | 487 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
482 | 488 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
483 | 489 | data_f3_data_out_ren => data_f3_data_out_ren , |
|
484 | 490 | |
|
485 | 491 | ------------------------------------------------------------------------- |
|
486 | 492 | observation_reg => OPEN |
|
487 | 493 | |
|
488 | 494 | ); |
|
489 | 495 | |
|
490 | 496 | |
|
491 | 497 | ----------------------------------------------------------------------------- |
|
492 | 498 | -- TEMP |
|
493 | 499 | ----------------------------------------------------------------------------- |
|
494 | 500 | |
|
495 | 501 | PROCESS (clk, rstn) |
|
496 | 502 | BEGIN -- PROCESS |
|
497 | 503 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
498 | 504 | data_f0_data_out_valid <= '0'; |
|
499 | 505 | data_f0_data_out_valid_burst <= '0'; |
|
500 | 506 | data_f1_data_out_valid <= '0'; |
|
501 | 507 | data_f1_data_out_valid_burst <= '0'; |
|
502 | 508 | data_f2_data_out_valid <= '0'; |
|
503 | 509 | data_f2_data_out_valid_burst <= '0'; |
|
504 | 510 | data_f3_data_out_valid <= '0'; |
|
505 | 511 | data_f3_data_out_valid_burst <= '0'; |
|
506 | 512 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
507 | 513 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
508 | 514 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
509 | 515 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
510 | 516 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
511 | 517 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
512 | 518 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
513 | 519 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
514 | 520 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
515 | 521 | END IF; |
|
516 | 522 | END PROCESS; |
|
517 | 523 | |
|
518 | 524 | data_f0_addr_out <= data_f0_addr_out_s; |
|
519 | 525 | data_f1_addr_out <= data_f1_addr_out_s; |
|
520 | 526 | data_f2_addr_out <= data_f2_addr_out_s; |
|
521 | 527 | data_f3_addr_out <= data_f3_addr_out_s; |
|
522 | 528 | |
|
523 | 529 | ----------------------------------------------------------------------------- |
|
524 | 530 | -- RoundRobin Selection For DMA |
|
525 | 531 | ----------------------------------------------------------------------------- |
|
526 | 532 | |
|
527 | 533 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
528 | 534 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
529 | 535 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
530 | 536 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
531 | 537 | |
|
532 | 538 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
533 | 539 | PORT MAP ( |
|
534 | 540 | clk => clk, |
|
535 | 541 | rstn => rstn, |
|
536 | 542 | in_valid => dma_rr_valid, |
|
537 | 543 | out_grant => dma_rr_grant_s); |
|
538 | 544 | |
|
539 | 545 | dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst; |
|
540 | 546 | dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1'; |
|
541 | 547 | dma_rr_valid_ms(2) <= '0'; |
|
542 | 548 | dma_rr_valid_ms(3) <= '0'; |
|
543 | 549 | |
|
544 | 550 | RR_Arbiter_4_2 : RR_Arbiter_4 |
|
545 | 551 | PORT MAP ( |
|
546 | 552 | clk => clk, |
|
547 | 553 | rstn => rstn, |
|
548 | 554 | in_valid => dma_rr_valid_ms, |
|
549 | 555 | out_grant => dma_rr_grant_ms); |
|
550 | 556 | |
|
551 | 557 | dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s; |
|
552 | 558 | |
|
553 | 559 | |
|
554 | 560 | ----------------------------------------------------------------------------- |
|
555 | 561 | -- in : dma_rr_grant |
|
556 | 562 | -- send |
|
557 | 563 | -- out : dma_sel |
|
558 | 564 | -- dma_valid_burst |
|
559 | 565 | -- dma_sel_valid |
|
560 | 566 | ----------------------------------------------------------------------------- |
|
561 | 567 | PROCESS (clk, rstn) |
|
562 | 568 | BEGIN -- PROCESS |
|
563 | 569 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
564 | 570 | dma_sel <= (OTHERS => '0'); |
|
565 | 571 | dma_send <= '0'; |
|
566 | 572 | dma_valid_burst <= '0'; |
|
567 | 573 | data_ms_done <= '0'; |
|
568 | 574 | dma_ms_ongoing <= '0'; |
|
569 | 575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
570 | 576 | IF run = '1' THEN |
|
571 | 577 | data_ms_done <= '0'; |
|
572 | 578 | IF dma_sel = "00000" OR dma_done = '1' THEN |
|
573 | 579 | dma_sel <= dma_rr_grant; |
|
574 | 580 | IF dma_rr_grant(0) = '1' THEN |
|
575 | 581 | dma_ms_ongoing <= '0'; |
|
576 | 582 | dma_send <= '1'; |
|
577 | 583 | dma_valid_burst <= data_f0_data_out_valid_burst; |
|
578 | 584 | dma_sel_valid <= data_f0_data_out_valid; |
|
579 | 585 | ELSIF dma_rr_grant(1) = '1' THEN |
|
580 | 586 | dma_ms_ongoing <= '0'; |
|
581 | 587 | dma_send <= '1'; |
|
582 | 588 | dma_valid_burst <= data_f1_data_out_valid_burst; |
|
583 | 589 | dma_sel_valid <= data_f1_data_out_valid; |
|
584 | 590 | ELSIF dma_rr_grant(2) = '1' THEN |
|
585 | 591 | dma_ms_ongoing <= '0'; |
|
586 | 592 | dma_send <= '1'; |
|
587 | 593 | dma_valid_burst <= data_f2_data_out_valid_burst; |
|
588 | 594 | dma_sel_valid <= data_f2_data_out_valid; |
|
589 | 595 | ELSIF dma_rr_grant(3) = '1' THEN |
|
590 | 596 | dma_ms_ongoing <= '0'; |
|
591 | 597 | dma_send <= '1'; |
|
592 | 598 | dma_valid_burst <= data_f3_data_out_valid_burst; |
|
593 | 599 | dma_sel_valid <= data_f3_data_out_valid; |
|
594 | 600 | ELSIF dma_rr_grant(4) = '1' THEN |
|
595 | 601 | dma_ms_ongoing <= '1'; |
|
596 | 602 | dma_send <= '1'; |
|
597 | 603 | dma_valid_burst <= data_ms_valid_burst; |
|
598 | 604 | dma_sel_valid <= data_ms_valid; |
|
599 | 605 | --ELSE |
|
600 | 606 | --dma_ms_ongoing <= '0'; |
|
601 | 607 | END IF; |
|
602 | 608 | |
|
603 | 609 | IF dma_ms_ongoing = '1' AND dma_done = '1' THEN |
|
604 | 610 | data_ms_done <= '1'; |
|
605 | 611 | END IF; |
|
606 | 612 | ELSE |
|
607 | 613 | dma_sel <= dma_sel; |
|
608 | 614 | dma_send <= '0'; |
|
609 | 615 | END IF; |
|
610 | 616 | ELSE |
|
611 | 617 | data_ms_done <= '0'; |
|
612 | 618 | dma_sel <= (OTHERS => '0'); |
|
613 | 619 | dma_send <= '0'; |
|
614 | 620 | dma_valid_burst <= '0'; |
|
615 | 621 | END IF; |
|
616 | 622 | END IF; |
|
617 | 623 | END PROCESS; |
|
618 | 624 | |
|
619 | 625 | |
|
620 | 626 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
621 | 627 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
622 | 628 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
623 | 629 | data_f3_addr_out WHEN dma_sel(3) = '1' ELSE |
|
624 | 630 | data_ms_addr; |
|
625 | 631 | |
|
626 | 632 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
627 | 633 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
628 | 634 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
629 | 635 | data_f3_data_out WHEN dma_sel(3) = '1' ELSE |
|
630 | 636 | data_ms_data; |
|
631 | 637 | |
|
632 | 638 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
633 | 639 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
634 | 640 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
635 | 641 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
636 | 642 | data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1'; |
|
637 | 643 | |
|
638 | 644 | dma_data_2 <= dma_data; |
|
639 | 645 | |
|
640 | 646 | |
|
641 | 647 | ----------------------------------------------------------------------------- |
|
642 | 648 | -- DMA |
|
643 | 649 | ----------------------------------------------------------------------------- |
|
644 | 650 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
645 | 651 | GENERIC MAP ( |
|
646 | 652 | tech => inferred, |
|
647 | 653 | hindex => hindex) |
|
648 | 654 | PORT MAP ( |
|
649 | 655 | HCLK => clk, |
|
650 | 656 | HRESETn => rstn, |
|
651 | 657 | run => run, |
|
652 | 658 | AHB_Master_In => ahbi, |
|
653 | 659 | AHB_Master_Out => ahbo, |
|
654 | 660 | |
|
655 | 661 | send => dma_send, |
|
656 | 662 | valid_burst => dma_valid_burst, |
|
657 | 663 | done => dma_done, |
|
658 | 664 | ren => dma_ren, |
|
659 | 665 | address => dma_address, |
|
660 | 666 | data => dma_data_2); |
|
661 | 667 | |
|
662 | 668 | ----------------------------------------------------------------------------- |
|
663 | 669 | -- Matrix Spectral |
|
664 | 670 | ----------------------------------------------------------------------------- |
|
665 | 671 | sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
666 | 672 | NOT(sample_f0_val) & NOT(sample_f0_val); |
|
667 | 673 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
668 | 674 | NOT(sample_f1_val) & NOT(sample_f1_val); |
|
669 | 675 | sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
670 | 676 | NOT(sample_f3_val) & NOT(sample_f3_val); |
|
671 | 677 | |
|
672 | 678 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
673 | 679 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
674 | 680 | sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
675 | 681 | |
|
676 | 682 | ------------------------------------------------------------------------------- |
|
677 | 683 | |
|
678 | 684 | ms_softandhard_rstn <= rstn AND run_ms AND run; |
|
679 | 685 | |
|
680 | 686 | ----------------------------------------------------------------------------- |
|
681 | 687 | lpp_lfr_ms_1 : lpp_lfr_ms |
|
682 | 688 | GENERIC MAP ( |
|
683 | 689 | Mem_use => Mem_use) |
|
684 | 690 | PORT MAP ( |
|
685 | 691 | clk => clk, |
|
686 | 692 | rstn => ms_softandhard_rstn, --rstn, |
|
687 | 693 | |
|
688 | 694 | coarse_time => coarse_time, |
|
689 | 695 | fine_time => fine_time, |
|
690 | 696 | |
|
691 | 697 | sample_f0_wen => sample_f0_wen, |
|
692 | 698 | sample_f0_wdata => sample_f0_wdata, |
|
693 | 699 | sample_f1_wen => sample_f1_wen, |
|
694 | 700 | sample_f1_wdata => sample_f1_wdata, |
|
695 | 701 | sample_f2_wen => sample_f3_wen, -- TODO |
|
696 | 702 | sample_f2_wdata => sample_f3_wdata,-- TODO |
|
697 | 703 | |
|
698 | 704 | dma_addr => data_ms_addr, -- |
|
699 | 705 | dma_data => data_ms_data, -- |
|
700 | 706 | dma_valid => data_ms_valid, -- |
|
701 | 707 | dma_valid_burst => data_ms_valid_burst, -- |
|
702 | 708 | dma_ren => data_ms_ren, -- |
|
703 | 709 | dma_done => data_ms_done, -- |
|
704 | 710 | |
|
705 | 711 | ready_matrix_f0 => ready_matrix_f0, |
|
706 | 712 | ready_matrix_f1 => ready_matrix_f1, |
|
707 | 713 | ready_matrix_f2 => ready_matrix_f2, |
|
708 | 714 | error_bad_component_error => error_bad_component_error, |
|
709 | 715 | error_buffer_full => error_buffer_full, |
|
710 | 716 | error_input_fifo_write => error_input_fifo_write, |
|
711 | 717 | |
|
712 | 718 | debug_reg => debug_ms,--observation_reg, |
|
719 | observation_vector_0 => observation_vector_0, | |
|
720 | observation_vector_1 => observation_vector_1, | |
|
713 | 721 | |
|
714 | 722 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
715 | 723 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
716 | 724 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
717 | 725 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
718 | 726 | config_active_interruption_onError => config_active_interruption_onError, |
|
719 | 727 | addr_matrix_f0 => addr_matrix_f0, |
|
720 | 728 | addr_matrix_f1 => addr_matrix_f1, |
|
721 | 729 | addr_matrix_f2 => addr_matrix_f2, |
|
722 | 730 | |
|
723 | 731 | matrix_time_f0 => matrix_time_f0, |
|
724 | 732 | matrix_time_f1 => matrix_time_f1, |
|
725 | 733 | matrix_time_f2 => matrix_time_f2); |
|
726 | 734 | |
|
727 | 735 | ----------------------------------------------------------------------------- |
|
728 | observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) & | |
|
729 | dma_ms_ongoing & -- 8 | |
|
730 | data_ms_done & -- 7 | |
|
731 | dma_done & -- 6 | |
|
732 | dma_sel & -- 5 .. 1 | |
|
733 | ms_softandhard_rstn; -- 0 | |
|
736 | ||
|
737 | ||
|
738 | observation_reg(31 DOWNTO 0) <= | |
|
739 | dma_sel(4) & -- 31 | |
|
740 | dma_ms_ongoing & -- 30 | |
|
741 | data_ms_done & -- 29 | |
|
742 | dma_done & -- 28 | |
|
743 | ms_softandhard_rstn & --27 | |
|
744 | debug_ms(14 DOWNTO 12) & -- 26 .. 24 | |
|
745 | debug_ms(11 DOWNTO 0) & -- 23 .. 12 | |
|
746 | debug_signal(11 DOWNTO 0); -- 11 .. 0 | |
|
734 | 747 | |
|
735 | 748 | END beh; |
@@ -1,675 +1,697 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | -- jean-christophe.pellion@easii-ic.com |
|
22 | 22 | ---------------------------------------------------------------------------- |
|
23 | 23 | LIBRARY ieee; |
|
24 | 24 | USE ieee.std_logic_1164.ALL; |
|
25 | 25 | USE ieee.numeric_std.ALL; |
|
26 | 26 | LIBRARY grlib; |
|
27 | 27 | USE grlib.amba.ALL; |
|
28 | 28 | USE grlib.stdlib.ALL; |
|
29 | 29 | USE grlib.devices.ALL; |
|
30 | 30 | LIBRARY lpp; |
|
31 | 31 | USE lpp.lpp_lfr_pkg.ALL; |
|
32 | 32 | --USE lpp.lpp_amba.ALL; |
|
33 | 33 | USE lpp.apb_devices_list.ALL; |
|
34 | 34 | USE lpp.lpp_memory.ALL; |
|
35 | 35 | LIBRARY techmap; |
|
36 | 36 | USE techmap.gencomp.ALL; |
|
37 | 37 | |
|
38 | 38 | ENTITY lpp_lfr_apbreg IS |
|
39 | 39 | GENERIC ( |
|
40 | 40 | nb_data_by_buffer_size : INTEGER := 11; |
|
41 | 41 | nb_word_by_buffer_size : INTEGER := 11; |
|
42 | 42 | nb_snapshot_param_size : INTEGER := 11; |
|
43 | 43 | delta_vector_size : INTEGER := 20; |
|
44 | 44 | delta_vector_size_f0_2 : INTEGER := 3; |
|
45 | 45 | |
|
46 | 46 | pindex : INTEGER := 4; |
|
47 | 47 | paddr : INTEGER := 4; |
|
48 | 48 | pmask : INTEGER := 16#fff#; |
|
49 | 49 | pirq_ms : INTEGER := 0; |
|
50 | 50 | pirq_wfp : INTEGER := 1; |
|
51 | 51 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000"); |
|
52 | 52 | PORT ( |
|
53 | 53 | -- AMBA AHB system signals |
|
54 | 54 | HCLK : IN STD_ULOGIC; |
|
55 | 55 | HRESETn : IN STD_ULOGIC; |
|
56 | 56 | |
|
57 | 57 | -- AMBA APB Slave Interface |
|
58 | 58 | apbi : IN apb_slv_in_type; |
|
59 | 59 | apbo : OUT apb_slv_out_type; |
|
60 | 60 | |
|
61 | 61 | --------------------------------------------------------------------------- |
|
62 | 62 | -- Spectral Matrix Reg |
|
63 | 63 | run_ms : OUT STD_LOGIC; |
|
64 | 64 | -- IN |
|
65 | 65 | ready_matrix_f0 : IN STD_LOGIC; |
|
66 | 66 | ready_matrix_f1 : IN STD_LOGIC; |
|
67 | 67 | ready_matrix_f2 : IN STD_LOGIC; |
|
68 | 68 | |
|
69 | 69 | error_bad_component_error : IN STD_LOGIC; |
|
70 | 70 | error_buffer_full : IN STD_LOGIC; -- TODO |
|
71 | 71 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO |
|
72 | 72 | |
|
73 | 73 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | 74 | |
|
75 | 75 | -- OUT |
|
76 | 76 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
77 | 77 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
78 | 78 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
79 | 79 | |
|
80 | 80 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
81 | 81 | config_active_interruption_onError : OUT STD_LOGIC; |
|
82 | 82 | |
|
83 | 83 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | 85 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
86 | 86 | |
|
87 | 87 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | 88 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
89 | 89 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
90 | 90 | |
|
91 | 91 | --------------------------------------------------------------------------- |
|
92 | 92 | --------------------------------------------------------------------------- |
|
93 | 93 | -- WaveForm picker Reg |
|
94 | 94 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
95 | 95 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
96 | 96 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
97 | 97 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
98 | 98 | |
|
99 | 99 | -- OUT |
|
100 | 100 | data_shaping_BW : OUT STD_LOGIC; |
|
101 | 101 | data_shaping_SP0 : OUT STD_LOGIC; |
|
102 | 102 | data_shaping_SP1 : OUT STD_LOGIC; |
|
103 | 103 | data_shaping_R0 : OUT STD_LOGIC; |
|
104 | 104 | data_shaping_R1 : OUT STD_LOGIC; |
|
105 | 105 | |
|
106 | 106 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
107 | 107 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
108 | 108 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
109 | 109 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
110 | 110 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
111 | 111 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
112 | 112 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
113 | 113 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
114 | 114 | |
|
115 | 115 | enable_f0 : OUT STD_LOGIC; |
|
116 | 116 | enable_f1 : OUT STD_LOGIC; |
|
117 | 117 | enable_f2 : OUT STD_LOGIC; |
|
118 | 118 | enable_f3 : OUT STD_LOGIC; |
|
119 | 119 | |
|
120 | 120 | burst_f0 : OUT STD_LOGIC; |
|
121 | 121 | burst_f1 : OUT STD_LOGIC; |
|
122 | 122 | burst_f2 : OUT STD_LOGIC; |
|
123 | 123 | |
|
124 | 124 | run : OUT STD_LOGIC; |
|
125 | 125 | |
|
126 | 126 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
127 | 127 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
128 | 128 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | 129 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
130 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
131 | --------------------------------------------------------------------------- | |
|
132 | debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
131 | 133 | --------------------------------------------------------------------------- |
|
132 | 134 | ); |
|
133 | 135 | |
|
134 | 136 | END lpp_lfr_apbreg; |
|
135 | 137 | |
|
136 | 138 | ARCHITECTURE beh OF lpp_lfr_apbreg IS |
|
137 | 139 | |
|
138 | 140 | CONSTANT REVISION : INTEGER := 1; |
|
139 | 141 | |
|
140 | 142 | CONSTANT pconfig : apb_config_type := ( |
|
141 | 143 | 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp), |
|
142 | 144 | 1 => apb_iobar(paddr, pmask)); |
|
143 | ||
|
145 | ||
|
144 | 146 | TYPE lpp_SpectralMatrix_regs IS RECORD |
|
145 | 147 | config_active_interruption_onNewMatrix : STD_LOGIC; |
|
146 | 148 | config_active_interruption_onError : STD_LOGIC; |
|
147 | 149 | config_ms_run : STD_LOGIC; |
|
148 | 150 | status_ready_matrix_f0_0 : STD_LOGIC; |
|
149 | 151 | status_ready_matrix_f1_0 : STD_LOGIC; |
|
150 | 152 | status_ready_matrix_f2_0 : STD_LOGIC; |
|
151 | 153 | status_ready_matrix_f0_1 : STD_LOGIC; |
|
152 | 154 | status_ready_matrix_f1_1 : STD_LOGIC; |
|
153 | 155 | status_ready_matrix_f2_1 : STD_LOGIC; |
|
154 | 156 | status_error_bad_component_error : STD_LOGIC; |
|
155 | 157 | status_error_buffer_full : STD_LOGIC; |
|
156 | 158 | status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
157 | ||
|
158 |
addr_matrix_f0_0 |
|
|
159 |
addr_matrix_f0_1 |
|
|
160 |
addr_matrix_f1_0 |
|
|
161 |
addr_matrix_f1_1 |
|
|
162 |
addr_matrix_f2_0 |
|
|
163 |
addr_matrix_f2_1 |
|
|
164 | ||
|
165 |
time_matrix_f0_0 |
|
|
166 |
time_matrix_f0_1 |
|
|
167 |
time_matrix_f1_0 |
|
|
168 |
time_matrix_f1_1 |
|
|
169 |
time_matrix_f2_0 |
|
|
170 |
time_matrix_f2_1 |
|
|
159 | ||
|
160 | addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
161 | addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
162 | addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
163 | addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
164 | addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
165 | addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
166 | ||
|
167 | time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
168 | time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
169 | time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
170 | time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
171 | time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
172 | time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
171 | 173 | END RECORD; |
|
172 | 174 | SIGNAL reg_sp : lpp_SpectralMatrix_regs; |
|
173 | 175 | |
|
174 | 176 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
175 | 177 | status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
176 | 178 | status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
177 | 179 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
178 | 180 | data_shaping_BW : STD_LOGIC; |
|
179 | 181 | data_shaping_SP0 : STD_LOGIC; |
|
180 | 182 | data_shaping_SP1 : STD_LOGIC; |
|
181 | 183 | data_shaping_R0 : STD_LOGIC; |
|
182 | 184 | data_shaping_R1 : STD_LOGIC; |
|
183 | 185 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
184 | 186 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
185 | 187 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
186 | 188 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
187 | 189 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
188 | 190 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
189 | 191 | nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
190 | 192 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
191 | 193 | enable_f0 : STD_LOGIC; |
|
192 | 194 | enable_f1 : STD_LOGIC; |
|
193 | 195 | enable_f2 : STD_LOGIC; |
|
194 | 196 | enable_f3 : STD_LOGIC; |
|
195 | 197 | burst_f0 : STD_LOGIC; |
|
196 | 198 | burst_f1 : STD_LOGIC; |
|
197 | 199 | burst_f2 : STD_LOGIC; |
|
198 | 200 | run : STD_LOGIC; |
|
199 | 201 | addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
200 | 202 | addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
201 | 203 | addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
202 | 204 | addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
203 | 205 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
204 | 206 | END RECORD; |
|
205 | 207 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
206 | 208 | |
|
207 | 209 | SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
208 | 210 | |
|
209 | 211 | ----------------------------------------------------------------------------- |
|
210 | 212 | -- IRQ |
|
211 | 213 | ----------------------------------------------------------------------------- |
|
212 | 214 | CONSTANT IRQ_WFP_SIZE : INTEGER := 12; |
|
213 | 215 | SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
214 | 216 | SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
215 | 217 | SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
216 | 218 | SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0); |
|
217 | 219 | SIGNAL ored_irq_wfp : STD_LOGIC; |
|
218 | 220 | |
|
219 | 221 | ----------------------------------------------------------------------------- |
|
220 | 222 | -- |
|
221 | 223 | ----------------------------------------------------------------------------- |
|
222 | 224 | SIGNAL reg0_ready_matrix_f0 : STD_LOGIC; |
|
223 | 225 | SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
224 | 226 | SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
225 | ||
|
227 | ||
|
226 | 228 | SIGNAL reg1_ready_matrix_f0 : STD_LOGIC; |
|
227 | 229 | SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
228 | 230 | SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
229 | ||
|
231 | ||
|
230 | 232 | SIGNAL reg0_ready_matrix_f1 : STD_LOGIC; |
|
231 | 233 | SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
232 | 234 | SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
233 | ||
|
235 | ||
|
234 | 236 | SIGNAL reg1_ready_matrix_f1 : STD_LOGIC; |
|
235 | 237 | SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
236 |
SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
237 | ||
|
238 | SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
239 | ||
|
238 | 240 | SIGNAL reg0_ready_matrix_f2 : STD_LOGIC; |
|
239 | 241 | SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
240 | 242 | SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
241 | ||
|
243 | ||
|
242 | 244 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; |
|
243 | 245 | SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
244 |
SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
|
246 | SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
247 | SIGNAL apbo_irq_ms : STD_LOGIC; | |
|
248 | SIGNAL apbo_irq_wfp : STD_LOGIC; | |
|
245 | 249 | |
|
246 | 250 | BEGIN -- beh |
|
247 | 251 | |
|
248 | 252 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; |
|
249 | 253 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
250 | 254 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
251 | 255 | |
|
252 | 256 | config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix; |
|
253 | 257 | config_active_interruption_onError <= reg_sp.config_active_interruption_onError; |
|
254 | ||
|
255 | ||
|
258 | ||
|
259 | ||
|
256 | 260 | -- addr_matrix_f0 <= reg_sp.addr_matrix_f0; |
|
257 | 261 | -- addr_matrix_f1 <= reg_sp.addr_matrix_f1; |
|
258 | 262 | -- addr_matrix_f2 <= reg_sp.addr_matrix_f2; |
|
259 | 263 | |
|
260 | 264 | |
|
261 | 265 | data_shaping_BW <= NOT reg_wp.data_shaping_BW; |
|
262 | 266 | data_shaping_SP0 <= reg_wp.data_shaping_SP0; |
|
263 | 267 | data_shaping_SP1 <= reg_wp.data_shaping_SP1; |
|
264 | 268 | data_shaping_R0 <= reg_wp.data_shaping_R0; |
|
265 | 269 | data_shaping_R1 <= reg_wp.data_shaping_R1; |
|
266 | 270 | |
|
267 | 271 | delta_snapshot <= reg_wp.delta_snapshot; |
|
268 | 272 | delta_f0 <= reg_wp.delta_f0; |
|
269 | 273 | delta_f0_2 <= reg_wp.delta_f0_2; |
|
270 | 274 | delta_f1 <= reg_wp.delta_f1; |
|
271 | 275 | delta_f2 <= reg_wp.delta_f2; |
|
272 | 276 | nb_data_by_buffer <= reg_wp.nb_data_by_buffer; |
|
273 | 277 | nb_word_by_buffer <= reg_wp.nb_word_by_buffer; |
|
274 | 278 | nb_snapshot_param <= reg_wp.nb_snapshot_param; |
|
275 | 279 | |
|
276 | 280 | enable_f0 <= reg_wp.enable_f0; |
|
277 | 281 | enable_f1 <= reg_wp.enable_f1; |
|
278 | 282 | enable_f2 <= reg_wp.enable_f2; |
|
279 | 283 | enable_f3 <= reg_wp.enable_f3; |
|
280 | 284 | |
|
281 | 285 | burst_f0 <= reg_wp.burst_f0; |
|
282 | 286 | burst_f1 <= reg_wp.burst_f1; |
|
283 | 287 | burst_f2 <= reg_wp.burst_f2; |
|
284 | 288 | |
|
285 | 289 | run <= reg_wp.run; |
|
286 | 290 | |
|
287 | 291 | addr_data_f0 <= reg_wp.addr_data_f0; |
|
288 | 292 | addr_data_f1 <= reg_wp.addr_data_f1; |
|
289 | 293 | addr_data_f2 <= reg_wp.addr_data_f2; |
|
290 | 294 | addr_data_f3 <= reg_wp.addr_data_f3; |
|
291 | 295 | |
|
292 | 296 | start_date <= reg_wp.start_date; |
|
293 | 297 | |
|
294 | 298 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
295 | 299 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
296 | 300 | BEGIN -- PROCESS lpp_dma_top |
|
297 | 301 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
298 | 302 | reg_sp.config_active_interruption_onNewMatrix <= '0'; |
|
299 | 303 | reg_sp.config_active_interruption_onError <= '0'; |
|
300 | 304 | reg_sp.config_ms_run <= '1'; |
|
301 | 305 | reg_sp.status_ready_matrix_f0_0 <= '0'; |
|
302 | 306 | reg_sp.status_ready_matrix_f1_0 <= '0'; |
|
303 | 307 | reg_sp.status_ready_matrix_f2_0 <= '0'; |
|
304 | 308 | reg_sp.status_ready_matrix_f0_1 <= '0'; |
|
305 | 309 | reg_sp.status_ready_matrix_f1_1 <= '0'; |
|
306 | 310 | reg_sp.status_ready_matrix_f2_1 <= '0'; |
|
307 | 311 | reg_sp.status_error_bad_component_error <= '0'; |
|
308 | 312 | reg_sp.status_error_buffer_full <= '0'; |
|
309 | 313 | reg_sp.status_error_input_fifo_write <= (OTHERS => '0'); |
|
310 | 314 | |
|
311 | 315 | reg_sp.addr_matrix_f0_0 <= (OTHERS => '0'); |
|
312 | 316 | reg_sp.addr_matrix_f1_0 <= (OTHERS => '0'); |
|
313 | 317 | reg_sp.addr_matrix_f2_0 <= (OTHERS => '0'); |
|
314 | 318 | |
|
315 | 319 | reg_sp.addr_matrix_f0_1 <= (OTHERS => '0'); |
|
316 | 320 | reg_sp.addr_matrix_f1_1 <= (OTHERS => '0'); |
|
317 | 321 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); |
|
318 | ||
|
322 | ||
|
319 | 323 | -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok |
|
320 | 324 | -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok |
|
321 | 325 | -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok |
|
322 | ||
|
326 | ||
|
323 | 327 | -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok |
|
324 | 328 | --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok |
|
325 | 329 | -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok |
|
326 | 330 | |
|
327 | 331 | prdata <= (OTHERS => '0'); |
|
328 | 332 | |
|
329 | apbo.pirq <= (OTHERS => '0'); | |
|
333 | ||
|
334 | apbo_irq_ms <= '0'; | |
|
335 | apbo_irq_wfp <= '0'; | |
|
336 | ||
|
330 | 337 |
|
|
331 | 338 |
|
|
332 | 339 | |
|
333 | 340 | reg_wp.data_shaping_BW <= '0'; |
|
334 | 341 | reg_wp.data_shaping_SP0 <= '0'; |
|
335 | 342 | reg_wp.data_shaping_SP1 <= '0'; |
|
336 | 343 | reg_wp.data_shaping_R0 <= '0'; |
|
337 | 344 | reg_wp.data_shaping_R1 <= '0'; |
|
338 | 345 | reg_wp.enable_f0 <= '0'; |
|
339 | 346 | reg_wp.enable_f1 <= '0'; |
|
340 | 347 | reg_wp.enable_f2 <= '0'; |
|
341 | 348 | reg_wp.enable_f3 <= '0'; |
|
342 | 349 | reg_wp.burst_f0 <= '0'; |
|
343 | 350 | reg_wp.burst_f1 <= '0'; |
|
344 | 351 | reg_wp.burst_f2 <= '0'; |
|
345 | 352 | reg_wp.run <= '0'; |
|
346 | 353 | reg_wp.addr_data_f0 <= (OTHERS => '0'); |
|
347 | 354 | reg_wp.addr_data_f1 <= (OTHERS => '0'); |
|
348 | 355 | reg_wp.addr_data_f2 <= (OTHERS => '0'); |
|
349 | 356 | reg_wp.addr_data_f3 <= (OTHERS => '0'); |
|
350 | 357 | reg_wp.status_full <= (OTHERS => '0'); |
|
351 | 358 | reg_wp.status_full_err <= (OTHERS => '0'); |
|
352 | 359 | reg_wp.status_new_err <= (OTHERS => '0'); |
|
353 | 360 | reg_wp.delta_snapshot <= (OTHERS => '0'); |
|
354 | 361 | reg_wp.delta_f0 <= (OTHERS => '0'); |
|
355 | 362 | reg_wp.delta_f0_2 <= (OTHERS => '0'); |
|
356 | 363 | reg_wp.delta_f1 <= (OTHERS => '0'); |
|
357 | 364 | reg_wp.delta_f2 <= (OTHERS => '0'); |
|
358 | 365 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
359 | 366 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
360 | 367 | reg_wp.start_date <= (OTHERS => '0'); |
|
361 | 368 | |
|
362 | 369 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
363 | 370 | |
|
364 | 371 | status_full_ack <= (OTHERS => '0'); |
|
365 | 372 | |
|
366 | 373 | reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0; |
|
367 | 374 | reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1; |
|
368 | 375 | reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2; |
|
369 | 376 | |
|
370 | 377 | reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0; |
|
371 | 378 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; |
|
372 | 379 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; |
|
373 | 380 | |
|
374 | 381 | reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error; |
|
375 | 382 | |
|
376 | 383 | reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full; |
|
377 | 384 | reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0); |
|
378 | 385 | reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1); |
|
379 | 386 | reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2); |
|
380 | 387 | |
|
381 | 388 | |
|
382 | 389 | |
|
383 | 390 | all_status : FOR I IN 3 DOWNTO 0 LOOP |
|
384 | 391 | reg_wp.status_full(I) <= status_full(I) AND reg_wp.run; |
|
385 | 392 | reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run; |
|
386 | 393 | reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run; |
|
387 | 394 | END LOOP all_status; |
|
388 | 395 | |
|
389 | 396 | paddr := "000000"; |
|
390 | 397 | paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); |
|
391 | 398 | prdata <= (OTHERS => '0'); |
|
392 | 399 | IF apbi.psel(pindex) = '1' THEN |
|
393 | 400 | -- APB DMA READ -- |
|
394 | 401 | CASE paddr(7 DOWNTO 2) IS |
|
395 |
|
|
|
402 | --0 | |
|
396 | 403 | WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix; |
|
397 | 404 | prdata(1) <= reg_sp.config_active_interruption_onError; |
|
398 | 405 | prdata(2) <= reg_sp.config_ms_run; |
|
399 | 406 | --1 |
|
400 | 407 | WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
401 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
402 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
|
403 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
|
404 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
|
405 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
|
406 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
|
407 | prdata(7) <= reg_sp.status_error_buffer_full; | |
|
408 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
|
409 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
|
408 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
|
409 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
|
410 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
|
411 | prdata(4) <= reg_sp.status_ready_matrix_f2_0; | |
|
412 | prdata(5) <= reg_sp.status_ready_matrix_f2_1; | |
|
413 | prdata(6) <= reg_sp.status_error_bad_component_error; | |
|
414 | prdata(7) <= reg_sp.status_error_buffer_full; | |
|
415 | prdata(8) <= reg_sp.status_error_input_fifo_write(0); | |
|
416 | prdata(9) <= reg_sp.status_error_input_fifo_write(1); | |
|
410 | 417 | prdata(10) <= reg_sp.status_error_input_fifo_write(2); |
|
411 | 418 | --2 |
|
412 | 419 | WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0; |
|
413 | 420 | --3 |
|
414 | 421 | WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1; |
|
415 | 422 | --4 |
|
416 | 423 | WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0; |
|
417 | 424 | --5 |
|
418 | 425 | WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1; |
|
419 | 426 | --6 |
|
420 | 427 | WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0; |
|
421 | 428 | --7 |
|
422 | 429 | WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1; |
|
423 | 430 | --8 |
|
424 | 431 | WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16); |
|
425 | 432 | --9 |
|
426 |
WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO |
|
|
433 | WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0); | |
|
427 | 434 | --10 |
|
428 | 435 | WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16); |
|
429 | 436 | --11 |
|
430 |
WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO |
|
|
437 | WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0); | |
|
431 | 438 | --12 |
|
432 | 439 | WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16); |
|
433 | 440 | --13 |
|
434 |
WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO |
|
|
441 | WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0); | |
|
435 | 442 | --14 |
|
436 | 443 | WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16); |
|
437 | 444 | --15 |
|
438 |
WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO |
|
|
445 | WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0); | |
|
439 | 446 | --16 |
|
440 | 447 | WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16); |
|
441 | 448 | --17 |
|
442 |
WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO |
|
|
449 | WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0); | |
|
443 | 450 | --18 |
|
444 | 451 | WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); |
|
445 | 452 | --19 |
|
446 |
WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO |
|
|
453 | WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |
|
447 | 454 | --------------------------------------------------------------------- |
|
448 | 455 | --20 |
|
449 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
456 | WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW; | |
|
450 | 457 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
451 | 458 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
452 | 459 | prdata(3) <= reg_wp.data_shaping_R0; |
|
453 | 460 | prdata(4) <= reg_wp.data_shaping_R1; |
|
454 | 461 | --21 |
|
455 | 462 | WHEN "010101" => prdata(0) <= reg_wp.enable_f0; |
|
456 | 463 | prdata(1) <= reg_wp.enable_f1; |
|
457 | 464 | prdata(2) <= reg_wp.enable_f2; |
|
458 | 465 | prdata(3) <= reg_wp.enable_f3; |
|
459 | 466 | prdata(4) <= reg_wp.burst_f0; |
|
460 | 467 | prdata(5) <= reg_wp.burst_f1; |
|
461 | 468 | prdata(6) <= reg_wp.burst_f2; |
|
462 | 469 | prdata(7) <= reg_wp.run; |
|
463 | 470 | --22 |
|
464 | 471 | WHEN "010110" => prdata <= reg_wp.addr_data_f0; |
|
465 | 472 | --23 |
|
466 | 473 | WHEN "010111" => prdata <= reg_wp.addr_data_f1; |
|
467 | 474 | --24 |
|
468 | 475 | WHEN "011000" => prdata <= reg_wp.addr_data_f2; |
|
469 | 476 | --25 |
|
470 | 477 | WHEN "011001" => prdata <= reg_wp.addr_data_f3; |
|
471 | 478 | --26 |
|
472 | 479 | WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full; |
|
473 | 480 | prdata(7 DOWNTO 4) <= reg_wp.status_full_err; |
|
474 | 481 | prdata(11 DOWNTO 8) <= reg_wp.status_new_err; |
|
475 | 482 | --27 |
|
476 | 483 | WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
477 | 484 | --28 |
|
478 | 485 | WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
479 | 486 | --29 |
|
480 | 487 | WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
481 | 488 | --30 |
|
482 | 489 | WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
483 | 490 | --31 |
|
484 | 491 | WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
485 | 492 | --32 |
|
486 | 493 | WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
487 | 494 | --33 |
|
488 | 495 | WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
489 | 496 | --34 |
|
490 | 497 | WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
491 | 498 | --35 |
|
492 | 499 | WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer; |
|
493 | 500 | ---------------------------------------------------- |
|
494 | 501 | WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); |
|
495 | 502 | WHEN OTHERS => NULL; |
|
496 | 503 | |
|
497 | 504 | END CASE; |
|
498 | 505 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
499 | 506 | -- APB DMA WRITE -- |
|
500 | 507 | CASE paddr(7 DOWNTO 2) IS |
|
501 | 508 | -- |
|
502 | 509 | WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
503 |
reg_sp.config_active_interruption_onError |
|
|
504 |
reg_sp.config_ms_run |
|
|
505 | WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0); | |
|
506 | reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1); | |
|
507 | reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2); | |
|
508 | reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3); | |
|
509 | reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4); | |
|
510 | reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5); | |
|
511 | reg_sp.status_error_bad_component_error <= apbi.pwdata(6); | |
|
512 | reg_sp.status_error_buffer_full <= apbi.pwdata(7); | |
|
513 | reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8); | |
|
514 | reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9); | |
|
515 | reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10); | |
|
516 | --2 | |
|
517 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
518 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
519 |
WHEN "000 |
|
|
520 |
WHEN "000 |
|
|
521 |
WHEN "0001 |
|
|
522 |
WHEN "0001 |
|
|
510 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
|
511 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
|
512 | ||
|
513 | WHEN "000001" => | |
|
514 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0; | |
|
515 | reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0; | |
|
516 | reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1; | |
|
517 | reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1; | |
|
518 | reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2; | |
|
519 | reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2; | |
|
520 | reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error; | |
|
521 | reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full; | |
|
522 | reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); | |
|
523 | reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); | |
|
524 | reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); | |
|
525 | --2 | |
|
526 | WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
|
527 | WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
|
528 | WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata; | |
|
529 | WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata; | |
|
530 | WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
|
531 | WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
|
523 | 532 | --8 to 19 |
|
524 | 533 | --20 |
|
525 | 534 | WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
526 | 535 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
527 | 536 | reg_wp.data_shaping_SP1 <= apbi.pwdata(2); |
|
528 | 537 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
529 | 538 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
530 | 539 | WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0); |
|
531 | 540 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
532 | 541 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
533 | 542 | reg_wp.enable_f3 <= apbi.pwdata(3); |
|
534 | 543 | reg_wp.burst_f0 <= apbi.pwdata(4); |
|
535 | 544 | reg_wp.burst_f1 <= apbi.pwdata(5); |
|
536 | 545 | reg_wp.burst_f2 <= apbi.pwdata(6); |
|
537 | 546 | reg_wp.run <= apbi.pwdata(7); |
|
538 | 547 | --22 |
|
539 | 548 | WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata; |
|
540 | 549 | WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata; |
|
541 | 550 | WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata; |
|
542 | 551 | WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata; |
|
543 | 552 | --26 |
|
544 | 553 | WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0); |
|
545 | 554 | reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4); |
|
546 | 555 | reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8); |
|
547 | 556 | status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0); |
|
548 | 557 | status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1); |
|
549 | 558 | status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2); |
|
550 | 559 | status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3); |
|
551 | 560 | WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
552 | 561 | WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
553 | 562 | WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0); |
|
554 | 563 | WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
555 | 564 | WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
556 | 565 | WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
557 | 566 | WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
558 | 567 | WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
559 | 568 | WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0); |
|
560 | 569 | -- |
|
561 | 570 | WHEN OTHERS => NULL; |
|
562 | 571 | END CASE; |
|
563 | 572 | END IF; |
|
564 | 573 | END IF; |
|
565 | ||
|
566 |
apbo |
|
|
574 | --apbo.pirq(pirq_ms) <= | |
|
575 | apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
|
567 | 576 | ready_matrix_f1 OR |
|
568 | 577 | ready_matrix_f2) |
|
569 | 578 | ) |
|
570 | 579 | OR |
|
571 | 580 | (reg_sp.config_active_interruption_onError AND ( |
|
572 | 581 | error_bad_component_error |
|
573 | 582 | OR error_buffer_full |
|
574 | 583 | OR error_input_fifo_write(0) |
|
575 | 584 | OR error_input_fifo_write(1) |
|
576 | 585 | OR error_input_fifo_write(2)) |
|
577 | 586 | )); |
|
578 | ||
|
579 |
apbo |
|
|
587 | -- apbo.pirq(pirq_wfp) | |
|
588 | apbo_irq_wfp<= ored_irq_wfp; | |
|
580 | 589 | |
|
581 | 590 | END IF; |
|
582 | 591 | END PROCESS lpp_lfr_apbreg; |
|
583 | ||
|
592 | ||
|
593 | apbo.pirq(pirq_ms) <= apbo_irq_ms; | |
|
594 | apbo.pirq(pirq_wfp) <= apbo_irq_wfp; | |
|
595 | ||
|
584 | 596 |
|
|
585 | 597 | apbo.pconfig <= pconfig; |
|
586 | 598 | apbo.prdata <= prdata; |
|
587 | 599 | |
|
588 | 600 | ----------------------------------------------------------------------------- |
|
589 | 601 | -- IRQ |
|
590 | 602 | ----------------------------------------------------------------------------- |
|
591 | 603 | irq_wfp_reg_s <= status_full & status_full_err & status_new_err; |
|
592 | 604 | |
|
593 | 605 | PROCESS (HCLK, HRESETn) |
|
594 | 606 | BEGIN -- PROCESS |
|
595 | 607 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
596 | 608 | irq_wfp_reg <= (OTHERS => '0'); |
|
597 | 609 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
598 | 610 | irq_wfp_reg <= irq_wfp_reg_s; |
|
599 | 611 | END IF; |
|
600 | 612 | END PROCESS; |
|
601 | 613 | |
|
602 | 614 | all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE |
|
603 | 615 | irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I); |
|
604 | 616 | END GENERATE all_irq_wfp; |
|
605 | 617 | |
|
606 | 618 | irq_wfp_ZERO <= (OTHERS => '0'); |
|
607 | 619 | ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1'; |
|
608 | 620 | |
|
609 | 621 | run_ms <= reg_sp.config_ms_run; |
|
610 | 622 | |
|
611 | 623 | ----------------------------------------------------------------------------- |
|
612 | 624 | -- |
|
613 | 625 | ----------------------------------------------------------------------------- |
|
614 | 626 | lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer |
|
615 | 627 | PORT MAP ( |
|
616 | 628 | clk => HCLK, |
|
617 | 629 | rstn => HRESETn, |
|
618 | 630 | |
|
619 | 631 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, |
|
620 | 632 | reg0_ready_matrix => reg0_ready_matrix_f0, |
|
621 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0, | |
|
622 | reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0, | |
|
633 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, | |
|
634 | reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0, | |
|
623 | 635 | |
|
624 | 636 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1, |
|
625 |
reg1_ready_matrix => reg1_ready_matrix_f0, |
|
|
626 | reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0, | |
|
627 | reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0, | |
|
637 | reg1_ready_matrix => reg1_ready_matrix_f0, | |
|
638 | reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0, | |
|
639 | reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0, | |
|
628 | 640 | |
|
629 |
ready_matrix |
|
|
630 |
status_ready_matrix |
|
|
631 |
addr_matrix |
|
|
632 |
matrix_time |
|
|
641 | ready_matrix => ready_matrix_f0, | |
|
642 | status_ready_matrix => status_ready_matrix_f0, | |
|
643 | addr_matrix => addr_matrix_f0, | |
|
644 | matrix_time => matrix_time_f0); | |
|
633 | 645 | |
|
634 | 646 | lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer |
|
635 | 647 | PORT MAP ( |
|
636 | 648 | clk => HCLK, |
|
637 | 649 | rstn => HRESETn, |
|
638 | 650 | |
|
639 | 651 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
|
640 | 652 | reg0_ready_matrix => reg0_ready_matrix_f1, |
|
641 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1, | |
|
642 | reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1, | |
|
653 | reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1, | |
|
654 | reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1, | |
|
643 | 655 | |
|
644 | 656 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1, |
|
645 | 657 | reg1_ready_matrix => reg1_ready_matrix_f1, |
|
646 | reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1, | |
|
647 | reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1, | |
|
658 | reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1, | |
|
659 | reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1, | |
|
648 | 660 | |
|
649 |
ready_matrix |
|
|
650 |
status_ready_matrix |
|
|
651 |
addr_matrix |
|
|
652 |
matrix_time |
|
|
653 | ||
|
661 | ready_matrix => ready_matrix_f1, | |
|
662 | status_ready_matrix => status_ready_matrix_f1, | |
|
663 | addr_matrix => addr_matrix_f1, | |
|
664 | matrix_time => matrix_time_f1); | |
|
665 | ||
|
654 | 666 | lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer |
|
655 | 667 | PORT MAP ( |
|
656 | 668 | clk => HCLK, |
|
657 | 669 | rstn => HRESETn, |
|
658 | 670 | |
|
659 | 671 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
|
660 | 672 | reg0_ready_matrix => reg0_ready_matrix_f2, |
|
661 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2, | |
|
662 | reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2, | |
|
673 | reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2, | |
|
674 | reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2, | |
|
663 | 675 | |
|
664 | 676 | reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1, |
|
665 | 677 | reg1_ready_matrix => reg1_ready_matrix_f2, |
|
666 | reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2, | |
|
667 | reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2, | |
|
678 | reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2, | |
|
679 | reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2, | |
|
680 | ||
|
681 | ready_matrix => ready_matrix_f2, | |
|
682 | status_ready_matrix => status_ready_matrix_f2, | |
|
683 | addr_matrix => addr_matrix_f2, | |
|
684 | matrix_time => matrix_time_f2); | |
|
668 | 685 | |
|
669 | ready_matrix => ready_matrix_f2, | |
|
670 | status_ready_matrix => status_ready_matrix_f2, | |
|
671 | addr_matrix => addr_matrix_f2, | |
|
672 | matrix_time => matrix_time_f2); | |
|
673 | ||
|
674 | ||
|
686 | ----------------------------------------------------------------------------- | |
|
687 | debug_signal(31 DOWNTO 12) <= (OTHERS => '0'); | |
|
688 | debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11 | |
|
689 | reg_sp.status_error_input_fifo_write(2) &--10 | |
|
690 | reg_sp.status_error_input_fifo_write(1) &--9 | |
|
691 | reg_sp.status_error_input_fifo_write(0) &--8 | |
|
692 | reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6 | |
|
693 | reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4 | |
|
694 | reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2 | |
|
695 | reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0 | |
|
696 | ||
|
675 | 697 | END beh; |
@@ -1,929 +1,942 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_memory.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.spectral_matrix_package.ALL; |
|
9 | 9 | USE lpp.lpp_dma_pkg.ALL; |
|
10 | 10 | USE lpp.lpp_Header.ALL; |
|
11 | 11 | USE lpp.lpp_matrix.ALL; |
|
12 | 12 | USE lpp.lpp_matrix.ALL; |
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.lpp_fft.ALL; |
|
15 | 15 | USE lpp.fft_components.ALL; |
|
16 | 16 | |
|
17 | 17 | ENTITY lpp_lfr_ms IS |
|
18 | 18 | GENERIC ( |
|
19 | 19 | Mem_use : INTEGER := use_RAM |
|
20 | 20 | ); |
|
21 | 21 | PORT ( |
|
22 | 22 | clk : IN STD_LOGIC; |
|
23 | 23 | rstn : IN STD_LOGIC; |
|
24 | 24 | |
|
25 | 25 | --------------------------------------------------------------------------- |
|
26 | 26 | -- DATA INPUT |
|
27 | 27 | --------------------------------------------------------------------------- |
|
28 | 28 | -- TIME |
|
29 | 29 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
30 | 30 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
31 | 31 | -- |
|
32 | 32 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
33 | 33 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
34 | 34 | -- |
|
35 | 35 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
36 | 36 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
37 | 37 | -- |
|
38 | 38 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
39 | 39 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
40 | 40 | |
|
41 | 41 | --------------------------------------------------------------------------- |
|
42 | 42 | -- DMA |
|
43 | 43 | --------------------------------------------------------------------------- |
|
44 | 44 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
45 | 45 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
46 | 46 | dma_valid : OUT STD_LOGIC; |
|
47 | 47 | dma_valid_burst : OUT STD_LOGIC; |
|
48 | 48 | dma_ren : IN STD_LOGIC; |
|
49 | 49 | dma_done : IN STD_LOGIC; |
|
50 | 50 | |
|
51 | 51 | -- Reg out |
|
52 | 52 | ready_matrix_f0 : OUT STD_LOGIC; |
|
53 | 53 | ready_matrix_f1 : OUT STD_LOGIC; |
|
54 | 54 | ready_matrix_f2 : OUT STD_LOGIC; |
|
55 | 55 | error_bad_component_error : OUT STD_LOGIC; |
|
56 | 56 | error_buffer_full : OUT STD_LOGIC; |
|
57 | 57 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
58 | 58 | |
|
59 | 59 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | -- | |
|
61 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
62 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
60 | 63 | |
|
61 | 64 | -- Reg In |
|
62 | 65 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
63 | 66 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
64 | 67 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
65 | 68 | |
|
66 | 69 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
67 | 70 | config_active_interruption_onError : IN STD_LOGIC; |
|
68 | 71 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
69 | 72 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
70 | 73 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
71 | 74 | |
|
72 | 75 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
73 | 76 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
74 | 77 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
75 | 78 | |
|
76 | 79 | ); |
|
77 | 80 | END; |
|
78 | 81 | |
|
79 | 82 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
80 | 83 | |
|
81 | 84 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
82 | 85 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
83 | 86 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
84 | 87 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | 88 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
86 | 89 | |
|
87 | 90 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
88 | 91 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | 92 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | 93 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | 94 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
92 | 95 | |
|
93 | 96 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
94 | 97 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
95 | 98 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
96 | 99 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | 100 | |
|
98 | 101 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
99 | 102 | |
|
100 | 103 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
101 | 104 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
102 | 105 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
103 | 106 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | 107 | |
|
105 | 108 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
106 | 109 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
107 | 110 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
108 | 111 | |
|
109 | 112 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
110 | 113 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
111 | 114 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
112 | 115 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
113 | 116 | |
|
114 | 117 | ----------------------------------------------------------------------------- |
|
115 | 118 | -- FSM / SWITCH SELECT CHANNEL |
|
116 | 119 | ----------------------------------------------------------------------------- |
|
117 | 120 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
118 | 121 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
119 | 122 | SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
120 | 123 | |
|
121 | 124 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
122 | 125 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
123 | 126 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
124 | 127 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
125 | 128 | |
|
126 | 129 | ----------------------------------------------------------------------------- |
|
127 | 130 | -- FSM LOAD FFT |
|
128 | 131 | ----------------------------------------------------------------------------- |
|
129 | 132 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
130 | 133 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
131 | 134 | SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
132 | 135 | |
|
133 | 136 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
134 | 137 | SIGNAL sample_load : STD_LOGIC; |
|
135 | 138 | SIGNAL sample_valid : STD_LOGIC; |
|
136 | 139 | SIGNAL sample_valid_r : STD_LOGIC; |
|
137 | 140 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
138 | 141 | |
|
139 | 142 | |
|
140 | 143 | ----------------------------------------------------------------------------- |
|
141 | 144 | -- FFT |
|
142 | 145 | ----------------------------------------------------------------------------- |
|
143 | 146 | SIGNAL fft_read : STD_LOGIC; |
|
144 | 147 | SIGNAL fft_pong : STD_LOGIC; |
|
145 | 148 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
146 | 149 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
147 | 150 | SIGNAL fft_data_valid : STD_LOGIC; |
|
148 | 151 | SIGNAL fft_ready : STD_LOGIC; |
|
149 | 152 | ----------------------------------------------------------------------------- |
|
150 | 153 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
151 | 154 | ----------------------------------------------------------------------------- |
|
152 | 155 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
153 | 156 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
154 | 157 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
155 | 158 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
156 | 159 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
157 | 160 | SIGNAL current_fifo_full : STD_LOGIC; |
|
158 | 161 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
159 | 162 | |
|
160 | 163 | ----------------------------------------------------------------------------- |
|
161 | 164 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
162 | 165 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
163 | 166 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
164 | 167 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
165 | 168 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
166 | 169 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
167 | 170 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
168 | 171 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
169 | 172 | ----------------------------------------------------------------------------- |
|
170 | 173 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
171 | 174 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
172 | 175 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
173 | 176 | |
|
174 | 177 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
175 | 178 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
176 | 179 | SIGNAL SM_correlation_done : STD_LOGIC; |
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177 | 180 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
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178 | 181 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
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179 | 182 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
180 | 183 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
181 | 184 | |
|
182 | 185 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
183 | 186 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
184 | 187 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
185 | 188 | |
|
186 | 189 | SIGNAL current_matrix_write : STD_LOGIC; |
|
187 | 190 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
188 | 191 | ----------------------------------------------------------------------------- |
|
189 | 192 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
190 | 193 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
191 | 194 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
192 | 195 | |
|
193 | 196 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
194 | 197 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
195 | 198 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
196 | 199 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
197 | 200 | ----------------------------------------------------------------------------- |
|
198 | 201 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
199 | 202 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
200 | 203 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
201 | 204 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
202 | 205 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
203 | 206 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
204 | 207 | |
|
205 | 208 | ----------------------------------------------------------------------------- |
|
206 | 209 | -- TIME REG & INFOs |
|
207 | 210 | ----------------------------------------------------------------------------- |
|
208 | 211 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
209 | 212 | |
|
210 | 213 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
211 | 214 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
212 | 215 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
213 | 216 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
214 | 217 | |
|
215 | 218 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
216 | 219 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
217 | 220 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
218 | 221 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
219 | 222 | |
|
220 | 223 | --SIGNAL time_update_f0_A : STD_LOGIC; |
|
221 | 224 | --SIGNAL time_update_f0_B : STD_LOGIC; |
|
222 | 225 | --SIGNAL time_update_f1 : STD_LOGIC; |
|
223 | 226 | --SIGNAL time_update_f2 : STD_LOGIC; |
|
224 | 227 | -- |
|
225 | 228 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
226 | 229 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
227 | 230 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
228 | 231 | |
|
229 | 232 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
230 | 233 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
231 | 234 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
232 | 235 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
233 | 236 | ----------------------------------------------------------------------------- |
|
234 | 237 | |
|
235 | 238 | BEGIN |
|
236 | 239 | |
|
237 | 240 | |
|
238 | 241 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
239 | 242 | |
|
240 | 243 | |
|
241 | 244 | switch_f0_inst : spectral_matrix_switch_f0 |
|
242 | 245 | PORT MAP ( |
|
243 | 246 | clk => clk, |
|
244 | 247 | rstn => rstn, |
|
245 | 248 | |
|
246 | 249 | sample_wen => sample_f0_wen, |
|
247 | 250 | |
|
248 | 251 | fifo_A_empty => sample_f0_A_empty, |
|
249 | 252 | fifo_A_full => sample_f0_A_full, |
|
250 | 253 | fifo_A_wen => sample_f0_A_wen, |
|
251 | 254 | |
|
252 | 255 | fifo_B_empty => sample_f0_B_empty, |
|
253 | 256 | fifo_B_full => sample_f0_B_full, |
|
254 | 257 | fifo_B_wen => sample_f0_B_wen, |
|
255 | 258 | |
|
256 | 259 | error_wen => error_wen_f0); -- TODO |
|
257 | 260 | |
|
258 | 261 | ----------------------------------------------------------------------------- |
|
259 | 262 | -- FIFO IN |
|
260 | 263 | ----------------------------------------------------------------------------- |
|
261 | 264 | lppFIFOxN_f0_a : lppFIFOxN |
|
262 | 265 | GENERIC MAP ( |
|
263 | 266 | tech => 0, |
|
264 | 267 | Mem_use => Mem_use, |
|
265 | 268 | Data_sz => 16, |
|
266 | 269 | Addr_sz => 8, |
|
267 | 270 | FifoCnt => 5) |
|
268 | 271 | PORT MAP ( |
|
269 | 272 | clk => clk, |
|
270 | 273 | rstn => rstn, |
|
271 | 274 | |
|
272 | 275 | ReUse => (OTHERS => '0'), |
|
273 | 276 | |
|
274 | 277 | wen => sample_f0_A_wen, |
|
275 | 278 | wdata => sample_f0_wdata, |
|
276 | 279 | |
|
277 | 280 | ren => sample_f0_A_ren, |
|
278 | 281 | rdata => sample_f0_A_rdata, |
|
279 | 282 | |
|
280 | 283 | empty => sample_f0_A_empty, |
|
281 | 284 | full => sample_f0_A_full, |
|
282 | 285 | almost_full => OPEN); |
|
283 | 286 | |
|
284 | 287 | lppFIFOxN_f0_b : lppFIFOxN |
|
285 | 288 | GENERIC MAP ( |
|
286 | 289 | tech => 0, |
|
287 | 290 | Mem_use => Mem_use, |
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288 | 291 | Data_sz => 16, |
|
289 | 292 | Addr_sz => 8, |
|
290 | 293 | FifoCnt => 5) |
|
291 | 294 | PORT MAP ( |
|
292 | 295 | clk => clk, |
|
293 | 296 | rstn => rstn, |
|
294 | 297 | |
|
295 | 298 | ReUse => (OTHERS => '0'), |
|
296 | 299 | |
|
297 | 300 | wen => sample_f0_B_wen, |
|
298 | 301 | wdata => sample_f0_wdata, |
|
299 | 302 | ren => sample_f0_B_ren, |
|
300 | 303 | rdata => sample_f0_B_rdata, |
|
301 | 304 | empty => sample_f0_B_empty, |
|
302 | 305 | full => sample_f0_B_full, |
|
303 | 306 | almost_full => OPEN); |
|
304 | 307 | |
|
305 | 308 | lppFIFOxN_f1 : lppFIFOxN |
|
306 | 309 | GENERIC MAP ( |
|
307 | 310 | tech => 0, |
|
308 | 311 | Mem_use => Mem_use, |
|
309 | 312 | Data_sz => 16, |
|
310 | 313 | Addr_sz => 8, |
|
311 | 314 | FifoCnt => 5) |
|
312 | 315 | PORT MAP ( |
|
313 | 316 | clk => clk, |
|
314 | 317 | rstn => rstn, |
|
315 | 318 | |
|
316 | 319 | ReUse => (OTHERS => '0'), |
|
317 | 320 | |
|
318 | 321 | wen => sample_f1_wen, |
|
319 | 322 | wdata => sample_f1_wdata, |
|
320 | 323 | ren => sample_f1_ren, |
|
321 | 324 | rdata => sample_f1_rdata, |
|
322 | 325 | empty => sample_f1_empty, |
|
323 | 326 | full => sample_f1_full, |
|
324 | 327 | almost_full => sample_f1_almost_full); |
|
325 | 328 | |
|
326 | 329 | |
|
327 | 330 | one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1'; |
|
328 | 331 | |
|
329 | 332 | PROCESS (clk, rstn) |
|
330 | 333 | BEGIN -- PROCESS |
|
331 | 334 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
332 | 335 | one_sample_f1_full <= '0'; |
|
333 | 336 | error_wen_f1 <= '0'; |
|
334 | 337 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
335 | 338 | IF sample_f1_full = "00000" THEN |
|
336 | 339 | one_sample_f1_full <= '0'; |
|
337 | 340 | ELSE |
|
338 | 341 | one_sample_f1_full <= '1'; |
|
339 | 342 | END IF; |
|
340 | 343 | error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
341 | 344 | END IF; |
|
342 | 345 | END PROCESS; |
|
343 | 346 | |
|
344 | 347 | |
|
345 | 348 | lppFIFOxN_f2 : lppFIFOxN |
|
346 | 349 | GENERIC MAP ( |
|
347 | 350 | tech => 0, |
|
348 | 351 | Mem_use => Mem_use, |
|
349 | 352 | Data_sz => 16, |
|
350 | 353 | Addr_sz => 8, |
|
351 | 354 | FifoCnt => 5) |
|
352 | 355 | PORT MAP ( |
|
353 | 356 | clk => clk, |
|
354 | 357 | rstn => rstn, |
|
355 | 358 | |
|
356 | 359 | ReUse => (OTHERS => '0'), |
|
357 | 360 | |
|
358 | 361 | wen => sample_f2_wen, |
|
359 | 362 | wdata => sample_f2_wdata, |
|
360 | 363 | ren => sample_f2_ren, |
|
361 | 364 | rdata => sample_f2_rdata, |
|
362 | 365 | empty => sample_f2_empty, |
|
363 | 366 | full => sample_f2_full, |
|
364 | 367 | almost_full => OPEN); |
|
365 | 368 | |
|
366 | 369 | |
|
367 | 370 | one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1'; |
|
368 | 371 | |
|
369 | 372 | PROCESS (clk, rstn) |
|
370 | 373 | BEGIN -- PROCESS |
|
371 | 374 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
372 | 375 | one_sample_f2_full <= '0'; |
|
373 | 376 | error_wen_f2 <= '0'; |
|
374 | 377 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
375 | 378 | IF sample_f2_full = "00000" THEN |
|
376 | 379 | one_sample_f2_full <= '0'; |
|
377 | 380 | ELSE |
|
378 | 381 | one_sample_f2_full <= '1'; |
|
379 | 382 | END IF; |
|
380 | 383 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
381 | 384 | END IF; |
|
382 | 385 | END PROCESS; |
|
383 | 386 | |
|
384 | 387 | ----------------------------------------------------------------------------- |
|
385 | 388 | -- FSM SELECT CHANNEL |
|
386 | 389 | ----------------------------------------------------------------------------- |
|
387 | 390 | PROCESS (clk, rstn) |
|
388 | 391 | BEGIN |
|
389 | 392 | IF rstn = '0' THEN |
|
390 | 393 | state_fsm_select_channel <= IDLE; |
|
391 | 394 | ELSIF clk'EVENT AND clk = '1' THEN |
|
392 | 395 | CASE state_fsm_select_channel IS |
|
393 | 396 | WHEN IDLE => |
|
394 | 397 | IF sample_f1_full = "11111" THEN |
|
395 | 398 | state_fsm_select_channel <= SWITCH_F1; |
|
396 | 399 | ELSIF sample_f1_almost_full = "00000" THEN |
|
397 | 400 | IF sample_f0_A_full = "11111" THEN |
|
398 | 401 | state_fsm_select_channel <= SWITCH_F0_A; |
|
399 | 402 | ELSIF sample_f0_B_full = "11111" THEN |
|
400 | 403 | state_fsm_select_channel <= SWITCH_F0_B; |
|
401 | 404 | ELSIF sample_f2_full = "11111" THEN |
|
402 | 405 | state_fsm_select_channel <= SWITCH_F2; |
|
403 | 406 | END IF; |
|
404 | 407 | END IF; |
|
405 | 408 | |
|
406 | 409 | WHEN SWITCH_F0_A => |
|
407 | 410 | IF sample_f0_A_empty = "11111" THEN |
|
408 | 411 | state_fsm_select_channel <= IDLE; |
|
409 | 412 | END IF; |
|
410 | 413 | WHEN SWITCH_F0_B => |
|
411 | 414 | IF sample_f0_B_empty = "11111" THEN |
|
412 | 415 | state_fsm_select_channel <= IDLE; |
|
413 | 416 | END IF; |
|
414 | 417 | WHEN SWITCH_F1 => |
|
415 | 418 | IF sample_f1_empty = "11111" THEN |
|
416 | 419 | state_fsm_select_channel <= IDLE; |
|
417 | 420 | END IF; |
|
418 | 421 | WHEN SWITCH_F2 => |
|
419 | 422 | IF sample_f2_empty = "11111" THEN |
|
420 | 423 | state_fsm_select_channel <= IDLE; |
|
421 | 424 | END IF; |
|
422 | 425 | WHEN OTHERS => NULL; |
|
423 | 426 | END CASE; |
|
424 | 427 | |
|
425 | 428 | END IF; |
|
426 | 429 | END PROCESS; |
|
427 | 430 | |
|
428 | 431 | PROCESS (clk, rstn) |
|
429 | 432 | BEGIN |
|
430 | 433 | IF rstn = '0' THEN |
|
431 | 434 | pre_state_fsm_select_channel <= IDLE; |
|
432 | 435 | ELSIF clk'EVENT AND clk = '1' THEN |
|
433 | 436 | pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
434 | 437 | END IF; |
|
435 | 438 | END PROCESS; |
|
436 | 439 | |
|
437 | 440 | |
|
438 | 441 | ----------------------------------------------------------------------------- |
|
439 | 442 | -- SWITCH SELECT CHANNEL |
|
440 | 443 | ----------------------------------------------------------------------------- |
|
441 | 444 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
442 | 445 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
443 | 446 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
444 | 447 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
445 | 448 | (OTHERS => '1'); |
|
446 | 449 | |
|
447 | 450 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
448 | 451 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
449 | 452 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
450 | 453 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
451 | 454 | (OTHERS => '0'); |
|
452 | 455 | |
|
453 | 456 | sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
454 | 457 | sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
455 | 458 | sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
456 | 459 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
457 | 460 | |
|
458 | 461 | |
|
459 | 462 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
460 | 463 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
461 | 464 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
462 | 465 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
463 | 466 | |
|
464 | 467 | |
|
465 | 468 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
466 | 469 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
467 | 470 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
468 | 471 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
469 | 472 | |
|
470 | 473 | ----------------------------------------------------------------------------- |
|
471 | 474 | -- FSM LOAD FFT |
|
472 | 475 | ----------------------------------------------------------------------------- |
|
473 | 476 | |
|
474 | 477 | sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1'); |
|
475 | 478 | |
|
476 | 479 | PROCESS (clk, rstn) |
|
477 | 480 | BEGIN |
|
478 | 481 | IF rstn = '0' THEN |
|
479 | 482 | sample_ren_s <= (OTHERS => '1'); |
|
480 | 483 | state_fsm_load_FFT <= IDLE; |
|
481 | 484 | status_MS_input <= (OTHERS => '0'); |
|
482 | 485 | --next_state_fsm_load_FFT <= IDLE; |
|
483 | 486 | --sample_valid <= '0'; |
|
484 | 487 | ELSIF clk'EVENT AND clk = '1' THEN |
|
485 | 488 | CASE state_fsm_load_FFT IS |
|
486 | 489 | WHEN IDLE => |
|
487 | 490 | --sample_valid <= '0'; |
|
488 | 491 | sample_ren_s <= (OTHERS => '1'); |
|
489 | 492 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
490 | 493 | state_fsm_load_FFT <= FIFO_1; |
|
491 | 494 | status_MS_input <= status_channel; |
|
492 | 495 | END IF; |
|
493 | 496 | |
|
494 | 497 | WHEN FIFO_1 => |
|
495 | 498 | sample_ren_s <= "1111" & NOT(sample_load); |
|
496 | 499 | IF sample_empty(0) = '1' THEN |
|
497 | 500 | sample_ren_s <= (OTHERS => '1'); |
|
498 | 501 | state_fsm_load_FFT <= FIFO_2; |
|
499 | 502 | END IF; |
|
500 | 503 | |
|
501 | 504 | WHEN FIFO_2 => |
|
502 | 505 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
503 | 506 | IF sample_empty(1) = '1' THEN |
|
504 | 507 | sample_ren_s <= (OTHERS => '1'); |
|
505 | 508 | state_fsm_load_FFT <= FIFO_3; |
|
506 | 509 | END IF; |
|
507 | 510 | |
|
508 | 511 | WHEN FIFO_3 => |
|
509 | 512 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
510 | 513 | IF sample_empty(2) = '1' THEN |
|
511 | 514 | sample_ren_s <= (OTHERS => '1'); |
|
512 | 515 | state_fsm_load_FFT <= FIFO_4; |
|
513 | 516 | END IF; |
|
514 | 517 | |
|
515 | 518 | WHEN FIFO_4 => |
|
516 | 519 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
517 | 520 | IF sample_empty(3) = '1' THEN |
|
518 | 521 | sample_ren_s <= (OTHERS => '1'); |
|
519 | 522 | state_fsm_load_FFT <= FIFO_5; |
|
520 | 523 | END IF; |
|
521 | 524 | |
|
522 | 525 | WHEN FIFO_5 => |
|
523 | 526 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
524 | 527 | IF sample_empty(4) = '1' THEN |
|
525 | 528 | sample_ren_s <= (OTHERS => '1'); |
|
526 | 529 | state_fsm_load_FFT <= IDLE; |
|
527 | 530 | END IF; |
|
528 | 531 | WHEN OTHERS => NULL; |
|
529 | 532 | END CASE; |
|
530 | 533 | END IF; |
|
531 | 534 | END PROCESS; |
|
532 | 535 | |
|
533 | 536 | PROCESS (clk, rstn) |
|
534 | 537 | BEGIN |
|
535 | 538 | IF rstn = '0' THEN |
|
536 | 539 | sample_valid_r <= '0'; |
|
537 | 540 | next_state_fsm_load_FFT <= IDLE; |
|
538 | 541 | ELSIF clk'EVENT AND clk = '1' THEN |
|
539 | 542 | next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
540 | 543 | IF sample_ren_s = "11111" THEN |
|
541 | 544 | sample_valid_r <= '0'; |
|
542 | 545 | ELSE |
|
543 | 546 | sample_valid_r <= '1'; |
|
544 | 547 | END IF; |
|
545 | 548 | END IF; |
|
546 | 549 | END PROCESS; |
|
547 | 550 | |
|
548 | 551 | sample_valid <= sample_valid_r AND sample_load; |
|
549 | 552 | |
|
550 | 553 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
551 | 554 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
552 | 555 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
553 | 556 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
554 | 557 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
555 | 558 | |
|
556 | 559 | ----------------------------------------------------------------------------- |
|
557 | 560 | -- FFT |
|
558 | 561 | ----------------------------------------------------------------------------- |
|
559 | 562 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT |
|
560 | 563 | PORT MAP ( |
|
561 | 564 | clk => clk, |
|
562 | 565 | rstn => rstn, |
|
563 | 566 | sample_valid => sample_valid, |
|
564 | 567 | fft_read => fft_read, |
|
565 | 568 | sample_data => sample_data, |
|
566 | 569 | sample_load => sample_load, |
|
567 | 570 | fft_pong => fft_pong, |
|
568 | 571 | fft_data_im => fft_data_im, |
|
569 | 572 | fft_data_re => fft_data_re, |
|
570 | 573 | fft_data_valid => fft_data_valid, |
|
571 | 574 | fft_ready => fft_ready); |
|
572 | 575 | |
|
576 | observation_vector_0(5 DOWNTO 0) <= fft_ready & --5 | |
|
577 | fft_data_valid & --4 | |
|
578 | fft_pong & --3 | |
|
579 | sample_load & --2 | |
|
580 | fft_read & --1 | |
|
581 | sample_valid; --0 | |
|
582 | ||
|
583 | ||
|
573 | 584 |
|
|
574 | 585 | PROCESS (clk, rstn) |
|
575 | 586 | BEGIN |
|
576 | 587 | IF rstn = '0' THEN |
|
577 | 588 | state_fsm_load_MS_memory <= IDLE; |
|
578 | 589 | current_fifo_load <= "00001"; |
|
579 | 590 | ELSIF clk'EVENT AND clk = '1' THEN |
|
580 | 591 | CASE state_fsm_load_MS_memory IS |
|
581 | 592 | WHEN IDLE => |
|
582 | 593 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
583 | 594 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
584 | 595 | END IF; |
|
585 | 596 | WHEN LOAD_FIFO => |
|
586 | 597 | IF current_fifo_full = '1' THEN |
|
587 | 598 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
588 | 599 | END IF; |
|
589 | 600 | WHEN TRASH_FFT => |
|
590 | 601 | IF fft_ready = '0' THEN |
|
591 | 602 | state_fsm_load_MS_memory <= IDLE; |
|
592 | 603 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
593 | 604 | END IF; |
|
594 | 605 | WHEN OTHERS => NULL; |
|
595 | 606 | END CASE; |
|
596 | 607 | |
|
597 | 608 | END IF; |
|
598 | 609 | END PROCESS; |
|
599 | 610 | |
|
600 | 611 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
601 | 612 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
602 | 613 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
603 | 614 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
604 | 615 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
605 | 616 | |
|
606 | 617 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
607 | 618 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
608 | 619 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
609 | 620 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
610 | 621 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
611 | 622 | |
|
612 | 623 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
613 | 624 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
614 | 625 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
615 | 626 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
616 | 627 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
617 | 628 | |
|
618 | 629 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
619 | 630 | |
|
620 | 631 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE |
|
621 | 632 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
622 | 633 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
623 | 634 | AND current_fifo_load(I) = '1' |
|
624 | 635 | ELSE '1'; |
|
625 | 636 | END GENERATE all_fifo; |
|
626 | 637 | |
|
627 | 638 | PROCESS (clk, rstn) |
|
628 | 639 | BEGIN |
|
629 | 640 | IF rstn = '0' THEN |
|
630 | 641 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
631 | 642 | ELSIF clk'EVENT AND clk = '1' THEN |
|
632 | 643 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
633 | 644 | END IF; |
|
634 | 645 | END PROCESS; |
|
635 | 646 | |
|
636 | 647 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
637 | 648 | (fft_data_im & fft_data_re) & |
|
638 | 649 | (fft_data_im & fft_data_re) & |
|
639 | 650 | (fft_data_im & fft_data_re) & |
|
640 | 651 | (fft_data_im & fft_data_re); |
|
652 | ----------------------------------------------------------------------------- | |
|
653 | ||
|
641 | 654 |
|
|
642 | 655 |
|
|
643 | 656 | Mem_In_SpectralMatrix : lppFIFOxN |
|
644 | 657 | GENERIC MAP ( |
|
645 | 658 | tech => 0, |
|
646 | 659 | Mem_use => Mem_use, |
|
647 | 660 | Data_sz => 32, --16, |
|
648 | 661 | Addr_sz => 7, --8 |
|
649 | 662 | FifoCnt => 5) |
|
650 | 663 | PORT MAP ( |
|
651 | 664 | clk => clk, |
|
652 | 665 | rstn => rstn, |
|
653 | 666 | |
|
654 | 667 | ReUse => MEM_IN_SM_ReUse, |
|
655 | 668 | |
|
656 | 669 | wen => MEM_IN_SM_wen, |
|
657 | 670 | wdata => MEM_IN_SM_wData, |
|
658 | 671 | |
|
659 | 672 | ren => MEM_IN_SM_ren, |
|
660 | 673 | rdata => MEM_IN_SM_rData, |
|
661 | 674 | full => MEM_IN_SM_Full, |
|
662 | 675 | empty => MEM_IN_SM_Empty, |
|
663 | 676 | almost_full => OPEN); |
|
664 | 677 | |
|
665 | 678 | ----------------------------------------------------------------------------- |
|
666 | 679 | MS_control_1 : MS_control |
|
667 | 680 | PORT MAP ( |
|
668 | 681 | clk => clk, |
|
669 | 682 | rstn => rstn, |
|
670 | 683 | |
|
671 | 684 | current_status_ms => status_MS_input, |
|
672 | 685 | |
|
673 | 686 | fifo_in_lock => MEM_IN_SM_locked, |
|
674 | 687 | fifo_in_data => MEM_IN_SM_rdata, |
|
675 | 688 | fifo_in_full => MEM_IN_SM_Full, |
|
676 | 689 | fifo_in_empty => MEM_IN_SM_Empty, |
|
677 | 690 | fifo_in_ren => MEM_IN_SM_ren, |
|
678 | 691 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
679 | 692 | |
|
680 | 693 | fifo_out_data => SM_in_data, |
|
681 | 694 | fifo_out_ren => SM_in_ren, |
|
682 | 695 | fifo_out_empty => SM_in_empty, |
|
683 | 696 | |
|
684 | 697 | current_status_component => status_component, |
|
685 | 698 | |
|
686 | 699 | correlation_start => SM_correlation_start, |
|
687 | 700 | correlation_auto => SM_correlation_auto, |
|
688 | 701 | correlation_done => SM_correlation_done); |
|
689 | 702 | |
|
690 | 703 | |
|
691 | 704 | MS_calculation_1 : MS_calculation |
|
692 | 705 | PORT MAP ( |
|
693 | 706 | clk => clk, |
|
694 | 707 | rstn => rstn, |
|
695 | 708 | |
|
696 | 709 | fifo_in_data => SM_in_data, |
|
697 | 710 | fifo_in_ren => SM_in_ren, |
|
698 | 711 | fifo_in_empty => SM_in_empty, |
|
699 | 712 | |
|
700 | 713 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
701 | 714 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
702 | 715 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
703 | 716 | |
|
704 | 717 | correlation_start => SM_correlation_start, |
|
705 | 718 | correlation_auto => SM_correlation_auto, |
|
706 | 719 | correlation_begin => SM_correlation_begin, |
|
707 | 720 | correlation_done => SM_correlation_done); |
|
708 | 721 | |
|
709 | 722 | ----------------------------------------------------------------------------- |
|
710 | 723 | PROCESS (clk, rstn) |
|
711 | 724 | BEGIN -- PROCESS |
|
712 | 725 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
713 | 726 | current_matrix_write <= '0'; |
|
714 | 727 | current_matrix_wait_empty <= '1'; |
|
715 | 728 | status_component_fifo_0 <= (OTHERS => '0'); |
|
716 | 729 | status_component_fifo_1 <= (OTHERS => '0'); |
|
717 | 730 | status_component_fifo_0_end <= '0'; |
|
718 | 731 | status_component_fifo_1_end <= '0'; |
|
719 | 732 | SM_correlation_done_reg1 <= '0'; |
|
720 | 733 | SM_correlation_done_reg2 <= '0'; |
|
721 | 734 | SM_correlation_done_reg3 <= '0'; |
|
722 | 735 | |
|
723 | 736 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
724 | 737 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
725 | 738 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
726 | 739 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; |
|
727 | 740 | status_component_fifo_0_end <= '0'; |
|
728 | 741 | status_component_fifo_1_end <= '0'; |
|
729 | 742 | IF SM_correlation_begin = '1' THEN |
|
730 | 743 | IF current_matrix_write = '0' THEN |
|
731 | 744 | status_component_fifo_0 <= status_component; |
|
732 | 745 | ELSE |
|
733 | 746 | status_component_fifo_1 <= status_component; |
|
734 | 747 | END IF; |
|
735 | 748 | END IF; |
|
736 | 749 | |
|
737 | 750 | IF SM_correlation_done_reg3 = '1' THEN |
|
738 | 751 | IF current_matrix_write = '0' THEN |
|
739 | 752 | status_component_fifo_0_end <= '1'; |
|
740 | 753 | ELSE |
|
741 | 754 | status_component_fifo_1_end <= '1'; |
|
742 | 755 | END IF; |
|
743 | 756 | current_matrix_wait_empty <= '1'; |
|
744 | 757 | current_matrix_write <= NOT current_matrix_write; |
|
745 | 758 | END IF; |
|
746 | 759 | |
|
747 | 760 | IF current_matrix_wait_empty <= '1' THEN |
|
748 | 761 | IF current_matrix_write = '0' THEN |
|
749 | 762 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
750 | 763 | ELSE |
|
751 | 764 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
752 | 765 | END IF; |
|
753 | 766 | END IF; |
|
754 | 767 | |
|
755 | 768 | END IF; |
|
756 | 769 | END PROCESS; |
|
757 | 770 | |
|
758 | 771 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
759 | 772 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
760 | 773 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
761 | 774 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE |
|
762 | 775 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
763 | 776 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
764 | 777 | MEM_OUT_SM_Full(1); |
|
765 | 778 | |
|
766 | 779 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
767 | 780 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
768 | 781 | |
|
769 | 782 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
770 | 783 | ----------------------------------------------------------------------------- |
|
771 | 784 | |
|
772 | 785 | Mem_Out_SpectralMatrix : lppFIFOxN |
|
773 | 786 | GENERIC MAP ( |
|
774 | 787 | tech => 0, |
|
775 | 788 | Mem_use => Mem_use, |
|
776 | 789 | Data_sz => 32, |
|
777 | 790 | Addr_sz => 8, |
|
778 | 791 | FifoCnt => 2) |
|
779 | 792 | PORT MAP ( |
|
780 | 793 | clk => clk, |
|
781 | 794 | rstn => rstn, |
|
782 | 795 | |
|
783 | 796 | ReUse => (OTHERS => '0'), |
|
784 | 797 | |
|
785 | 798 | wen => MEM_OUT_SM_Write, |
|
786 | 799 | wdata => MEM_OUT_SM_Data_in, |
|
787 | 800 | |
|
788 | 801 | ren => MEM_OUT_SM_Read, |
|
789 | 802 | rdata => MEM_OUT_SM_Data_out, |
|
790 | 803 | |
|
791 | 804 | full => MEM_OUT_SM_Full, |
|
792 | 805 | empty => MEM_OUT_SM_Empty, |
|
793 | 806 | almost_full => OPEN); |
|
794 | 807 | |
|
795 | 808 | ----------------------------------------------------------------------------- |
|
796 | 809 | -- MEM_OUT_SM_Read <= "00"; |
|
797 | 810 | PROCESS (clk, rstn) |
|
798 | 811 | BEGIN |
|
799 | 812 | IF rstn = '0' THEN |
|
800 | 813 | fifo_0_ready <= '0'; |
|
801 | 814 | fifo_1_ready <= '0'; |
|
802 | 815 | fifo_ongoing <= '0'; |
|
803 | 816 | ELSIF clk'EVENT AND clk = '1' THEN |
|
804 | 817 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
805 | 818 | fifo_ongoing <= '1'; |
|
806 | 819 | fifo_0_ready <= '0'; |
|
807 | 820 | ELSIF status_component_fifo_0_end = '1' THEN |
|
808 | 821 | fifo_0_ready <= '1'; |
|
809 | 822 | END IF; |
|
810 | 823 | |
|
811 | 824 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
812 | 825 | fifo_ongoing <= '0'; |
|
813 | 826 | fifo_1_ready <= '0'; |
|
814 | 827 | ELSIF status_component_fifo_1_end = '1' THEN |
|
815 | 828 | fifo_1_ready <= '1'; |
|
816 | 829 | END IF; |
|
817 | 830 | |
|
818 | 831 | END IF; |
|
819 | 832 | END PROCESS; |
|
820 | 833 | |
|
821 | 834 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
822 | 835 | '1' WHEN fifo_0_ready = '0' ELSE |
|
823 | 836 | FSM_DMA_fifo_ren; |
|
824 | 837 | |
|
825 | 838 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
826 | 839 | '1' WHEN fifo_1_ready = '0' ELSE |
|
827 | 840 | FSM_DMA_fifo_ren; |
|
828 | 841 | |
|
829 | 842 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
830 | 843 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
831 | 844 | '1'; |
|
832 | 845 | |
|
833 | 846 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
834 | 847 | status_component_fifo_1; |
|
835 | 848 | |
|
836 | 849 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
837 | 850 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
838 | 851 | |
|
839 | 852 | ----------------------------------------------------------------------------- |
|
840 | 853 | lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
841 | 854 | PORT MAP ( |
|
842 | 855 | HCLK => clk, |
|
843 | 856 | HRESETn => rstn, |
|
844 | 857 | |
|
845 | 858 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
846 | 859 | fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), |
|
847 | 860 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
848 | 861 | fifo_data => FSM_DMA_fifo_data, |
|
849 | 862 | fifo_empty => FSM_DMA_fifo_empty, |
|
850 | 863 | fifo_ren => FSM_DMA_fifo_ren, |
|
851 | 864 | |
|
852 | 865 | dma_addr => dma_addr, |
|
853 | 866 | dma_data => dma_data, |
|
854 | 867 | dma_valid => dma_valid, |
|
855 | 868 | dma_valid_burst => dma_valid_burst, |
|
856 | 869 | dma_ren => dma_ren, |
|
857 | 870 | dma_done => dma_done, |
|
858 | 871 | |
|
859 | 872 | ready_matrix_f0 => ready_matrix_f0, |
|
860 | 873 | ready_matrix_f1 => ready_matrix_f1, |
|
861 | 874 | ready_matrix_f2 => ready_matrix_f2, |
|
862 | 875 | |
|
863 | 876 | error_bad_component_error => error_bad_component_error, |
|
864 | 877 | error_buffer_full => error_buffer_full, |
|
865 | 878 | |
|
866 | 879 | debug_reg => debug_reg, |
|
867 | 880 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
868 | 881 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
869 | 882 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
870 | 883 | |
|
871 | 884 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
872 | 885 | config_active_interruption_onError => config_active_interruption_onError, |
|
873 | 886 | |
|
874 | 887 | addr_matrix_f0 => addr_matrix_f0, |
|
875 | 888 | addr_matrix_f1 => addr_matrix_f1, |
|
876 | 889 | addr_matrix_f2 => addr_matrix_f2, |
|
877 | 890 | |
|
878 | 891 | matrix_time_f0 => matrix_time_f0, |
|
879 | 892 | matrix_time_f1 => matrix_time_f1, |
|
880 | 893 | matrix_time_f2 => matrix_time_f2 |
|
881 | 894 | ); |
|
882 | 895 | ----------------------------------------------------------------------------- |
|
883 | 896 | |
|
884 | 897 | |
|
885 | 898 | |
|
886 | 899 | |
|
887 | 900 | |
|
888 | 901 | ----------------------------------------------------------------------------- |
|
889 | 902 | -- TIME MANAGMENT |
|
890 | 903 | ----------------------------------------------------------------------------- |
|
891 | 904 | all_time <= coarse_time & fine_time; |
|
892 | 905 | -- |
|
893 | 906 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; |
|
894 | 907 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; |
|
895 | 908 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
896 | 909 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; |
|
897 | 910 | |
|
898 | 911 | all_time_reg: FOR I IN 0 TO 3 GENERATE |
|
899 | 912 | |
|
900 | 913 | PROCESS (clk, rstn) |
|
901 | 914 | BEGIN |
|
902 | 915 | IF rstn = '0' THEN |
|
903 | 916 | f_empty_reg(I) <= '1'; |
|
904 | 917 | ELSIF clk'event AND clk = '1' THEN |
|
905 | 918 | f_empty_reg(I) <= f_empty(I); |
|
906 | 919 | END IF; |
|
907 | 920 | END PROCESS; |
|
908 | 921 | |
|
909 | 922 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; |
|
910 | 923 | |
|
911 | 924 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
912 | 925 | PORT MAP ( |
|
913 | 926 | clk => clk, |
|
914 | 927 | rstn => rstn, |
|
915 | 928 | time_in => all_time, |
|
916 | 929 | update_1 => time_update_f(I), |
|
917 | 930 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) |
|
918 | 931 | ); |
|
919 | 932 | |
|
920 | 933 | END GENERATE all_time_reg; |
|
921 | 934 | |
|
922 | 935 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); |
|
923 | 936 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); |
|
924 | 937 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); |
|
925 | 938 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); |
|
926 | 939 | |
|
927 | 940 | ----------------------------------------------------------------------------- |
|
928 | 941 | |
|
929 | 942 | END Behavioral; |
@@ -1,298 +1,299 | |||
|
1 | 1 | |
|
2 | 2 | ------------------------------------------------------------------------------ |
|
3 | 3 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
4 | 4 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
5 | 5 | -- |
|
6 | 6 | -- This program is free software; you can redistribute it and/or modify |
|
7 | 7 | -- it under the terms of the GNU General Public License as published by |
|
8 | 8 | -- the Free Software Foundation; either version 3 of the License, or |
|
9 | 9 | -- (at your option) any later version. |
|
10 | 10 | -- |
|
11 | 11 | -- This program is distributed in the hope that it will be useful, |
|
12 | 12 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
13 | 13 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
14 | 14 | -- GNU General Public License for more details. |
|
15 | 15 | -- |
|
16 | 16 | -- You should have received a copy of the GNU General Public License |
|
17 | 17 | -- along with this program; if not, write to the Free Software |
|
18 | 18 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
19 | 19 | ------------------------------------------------------------------------------- |
|
20 | 20 | -- Author : Jean-christophe Pellion |
|
21 | 21 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
22 | 22 | -- jean-christophe.pellion@easii-ic.com |
|
23 | 23 | ------------------------------------------------------------------------------- |
|
24 | 24 | LIBRARY ieee; |
|
25 | 25 | USE ieee.std_logic_1164.ALL; |
|
26 | 26 | USE ieee.numeric_std.ALL; |
|
27 | 27 | LIBRARY grlib; |
|
28 | 28 | USE grlib.amba.ALL; |
|
29 | 29 | USE grlib.stdlib.ALL; |
|
30 | 30 | USE grlib.devices.ALL; |
|
31 | 31 | USE GRLIB.DMA2AHB_Package.ALL; |
|
32 | 32 | LIBRARY lpp; |
|
33 | 33 | USE lpp.lpp_amba.ALL; |
|
34 | 34 | USE lpp.apb_devices_list.ALL; |
|
35 | 35 | USE lpp.lpp_memory.ALL; |
|
36 | 36 | USE lpp.lpp_dma_pkg.ALL; |
|
37 | 37 | LIBRARY techmap; |
|
38 | 38 | USE techmap.gencomp.ALL; |
|
39 | 39 | |
|
40 | 40 | |
|
41 | 41 | ENTITY lpp_lfr_ms_fsmdma IS |
|
42 | 42 | PORT ( |
|
43 | 43 | -- AMBA AHB system signals |
|
44 | 44 | HCLK : IN STD_ULOGIC; |
|
45 | 45 | HRESETn : IN STD_ULOGIC; |
|
46 | 46 | |
|
47 | 47 | --------------------------------------------------------------------------- |
|
48 | 48 | -- FIFO - IN |
|
49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
53 | fifo_empty : IN STD_LOGIC; | |
|
54 | fifo_ren : OUT STD_LOGIC; | |
|
49 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |
|
50 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
|
51 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); | |
|
52 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
53 | fifo_empty : IN STD_LOGIC; | |
|
54 | fifo_ren : OUT STD_LOGIC; | |
|
55 | 55 | |
|
56 | 56 | --------------------------------------------------------------------------- |
|
57 | 57 | -- DMA - OUT |
|
58 | 58 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
59 | 59 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
60 | 60 | dma_valid : OUT STD_LOGIC; |
|
61 | 61 | dma_valid_burst : OUT STD_LOGIC; |
|
62 | 62 | dma_ren : IN STD_LOGIC; |
|
63 | 63 | dma_done : IN STD_LOGIC; |
|
64 | 64 | |
|
65 | 65 | --------------------------------------------------------------------------- |
|
66 | 66 | -- Reg out |
|
67 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
67 | ready_matrix_f0 : OUT STD_LOGIC; | |
|
68 | 68 | ready_matrix_f1 : OUT STD_LOGIC; |
|
69 | 69 | ready_matrix_f2 : OUT STD_LOGIC; |
|
70 | 70 | |
|
71 | 71 | error_bad_component_error : OUT STD_LOGIC; |
|
72 | 72 | error_buffer_full : OUT STD_LOGIC; |
|
73 | 73 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
74 | 74 | |
|
75 | 75 | -- Reg In |
|
76 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
76 | status_ready_matrix_f0 : IN STD_LOGIC; | |
|
77 | 77 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
78 | 78 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
79 | 79 | |
|
80 | 80 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
81 | 81 | config_active_interruption_onError : IN STD_LOGIC; |
|
82 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
82 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
|
83 | 83 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
84 | 84 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
85 | 85 | |
|
86 | 86 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
87 | 87 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
88 | 88 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
89 | 89 | |
|
90 | 90 | ); |
|
91 | 91 | END; |
|
92 | 92 | |
|
93 | 93 | ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS |
|
94 | 94 | ----------------------------------------------------------------------------- |
|
95 | 95 | TYPE state_DMAWriteBurst IS (IDLE, |
|
96 | 96 | CHECK_COMPONENT_TYPE, |
|
97 | 97 | WRITE_COARSE_TIME, |
|
98 | 98 | WRITE_FINE_TIME, |
|
99 | 99 | TRASH_FIFO, |
|
100 | 100 | SEND_DATA, |
|
101 | 101 | WAIT_DATA_ACK |
|
102 | 102 | ); |
|
103 | 103 | SIGNAL state : state_DMAWriteBurst; |
|
104 | 104 | |
|
105 | 105 | SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
106 | 106 | SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
107 | 107 | SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SIGNAL header_check_ok : STD_LOGIC; |
|
109 | 109 | SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
110 | 110 | SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
111 | 111 | ----------------------------------------------------------------------------- |
|
112 | 112 | ----------------------------------------------------------------------------- |
|
113 | 113 | |
|
114 | 114 | SIGNAL component_send : STD_LOGIC; |
|
115 | 115 | SIGNAL component_send_ok : STD_LOGIC; |
|
116 | 116 | ----------------------------------------------------------------------------- |
|
117 | 117 | SIGNAL fifo_ren_trash : STD_LOGIC; |
|
118 | 118 | |
|
119 | 119 | ----------------------------------------------------------------------------- |
|
120 | 120 | SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
121 | 121 | ----------------------------------------------------------------------------- |
|
122 | 122 | SIGNAL log_empty_fifo : STD_LOGIC; |
|
123 | 123 | ----------------------------------------------------------------------------- |
|
124 | 124 | |
|
125 | 125 | SIGNAL matrix_buffer_ready : STD_LOGIC; |
|
126 | 126 | BEGIN |
|
127 | 127 | |
|
128 | 128 | debug_reg <= debug_reg_s; |
|
129 | 129 | |
|
130 | 130 | |
|
131 | 131 | matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE |
|
132 | 132 | '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE |
|
133 | 133 | '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE |
|
134 | 134 | '0'; |
|
135 | 135 | |
|
136 | 136 | header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111" |
|
137 | 137 | '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE |
|
138 | 138 | '1' WHEN component_type = component_type_pre + "0001" ELSE |
|
139 | 139 | '0'; |
|
140 | 140 | |
|
141 | 141 | address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE |
|
142 | 142 | addr_matrix_f1 WHEN matrix_type = "01" ELSE |
|
143 | 143 | addr_matrix_f2 WHEN matrix_type = "10" ELSE |
|
144 | 144 | (OTHERS => '0'); |
|
145 | 145 | |
|
146 | 146 | debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); |
|
147 | 147 | ----------------------------------------------------------------------------- |
|
148 | 148 | -- DMA control |
|
149 | 149 | ----------------------------------------------------------------------------- |
|
150 | 150 | DMAWriteFSM_p : PROCESS (HCLK, HRESETn) |
|
151 | 151 | BEGIN |
|
152 | 152 | IF HRESETn = '0' THEN |
|
153 | 153 | matrix_type <= (OTHERS => '0'); |
|
154 | 154 | component_type <= (OTHERS => '0'); |
|
155 | 155 | state <= IDLE; |
|
156 | 156 | ready_matrix_f0 <= '0'; |
|
157 | 157 | ready_matrix_f1 <= '0'; |
|
158 | 158 | ready_matrix_f2 <= '0'; |
|
159 | 159 | error_bad_component_error <= '0'; |
|
160 | 160 | error_buffer_full <= '0'; -- TODO |
|
161 | 161 | component_type_pre <= "0000"; |
|
162 | 162 | fifo_ren_trash <= '1'; |
|
163 | 163 | component_send <= '0'; |
|
164 | 164 | address <= (OTHERS => '0'); |
|
165 | 165 | |
|
166 | 166 | debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0'); |
|
167 | 167 | debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0'); |
|
168 | 168 | debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0'); |
|
169 | 169 | debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0'); |
|
170 | 170 | debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0'); |
|
171 | 171 | |
|
172 | 172 | log_empty_fifo <= '0'; |
|
173 | 173 | |
|
174 | 174 | matrix_time_f0 <= (OTHERS => '0'); |
|
175 | 175 | matrix_time_f1 <= (OTHERS => '0'); |
|
176 | 176 | matrix_time_f2 <= (OTHERS => '0'); |
|
177 | 177 | |
|
178 | 178 | ELSIF HCLK'EVENT AND HCLK = '1' THEN |
|
179 | 179 | -- |
|
180 | 180 | debug_reg_s(3) <= status_ready_matrix_f0; |
|
181 | 181 | debug_reg_s(4) <= status_ready_matrix_f1; |
|
182 | 182 | debug_reg_s(5) <= status_ready_matrix_f2; |
|
183 | 183 | debug_reg_s(6) <= '0'; |
|
184 | 184 | debug_reg_s(7) <= '0'; |
|
185 | 185 | debug_reg_s(8) <= '0'; |
|
186 | 186 | debug_reg_s(10 DOWNTO 9) <= matrix_type; |
|
187 | 187 | debug_reg_s(14 DOWNTO 11) <= component_type; |
|
188 | 188 | |
|
189 | 189 | -- |
|
190 | 190 | |
|
191 | 191 | |
|
192 | 192 | |
|
193 | ready_matrix_f0 <= '0'; | |
|
193 | ready_matrix_f0 <= '0'; | |
|
194 | 194 | ready_matrix_f1 <= '0'; |
|
195 | 195 | ready_matrix_f2 <= '0'; |
|
196 | 196 | error_bad_component_error <= '0'; |
|
197 | 197 | error_buffer_full <= '0'; |
|
198 | 198 | |
|
199 | 199 | CASE state IS |
|
200 | 200 | WHEN IDLE => |
|
201 | 201 | debug_reg_s(2 DOWNTO 0) <= "000"; |
|
202 | 202 | IF fifo_empty = '0' THEN |
|
203 | 203 | state <= CHECK_COMPONENT_TYPE; |
|
204 | 204 | matrix_type <= fifo_matrix_type; |
|
205 | 205 | component_type <= fifo_matrix_component; |
|
206 | 206 | component_type_pre <= component_type; |
|
207 | 207 | END IF; |
|
208 | 208 | |
|
209 | 209 | log_empty_fifo <= '0'; |
|
210 | 210 | |
|
211 | 211 | WHEN CHECK_COMPONENT_TYPE => |
|
212 | 212 | debug_reg_s(2 DOWNTO 0) <= "001"; |
|
213 | 213 | |
|
214 | 214 | IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN |
|
215 | 215 | IF component_type = "0000" THEN |
|
216 | 216 | address <= address_matrix; |
|
217 | 217 | CASE matrix_type IS |
|
218 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; | |
|
218 | WHEN "00" => matrix_time_f0 <= fifo_matrix_time; | |
|
219 | 219 | WHEN "01" => matrix_time_f1 <= fifo_matrix_time; |
|
220 | 220 | WHEN "10" => matrix_time_f2 <= fifo_matrix_time; |
|
221 | 221 | WHEN OTHERS => NULL; |
|
222 | 222 | END CASE; |
|
223 | 223 | component_send <= '1'; |
|
224 | 224 | END IF; |
|
225 | 225 | state <= SEND_DATA; |
|
226 | 226 | -- |
|
227 | 227 | ELSE |
|
228 | 228 | error_bad_component_error <= NOT header_check_ok; |
|
229 | 229 | error_buffer_full <= NOT matrix_buffer_ready; -- TODO |
|
230 | 230 | component_type_pre <= "0000"; |
|
231 | 231 | state <= TRASH_FIFO; |
|
232 | 232 | END IF; |
|
233 | 233 | |
|
234 | 234 | WHEN TRASH_FIFO => |
|
235 | 235 | debug_reg_s(2 DOWNTO 0) <= "100"; |
|
236 | ||
|
236 | ||
|
237 | error_buffer_full <= '0'; | |
|
237 | 238 | error_bad_component_error <= '0'; |
|
238 | 239 | IF fifo_empty = '1' THEN |
|
239 | 240 | state <= IDLE; |
|
240 | 241 | fifo_ren_trash <= '1'; |
|
241 | 242 | ELSE |
|
242 | 243 | fifo_ren_trash <= '0'; |
|
243 | 244 | END IF; |
|
244 | 245 | |
|
245 | 246 | WHEN SEND_DATA => |
|
246 | 247 | debug_reg_s(2 DOWNTO 0) <= "010"; |
|
247 | 248 | |
|
248 | 249 | IF fifo_empty = '1' OR log_empty_fifo = '1' THEN |
|
249 | 250 | state <= IDLE; |
|
250 | 251 | IF component_type = "1110" THEN |
|
251 | 252 | CASE matrix_type IS |
|
252 | 253 | WHEN "00" => |
|
253 | 254 | ready_matrix_f0 <= '1'; |
|
254 | 255 | debug_reg_s(6) <= '1'; |
|
255 | 256 | WHEN "01" => |
|
256 | 257 | ready_matrix_f1 <= '1'; |
|
257 | 258 | debug_reg_s(7) <= '1'; |
|
258 | 259 | WHEN "10" => |
|
259 | 260 | ready_matrix_f2 <= '1'; |
|
260 | 261 | debug_reg_s(8) <= '1'; |
|
261 | 262 | WHEN OTHERS => NULL; |
|
262 | 263 | END CASE; |
|
263 | 264 | END IF; |
|
264 | 265 | ELSE |
|
265 | 266 | component_send <= '1'; |
|
266 | 267 | address <= address; |
|
267 | 268 | state <= WAIT_DATA_ACK; |
|
268 | 269 | END IF; |
|
269 | 270 | |
|
270 | 271 | WHEN WAIT_DATA_ACK => |
|
271 | 272 | log_empty_fifo <= fifo_empty OR log_empty_fifo; |
|
272 | 273 | |
|
273 | 274 | debug_reg_s(2 DOWNTO 0) <= "011"; |
|
274 | 275 | |
|
275 | 276 | IF dma_ren = '0' THEN |
|
276 | 277 | component_send <= '0'; |
|
277 | 278 | END IF; |
|
278 | 279 | |
|
279 | 280 | IF component_send_ok = '1' THEN |
|
280 | 281 | address <= address + 64; |
|
281 | 282 | state <= SEND_DATA; |
|
282 | 283 | END IF; |
|
283 | 284 | |
|
284 | 285 | WHEN OTHERS => NULL; |
|
285 | 286 | END CASE; |
|
286 | 287 | |
|
287 | 288 | END IF; |
|
288 | 289 | END PROCESS DMAWriteFSM_p; |
|
289 | 290 | |
|
290 | 291 | dma_valid_burst <= component_send; |
|
291 | 292 | dma_valid <= '0'; |
|
292 | 293 | dma_data <= fifo_data; |
|
293 | 294 | dma_addr <= address; |
|
294 | 295 | fifo_ren <= dma_ren AND fifo_ren_trash; |
|
295 | 296 | |
|
296 | 297 | component_send_ok <= dma_done; |
|
297 | 298 | |
|
298 | 299 | END Behavioral; |
@@ -1,406 +1,416 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | |
|
4 | 4 | LIBRARY grlib; |
|
5 | 5 | USE grlib.amba.ALL; |
|
6 | 6 | |
|
7 | 7 | LIBRARY lpp; |
|
8 | 8 | USE lpp.lpp_ad_conv.ALL; |
|
9 | 9 | USE lpp.iir_filter.ALL; |
|
10 | 10 | USE lpp.FILTERcfg.ALL; |
|
11 | 11 | USE lpp.lpp_memory.ALL; |
|
12 | 12 | LIBRARY techmap; |
|
13 | 13 | USE techmap.gencomp.ALL; |
|
14 | 14 | |
|
15 | 15 | PACKAGE lpp_lfr_pkg IS |
|
16 | 16 | ----------------------------------------------------------------------------- |
|
17 | 17 | -- TEMP |
|
18 | 18 | ----------------------------------------------------------------------------- |
|
19 | 19 | COMPONENT lpp_lfr_ms_test |
|
20 | 20 | GENERIC ( |
|
21 | 21 | Mem_use : INTEGER); |
|
22 | 22 | PORT ( |
|
23 | 23 | clk : IN STD_LOGIC; |
|
24 | 24 | rstn : IN STD_LOGIC; |
|
25 | 25 | |
|
26 | 26 | -- TIME |
|
27 | 27 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
28 | 28 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
29 | 29 | -- |
|
30 | 30 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
31 | 31 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
32 | 32 | -- |
|
33 | 33 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
34 | 34 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
35 | 35 | -- |
|
36 | 36 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
37 | 37 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
38 | 38 | |
|
39 | 39 | |
|
40 | 40 | |
|
41 | 41 | --------------------------------------------------------------------------- |
|
42 | 42 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
43 | 43 | |
|
44 | 44 | -- |
|
45 | 45 | --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
46 | 46 | --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
47 | 47 | --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
48 | 48 | --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
49 | 49 | |
|
50 | 50 | --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
51 | 51 | |
|
52 | 52 | -- IN |
|
53 | 53 | MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
54 | 54 | |
|
55 | 55 | ----------------------------------------------------------------------------- |
|
56 | 56 | |
|
57 | 57 | status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
58 | 58 | SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
59 | 59 | SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
60 | 60 | SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
61 | 61 | |
|
62 | 62 | SM_correlation_start : OUT STD_LOGIC; |
|
63 | 63 | SM_correlation_auto : OUT STD_LOGIC; |
|
64 | 64 | SM_correlation_done : IN STD_LOGIC |
|
65 | 65 | ); |
|
66 | 66 | END COMPONENT; |
|
67 | 67 | |
|
68 | 68 | |
|
69 | 69 | ----------------------------------------------------------------------------- |
|
70 | 70 | COMPONENT lpp_lfr_ms |
|
71 | 71 | GENERIC ( |
|
72 | 72 | Mem_use : INTEGER |
|
73 | 73 | ); |
|
74 | 74 | PORT ( |
|
75 | 75 | clk : IN STD_LOGIC; |
|
76 | 76 | rstn : IN STD_LOGIC; |
|
77 | 77 | |
|
78 | 78 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
79 | 79 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
80 | 80 | |
|
81 | 81 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
82 | 82 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
83 | 83 | |
|
84 | 84 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
85 | 85 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
86 | 86 | |
|
87 | 87 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | 88 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
89 | 89 | |
|
90 | 90 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
91 | 91 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
92 | 92 | dma_valid : OUT STD_LOGIC; |
|
93 | 93 | dma_valid_burst : OUT STD_LOGIC; |
|
94 | 94 | dma_ren : IN STD_LOGIC; |
|
95 | 95 | dma_done : IN STD_LOGIC; |
|
96 | 96 | |
|
97 | 97 | ready_matrix_f0 : OUT STD_LOGIC; |
|
98 | 98 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
99 | 99 | ready_matrix_f1 : OUT STD_LOGIC; |
|
100 | 100 | ready_matrix_f2 : OUT STD_LOGIC; |
|
101 | 101 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
102 | 102 | error_bad_component_error : OUT STD_LOGIC; |
|
103 | 103 | error_buffer_full : OUT STD_LOGIC; |
|
104 | 104 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
105 | 105 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
106 | -- | |
|
107 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
108 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
109 | ------------------------------------------------------------------------- | |
|
106 | 110 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
107 | 111 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
108 | 112 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
109 | 113 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
110 | 114 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
111 | 115 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
112 | 116 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
113 | 117 | config_active_interruption_onError : IN STD_LOGIC; |
|
114 | 118 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
115 | 119 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
116 | 120 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
117 | 121 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
118 | 122 | |
|
119 | 123 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
120 | 124 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
121 | 125 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
122 | 126 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)); |
|
123 | 127 | END COMPONENT; |
|
124 | 128 | |
|
125 | 129 | COMPONENT lpp_lfr_ms_fsmdma |
|
126 | 130 | PORT ( |
|
127 | 131 | HCLK : IN STD_ULOGIC; |
|
128 | 132 | HRESETn : IN STD_ULOGIC; |
|
129 | 133 | fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
130 | 134 | fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
131 | 135 | fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
132 | 136 | fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
133 | 137 | fifo_empty : IN STD_LOGIC; |
|
134 | 138 | fifo_ren : OUT STD_LOGIC; |
|
135 | 139 | --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
136 | 140 | --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
137 | 141 | --fifo_empty : IN STD_LOGIC; |
|
138 | 142 | --fifo_ren : OUT STD_LOGIC; |
|
139 | 143 | --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
140 | 144 | --header_val : IN STD_LOGIC; |
|
141 | 145 | --header_ack : OUT STD_LOGIC; |
|
142 | 146 | dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
143 | 147 | dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
144 | 148 | dma_valid : OUT STD_LOGIC; |
|
145 | 149 | dma_valid_burst : OUT STD_LOGIC; |
|
146 | 150 | dma_ren : IN STD_LOGIC; |
|
147 | 151 | dma_done : IN STD_LOGIC; |
|
148 | 152 | ready_matrix_f0 : OUT STD_LOGIC; |
|
149 | 153 | -- ready_matrix_f0_1 : OUT STD_LOGIC; |
|
150 | 154 | ready_matrix_f1 : OUT STD_LOGIC; |
|
151 | 155 | ready_matrix_f2 : OUT STD_LOGIC; |
|
152 | 156 | -- error_anticipating_empty_fifo : OUT STD_LOGIC; |
|
153 | 157 | error_bad_component_error : OUT STD_LOGIC; |
|
154 | 158 | error_buffer_full : OUT STD_LOGIC; |
|
155 | 159 | debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
156 | 160 | status_ready_matrix_f0 : IN STD_LOGIC; |
|
157 | 161 | -- status_ready_matrix_f0_1 : IN STD_LOGIC; |
|
158 | 162 | status_ready_matrix_f1 : IN STD_LOGIC; |
|
159 | 163 | status_ready_matrix_f2 : IN STD_LOGIC; |
|
160 | 164 | -- status_error_anticipating_empty_fifo : IN STD_LOGIC; |
|
161 | 165 | -- status_error_bad_component_error : IN STD_LOGIC; |
|
162 | 166 | config_active_interruption_onNewMatrix : IN STD_LOGIC; |
|
163 | 167 | config_active_interruption_onError : IN STD_LOGIC; |
|
164 | 168 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
165 | 169 | -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
166 | 170 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
167 | 171 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
168 | 172 | |
|
169 | 173 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
170 | 174 | -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
171 | 175 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
172 | 176 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) |
|
173 | 177 | ); |
|
174 | 178 | END COMPONENT; |
|
175 | 179 | |
|
176 | 180 | COMPONENT lpp_lfr_ms_FFT |
|
177 | 181 | PORT ( |
|
178 | 182 | clk : IN STD_LOGIC; |
|
179 | 183 | rstn : IN STD_LOGIC; |
|
180 | 184 | sample_valid : IN STD_LOGIC; |
|
181 | 185 | fft_read : IN STD_LOGIC; |
|
182 | 186 | sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
183 | 187 | sample_load : OUT STD_LOGIC; |
|
184 | 188 | fft_pong : OUT STD_LOGIC; |
|
185 | 189 | fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
186 | 190 | fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
187 | 191 | fft_data_valid : OUT STD_LOGIC; |
|
188 | 192 | fft_ready : OUT STD_LOGIC); |
|
189 | 193 | END COMPONENT; |
|
190 | 194 | |
|
191 | 195 | COMPONENT lpp_lfr_filter |
|
192 | 196 | GENERIC ( |
|
193 | 197 | Mem_use : INTEGER); |
|
194 | 198 | PORT ( |
|
195 | 199 | sample : IN Samples(7 DOWNTO 0); |
|
196 | 200 | sample_val : IN STD_LOGIC; |
|
197 | 201 | clk : IN STD_LOGIC; |
|
198 | 202 | rstn : IN STD_LOGIC; |
|
199 | 203 | data_shaping_SP0 : IN STD_LOGIC; |
|
200 | 204 | data_shaping_SP1 : IN STD_LOGIC; |
|
201 | 205 | data_shaping_R0 : IN STD_LOGIC; |
|
202 | 206 | data_shaping_R1 : IN STD_LOGIC; |
|
203 | 207 | sample_f0_val : OUT STD_LOGIC; |
|
204 | 208 | sample_f1_val : OUT STD_LOGIC; |
|
205 | 209 | sample_f2_val : OUT STD_LOGIC; |
|
206 | 210 | sample_f3_val : OUT STD_LOGIC; |
|
207 | 211 | sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
208 | 212 | sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
209 | 213 | sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
|
210 | 214 | sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); |
|
211 | 215 | END COMPONENT; |
|
212 | 216 | |
|
213 | 217 | COMPONENT lpp_lfr |
|
214 | 218 | GENERIC ( |
|
215 | 219 | Mem_use : INTEGER; |
|
216 | 220 | nb_data_by_buffer_size : INTEGER; |
|
217 | 221 | nb_word_by_buffer_size : INTEGER; |
|
218 | 222 | nb_snapshot_param_size : INTEGER; |
|
219 | 223 | delta_vector_size : INTEGER; |
|
220 | 224 | delta_vector_size_f0_2 : INTEGER; |
|
221 | 225 | pindex : INTEGER; |
|
222 | 226 | paddr : INTEGER; |
|
223 | 227 | pmask : INTEGER; |
|
224 | 228 | pirq_ms : INTEGER; |
|
225 | 229 | pirq_wfp : INTEGER; |
|
226 | 230 | hindex : INTEGER; |
|
227 | 231 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) |
|
228 | 232 | ); |
|
229 | 233 | PORT ( |
|
230 | 234 | clk : IN STD_LOGIC; |
|
231 | 235 | rstn : IN STD_LOGIC; |
|
232 | 236 | sample_B : IN Samples(2 DOWNTO 0); |
|
233 | 237 | sample_E : IN Samples(4 DOWNTO 0); |
|
234 | 238 | sample_val : IN STD_LOGIC; |
|
235 | 239 | apbi : IN apb_slv_in_type; |
|
236 | 240 | apbo : OUT apb_slv_out_type; |
|
237 | 241 | ahbi : IN AHB_Mst_In_Type; |
|
238 | 242 | ahbo : OUT AHB_Mst_Out_Type; |
|
239 | 243 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
240 | 244 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
241 | 245 | data_shaping_BW : OUT STD_LOGIC; |
|
246 | -- | |
|
247 | observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
248 | observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0); | |
|
242 | 249 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
243 | 250 | ); |
|
244 | 251 | END COMPONENT; |
|
245 | 252 | |
|
246 | 253 | ----------------------------------------------------------------------------- |
|
247 | 254 | -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System) |
|
248 | 255 | ----------------------------------------------------------------------------- |
|
249 | 256 | COMPONENT lpp_lfr_WFP_nMS |
|
250 | 257 | GENERIC ( |
|
251 | 258 | Mem_use : INTEGER; |
|
252 | 259 | nb_data_by_buffer_size : INTEGER; |
|
253 | 260 | nb_word_by_buffer_size : INTEGER; |
|
254 | 261 | nb_snapshot_param_size : INTEGER; |
|
255 | 262 | delta_vector_size : INTEGER; |
|
256 | 263 | delta_vector_size_f0_2 : INTEGER; |
|
257 | 264 | pindex : INTEGER; |
|
258 | 265 | paddr : INTEGER; |
|
259 | 266 | pmask : INTEGER; |
|
260 | 267 | pirq_ms : INTEGER; |
|
261 | 268 | pirq_wfp : INTEGER; |
|
262 | 269 | hindex : INTEGER; |
|
263 | 270 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
264 | 271 | PORT ( |
|
265 | 272 | clk : IN STD_LOGIC; |
|
266 | 273 | rstn : IN STD_LOGIC; |
|
267 | 274 | sample_B : IN Samples(2 DOWNTO 0); |
|
268 | 275 | sample_E : IN Samples(4 DOWNTO 0); |
|
269 | 276 | sample_val : IN STD_LOGIC; |
|
270 | 277 | apbi : IN apb_slv_in_type; |
|
271 | 278 | apbo : OUT apb_slv_out_type; |
|
272 | 279 | ahbi : IN AHB_Mst_In_Type; |
|
273 | 280 | ahbo : OUT AHB_Mst_Out_Type; |
|
274 | 281 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
275 | 282 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
276 | 283 | data_shaping_BW : OUT STD_LOGIC; |
|
277 | 284 | observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
278 | 285 | END COMPONENT; |
|
279 | 286 | ----------------------------------------------------------------------------- |
|
280 | 287 | COMPONENT lpp_lfr_apbreg |
|
281 | 288 | GENERIC ( |
|
282 | 289 | nb_data_by_buffer_size : INTEGER; |
|
283 | 290 | nb_word_by_buffer_size : INTEGER; |
|
284 | 291 | nb_snapshot_param_size : INTEGER; |
|
285 | 292 | delta_vector_size : INTEGER; |
|
286 | 293 | delta_vector_size_f0_2 : INTEGER; |
|
287 | 294 | pindex : INTEGER; |
|
288 | 295 | paddr : INTEGER; |
|
289 | 296 | pmask : INTEGER; |
|
290 | 297 | pirq_ms : INTEGER; |
|
291 | 298 | pirq_wfp : INTEGER; |
|
292 | 299 | top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); |
|
293 | 300 | PORT ( |
|
294 | 301 | HCLK : IN STD_ULOGIC; |
|
295 | 302 | HRESETn : IN STD_ULOGIC; |
|
296 | 303 | apbi : IN apb_slv_in_type; |
|
297 | 304 | apbo : OUT apb_slv_out_type; |
|
298 | 305 | run_ms : OUT STD_LOGIC; |
|
299 | 306 | ready_matrix_f0 : IN STD_LOGIC; |
|
300 | 307 | ready_matrix_f1 : IN STD_LOGIC; |
|
301 | 308 | ready_matrix_f2 : IN STD_LOGIC; |
|
302 | 309 | error_bad_component_error : IN STD_LOGIC; |
|
303 | 310 | error_buffer_full : in STD_LOGIC; |
|
304 | 311 | error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
305 | 312 | --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
306 | 313 | status_ready_matrix_f0 : OUT STD_LOGIC; |
|
307 | 314 | status_ready_matrix_f1 : OUT STD_LOGIC; |
|
308 | 315 | status_ready_matrix_f2 : OUT STD_LOGIC; |
|
309 | 316 | config_active_interruption_onNewMatrix : OUT STD_LOGIC; |
|
310 | 317 | config_active_interruption_onError : OUT STD_LOGIC; |
|
311 | 318 | addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
312 | 319 | -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
313 | 320 | addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
314 | 321 | addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
315 | 322 | matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
316 | 323 | -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
317 | 324 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
318 | 325 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
319 | 326 | status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
320 | 327 | status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
321 | 328 | status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
322 | 329 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
323 | 330 | data_shaping_BW : OUT STD_LOGIC; |
|
324 | 331 | data_shaping_SP0 : OUT STD_LOGIC; |
|
325 | 332 | data_shaping_SP1 : OUT STD_LOGIC; |
|
326 | 333 | data_shaping_R0 : OUT STD_LOGIC; |
|
327 | 334 | data_shaping_R1 : OUT STD_LOGIC; |
|
328 | 335 | delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
329 | 336 | delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
330 | 337 | delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
331 | 338 | delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
332 | 339 | delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
333 | 340 | nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
334 | 341 | nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
335 | 342 | nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
336 | 343 | enable_f0 : OUT STD_LOGIC; |
|
337 | 344 | enable_f1 : OUT STD_LOGIC; |
|
338 | 345 | enable_f2 : OUT STD_LOGIC; |
|
339 | 346 | enable_f3 : OUT STD_LOGIC; |
|
340 | 347 | burst_f0 : OUT STD_LOGIC; |
|
341 | 348 | burst_f1 : OUT STD_LOGIC; |
|
342 | 349 | burst_f2 : OUT STD_LOGIC; |
|
343 | 350 | run : OUT STD_LOGIC; |
|
344 | 351 | addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
345 | 352 | addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
346 | 353 | addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
347 | 354 | addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
348 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0) | |
|
355 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
|
356 | ||
|
357 | debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
|
358 | ||
|
349 | 359 |
|
|
350 | 360 | END COMPONENT; |
|
351 | 361 | |
|
352 | 362 | |
|
353 | 363 | |
|
354 | 364 | COMPONENT lpp_top_ms |
|
355 | 365 | GENERIC ( |
|
356 | 366 | Mem_use : INTEGER; |
|
357 | 367 | nb_burst_available_size : INTEGER; |
|
358 | 368 | nb_snapshot_param_size : INTEGER; |
|
359 | 369 | delta_snapshot_size : INTEGER; |
|
360 | 370 | delta_f2_f0_size : INTEGER; |
|
361 | 371 | delta_f2_f1_size : INTEGER; |
|
362 | 372 | pindex : INTEGER; |
|
363 | 373 | paddr : INTEGER; |
|
364 | 374 | pmask : INTEGER; |
|
365 | 375 | pirq_ms : INTEGER; |
|
366 | 376 | pirq_wfp : INTEGER; |
|
367 | 377 | hindex_wfp : INTEGER; |
|
368 | 378 | hindex_ms : INTEGER); |
|
369 | 379 | PORT ( |
|
370 | 380 | clk : IN STD_LOGIC; |
|
371 | 381 | rstn : IN STD_LOGIC; |
|
372 | 382 | sample_B : IN Samples14v(2 DOWNTO 0); |
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373 | 383 | sample_E : IN Samples14v(4 DOWNTO 0); |
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374 | 384 | sample_val : IN STD_LOGIC; |
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375 | 385 | apbi : IN apb_slv_in_type; |
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376 | 386 | apbo : OUT apb_slv_out_type; |
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377 | 387 | ahbi_ms : IN AHB_Mst_In_Type; |
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378 | 388 | ahbo_ms : OUT AHB_Mst_Out_Type; |
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379 | 389 | data_shaping_BW : OUT STD_LOGIC; |
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380 | 390 | matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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381 | 391 | matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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382 | 392 | matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0); |
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383 | 393 | matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0) |
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384 | 394 | |
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385 | 395 | ); |
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386 | 396 | END COMPONENT; |
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387 | 397 | |
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388 | 398 | COMPONENT lpp_apbreg_ms_pointer |
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389 | 399 | PORT ( |
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390 | 400 | clk : IN STD_LOGIC; |
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391 | 401 | rstn : IN STD_LOGIC; |
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392 | 402 | reg0_status_ready_matrix : IN STD_LOGIC; |
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393 | 403 | reg0_ready_matrix : OUT STD_LOGIC; |
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394 | 404 | reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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395 | 405 | reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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396 | 406 | reg1_status_ready_matrix : IN STD_LOGIC; |
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397 | 407 | reg1_ready_matrix : OUT STD_LOGIC; |
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398 | 408 | reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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399 | 409 | reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); |
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400 | 410 | ready_matrix : IN STD_LOGIC; |
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401 | 411 | status_ready_matrix : OUT STD_LOGIC; |
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402 | 412 | addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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403 | 413 | matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0)); |
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404 | 414 | END COMPONENT; |
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405 | 415 | |
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406 | 416 | END lpp_lfr_pkg; |
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