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LFR-EM and MINI-LFR x.1.64
pellion -
r550:8c147122ecd4 (MINI-LFR) WFP_MS-0-1-64 (LFR-EM) WFP_MS_1-1-64 JC
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 188 SIGNAL rstn_50 : STD_LOGIC;
189 189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 191 SIGNAL rstn_50_d3 : STD_LOGIC;
192 192
193 193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 195
196 196 --
197 197 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 198
199 199 --
200 200 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
202 202
203 203 BEGIN -- beh
204 204
205 205 -----------------------------------------------------------------------------
206 206 -- CLK
207 207 -----------------------------------------------------------------------------
208 208
209 209 --PROCESS(clk_50)
210 210 --BEGIN
211 211 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 212 -- clk_50_s <= NOT clk_50_s;
213 213 -- END IF;
214 214 --END PROCESS;
215 215
216 216 --PROCESS(clk_50_s)
217 217 --BEGIN
218 218 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 219 -- clk_25 <= NOT clk_25;
220 220 -- END IF;
221 221 --END PROCESS;
222 222
223 223 --PROCESS(clk_49)
224 224 --BEGIN
225 225 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 226 -- clk_24 <= NOT clk_24;
227 227 -- END IF;
228 228 --END PROCESS;
229 229
230 230 --PROCESS(clk_25)
231 231 --BEGIN
232 232 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 233 -- rstn_25 <= reset;
234 234 -- END IF;
235 235 --END PROCESS;
236 236
237 237 PROCESS (clk_50, reset)
238 238 BEGIN -- PROCESS
239 239 IF reset = '0' THEN -- asynchronous reset (active low)
240 240 clk_50_s <= '0';
241 241 rstn_50 <= '0';
242 242 rstn_50_d1 <= '0';
243 243 rstn_50_d2 <= '0';
244 244 rstn_50_d3 <= '0';
245 245
246 246 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 247 clk_50_s <= NOT clk_50_s;
248 248 rstn_50_d1 <= '1';
249 249 rstn_50_d2 <= rstn_50_d1;
250 250 rstn_50_d3 <= rstn_50_d2;
251 251 rstn_50 <= rstn_50_d3;
252 252 END IF;
253 253 END PROCESS;
254 254
255 255 PROCESS (clk_50_s, rstn_50)
256 256 BEGIN -- PROCESS
257 257 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 258 clk_25 <= '0';
259 259 rstn_25 <= '0';
260 260 rstn_25_d1 <= '0';
261 261 rstn_25_d2 <= '0';
262 262 rstn_25_d3 <= '0';
263 263 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 264 clk_25 <= NOT clk_25;
265 265 rstn_25_d1 <= '1';
266 266 rstn_25_d2 <= rstn_25_d1;
267 267 rstn_25_d3 <= rstn_25_d2;
268 268 rstn_25 <= rstn_25_d3;
269 269 END IF;
270 270 END PROCESS;
271 271
272 272 PROCESS (clk_49, reset)
273 273 BEGIN -- PROCESS
274 274 IF reset = '0' THEN -- asynchronous reset (active low)
275 275 clk_24 <= '0';
276 276 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 277 clk_24 <= NOT clk_24;
278 278 END IF;
279 279 END PROCESS;
280 280
281 281 -----------------------------------------------------------------------------
282 282
283 283 PROCESS (clk_25, rstn_25)
284 284 BEGIN -- PROCESS
285 285 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 286 LED0 <= '0';
287 287 LED1 <= '0';
288 288 LED2 <= '0';
289 289 --IO1 <= '0';
290 290 --IO2 <= '1';
291 291 --IO3 <= '0';
292 292 --IO4 <= '0';
293 293 --IO5 <= '0';
294 294 --IO6 <= '0';
295 295 --IO7 <= '0';
296 296 --IO8 <= '0';
297 297 --IO9 <= '0';
298 298 --IO10 <= '0';
299 299 --IO11 <= '0';
300 300 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 301 LED0 <= '0';
302 302 LED1 <= '1';
303 303 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 304 --IO1 <= '1';
305 305 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 306 --IO3 <= ADC_SDO(0);
307 307 --IO4 <= ADC_SDO(1);
308 308 --IO5 <= ADC_SDO(2);
309 309 --IO6 <= ADC_SDO(3);
310 310 --IO7 <= ADC_SDO(4);
311 311 --IO8 <= ADC_SDO(5);
312 312 --IO9 <= ADC_SDO(6);
313 313 --IO10 <= ADC_SDO(7);
314 314 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 315 END IF;
316 316 END PROCESS;
317 317
318 318 PROCESS (clk_24, rstn_25)
319 319 BEGIN -- PROCESS
320 320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
321 321 I00_s <= '0';
322 322 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 323 I00_s <= NOT I00_s;
324 324 END IF;
325 325 END PROCESS;
326 326 -- IO0 <= I00_s;
327 327
328 328 --UARTs
329 329 nCTS1 <= '1';
330 330 nCTS2 <= '1';
331 331 nDCD2 <= '1';
332 332
333 333 --
334 334
335 335 leon3_soc_1 : leon3_soc
336 336 GENERIC MAP (
337 337 fabtech => apa3e,
338 338 memtech => apa3e,
339 339 padtech => inferred,
340 340 clktech => inferred,
341 341 disas => 0,
342 342 dbguart => 0,
343 343 pclow => 2,
344 344 clk_freq => 25000,
345 345 IS_RADHARD => 0,
346 346 NB_CPU => 1,
347 347 ENABLE_FPU => 1,
348 348 FPU_NETLIST => 0,
349 349 ENABLE_DSU => 1,
350 350 ENABLE_AHB_UART => 1,
351 351 ENABLE_APB_UART => 1,
352 352 ENABLE_IRQMP => 1,
353 353 ENABLE_GPT => 1,
354 354 NB_AHB_MASTER => NB_AHB_MASTER,
355 355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 356 NB_APB_SLAVE => NB_APB_SLAVE,
357 357 ADDRESS_SIZE => 20,
358 358 USES_IAP_MEMCTRLR => 0)
359 359 PORT MAP (
360 360 clk => clk_25,
361 361 reset => rstn_25,
362 362 errorn => errorn,
363 363 ahbrxd => TXD1,
364 364 ahbtxd => RXD1,
365 365 urxd1 => TXD2,
366 366 utxd1 => RXD2,
367 367 address => SRAM_A,
368 368 data => SRAM_DQ,
369 369 nSRAM_BE0 => SRAM_nBE(0),
370 370 nSRAM_BE1 => SRAM_nBE(1),
371 371 nSRAM_BE2 => SRAM_nBE(2),
372 372 nSRAM_BE3 => SRAM_nBE(3),
373 373 nSRAM_WE => SRAM_nWE,
374 374 nSRAM_CE => SRAM_CE_s,
375 375 nSRAM_OE => SRAM_nOE,
376 376 nSRAM_READY => '0',
377 377 SRAM_MBE => OPEN,
378 378 apbi_ext => apbi_ext,
379 379 apbo_ext => apbo_ext,
380 380 ahbi_s_ext => ahbi_s_ext,
381 381 ahbo_s_ext => ahbo_s_ext,
382 382 ahbi_m_ext => ahbi_m_ext,
383 383 ahbo_m_ext => ahbo_m_ext);
384 384
385 385 SRAM_CE <= SRAM_CE_s(0);
386 386 -------------------------------------------------------------------------------
387 387 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 388 -------------------------------------------------------------------------------
389 389 apb_lfr_management_1 : apb_lfr_management
390 390 GENERIC MAP (
391 391 tech => apa3e,
392 392 pindex => 6,
393 393 paddr => 6,
394 394 pmask => 16#fff#,
395 395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 396 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 397 PORT MAP (
398 398 clk25MHz => clk_25,
399 399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 400 resetn => rstn_25,
401 401 grspw_tick => swno.tickout,
402 402 apbi => apbi_ext,
403 403 apbo => apbo_ext(6),
404 404 HK_sample => sample_hk,
405 405 HK_val => sample_val,
406 406 HK_sel => HK_SEL,
407 407 DAC_SDO => OPEN,
408 408 DAC_SCK => OPEN,
409 409 DAC_SYNC => OPEN,
410 410 DAC_CAL_EN => OPEN,
411 411 coarse_time => coarse_time,
412 412 fine_time => fine_time,
413 413 LFR_soft_rstn => LFR_soft_rstn
414 414 );
415 415
416 416 -----------------------------------------------------------------------
417 417 --- SpaceWire --------------------------------------------------------
418 418 -----------------------------------------------------------------------
419 419
420 420 SPW_EN <= '1';
421 421
422 422 spw_clk <= clk_50_s;
423 423 spw_rxtxclk <= spw_clk;
424 424 spw_rxclkn <= NOT spw_rxtxclk;
425 425
426 426 -- PADS for SPW1
427 427 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
428 428 PORT MAP (SPW_NOM_DIN, dtmp(0));
429 429 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
430 430 PORT MAP (SPW_NOM_SIN, stmp(0));
431 431 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
432 432 PORT MAP (SPW_NOM_DOUT, swno.d(0));
433 433 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
434 434 PORT MAP (SPW_NOM_SOUT, swno.s(0));
435 435 -- PADS FOR SPW2
436 436 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
437 437 PORT MAP (SPW_RED_SIN, dtmp(1));
438 438 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 439 PORT MAP (SPW_RED_DIN, stmp(1));
440 440 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
441 441 PORT MAP (SPW_RED_DOUT, swno.d(1));
442 442 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
443 443 PORT MAP (SPW_RED_SOUT, swno.s(1));
444 444
445 445 -- GRSPW PHY
446 446 --spw1_input: if CFG_SPW_GRSPW = 1 generate
447 447 spw_inputloop : FOR j IN 0 TO 1 GENERATE
448 448 spw_phy0 : grspw_phy
449 449 GENERIC MAP(
450 450 tech => apa3e,
451 451 rxclkbuftype => 1,
452 452 scantest => 0)
453 453 PORT MAP(
454 454 rxrst => swno.rxrst,
455 455 di => dtmp(j),
456 456 si => stmp(j),
457 457 rxclko => spw_rxclk(j),
458 458 do => swni.d(j),
459 459 ndo => swni.nd(j*5+4 DOWNTO j*5),
460 460 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
461 461 END GENERATE spw_inputloop;
462 462
463 463 swni.rmapnodeaddr <= (OTHERS => '0');
464 464
465 465 -- SPW core
466 466 sw0 : grspwm GENERIC MAP(
467 467 tech => apa3e,
468 468 hindex => 1,
469 469 pindex => 5,
470 470 paddr => 5,
471 471 pirq => 11,
472 472 sysfreq => 25000, -- CPU_FREQ
473 473 rmap => 1,
474 474 rmapcrc => 1,
475 475 fifosize1 => 16,
476 476 fifosize2 => 16,
477 477 rxclkbuftype => 1,
478 478 rxunaligned => 0,
479 479 rmapbufs => 4,
480 480 ft => 0,
481 481 netlist => 0,
482 482 ports => 2,
483 483 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
484 484 memtech => apa3e,
485 485 destkey => 2,
486 486 spwcore => 1
487 487 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
488 488 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
489 489 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
490 490 )
491 491 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
492 492 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
493 493 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
494 494 swni, swno);
495 495
496 496 swni.tickin <= '0';
497 497 swni.rmapen <= '1';
498 498 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
499 499 swni.tickinraw <= '0';
500 500 swni.timein <= (OTHERS => '0');
501 501 swni.dcrstval <= (OTHERS => '0');
502 502 swni.timerrstval <= (OTHERS => '0');
503 503
504 504 -------------------------------------------------------------------------------
505 505 -- LFR ------------------------------------------------------------------------
506 506 -------------------------------------------------------------------------------
507 507
508 508
509 509 LFR_rstn <= LFR_soft_rstn AND rstn_25;
510 510 --LFR_rstn <= rstn_25;
511 511
512 512 lpp_lfr_1 : lpp_lfr
513 513 GENERIC MAP (
514 514 Mem_use => use_RAM,
515 515 nb_data_by_buffer_size => 32,
516 516 nb_snapshot_param_size => 32,
517 517 delta_vector_size => 32,
518 518 delta_vector_size_f0_2 => 7, -- log2(96)
519 519 pindex => 15,
520 520 paddr => 15,
521 521 pmask => 16#fff#,
522 522 pirq_ms => 6,
523 523 pirq_wfp => 14,
524 524 hindex => 2,
525 top_lfr_version => X"00013F") -- aa.bb.cc version
525 top_lfr_version => X"000140") -- aa.bb.cc version
526 526 PORT MAP (
527 527 clk => clk_25,
528 528 rstn => LFR_rstn,
529 529 sample_B => sample_s(2 DOWNTO 0),
530 530 sample_E => sample_s(7 DOWNTO 3),
531 531 sample_val => sample_val,
532 532 apbi => apbi_ext,
533 533 apbo => apbo_ext(15),
534 534 ahbi => ahbi_m_ext,
535 535 ahbo => ahbo_m_ext(2),
536 536 coarse_time => coarse_time,
537 537 fine_time => fine_time,
538 538 data_shaping_BW => bias_fail_sw_sig,
539 539 debug_vector => lfr_debug_vector,
540 540 debug_vector_ms => lfr_debug_vector_ms
541 541 );
542 542
543 543 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
544 544 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
545 545 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
546 546 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
547 547 IO0 <= rstn_25;
548 548 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
549 549 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
550 550 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
551 551 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
552 552 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
553 553 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
554 554 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
555 555
556 556 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
557 557 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
558 558 END GENERATE all_sample;
559 559
560 560 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
561 561 GENERIC MAP(
562 562 ChannelCount => 8,
563 563 SampleNbBits => 14,
564 564 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
565 565 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
566 566 PORT MAP (
567 567 -- CONV
568 568 cnv_clk => clk_24,
569 569 cnv_rstn => rstn_25,
570 570 cnv => ADC_nCS_sig,
571 571 -- DATA
572 572 clk => clk_25,
573 573 rstn => rstn_25,
574 574 sck => ADC_CLK_sig,
575 575 sdo => ADC_SDO_sig,
576 576 -- SAMPLE
577 577 sample => sample,
578 578 sample_val => sample_val);
579 579
580 580 --IO10 <= ADC_SDO_sig(5);
581 581 --IO9 <= ADC_SDO_sig(4);
582 582 --IO8 <= ADC_SDO_sig(3);
583 583
584 584 ADC_nCS <= ADC_nCS_sig;
585 585 ADC_CLK <= ADC_CLK_sig;
586 586 ADC_SDO_sig <= ADC_SDO;
587 587
588 588 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
589 589 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 590 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 591 (OTHERS => '0');
592 592
593 593
594 594 ----------------------------------------------------------------------
595 595 --- GPIO -----------------------------------------------------------
596 596 ----------------------------------------------------------------------
597 597
598 598 grgpio0 : grgpio
599 599 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
600 600 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
601 601
602 602 gpioi.sig_en <= (OTHERS => '0');
603 603 gpioi.sig_in <= (OTHERS => '0');
604 604 gpioi.din <= (OTHERS => '0');
605 605 --pio_pad_0 : iopad
606 606 -- GENERIC MAP (tech => CFG_PADTECH)
607 607 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
608 608 --pio_pad_1 : iopad
609 609 -- GENERIC MAP (tech => CFG_PADTECH)
610 610 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
611 611 --pio_pad_2 : iopad
612 612 -- GENERIC MAP (tech => CFG_PADTECH)
613 613 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
614 614 --pio_pad_3 : iopad
615 615 -- GENERIC MAP (tech => CFG_PADTECH)
616 616 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
617 617 --pio_pad_4 : iopad
618 618 -- GENERIC MAP (tech => CFG_PADTECH)
619 619 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
620 620 --pio_pad_5 : iopad
621 621 -- GENERIC MAP (tech => CFG_PADTECH)
622 622 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
623 623 --pio_pad_6 : iopad
624 624 -- GENERIC MAP (tech => CFG_PADTECH)
625 625 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
626 626 --pio_pad_7 : iopad
627 627 -- GENERIC MAP (tech => CFG_PADTECH)
628 628 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
629 629
630 630 PROCESS (clk_25, rstn_25)
631 631 BEGIN -- PROCESS
632 632 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
633 633 -- --IO0 <= '0';
634 634 -- IO1 <= '0';
635 635 -- IO2 <= '0';
636 636 -- IO3 <= '0';
637 637 -- IO4 <= '0';
638 638 -- IO5 <= '0';
639 639 -- IO6 <= '0';
640 640 -- IO7 <= '0';
641 641 IO8 <= '0';
642 642 IO9 <= '0';
643 643 IO10 <= '0';
644 644 IO11 <= '0';
645 645 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
646 646 CASE gpioo.dout(2 DOWNTO 0) IS
647 647 WHEN "011" =>
648 648 -- --IO0 <= observation_reg(0 );
649 649 -- IO1 <= observation_reg(1 );
650 650 -- IO2 <= observation_reg(2 );
651 651 -- IO3 <= observation_reg(3 );
652 652 -- IO4 <= observation_reg(4 );
653 653 -- IO5 <= observation_reg(5 );
654 654 -- IO6 <= observation_reg(6 );
655 655 -- IO7 <= observation_reg(7 );
656 656 IO8 <= observation_reg(8);
657 657 IO9 <= observation_reg(9);
658 658 IO10 <= observation_reg(10);
659 659 IO11 <= observation_reg(11);
660 660 WHEN "001" =>
661 661 -- --IO0 <= observation_reg(0 + 12);
662 662 -- IO1 <= observation_reg(1 + 12);
663 663 -- IO2 <= observation_reg(2 + 12);
664 664 -- IO3 <= observation_reg(3 + 12);
665 665 -- IO4 <= observation_reg(4 + 12);
666 666 -- IO5 <= observation_reg(5 + 12);
667 667 -- IO6 <= observation_reg(6 + 12);
668 668 -- IO7 <= observation_reg(7 + 12);
669 669 IO8 <= observation_reg(8 + 12);
670 670 IO9 <= observation_reg(9 + 12);
671 671 IO10 <= observation_reg(10 + 12);
672 672 IO11 <= observation_reg(11 + 12);
673 673 WHEN "010" =>
674 674 -- --IO0 <= observation_reg(0 + 12 + 12);
675 675 -- IO1 <= observation_reg(1 + 12 + 12);
676 676 -- IO2 <= observation_reg(2 + 12 + 12);
677 677 -- IO3 <= observation_reg(3 + 12 + 12);
678 678 -- IO4 <= observation_reg(4 + 12 + 12);
679 679 -- IO5 <= observation_reg(5 + 12 + 12);
680 680 -- IO6 <= observation_reg(6 + 12 + 12);
681 681 -- IO7 <= observation_reg(7 + 12 + 12);
682 682 IO8 <= '0';
683 683 IO9 <= '0';
684 684 IO10 <= '0';
685 685 IO11 <= '0';
686 686 WHEN "000" =>
687 687 -- --IO0 <= observation_vector_0(0 );
688 688 -- IO1 <= observation_vector_0(1 );
689 689 -- IO2 <= observation_vector_0(2 );
690 690 -- IO3 <= observation_vector_0(3 );
691 691 -- IO4 <= observation_vector_0(4 );
692 692 -- IO5 <= observation_vector_0(5 );
693 693 -- IO6 <= observation_vector_0(6 );
694 694 -- IO7 <= observation_vector_0(7 );
695 695 IO8 <= observation_vector_0(8);
696 696 IO9 <= observation_vector_0(9);
697 697 IO10 <= observation_vector_0(10);
698 698 IO11 <= observation_vector_0(11);
699 699 WHEN "100" =>
700 700 -- --IO0 <= observation_vector_1(0 );
701 701 -- IO1 <= observation_vector_1(1 );
702 702 -- IO2 <= observation_vector_1(2 );
703 703 -- IO3 <= observation_vector_1(3 );
704 704 -- IO4 <= observation_vector_1(4 );
705 705 -- IO5 <= observation_vector_1(5 );
706 706 -- IO6 <= observation_vector_1(6 );
707 707 -- IO7 <= observation_vector_1(7 );
708 708 IO8 <= observation_vector_1(8);
709 709 IO9 <= observation_vector_1(9);
710 710 IO10 <= observation_vector_1(10);
711 711 IO11 <= observation_vector_1(11);
712 712 WHEN OTHERS => NULL;
713 713 END CASE;
714 714
715 715 END IF;
716 716 END PROCESS;
717 717 -----------------------------------------------------------------------------
718 718 --
719 719 -----------------------------------------------------------------------------
720 720 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
721 721 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
722 722 apbo_ext(I) <= apb_none;
723 723 END GENERATE apbo_ext_not_used;
724 724 END GENERATE all_apbo_ext;
725 725
726 726
727 727 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
728 728 ahbo_s_ext(I) <= ahbs_none;
729 729 END GENERATE all_ahbo_ext;
730 730
731 731 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
732 732 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
733 733 ahbo_m_ext(I) <= ahbm_none;
734 734 END GENERATE ahbo_m_ext_not_used;
735 735 END GENERATE all_ahbo_m_ext;
736 736
737 737 END beh;
Show file before | Show file after | Hide comments
@@ -1,53 +1,52
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 21 CLEAN=soft-clean
22 22
23 23 TECHLIBS = proasic3e
24 24
25 25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 26 tmtc openchip hynix ihp gleichmann micron usbhc
27 27
28 28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 30 ./amba_lcd_16x2_ctrlr \
31 31 ./general_purpose/lpp_AMR \
32 32 ./general_purpose/lpp_balise \
33 33 ./general_purpose/lpp_delay \
34 34 ./lpp_bootloader \
35 35 ./lpp_uart \
36 36 ./lpp_usb \
37 37 ./dsp/lpp_fft_rtax \
38 38 ./lpp_sim/CY7C1061DV33 \
39 39
40 40 FILESKIP =i2cmst.vhd \
41 41 APB_MULTI_DIODE.vhd \
42 42 APB_SIMPLE_DIODE.vhd \
43 43 Top_MatrixSpec.vhd \
44 44 APB_FFT.vhd \
45 45 CoreFFT_simu.vhd \
46 lpp_lfr_apbreg_simu.vhd \
47 MUXN.vhd
46 lpp_lfr_apbreg_simu.vhd
48 47
49 48 include $(GRLIB)/bin/Makefile
50 49 include $(GRLIB)/software/leon3/Makefile
51 50
52 51 ################## project specific targets ##########################
53 52
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