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APB_MATRIX added, first version
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Driver de l'ALU
27
28 entity ALU_Driver is
29 generic(
30 Input_SZ_1 : integer := 16;
31 Input_SZ_2 : integer := 16);
32 port(
33 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
37 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
38 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
39 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
40 Read : out std_logic; --! Flag, opοΏ½rande disponible
41 CTRL : out std_logic_vector(4 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
42 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
43 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second OpοΏ½rande
44 );
45 end ALU_Driver;
46
47 --! @details Les opοΏ½randes sont issue des donnοΏ½es d'entrοΏ½es et associοΏ½ aux bonnes valeurs sur CTRL, les diffοΏ½rentes opοΏ½rations sont effectuοΏ½es
48
49 architecture ar_ALU_Driver of ALU_Driver is
50
51 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
52 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
53 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
54 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
55
56 signal go_st : std_logic;
57 signal Take_reg : std_logic;
58 signal Received_reg : std_logic;
59
60 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
61 signal ect : etat;
62 signal st : etat;
63
64 begin
65 process(clk,reset)
66 begin
67
68 if(reset='0')then
69 ect <= eX;
70 st <= e0;
71 go_st <= '0';
72 CTRL <= "10000";
73 Read <= '0';
74 Valid <= '0';
75 Take_reg <= '0';
76 Received_reg <= '0';
77
78 elsif(clk'event and clk='1')then
79 Take_reg <= Take;
80 Received_reg <= Received;
81
82 case ect is
83 when eX =>
84 go_st <= '0';
85 Read <= '1';
86 CTRL <= "10000";
87 ect <= e0;
88
89 when e0 =>
90 OP1re <= IN1;
91 OP2re <= IN2;
92 if(Take_reg='0' and Take='1')then
93 read <= '0';
94 ect <= e1;
95 end if;
96
97 when e1 =>
98 OP1 <= OP1re;
99 OP2 <= OP2re;
100 CTRL <= "00001";
101 Read <= '1';
102 ect <= idle;
103
104 when idle =>
105 OP1im <= IN1;
106 OP2im <= IN2;
107 CTRL <= "00000";
108 if(Take_reg='1' and Take='0')then
109 Read <= '0';
110 ect <= e2;
111 end if;
112
113 when e2 =>
114 OP1 <= OP1im;
115 OP2 <= OP2im;
116 CTRL <= "00001";
117 ect <= idle2;
118
119 when idle2 =>
120 CTRL <= "00000";
121 go_st <= '1';
122 if(Received_reg='0' and Received='1')then
123 ect <= e3;
124 end if;
125
126 when e3 =>
127 CTRL <= "10000";
128 go_st <= '0';
129 ect <= e4;
130
131 when e4 =>
132 OP1 <= OP1im;
133 OP2 <= OP2re;
134 CTRL <= "00001";
135 ect <= e5;
136
137 when e5 =>
138 OP1 <= OP1re;
139 OP2 <= OP2im;
140 CTRL <= "01001";
141 ect <= idle3;
142
143 when idle3 =>
144 CTRL <= "00000";
145 go_st <= '1';
146 if(Received_reg='1' and Received='0')then
147 ect <= eX;
148 end if;
149 end case;
150
151 case st is
152 when e0 =>
153 if(go_st='1')then
154 st <= e1;
155 end if;
156
157 when e1 =>
158 Valid <= '1';
159 st <= e2;
160
161 when e2 =>
162 if(Received_reg='0' and Received='1')then
163 Valid <= '0';
164 st <= idle;
165 end if;
166
167 when idle =>
168 st <= e3;
169
170 when e3 =>
171 if(go_st='1')then
172 st <= e4;
173 end if;
174
175 when e4 =>
176 Valid <= '1';
177 st <= e5;
178
179 when e5 =>
180 if(Received_reg='1' and Received='0')then
181 Valid <= '0';
182 st <= idle2;
183 end if;
184
185 when idle2 =>
186 st <= e0;
187
188 when others =>
189 null;
190 end case;
191
192 end if;
193 end process;
194
195 end ar_ALU_Driver; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Une ALU : Arithmetic and logical unit, permettant de rοΏ½aliser une ou plusieurs opοΏ½ration
27
28 entity ALU_v2 is
29 generic(
30 Arith_en : integer := 1;
31 Logic_en : integer := 1;
32 Input_SZ_1 : integer := 16;
33 Input_SZ_2 : integer := 9);
34 port(
35 clk : in std_logic; --! Horloge du composant
36 reset : in std_logic; --! Reset general du composant
37 ctrl : in std_logic_vector(4 downto 0); --! Permet de sοΏ½lectionner la/les opοΏ½ration dοΏ½sirοΏ½e
38 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier OpοΏ½rande
39 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second OpοΏ½rande
40 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! RοΏ½sultat de l'opοΏ½ration
41 );
42 end ALU_v2;
43
44 --! @details SοΏ½lection grace a l'entrοΏ½e "ctrl" :
45 --! Pause : IDLE = 00000
46 --! Multiplieur/Accumulateur : MAC = 0XX01
47 --! Multiplication : MULT = 0XX10
48 --! Addition : ADD = 0XX11
49 --! Complement a 2 : 2C = 011XX
50 --! Reset du MAC : CLRMAC = 10000
51
52 architecture ar_ALU_v2 of ALU_v2 is
53
54 signal clr_MAC : std_logic:='1';
55
56 begin
57
58 clr_MAC <= '1' when ctrl = "10000" else '0';
59
60 arith : if Arith_en = 1 generate
61 MACinst : entity work.MAC_v2
62 generic map(Input_SZ_1,Input_SZ_2)
63 port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES);
64 end generate;
65
66 end ar_ALU_v2; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_matrix.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
35 entity APB_Matrix is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
47 );
48 end APB_Matrix;
49
50
51 architecture ar_APB_Matrix of APB_Matrix is
52
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_MATRIX, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 type MATRIX_ctrlr_Reg is record
60 MATRIX_Cfg : std_logic_vector(3 downto 0);
61 MATRIX_INPUT1 : std_logic_vector(15 downto 0);
62 MATRIX_INPUT2 : std_logic_vector(15 downto 0);
63 MATRIX_Result : std_logic_vector(31 downto 0);
64 end record;
65
66 signal Valid : std_logic;
67 signal Read : std_logic;
68 signal Take : std_logic;
69 signal Received : std_logic;
70
71 signal Rec : MATRIX_ctrlr_Reg;
72 signal Rdata : std_logic_vector(31 downto 0);
73
74 begin
75
76 Take <= Rec.MATRIX_Cfg(0);
77 Rec.MATRIX_Cfg(1) <= Read;
78 Received <= Rec.MATRIX_Cfg(2);
79 Rec.MATRIX_Cfg(3) <= Valid;
80
81 SPEC_MATRIX : Matrix
82 generic map(16)
83 port map(clk,rst,Rec.MATRIX_INPUT1,Rec.MATRIX_INPUT2,Take,Received,Valid,Read,Rec.MATRIX_Result);
84
85 process(rst,clk)
86 begin
87 if(rst='0')then
88 Rec.MATRIX_INPUT1 <= (others => '0');
89 Rec.MATRIX_INPUT2 <= (others => '0');
90 Rec.MATRIX_Cfg(0) <= '0';
91 Rec.MATRIX_Cfg(2) <= '0';
92
93 elsif(clk'event and clk='1')then
94
95 --APB Write OP
96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
97 case apbi.paddr(abits-1 downto 2) is
98 when "000000" =>
99 Rec.MATRIX_Cfg(0) <= apbi.pwdata(0);
100 Rec.MATRIX_Cfg(2) <= apbi.pwdata(8);
101 when "000001" =>
102 Rec.MATRIX_INPUT1 <= apbi.pwdata(15 downto 0);
103 when "000010" =>
104 Rec.MATRIX_INPUT2 <= apbi.pwdata(15 downto 0);
105 when others =>
106 null;
107 end case;
108 end if;
109
110 --APB READ OP
111 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
112 case apbi.paddr(abits-1 downto 2) is
113 when "000000" =>
114 Rdata(31 downto 16) <= X"CCCC";
115 Rdata(15 downto 12) <= "000" & Rec.MATRIX_Cfg(3);
116 Rdata(11 downto 8) <= "000" & Rec.MATRIX_Cfg(2);
117 Rdata(7 downto 4) <= "000" & Rec.MATRIX_Cfg(1);
118 Rdata(3 downto 0) <= "000" & Rec.MATRIX_Cfg(0);
119 when "000001" =>
120 Rdata(31 downto 16) <= X"DDDD";
121 Rdata(15 downto 0) <= Rec.MATRIX_INPUT1;
122 when "000010" =>
123 Rdata(31 downto 16) <= X"DDDD";
124 Rdata(15 downto 0) <= Rec.MATRIX_INPUT2;
125 when "000011" =>
126 Rdata(31 downto 0) <= Rec.MATRIX_Result;
127 when others =>
128 Rdata <= (others => '0');
129 end case;
130 end if;
131
132 end if;
133 apbo.pconfig <= pconfig;
134 end process;
135
136 apbo.prdata <= Rdata when apbi.penable = '1';
137
138 end ar_APB_MATRIX; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Un MAC : Multiplier Accumulator Chip
27
28 entity MAC_v2 is
29 generic(
30 Input_SZ_A : integer := 8;
31 Input_SZ_B : integer := 8);
32 port(
33 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
35 clr_MAC : in std_logic; --! Un reset spοΏ½cifique au programme
36 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); --! Permet de sοΏ½lectionner la/les fonctionnalitοΏ½ dοΏ½sirοΏ½
37 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); --! Premier OpοΏ½rande
38 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); --! Second OpοΏ½rande
39 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) --! RοΏ½sultat du MAC
40 );
41 end MAC_v2;
42
43
44 architecture ar_MAC_v2 of MAC_v2 is
45
46
47 signal add,mult : std_logic;
48 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49
50 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
53
54 signal MACMUXsel : std_logic;
55 signal OP1_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 signal OP2_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
57
58 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
59 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
60
61 signal MACMUX2sel : std_logic;
62
63 signal add_D : std_logic;
64 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
65 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
66 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
67 signal MACMUXsel_D : std_logic;
68 signal MACMUX2sel_D : std_logic;
69 signal MACMUX2sel_D_D : std_logic;
70 signal clr_MAC_D : std_logic;
71 signal clr_MAC_D_D : std_logic;
72 signal MAC_MUL_ADD_2C_D : std_logic_vector(3 downto 0);
73
74
75 begin
76
77
78
79 --==============================================================
80 --=============M A C C O N T R O L E R=========================
81 --==============================================================
82 MAC_CONTROLER1 : entity work.MAC_CONTROLER
83 port map(
84 ctrl => MAC_MUL_ADD_2C_D(1 downto 0),
85 MULT => mult,
86 ADD => add,
87 MACMUX_sel => MACMUXsel,
88 MACMUX2_sel => MACMUX2sel
89
90 );
91 --==============================================================
92
93
94
95
96 --==============================================================
97 --=============M U L T I P L I E R==============================
98 --==============================================================
99 Multiplieri_nst : entity work.Multiplier
100 generic map(
101 Input_SZ_A => Input_SZ_A,
102 Input_SZ_B => Input_SZ_B
103 )
104 port map(
105 clk => clk,
106 reset => reset,
107 mult => mult,
108 OP1 => OP1_2C,
109 OP2 => OP2_2C,
110 RES => MULTout
111 );
112
113 --==============================================================
114
115
116
117
118 --==============================================================
119 --======================A D D E R ==============================
120 --==============================================================
121 adder_inst : entity work.Adder
122 generic map(
123 Input_SZ_A => Input_SZ_A+Input_SZ_B,
124 Input_SZ_B => Input_SZ_A+Input_SZ_B
125 )
126 port map(
127 clk => clk,
128 reset => reset,
129 clr => clr_MAC_D_D,
130 add => add_D,
131 OP1 => ADDERinA,
132 OP2 => ADDERinB,
133 RES => ADDERout
134 );
135
136 --==============================================================
137
138
139
140
141 --==============================================================
142 --===================TWO COMPLEMENTERS==========================
143 --==============================================================
144 TWO_COMPLEMENTER1 : entity work.TwoComplementer
145 generic map(
146 Input_SZ => Input_SZ_A
147 )
148 port map(
149 clk => clk,
150 reset => reset,
151 clr => clr_MAC,
152 TwoComp => MAC_MUL_ADD_2C(2),
153 OP => OP1,
154 RES => OP1_2C
155 );
156
157
158 TWO_COMPLEMENTER2 : entity work.TwoComplementer
159 generic map(
160 Input_SZ => Input_SZ_B
161 )
162 port map(
163 clk => clk,
164 reset => reset,
165 clr => clr_MAC,
166 TwoComp => MAC_MUL_ADD_2C(3),
167 OP => OP2,
168 RES => OP2_2C
169 );
170 --==============================================================
171
172 CTRL : entity work.MAC_REG
173 generic map(size => 2)
174 port map(
175 reset => reset,
176 clk => clk,
177 D => MAC_MUL_ADD_2C(1 downto 0),
178 Q => MAC_MUL_ADD_2C_D(1 downto 0)
179 );
180
181 clr_MACREG1 : entity work.MAC_REG
182 generic map(size => 1)
183 port map(
184 reset => reset,
185 clk => clk,
186 D(0) => clr_MAC,
187 Q(0) => clr_MAC_D
188 );
189
190 clr_MACREG2 : entity work.MAC_REG
191 generic map(size => 1)
192 port map(
193 reset => reset,
194 clk => clk,
195 D(0) => clr_MAC_D,
196 Q(0) => clr_MAC_D_D
197 );
198
199 addREG : entity work.MAC_REG
200 generic map(size => 1)
201 port map(
202 reset => reset,
203 clk => clk,
204 D(0) => add,
205 Q(0) => add_D
206 );
207
208
209 OP1REG : entity work.MAC_REG
210 generic map(size => Input_SZ_A)
211 port map(
212 reset => reset,
213 clk => clk,
214 D => OP1_2C,
215 Q => OP1_2C_D
216 );
217
218
219 OP2REG : entity work.MAC_REG
220 generic map(size => Input_SZ_B)
221 port map(
222 reset => reset,
223 clk => clk,
224 D => OP2_2C,
225 Q => OP2_2C_D
226 );
227
228
229 MULToutREG : entity work.MAC_REG
230 generic map(size => Input_SZ_A+Input_SZ_B)
231 port map(
232 reset => reset,
233 clk => clk,
234 D => MULTout,
235 Q => MULTout_D
236 );
237
238
239 MACMUXselREG : entity work.MAC_REG
240 generic map(size => 1)
241 port map(
242 reset => reset,
243 clk => clk,
244 D(0) => MACMUXsel,
245 Q(0) => MACMUXsel_D
246 );
247
248
249
250 MACMUX2selREG : entity work.MAC_REG
251 generic map(size => 1)
252 port map(
253 reset => reset,
254 clk => clk,
255 D(0) => MACMUX2sel,
256 Q(0) => MACMUX2sel_D
257 );
258
259
260 MACMUX2selREG2 : entity work.MAC_REG
261 generic map(size => 1)
262 port map(
263 reset => reset,
264 clk => clk,
265 D(0) => MACMUX2sel_D,
266 Q(0) => MACMUX2sel_D_D
267 );
268
269
270 --==============================================================
271 --======================M A C M U X ===========================
272 --==============================================================
273 MACMUX_inst : entity work.MAC_MUX
274 generic map(
275 Input_SZ_A => Input_SZ_A+Input_SZ_B,
276 Input_SZ_B => Input_SZ_A+Input_SZ_B
277
278 )
279 port map(
280 sel => MACMUXsel_D,
281 INA1 => ADDERout,
282 INA2 => OP2_Resz,
283 INB1 => MULTout,
284 INB2 => OP1_Resz,
285 OUTA => ADDERinA,
286 OUTB => ADDERinB
287 );
288 OP1_Resz <= std_logic_vector(resize(signed(OP1_2C_D),Input_SZ_A+Input_SZ_B));
289 OP2_Resz <= std_logic_vector(resize(signed(OP2_2C_D),Input_SZ_A+Input_SZ_B));
290 --==============================================================
291
292
293 --==============================================================
294 --======================M A C M U X2 ==========================
295 --==============================================================
296 MAC_MUX2_inst : entity work.MAC_MUX2
297 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
298 port map(
299 sel => MACMUX2sel_D_D,
300 RES2 => MULTout_D,
301 RES1 => ADDERout,
302 RES => RES
303 );
304
305
306 --==============================================================
307
308 end ar_MAC_v2;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme de calcule de Matrice Spectral, composοΏ½ d'une ALU et de son Driver
27
28 entity Matrix is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 raz : in std_logic; --! Reset general du composant
34 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
35 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! DonnοΏ½e d'entrοΏ½e
36 Take : in std_logic; --! Flag, opοΏ½rande rοΏ½cupοΏ½rοΏ½
37 Received : in std_logic; --! Flag, RοΏ½sultat bien ressu
38 Valid : out std_logic; --! Flag, RοΏ½sultat disponible
39 Read : out std_logic; --! Flag, opοΏ½rande disponible
40 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! RοΏ½sultat du calcul
41 );
42 end Matrix;
43
44
45 architecture ar_Matrix of Matrix is
46
47 signal CTRL : std_logic_vector(4 downto 0);
48 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
49 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
50
51 begin
52
53 DRIVE : entity work.ALU_Driver
54 generic map(Input_SZ,Input_SZ)
55 port map(clk,raz,IN1,IN2,Take,Received,Valid,Read,CTRL,OP1,OP2);
56
57
58 ALU : entity work.ALU_v2
59 generic map(1,0,Input_SZ,Input_SZ)
60 port map(clk,raz,CTRL,OP1,OP2,Result);
61
62
63 end ar_Matrix;
64
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@@ -0,0 +1,72
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme permetant de complοΏ½menter ou non les entrοΏ½es de l'ALU, et ainsi de travailler avec des nombres nοΏ½gatifs
27
28 entity TwoComplementer is
29 generic(
30 Input_SZ : integer := 16);
31 port(
32 clk : in std_logic; --! Horloge du composant
33 reset : in std_logic; --! Reset general du composant
34 clr : in std_logic; --! Un reset spοΏ½cifique au programme
35 TwoComp : in std_logic; --! Autorise l'utilisation du complοΏ½ment
36 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpοΏ½rande d'entrοΏ½e
37 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RοΏ½sultat, opοΏ½rande complοΏ½mentοΏ½ ou non
38 );
39 end TwoComplementer;
40
41
42 architecture ar_TwoComplementer of TwoComplementer is
43
44 signal REG : std_logic_vector(Input_SZ-1 downto 0);
45 signal OPinteger : integer;
46 signal RESCOMP : std_logic_vector(Input_SZ-1 downto 0);
47
48 begin
49
50 RES <= REG;
51 OPinteger <= to_integer(signed(OP));
52 RESCOMP <= std_logic_vector(to_signed(-OPinteger,Input_SZ));
53
54 process(clk,reset)
55 begin
56
57 if(reset='0')then
58 REG <= (others => '0');
59 elsif(clk'event and clk='1')then
60
61 if(clr='1')then
62 REG <= (others => '0');
63 elsif(TwoComp='1')then
64 REG <= RESCOMP;
65 else
66 REG <= OP;
67 end if;
68
69 end if;
70
71 end process;
72 end ar_TwoComplementer; No newline at end of file
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@@ -0,0 +1,133
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31
32 package lpp_matrix is
33
34 component APB_Matrix is
35 generic (
36 pindex : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
40 abits : integer := 8);
41 port (
42 clk : in std_logic; --! Horloge du composant
43 rst : in std_logic; --! Reset general du composant
44 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
45 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
46 );
47 end component;
48
49
50 component Matrix is
51 generic(
52 Input_SZ : integer := 16);
53 port(
54 clk : in std_logic;
55 raz : in std_logic;
56 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
57 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
58 Take : in std_logic;
59 Received : in std_logic;
60 Valid : out std_logic;
61 Read : out std_logic;
62 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
63 );
64 end component;
65
66
67 component ALU_Driver is
68 generic(
69 Input_SZ_1 : integer := 16;
70 Input_SZ_2 : integer := 16);
71 port(
72 clk : in std_logic;
73 reset : in std_logic;
74 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
75 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
76 Take : in std_logic;
77 Received : in std_logic;
78 Valid : out std_logic;
79 Read : out std_logic;
80 CTRL : out std_logic_vector(4 downto 0);
81 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
82 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
83 );
84 end component;
85
86
87 component ALU_v2 is
88 generic(
89 Arith_en : integer := 1;
90 Logic_en : integer := 1;
91 Input_SZ_1 : integer := 16;
92 Input_SZ_2 : integer := 9);
93 port(
94 clk : in std_logic;
95 reset : in std_logic;
96 ctrl : in std_logic_vector(4 downto 0);
97 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
98 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
99 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
100 );
101 end component;
102
103
104 component MAC_v2 is
105 generic(
106 Input_SZ_A : integer := 8;
107 Input_SZ_B : integer := 8);
108 port(
109 clk : in std_logic;
110 reset : in std_logic;
111 clr_MAC : in std_logic;
112 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
113 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
114 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
115 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
116 );
117 end component;
118
119
120 component TwoComplementer is
121 generic(
122 Input_SZ : integer := 16);
123 port(
124 clk : in std_logic;
125 reset : in std_logic;
126 clr : in std_logic;
127 TwoComp : in std_logic;
128 OP : in std_logic_vector(Input_SZ-1 downto 0);
129 RES : out std_logic_vector(Input_SZ-1 downto 0)
130 );
131 end component;
132
133 end; No newline at end of file
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@@ -1,14 +1,15
1 1 vendor VENDOR_LPP 19
2 2
3 3 device ROCKET_TM 1
4 4 device otherCore 2
5 5 device LPP_SIMPLE_DIODE 3
6 6 device LPP_MULTI_DIODE 4
7 7 device LPP_LCD_CTRLR 5
8 8 device LPP_UART 6
9 9 device LPP_CNA 7
10 10 device LPP_APB_ADC 8
11 11 device LPP_CHENILLARD 9
12 12 device LPP_IIR_CEL_FILTER 10
13 13 device LPP_FIFO 11
14 14 device LPP_FFT 12
15 device LPP_MATRIX 13
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@@ -1,46 +1,47
1 1 #------------------------------------------------------------------------------
2 2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 4 #--
5 5 #-- This program is free software; you can redistribute it and/or modify
6 6 #-- it under the terms of the GNU General Public License as published by
7 7 #-- the Free Software Foundation; either version 3 of the License, or
8 8 #-- (at your option) any later version.
9 9 #--
10 10 #-- This program is distributed in the hope that it will be useful,
11 11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 #-- GNU General Public License for more details.
14 14 #--
15 15 #-- You should have received a copy of the GNU General Public License
16 16 #-- along with this program; if not, write to the Free Software
17 17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 #------------------------------------------------------------------------------
19 19
20 20 .PHONY:doc
21 21
22 22 all:
23 23 mkdir -p lib/
24 24 mkdir -p includes/
25 25 make all -C libsrc
26 26 make all -C exemples
27 27
28 28 .PHONY:exemples lib
29 29
30 30 exemples:
31 31 make all -C exemples
32 32
33 33
34 34 lib:
35 35 mkdir -p lib/
36 36 mkdir -p includes/
37 37 make all -C libsrc
38 38
39 39 doc:
40 rm -R Doc/html/*
41 cp -R Doc/ressources/* Doc/html/
40 mkdir -p Doc/ressources/
41 mkdir -p Doc/html/
42 cp -f -R Doc/ressources/* Doc/html/
42 43 doxygen Doxyfile
43 44
44 45 clean:
45 46 rm lib/*
46 47 rm includes/*
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@@ -1,56 +1,98
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -----------------------------------------------------------------------------*/
22 22 #ifndef APB_FFT_DRIVER_H
23 23 #define APB_FFT_DRIVER_H
24 24
25 #define FFT_Empty 0x00100
26 #define FFT_Full 0x01000
25 /*! \file apb_fft_Driver.h
26 \brief LPP FFT driver.
27
28 This library is written to work with LPP_APB_FFT VHDL module from LPP's FreeVHDLIB. It calculate a fast fourier transforms,
29 from an input data table.
30
31 \todo Check "DEVICE1 => count = 2" function Open
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35 #define FFT_Empty 0x00100 /**< Used to know when the data can be send to the FFT module */
36 #define FFT_Full 0x01000 /**< Used to know when the data can be send to the FFT module */
27 37
28 38
29 39 /*===================================================
30 40 T Y P E S D E F
31 41 ====================================================*/
32
42 /*! \struct FFT_Driver
43 \brief Sturcture representing the fft registers
44 */
33 45 struct FFT_Driver
34 46 {
35 int RWDataReg;
36 int ReadAddrReg;
37 int ConfigReg;
38 int Dummy1;
39 int Dummy0;
40 int WriteAddrReg;
47 int RWDataReg; /**< \brief Data register Write/Read */
48 int ReadAddrReg; /**< \brief Address register for the reading operation */
49 int ConfigReg; /**< \brief Configuration register composed of Read enable Flag [HEX 0]
50 Write enable Flag [HEX 1]
51 Empty Flag [HEX 2]
52 Full Flag [HEX 3]
53 Dummy "C" [HEX 4/5/6/7] */
54 int Dummy1; /**< \brief Unused register, aesthetic interest */
55 int Dummy0; /**< \brief Unused register, aesthetic interest */
56 int WriteAddrReg; /**< \brief Address register for the writing operation */
41 57 };
42 58
43 59 typedef struct FFT_Driver FFT_Device;
44 60
45 61
46 62 /*===================================================
47 63 F U N C T I O N S
48 64 ====================================================*/
49
65 /*! \fn FFT_Device* openFFT(int count);
66 \brief Return count FFT.
67
68 This Function scans APB devices table and returns count FFT.
69
70 \param count The number of the FFT you whant to get. For example if you have 3 FFTS on your SOC you want
71 to use FFT1 so count = 2.
72 \return The pointer to the device.
73 */
50 74 FFT_Device* openFFT(int count);
51 int FftInput(int Tbl[],FFT_Device*);
52 int FftOutput(int Tbl[],FFT_Device*);
75
76 /*! \fn int FftInput(int Tbl[],FFT_Device*);
77 \brief Fill in the Input for the FFT
78
79 This function provides the data used by the FFT
80
81 \param Tbl[] The Table which contains the Data.
82 \param dev The FFT pointer.
83 */
84 int FftInput(int Tbl[],FFT_Device* dev);
85
86 /*! \fn int FftOutput(int Tbl[],FFT_Device*);
87 \brief Save data from the FFT
88
89 This function save the data generated by the FFT
90
91 \param Tbl[] The Table which will contains the Data.
92 \param dev The FFT pointer.
93 */
94 int FftOutput(int Tbl[],FFT_Device* dev);
53 95
54 96
55 97
56 98 #endif
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@@ -1,54 +1,76
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -----------------------------------------------------------------------------*/
22 22 #ifndef APB_FIFO_DRIVER_H
23 23 #define APB_FIFO_DRIVER_H
24
25 /*! \file apb_fifo_Driver.h
26 \brief LPP FIFO driver.
24 27
28 This library is written to work with LPP_APB_FIFO VHDL module from LPP's FreeVHDLIB. It represents a standard FIFO working,
29 used in many type of application.
30
31 \todo Check "DEVICE1 => count = 2" function Open
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
25 34
26 35
27 36 /*===================================================
28 37 T Y P E S D E F
29 38 ====================================================*/
30 39
31 /** Structure reprοΏ½sentant le registre du FIFO */
40 /*! \struct APB_FIFO_REG
41 \brief Sturcture representing the fifo registers
42 */
32 43 struct APB_FIFO_REG
33 44 {
34 int rwdata; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
35 int raddr; /**< Registre de donnοΏ½e sur 16 bits */
36 int cfgreg;
37 int dummy0;
38 int dummy1;
39 int waddr;
45 int rwdata; /**< \brief Data register Write/Read */
46 int raddr; /**< \brief Address register for the reading operation */
47 int cfgreg; /**< \brief Configuration register composed of Read enable Flag [HEX 0]
48 Write enable Flag [HEX 1]
49 Empty Flag [HEX 2]
50 Full Flag [HEX 3]
51 Dummy "C" [HEX 4/5/6/7] */
52 int dummy0; /**< \brief Unused register, aesthetic interest */
53 int dummy1; /**< \brief Unused register, aesthetic interest */
54 int waddr; /**< \brief Address register for the writing operation */
40 55 };
41 56
42 57 typedef struct APB_FIFO_REG APB_FIFO_Device;
43 58
44 59 /*===================================================
45 60 F U N C T I O N S
46 61 ====================================================*/
47 62
48 /** Ouvre l'accοΏ½ au FIFO */
63 /*! \fn APB_FIFO_Device* apbfifoOpen(int count);
64 \brief Return count FIFO.
65
66 This Function scans APB devices table and returns count FIFO.
67
68 \param count The number of the FIFO you whant to get. For example if you have 3 FIFOS on your SOC you want
69 to use FIFO1 so count = 2.
70 \return The pointer to the device.
71 */
49 72 APB_FIFO_Device* apbfifoOpen(int count);
50 73
51 74
52 75
53
54 76 #endif
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@@ -1,99 +1,121
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 19 /*-- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------*/
22 22 #ifndef APB_LCD_DRIVER_H
23 23 #define APB_LCD_DRIVER_H
24 24
25 25 #define readyFlag 1024
26 26 #define lcdCharCnt 80
27 27
28 28
29 /** @todo implemente some shift functions */
29 /*! \file apb_lcd_driver.h
30 \brief APB char LCD driver.
31
32 This library is written to work with apb_lcd VHDL module from LPP's VHDlib. It help you to drive char LCD.
33
34 \author Alexis Jeandet
35 \todo implemente some shift functions
36 */
30 37
31 38
32 39 /*===================================================
33 40 T Y P E S D E F
34 41 ====================================================*/
35 42
36 43
37
38 /** error type used for most of lcd functions */
39 typedef int lcd_err;
40
41 44 /** lcd error ennum for higher abstraction level when error decoding */
42 45 enum lcd_error
43 46 {
44 lcd_error_no_error, /**< no error append while function execution */
45 lcd_error_not_ready, /**< the lcd isn't available*/
46 lcd_error_not_openned, /**< the device guiven to the function isn't opened*/
47 lcd_error_too_long /**< the string guiven to the lcd is bigger than the lcd frame buffer memory */
47 lcd_error_no_error, /**< \brief no error append while function execution */
48 lcd_error_not_ready, /**< \brief the lcd isn't available*/
49 lcd_error_not_openned, /**< \brief the device guiven to the function isn't opened*/
50 lcd_error_too_long /**< \brief the string guiven to the lcd is bigger than the lcd frame buffer memory */
48 51 };
49 52
53 typedef enum lcd_error lcd_err;
50 54
51 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet */
55 /** for each command sended to the lcd driver a time should be guiven according to the lcd datasheet.
56 Don't worry about time, the lcd VHDL module should be aware of oscillator frequency.
57 */
52 58 enum lcd_CMD_time
53 59 {
54 lcd_4us = 0x0FF,
60 lcd_4us = 0x0FF,
55 61 lcd_100us = 0x1FF,
56 62 lcd_4ms = 0x2FF,
57 63 lcd_20ms = 0x3FF
58 64 };
59 65
60 /** list of availiable lcd commands use whith an AND mask whith cmd time */
66 /** list of availiable lcd commands use whith an AND mask whith cmd time
67 \todo implemente more commands.
68 */
61 69 enum lcd_CMD
62 70 {
63 71 CursorON = 0xF0E,
64 72 CursorOFF = 0xF0C
65 73 };
66 74
67 75 /** structure representing the lcd registers */
68 76 struct lcd_driver
69 77 {
70 78 int cfg_reg; /**< Configuration register composed of Ready flag [10], CMD time Value [9:8],
71 79 CMD to send [7:0]*/
72 80 int Frame_buff[lcdCharCnt]; /**< Frame Buffer space each address corresponds to a char on the lcd screen */
73 81 };
74 82
75 83 typedef struct lcd_driver lcd_device;
76 84
77 85 /*===================================================
78 86 F U N C T I O N S
79 87 ====================================================*/
80 88
81 /** says if the lcd is busy */
89 /*! \fn int lcdbusy(lcd_device * lcd);
90 \brief Say if the lcd screen is busy
91
92 \param lcd The lcd device to test.
93 \return True if the lcd is busy.
94 */
82 95 int lcdbusy(lcd_device * lcd);
83 96
84 /** Opens and returns the counth lcd found on APB bus else NULL */
97
98 /*! \fn lcd_device* lcdopen(int count);
99 \brief Return counth LCD.
100
101 This Function scans APB devices table and returns counth LCD.
102
103 \param count The number of the LCD you whant to get. For example if you have 3 LCD on your SOC you whant
104 to use LCD1 so count = 2.
105 \return The pointer to the device.
106 */
85 107 lcd_device* lcdopen(int count);
86 108
87 109 /** Sends a command to the given device, don't forget to guive the time of the cmd */
88 110 lcd_err lcdsendcmd(lcd_device* lcd,int cmd);
89 111
90 112 /** Sets a char on the given device at given position */
91 113 lcd_err lcdsetchar(lcd_device* lcd,int position,const char value);
92 114
93 115 /** Prints a message on the given device at given position, "\n" is understood but for others use sprintf before */
94 116 lcd_err lcdprint(lcd_device* lcd,int position,const char* value);
95 117
96 118 /** Writes space character on each adress of the lcd screen */
97 119 lcd_err lcdclear(lcd_device* lcd);
98 120
99 121 #endif
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@@ -1,56 +1,118
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 22 #ifndef APB_UART_DRIVER_H
23 #define APB_UART_DRIVER_H
24
23 #define APB_UART_DRIVER_H
24
25 /*! \file apb_uart_Driver.h
26 \brief LPP Uart driver.
27
28 This library is written to work with LPP_APB_UART VHDL module from LPP's FreeVHDLIB. It help you to print and get,
29 char or strings over uart.
25 30
26 #define BaudGenOnDuty 0
27 #define DataSended 0x10
28 #define NewData 0x100
29
31 \todo Check "DEVICE1 => count = 2" function Open
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35
36
37 #define BaudGenOnDuty 0 /**< Used to reset the Baud Generator (Capture Flag) */
38 #define DataSended 0x10 /**< Used to know when the data was send */
39 #define NewData 0x100 /**< Used to know if a New data is ready to be send */
40
30 41 /*===================================================
31 42 T Y P E S D E F
32 ====================================================*/
43 ====================================================*/
33 44
34 struct UART_Driver
35 {
36 int ConfigReg;
37 int DataWReg;
38 int DataRReg;
39 };
40
41 typedef struct UART_Driver UART_Device;
42
43
45 /*! \struct UART_Driver
46 \brief Sturcture representing the uart registers
47 */
48 struct UART_Driver
49 {
50 int ConfigReg; /**< \brief Configuration register composed of Capture Flag [HEX 0]
51 Sended Flag [HEX 1]
52 NewData Flag [HEX 2]
53 Dummy "E" [HEX 3/4]
54 BTrig Freq [HEX 5/6/7] */
55 int DataWReg; /**< \brief Data Write register */
56 int DataRReg; /**< \brief Data Read register */
57 };
58
59 typedef struct UART_Driver UART_Device;
60
61
44 62 /*===================================================
45 63 F U N C T I O N S
46 ====================================================*/
47
48
49 UART_Device* openUART(int count);
50 void uartputc(UART_Device* dev,char c);
51 void uartputs(UART_Device* dev,char* s);
52 char uartgetc(UART_Device* dev);
53 void uartgets(UART_Device* dev,char* s);
54
55
56 #endif
64 ====================================================*/
65
66 /*! \fn UART_Device* openUART(int count);
67 \brief Return count UART.
68
69 This Function scans APB devices table and returns count UART.
70
71 \param count The number of the UART you whant to get. For example if you have 3 UARTS on your SOC you want
72 to use UART1 so count = 2.
73 \return The pointer to the device.
74 */
75 UART_Device* openUART(int count);
76
77 /*! \fn void uartputc(UART_Device* dev,char c);
78 \brief Print char over given UART.
79
80 This Function puts the given char over the given UART.
81
82 \param dev The UART pointer.
83 \param c The char you whant to print.
84 */
85 void uartputc(UART_Device* dev,char c);
86
87 /*! \fn void uartputs(UART_Device* dev,char* s);
88 \brief Print string over given UART.
89
90 This Function puts the given string over the given UART.
91
92 \param dev The UART pointer.
93 \param s The string you whant to print.
94 */
95 void uartputs(UART_Device* dev,char* s);
96
97 /*! \fn char uartgetc(UART_Device* dev);
98 \brief Get char from given UART.
99
100 This Function get char from the given UART.
101
102 \param dev The UART pointer.
103 \return The read char.
104 */
105 char uartgetc(UART_Device* dev);
106
107 /*! \fn void uartgets(UART_Device* dev,char* s);
108 \brief Get string from given UART.
109
110 This Function get string from the given UART.
111
112 \param dev The UART pointer.
113 \param s The read string.
114 */
115 void uartgets(UART_Device* dev,char* s);
116
117
118 #endif
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@@ -1,62 +1,135
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------*/
19 19 /*-- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------*/
22 22 #ifndef LPP_APB_FUNCTIONS_H
23 23 #define LPP_APB_FUNCTIONS_H
24 24
25 #define APB_TBL_HEAD 0x800FF000
26 #define APB_BASE_ADDRS 0x80000000
27 #define APB_MAX_DEVICES 256
25 #define APB_TBL_HEAD 0x800FF000 /**< Start address of APB devices list on AHB2APB bridge*/
26 #define APB_BASE_ADDRS 0x80000000 /**< Start address of APB bus*/
27 #define APB_MAX_DEVICES 256 /**< Maximun device count on APB bus*/
28 28
29 29 #include "apb_devices_list.h"
30 30
31 /** @todo implemente a descriptor structure for any APB device */
31
32 /*! \file lpp_apb_functions.h
33 \brief General purpose APB functions.
34
35 This library is written to work with AHB2APB VHDL module from Gaisler's GRLIB. It help you to find your device
36 on the APB bus by providing scan functions, it extract information such as device Version, IRQ value, Address mask.
37 You can use it to print the APB devices list on your SOC.
38
39 \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
40 \todo implemente a descriptor structure for any APB device
41
42 */
32 43
33 44
34 /** Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature */
45 /*! \struct apbPnPreg
46 \brief Structure representing a device descriptor register on Grlib's AHB2APB brige with plug and play feature
47 */
35 48 struct apbPnPreg
36 49 {
37 int idReg; /**< id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
38 int bar; /**< Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
50 int idReg; /**< \brief id register composed of Vendor ID [31:24], Device ID [23:12], CT [11:10], Version [9:5], IRQ [4:0] */
51 int bar; /**< \brief Bank Address Register composed of Device's ADDRESS [31:20], MASK [14:4], TYPE [3:0] */
39 52 };
40 53
54
55 /*! \struct apbdevinfo
56 \brief Structure holding an APB device informations
57
58 This information are extracted from the descriptor registers on Grlib's AHB2APB brige with plug and play feature
59 */
41 60 struct apbdevinfo
42 61 {
43 int vendorID;
44 int productID;
45 int version;
46 int irq;
47 int address;
48 int mask;
62 int vendorID; /**< \brief Stores the Vendor ID of the current device */
63 int productID; /**< \brief Stores the Product ID of the current device */
64 int version; /**< \brief Stores the Version of the current device */
65 int irq; /**< \brief Stores the interrupt Number of the current device */
66 int address; /**< \brief Stores the base address of the current device */
67 int mask; /**< \brief Stores the address mask of the current device, it gives the address space of this device */
49 68 };
50 69
51 /** This Function scans APB devices table and returns counth device according to VID and PID */
70
71
72
73 /*! \fn int* apbgetdevice(int PID,int VID,int count);
74 \brief Find device with given VID/PID
75
76 This Function scans APB devices table and returns counth device according to VID and PID
77
78 \param PID The PID of the device you whant to get.
79 \param VID The VID of the device you whant to get.
80 \param count The number of the device you whant to get. For example if you have 3 UARTS on your SOC you whant
81 to use UART1 so count = 2.
82
83 \return The pointer to the device.
84 */
52 85 int* apbgetdevice(int PID,int VID,int count);
53 /** This Function scans APB devices table and returns counth device informations according VID and PID */
86
87 /*! \fn void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
88 \brief Record device informations with given VID/PID
89
90 This Function scans APB devices table and returns counth device informations according VID and PID.
91
92 \param PID The PID of the device you whant to get.
93 \param VID The VID of the device you whant to get.
94 \param count The number of the device you whant to get. For example if you have 3 UARTS on your SOC you whant
95 to use UART1 so count = 2.
96 \param devinfo The device information structure to be populated.
97 \example scanAPB.c
98 */
54 99 void apbgetdeviceinfofromid(int PID,int VID,int count,struct apbdevinfo* devinfo);
55 100
101
102 /*! \fn void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
103 \brief Record device informations with given AHB2APB Plugn'Play register.
104
105 This Function extract device informations from the given AHB2APB Plugn'Play register end write them in devinfo.
106
107 \param dev AHB2APB Plugn'Play register corresponding to the device.
108 \param devinfo The device information structure to be populated.
109 */
56 110 void apbgetdeviceinfofromdevptr(const struct apbPnPreg* dev,struct apbdevinfo* devinfo);
57 111
58 112
113
114 /*! \fn void apbprintdeviceinfo(struct apbdevinfo devinfo);
115 \brief Print given device informations in stdout.
116
117 \param devinfo The device information structure to be printed.
118 */
59 119 void apbprintdeviceinfo(struct apbdevinfo devinfo);
60 120
121
122
123 /*! \fn void apbprintdeviceslist();
124 \brief Print APB devices informations in stdout.
125
126 This function list all devices on APB bus and print theirs informations.
127
128 \example scanAPB.c
129 */
61 130 void apbprintdeviceslist();
131
132
133
62 134 #endif // LPP_APB_FUNCTIONS_H
135
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@@ -1,107 +1,109
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fft.all;
32 32 use lpp.lpp_memory.all;
33 33 use work.fft_components.all;
34 34
35 35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
36 36
37 37 entity APB_FFT is
38 38 generic (
39 39 pindex : integer := 0;
40 40 paddr : integer := 0;
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 44 Data_sz : integer := 32;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 48 clk : in std_logic; --! Horloge du composant
49 49 rst : in std_logic; --! Reset general du composant
50 50 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
51 51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 52 );
53 53 end APB_FFT;
54 54
55 55
56 56 architecture ar_APB_FFT of APB_FFT is
57 57
58 58 signal ReadEnable : std_logic;
59 59 signal WriteEnable : std_logic;
60 60 signal FlagEmpty : std_logic;
61 61 signal FlagFull : std_logic;
62 62 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
63 63 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
64 64 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
65 65 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
66 66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
67 67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
68 68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
69 69 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
70 70
71 71 signal start : std_logic;
72 72 signal load : std_logic;
73 73 signal rdy : std_logic;
74 signal zero : std_logic;
74 75
75 76 begin
76 77
77 78 APB : ApbDriver
78 79 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
79 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
80 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,zero,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
80 81
81 82
82 83 Extremum : Flag_Extremum
83 84 port map(clk,rst,load,rdy,FlagFull,FlagEmpty);
84 85
85 86
86 87 DEVICE : CoreFFT
87 88 generic map(
88 89 LOGPTS => gLOGPTS,
89 90 LOGLOGPTS => gLOGLOGPTS,
90 91 WSIZE => gWSIZE,
91 92 TWIDTH => gTWIDTH,
92 93 DWIDTH => gDWIDTH,
93 94 TDWIDTH => gTDWIDTH,
94 95 RND_MODE => gRND_MODE,
95 96 SCALE_MODE => gSCALE_MODE,
96 97 PTS => gPTS,
97 98 HALFPTS => gHALFPTS,
98 99 inBuf_RWDLY => gInBuf_RWDLY)
99 100 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
100 101
101 102 start <= not rst;
103 zero <= '0';
102 104
103 105 DataIn_re <= DataIn(31 downto 16);
104 106 DataIn_im <= DataIn(15 downto 0);
105 107 DataOut <= DataOut_re & DataOut_im;
106 108
107 109 end ar_APB_FFT; No newline at end of file
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@@ -1,77 +1,78
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_memory.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34 34
35 35 entity APB_FIFO is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
49 49 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
50 50 );
51 51 end APB_FIFO;
52 52
53 53
54 54 architecture ar_APB_FIFO of APB_FIFO is
55 55
56 56 signal ReadEnable : std_logic;
57 57 signal WriteEnable : std_logic;
58 58 signal FlagEmpty : std_logic;
59 59 signal FlagFull : std_logic;
60 signal ReUse : std_logic;
60 61 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
61 62 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
62 63 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
63 64 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
64 65
65 66 begin
66 67
67 68 APB : ApbDriver
68 69 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
69 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
70 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,ReUse,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
70 71
71 72
72 73 DEVICE : Top_FIFO
73 74 generic map(Data_sz,Addr_sz,addr_max_int)
74 port map(clk,rst,ReadEnable,WriteEnable,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
75 port map(clk,rst,ReadEnable,WriteEnable,ReUse,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
75 76
76 77
77 78 end ar_APB_FIFO; No newline at end of file
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@@ -1,154 +1,160
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31
32 32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
33 33
34 34 entity ApbDriver is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 LPP_DEVICE : integer;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 ReUse : out std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
52 53 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 54 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 55 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 56 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 57 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 58 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 59 );
59 60 end ApbDriver;
60 61
61 62 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
62 63
63 64 architecture ar_ApbDriver of ApbDriver is
64 65
65 66 constant REVISION : integer := 1;
66 67
67 68 constant pconfig : apb_config_type := (
68 69 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
69 70 1 => apb_iobar(paddr, pmask));
70 71
71 72 type DEVICE_ctrlr_Reg is record
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
73 74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
74 75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
75 76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
76 77 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
77 78 end record;
78 79
79 80 signal Rec : DEVICE_ctrlr_Reg;
80 81 signal Rdata : std_logic_vector(31 downto 0);
81 82
82 83 signal FlagRE : std_logic;
83 84 signal FlagWR : std_logic;
84 85
85 86 begin
86 87
87 88 Rec.DEVICE_Cfg(0) <= FlagRE;
88 89 Rec.DEVICE_Cfg(1) <= FlagWR;
89 90 Rec.DEVICE_Cfg(2) <= FlagEmpty;
90 91 Rec.DEVICE_Cfg(3) <= FlagFull;
92 ReUse <= Rec.DEVICE_Cfg(4);
91 93
92 94 DataIn <= Rec.DEVICE_DataW;
93 95 Rec.DEVICE_DataR <= DataOut;
94 96 Rec.DEVICE_AddrW <= AddrIn;
95 97 Rec.DEVICE_AddrR <= AddrOut;
96 98
97 99
98 100
99 101 process(rst,clk)
100 102 begin
101 103 if(rst='0')then
102 104 Rec.DEVICE_DataW <= (others => '0');
103 105 FlagWR <= '0';
104 106 FlagRE <= '0';
107 Rec.DEVICE_Cfg(4) <= '0';
105 108
106 109 elsif(clk'event and clk='1')then
107 110
108 111 --APB Write OP
109 112 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
110 113 case apbi.paddr(abits-1 downto 2) is
111 114 when "000000" =>
112 115 FlagWR <= '1';
113 116 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
117 when "000010" =>
118 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
114 119 when others =>
115 120 null;
116 121 end case;
117 122 else
118 123 FlagWR <= '0';
119 124 end if;
120 125
121 126 --APB Read OP
122 127 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
123 128 case apbi.paddr(abits-1 downto 2) is
124 129 when "000000" =>
125 130 FlagRE <= '1';
126 131 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
127 132 when "000001" =>
128 133 Rdata(31 downto 8) <= X"AAAAAA";
129 134 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
130 135 when "000101" =>
131 136 Rdata(31 downto 8) <= X"AAAAAA";
132 137 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
133 138 when "000010" =>
134 139 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
135 140 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
136 141 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
137 142 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
138 Rdata(31 downto 16) <= X"CCCC";
143 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
144 Rdata(31 downto 20) <= X"CCC";
139 145 when others =>
140 146 Rdata <= (others => '0');
141 147 end case;
142 148 else
143 149 FlagRE <= '0';
144 150 end if;
145 151
146 152 end if;
147 153 apbo.pconfig <= pconfig;
148 154 end process;
149 155
150 156 apbo.prdata <= Rdata when apbi.penable = '1';
151 157 WriteEnable <= FlagWR;
152 158 ReadEnable <= FlagRE;
153 159
154 160 end ar_ApbDriver; No newline at end of file
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@@ -1,86 +1,94
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 --! Programme de la FIFO de lecture
27 27
28 28 entity Fifo_Read is
29 29 generic(
30 30 Addr_sz : integer := 8;
31 31 addr_max_int : integer := 256);
32 32 port(
33 33 clk,raz : in std_logic; --! Horloge et reset general du composant
34 34 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
35 ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
35 36 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'οΏ½criture dans la mοΏ½moire
36 37 empty : out std_logic; --! Flag, MοΏ½moire vide
37 38 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire
38 39 );
39 40 end Fifo_Read;
40 41
41 42 --! @details En aval de la SRAM Gaisler
42 43
43 44 architecture ar_Fifo_Read of Fifo_Read is
44 45
45 46 signal Rad_int : integer range 0 to addr_max_int;
46 47 signal Rad_int_reg : integer range 0 to addr_max_int;
47 48 signal Wad_int : integer range 0 to addr_max_int;
48 49 signal Wad_int_reg : integer range 0 to addr_max_int;
49 50 signal flag_reg : std_logic;
50 51
51 52 begin
52 53 process (clk,raz)
53 54 begin
54 55 if(raz='0')then
55 56 Rad_int <= 0;
56 57 empty <= '1';
57 58
58 59 elsif(clk' event and clk='1')then
59 60 Wad_int_reg <= Wad_int;
60 61 Rad_int_reg <= Rad_int;
61 62 flag_reg <= flag_RE;
63
62 64
63 65 if(flag_reg ='0' and flag_RE='1')then
64 66 if(Rad_int=addr_max_int-1)then
65 67 Rad_int <= 0;
66 68 else
67 69 Rad_int <= Rad_int+1;
68 70 end if;
69 71 end if;
70 72
71 if(Rad_int_reg /= Rad_int)then
72 if(Rad_int=Wad_int)then
73 empty <= '1';
74 else
73 if(ReUse='1')then
74 Rad_int <= 0;
75 empty <= '0';
76 else
77 if(Rad_int_reg /= Rad_int)then
78 if(Rad_int=Wad_int)then
79 empty <= '1';
80 else
81 empty <= '0';
82 end if;
83 elsif(Wad_int_reg /= Wad_int)then
75 84 empty <= '0';
76 end if;
77 elsif(Wad_int_reg /= Wad_int)then
78 empty <= '0';
85 end if;
79 86 end if;
87
80 88 end if;
81 89 end process;
82 90
83 91 Wad_int <= to_integer(unsigned(Waddr));
84 92 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
85 93
86 94 end ar_Fifo_Read; No newline at end of file
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@@ -1,103 +1,106
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 use work.FIFO_Config.all;
26 26
27 27 --! Programme qui va permettre de "pipeliner" la FIFO, donnοΏ½e disponible en sortie dοΏ½ son οΏ½criture en entrοΏ½e de la FIFO
28 28
29 29 entity Link_Reg is
30 30 generic(Data_sz : integer := 16);
31 31 port(
32 32 clk,raz : in std_logic; --! Horloge et reset general du composant
33 33 Data_one : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en entrοΏ½e de la FIFO, cotοΏ½ οΏ½criture
34 34 Data_two : in std_logic_vector(Data_sz-1 downto 0); --! DonnοΏ½e en sortie de la FIFO, cotοΏ½ lecture
35 ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
35 36 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
36 37 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
37 38 empty : in std_logic; --! Flag, MοΏ½moire vide
38 39 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! DonnοΏ½e en sortie, pipelinοΏ½e
39 40 );
40 41 end Link_Reg;
41 42
42 43 architecture ar_Link_Reg of Link_Reg is
43 44
44 45 type etat is (e0,e1,e2,e3);
45 46 signal ect : etat;
46 47
47 48 begin
48 49 process (clk,raz)
49 50 begin
50 51 if(raz='0')then
51 52 Data_out <= (others => 'X');
52 53 ect <= e0;
53 54
54 55 elsif(clk' event and clk='1')then
55 56 case ect is
56 57 when e0 =>
57 58 if(flag_WR='1')then
58 59 Data_out <= Data_one;
59 60 ect <= e1;
61 elsif(ReUse='1')then
62 ect <= e1;
60 63 end if;
61 64
62 65 when e1 =>
63 66 if(flag_RE='1')then
64 67 Data_out <= Data_two;
65 68 ect <= e2;
66 69 end if;
67 70
68 71 when e2 =>
69 72 if(empty='1')then
70 73 ect <= e3;
71 74 else
72 75 Data_out <= Data_two;
73 76 ect <= e2;
74 77 end if;
75 78
76 79 when e3 =>
77 80 Data_out <= Data_two;
78 81 ect <= e0;
79 82
80 83 end case;
81 84 end if;
82 85 end process;
83 86
84 87 end ar_Link_Reg;
85 88
86 89
87 90
88 91
89 92
90 93
91 94
92 95
93 96
94 97
95 98
96 99
97 100
98 101
99 102
100 103
101 104
102 105
103 106
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@@ -1,124 +1,125
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library techmap;
26 26 use techmap.gencomp.all;
27 27 use work.config.all;
28 28 use lpp.lpp_memory.all;
29 29
30 30 --! Programme de la FIFO
31 31
32 32 entity Top_FIFO is
33 33 generic(
34 34 Data_sz : integer := 16;
35 35 Addr_sz : integer := 8;
36 36 addr_max_int : integer := 256
37 37 );
38 38 port(
39 39 clk,raz : in std_logic; --! Horloge et reset general du composant
40 40 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
41 41 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
42 ReUse : in std_logic; --! Flag, Permet de relire la mοΏ½moire du dοΏ½but
42 43 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
43 44 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
44 45 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
45 46 full : out std_logic; --! Flag, MοΏ½moire pleine
46 47 empty : out std_logic; --! Flag, MοΏ½moire vide
47 48 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
48 49 );
49 50 end Top_FIFO;
50 51
51 52 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
52 53 --! associοΏ½e a deux Drivers, un pour οΏ½crire l'autre pour lire cette mοΏ½moire
53 54
54 55 architecture ar_Top_FIFO of Top_FIFO is
55 56
56 57 component syncram_2p
57 58 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0);
58 59 port (
59 60 rclk : in std_ulogic;
60 61 renable : in std_ulogic;
61 62 raddress : in std_logic_vector((abits -1) downto 0);
62 63 dataout : out std_logic_vector((dbits -1) downto 0);
63 64 wclk : in std_ulogic;
64 65 write : in std_ulogic;
65 66 waddress : in std_logic_vector((abits -1) downto 0);
66 67 datain : in std_logic_vector((dbits -1) downto 0));
67 68 end component;
68 69
69 70 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
70 71 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
71 72 signal Data_int : std_logic_vector(Data_sz-1 downto 0);
72 73 signal s_empty : std_logic;
73 74 signal s_full : std_logic;
74 75 signal s_flag_RE : std_logic;
75 76 signal s_flag_WR : std_logic;
76 77
77 78 begin
78 79
79 80 WR : Fifo_Write
80 81 generic map(Addr_sz,addr_max_int)
81 82 port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr);
82 83
83 84
84 85 SRAM : syncram_2p
85 86 generic map(CFG_MEMTECH,Addr_sz,Data_sz)
86 87 port map(clk,s_flag_RE,Raddr,Data_int,clk,s_flag_WR,Waddr,Data_in);
87 88
88 89
89 90 link : Link_Reg
90 91 generic map(Data_sz)
91 port map(clk,raz,Data_in,Data_int,s_flag_RE,s_flag_WR,s_empty,Data_out);
92 port map(clk,raz,Data_in,Data_int,ReUse,s_flag_RE,s_flag_WR,s_empty,Data_out);
92 93
93 94 RE : Fifo_Read
94 95 generic map(Addr_sz,addr_max_int)
95 port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr);
96 port map(clk,raz,s_flag_RE,ReUse,Waddr,s_empty,Raddr);
96 97
97 98 process(clk,raz)
98 99 begin
99 100 if(raz='0')then
100 101 s_flag_RE <= '0';
101 102 s_flag_WR <= '0';
102 103
103 104 elsif(clk'event and clk='1')then
104 105 if(s_full='0')then
105 106 s_flag_WR <= Flag_WR;
106 107 else
107 108 s_flag_WR <= '0';
108 109 end if;
109 110
110 111 if(s_empty='0')then
111 112 s_flag_RE <= Flag_RE;
112 113 else
113 114 s_flag_RE <= '0';
114 115 end if;
115 116
116 117 end if;
117 118 end process;
118 119
119 120 full <= s_full;
120 121 empty <= s_empty;
121 122 Addr_RE <= Raddr;
122 123 Addr_WR <= Waddr;
123 124
124 125 end ar_Top_FIFO; No newline at end of file
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@@ -1,232 +1,236
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_memory is
33 33
34 34 --===========================================================|
35 35 --=================== FIFO ComplοΏ½te =========================|
36 36 --===========================================================|
37 37
38 38 component APB_FIFO is
39 39 generic (
40 40 pindex : integer := 0;
41 41 paddr : integer := 0;
42 42 pmask : integer := 16#fff#;
43 43 pirq : integer := 0;
44 44 abits : integer := 8;
45 45 Data_sz : integer := 16;
46 46 Addr_sz : integer := 8;
47 47 addr_max_int : integer := 256);
48 48 port (
49 49 clk : in std_logic;
50 50 rst : in std_logic;
51 51 apbi : in apb_slv_in_type;
52 52 apbo : out apb_slv_out_type
53 53 );
54 54 end component;
55 55
56 56
57 57 component ApbDriver is
58 58 generic (
59 59 pindex : integer := 0;
60 60 paddr : integer := 0;
61 61 pmask : integer := 16#fff#;
62 62 pirq : integer := 0;
63 63 abits : integer := 8;
64 64 LPP_DEVICE : integer;
65 65 Data_sz : integer := 16;
66 66 Addr_sz : integer := 8;
67 67 addr_max_int : integer := 256);
68 68 port (
69 69 clk : in std_logic;
70 70 rst : in std_logic;
71 71 ReadEnable : in std_logic;
72 72 WriteEnable : in std_logic;
73 73 FlagEmpty : in std_logic;
74 74 FlagFull : in std_logic;
75 ReUse : in std_logic;
75 76 DataIn : out std_logic_vector(Data_sz-1 downto 0);
76 77 DataOut : in std_logic_vector(Data_sz-1 downto 0);
77 78 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
78 79 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
79 80 apbi : in apb_slv_in_type;
80 81 apbo : out apb_slv_out_type
81 82 );
82 83 end component;
83 84
84 85
85 86 component Top_FIFO is
86 87 generic(
87 88 Data_sz : integer := 16;
88 89 Addr_sz : integer := 8;
89 90 addr_max_int : integer := 256
90 91 );
91 92 port(
92 93 clk,raz : in std_logic;
93 94 flag_RE : in std_logic;
94 95 flag_WR : in std_logic;
96 ReUse : in std_logic;
95 97 Data_in : in std_logic_vector(Data_sz-1 downto 0);
96 98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
97 99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
98 100 full : out std_logic;
99 101 empty : out std_logic;
100 102 Data_out : out std_logic_vector(Data_sz-1 downto 0)
101 103 );
102 104 end component;
103 105
104 106
105 107 component Fifo_Read is
106 108 generic(
107 109 Addr_sz : integer := 8;
108 110 addr_max_int : integer := 256);
109 111 port(
110 112 clk : in std_logic;
111 113 raz : in std_logic;
112 114 flag_RE : in std_logic;
115 ReUse : in std_logic;
113 116 Waddr : in std_logic_vector(addr_sz-1 downto 0);
114 117 empty : out std_logic;
115 118 Raddr : out std_logic_vector(addr_sz-1 downto 0)
116 119 );
117 120 end component;
118 121
119 122
120 123 component Fifo_Write is
121 124 generic(
122 125 Addr_sz : integer := 8;
123 126 addr_max_int : integer := 256);
124 127 port(
125 128 clk : in std_logic;
126 129 raz : in std_logic;
127 130 flag_WR : in std_logic;
128 131 Raddr : in std_logic_vector(addr_sz-1 downto 0);
129 132 full : out std_logic;
130 133 Waddr : out std_logic_vector(addr_sz-1 downto 0)
131 134 );
132 135 end component;
133 136
134 137
135 138 component Link_Reg is
136 139 generic(Data_sz : integer := 16);
137 140 port(
138 141 clk,raz : in std_logic;
139 142 Data_one : in std_logic_vector(Data_sz-1 downto 0);
140 143 Data_two : in std_logic_vector(Data_sz-1 downto 0);
144 ReUse : in std_logic;
141 145 flag_RE : in std_logic;
142 146 flag_WR : in std_logic;
143 147 empty : in std_logic;
144 148 Data_out : out std_logic_vector(Data_sz-1 downto 0)
145 149 );
146 150 end component;
147 151
148 152 --===========================================================|
149 153 --================= Demi FIFO Ecriture ======================|
150 154 --===========================================================|
151 155
152 156 component APB_FifoWrite is
153 157 generic (
154 158 pindex : integer := 0;
155 159 paddr : integer := 0;
156 160 pmask : integer := 16#fff#;
157 161 pirq : integer := 0;
158 162 abits : integer := 8;
159 163 Data_sz : integer := 16;
160 164 Addr_sz : integer := 8;
161 165 addr_max_int : integer := 256);
162 166 port (
163 167 clk : in std_logic;
164 168 rst : in std_logic;
165 169 apbi : in apb_slv_in_type;
166 170 apbo : out apb_slv_out_type
167 171 );
168 172 end component;
169 173
170 174
171 175 component Top_FifoWrite is
172 176 generic(
173 177 Data_sz : integer := 16;
174 178 Addr_sz : integer := 8;
175 179 addr_max_int : integer := 256);
176 180 port(
177 181 clk : in std_logic;
178 182 raz : in std_logic;
179 183 flag_RE : in std_logic;
180 184 flag_WR : in std_logic;
181 185 Data_in : in std_logic_vector(Data_sz-1 downto 0);
182 186 Raddr : in std_logic_vector(addr_sz-1 downto 0);
183 187 full : out std_logic;
184 188 empty : out std_logic;
185 189 Waddr : out std_logic_vector(addr_sz-1 downto 0);
186 190 Data_out : out std_logic_vector(Data_sz-1 downto 0)
187 191 );
188 192 end component;
189 193
190 194 --===========================================================|
191 195 --================== Demi FIFO Lecture ======================|
192 196 --===========================================================|
193 197
194 198 component APB_FifoRead is
195 199 generic (
196 200 pindex : integer := 0;
197 201 paddr : integer := 0;
198 202 pmask : integer := 16#fff#;
199 203 pirq : integer := 0;
200 204 abits : integer := 8;
201 205 Data_sz : integer := 16;
202 206 Addr_sz : integer := 8;
203 207 addr_max_int : integer := 256);
204 208 port (
205 209 clk : in std_logic;
206 210 rst : in std_logic;
207 211 apbi : in apb_slv_in_type;
208 212 apbo : out apb_slv_out_type
209 213 );
210 214 end component;
211 215
212 216
213 217 component Top_FifoRead is
214 218 generic(
215 219 Data_sz : integer := 16;
216 220 Addr_sz : integer := 8;
217 221 addr_max_int : integer := 256);
218 222 port(
219 223 clk : in std_logic;
220 224 raz : in std_logic;
221 225 flag_RE : in std_logic;
222 226 flag_WR : in std_logic;
223 227 Data_in : in std_logic_vector(Data_sz-1 downto 0);
224 228 Waddr : in std_logic_vector(addr_sz-1 downto 0);
225 229 full : out std_logic;
226 230 empty : out std_logic;
227 231 Raddr : out std_logic_vector(addr_sz-1 downto 0);
228 232 Data_out : out std_logic_vector(Data_sz-1 downto 0)
229 233 );
230 234 end component;
231 235
232 236 end;
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