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1 | 1 | # Top Level Design Parameters |
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2 | 2 | |
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3 | 3 | # Clocks |
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4 | 4 | |
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5 | 5 | create_clock -period 10.000000 -waveform {0.000000 5.000000} clk100MHz |
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6 | 6 | create_clock -period 20.344999 -waveform {0.000000 10.172500} clk49_152MHz |
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7 | 7 | create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q |
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8 | 8 | create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q |
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9 | 9 | create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q |
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10 |
create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} { |
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10 | create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {spw1_din spw1_sin spw2_din spw2_sin} | |
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11 | 11 | |
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12 | 12 | |
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13 | 13 | # False Paths Between Clocks |
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14 | 14 | |
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15 | 15 | |
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16 | 16 | # False Path Constraints |
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17 | 17 | |
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18 | 18 | |
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19 | 19 | # Maximum Delay Constraints |
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20 | 20 | |
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21 | 21 | |
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22 | 22 | # Multicycle Constraints |
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23 | 23 | |
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24 | 24 | |
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25 | 25 | # Virtual Clocks |
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26 | 26 | # Output Load Constraints |
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27 | 27 | # Driving Cell Constraints |
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28 | 28 | # Wire Loads |
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29 | 29 | # set_wire_load_mode top |
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30 | 30 | |
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31 | 31 | # Other Constraints |
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