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Add an arbitration in front of FFT based on Pong Status
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r380:77969963e689 (MINI-LFR) WFP_MS-0-1-17 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000110") -- aa.bb.cc version
431 top_lfr_version => X"000111") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "000" =>
533 WHEN "000" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "011" =>
572 WHEN "011" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,232 +1,44
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
3 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
4 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
5 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
6 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
7 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
8 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
9 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
10 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
11 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg
12 add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi
13 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo
14 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -group debug /tb/ready_reg
15 add wave -noupdate -group debug /tb/ready_reg
16 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
16 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
17 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
18 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_0
20 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_ms_1/observation_vector_0(2) {-color Blue} /tb/lpp_lfr_ms_1/observation_vector_0(0) {-color Blue}} /tb/lpp_lfr_ms_1/observation_vector_0
21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
22 add wave -noupdate -divider {New Divider}
22 add wave -noupdate -divider {New Divider}
23 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
23 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter
24 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
24 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_out
25 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
25 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fft_1/corefft_1/counter_wait
26 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
27 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
28 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
29 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
30 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
31 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
32 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
33 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
34 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
35 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
36 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
37 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
38 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
39 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
40 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
41 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
42 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
43 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
44 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
45 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
46 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
47 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
48 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
49 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
50 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
51 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
52 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
53 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
54 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
55 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
56 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
57 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
58 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
59 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
60 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
61 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
62 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
63 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
64 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
65 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
66 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
67 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
68 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
69 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
72 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
73 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
74 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
75 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
76 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
77 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
78 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
79 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
80 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
81 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
82 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
83 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
84 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
85 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
86 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
87 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
88 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
89 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
90 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
91 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
92 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
93 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
94 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
95 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
96 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
97 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
98 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
99 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
100 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
101 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
102 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
103 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
104 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
105 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
106 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
107 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
108 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
109 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
110 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
111 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
112 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
113 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
114 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
115 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
116 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
117 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
118 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
119 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
120 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
121 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
122 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
123 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
124 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
125 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
126 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
127 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
128 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
129 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
130 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
131 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
132 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
133 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
134 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
135 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
136 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
137 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
138 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
139 add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
140 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
141 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
142 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
143 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
144 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
145 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
146 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
147 add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
148 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
149 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
150 add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
151 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
152 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
153 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
154 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
155 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
156 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
157 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
158 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
159 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
160 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp
161 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
162 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
163 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
164 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
165 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
166 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
167 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
168 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
169 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
170 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
171 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
172 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
173 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
174 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
175 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
176 add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time
177 add wave -noupdate /tb/lpp_lfr_ms_1/fine_time
178 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time
179 add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
180 add wave -noupdate /tb/lpp_lfr_ms_1/status_component
181 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
182 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
183 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms
184 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component
185 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel
186 add wave -noupdate /tb/lpp_lfr_ms_1/all_time
187 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a
188 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b
189 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1
190 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2
191 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen
192 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren
193 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata
194 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full
195 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty
196 add wave -noupdate /tb/matrix_time_f0
197 add wave -noupdate /tb/matrix_time_f1
198 add wave -noupdate /tb/matrix_time_f2
199 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
200 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
201 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
202 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
203 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
204 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
205 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
206 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
207 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
208 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
209 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
210 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
211 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
212 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
213 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
214 TreeUpdate [SetDefaultTree]
26 TreeUpdate [SetDefaultTree]
215 WaveRestoreCursors {{Cursor 1} {137412164208 ps} 0}
27 WaveRestoreCursors {{Cursor 1} {20859515887 ps} 0}
216 configure wave -namecolwidth 486
28 configure wave -namecolwidth 253
217 configure wave -valuecolwidth 112
29 configure wave -valuecolwidth 112
218 configure wave -justifyvalue left
30 configure wave -justifyvalue left
219 configure wave -signalnamewidth 0
31 configure wave -signalnamewidth 0
220 configure wave -snapdistance 10
32 configure wave -snapdistance 10
221 configure wave -datasetprefix 0
33 configure wave -datasetprefix 0
222 configure wave -rowmargin 4
34 configure wave -rowmargin 4
223 configure wave -childrowmargin 2
35 configure wave -childrowmargin 2
224 configure wave -gridoffset 0
36 configure wave -gridoffset 0
225 configure wave -gridperiod 1
37 configure wave -gridperiod 1
226 configure wave -griddelta 40
38 configure wave -griddelta 40
227 configure wave -timeline 0
39 configure wave -timeline 0
228 configure wave -timelineunits ps
40 configure wave -timelineunits ps
229 update
41 update
230 WaveRestoreZoom {0 ps} {787501102500 ps}
42 WaveRestoreZoom {20840058904 ps} {20863099265 ps}
231 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
43 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
232 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
44 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,954 +1,970
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63
63
64 -- Reg In
64 -- Reg In
65 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
68
68
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78
78
79 );
79 );
80 END;
80 END;
81
81
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83
83
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89
89
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95
95
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100
100
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102
102
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107
107
108 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
111
111
112 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116
116
117 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
118 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123
123
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128
128
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 -- FSM LOAD FFT
130 -- FSM LOAD FFT
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135
135
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141
141
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- FFT
144 -- FFT
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
152 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176
176
177 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
184
184
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188
188
189 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
192 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
195
195
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207
207
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 -- TIME REG & INFOs
209 -- TIME REG & INFOs
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212
212
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217
217
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222
222
223 --SIGNAL time_update_f0_A : STD_LOGIC;
223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
227 --
227 --
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231
231
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237
237 SIGNAL ping_npong : STD_LOGIC;
238 SIGNAL sample_load_reg : STD_LOGIC;
239
238 BEGIN
240 BEGIN
239
241
240
242
241 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
243 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
242
244
243
245
244 switch_f0_inst : spectral_matrix_switch_f0
246 switch_f0_inst : spectral_matrix_switch_f0
245 PORT MAP (
247 PORT MAP (
246 clk => clk,
248 clk => clk,
247 rstn => rstn,
249 rstn => rstn,
248
250
249 sample_wen => sample_f0_wen,
251 sample_wen => sample_f0_wen,
250
252
251 fifo_A_empty => sample_f0_A_empty,
253 fifo_A_empty => sample_f0_A_empty,
252 fifo_A_full => sample_f0_A_full,
254 fifo_A_full => sample_f0_A_full,
253 fifo_A_wen => sample_f0_A_wen,
255 fifo_A_wen => sample_f0_A_wen,
254
256
255 fifo_B_empty => sample_f0_B_empty,
257 fifo_B_empty => sample_f0_B_empty,
256 fifo_B_full => sample_f0_B_full,
258 fifo_B_full => sample_f0_B_full,
257 fifo_B_wen => sample_f0_B_wen,
259 fifo_B_wen => sample_f0_B_wen,
258
260
259 error_wen => error_wen_f0); -- TODO
261 error_wen => error_wen_f0); -- TODO
260
262
261 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
262 -- FIFO IN
264 -- FIFO IN
263 -----------------------------------------------------------------------------
265 -----------------------------------------------------------------------------
264 lppFIFOxN_f0_a : lppFIFOxN
266 lppFIFOxN_f0_a : lppFIFOxN
265 GENERIC MAP (
267 GENERIC MAP (
266 tech => 0,
268 tech => 0,
267 Mem_use => Mem_use,
269 Mem_use => Mem_use,
268 Data_sz => 16,
270 Data_sz => 16,
269 Addr_sz => 8,
271 Addr_sz => 8,
270 FifoCnt => 5)
272 FifoCnt => 5)
271 PORT MAP (
273 PORT MAP (
272 clk => clk,
274 clk => clk,
273 rstn => rstn,
275 rstn => rstn,
274
276
275 ReUse => (OTHERS => '0'),
277 ReUse => (OTHERS => '0'),
276
278
277 wen => sample_f0_A_wen,
279 wen => sample_f0_A_wen,
278 wdata => sample_f0_wdata,
280 wdata => sample_f0_wdata,
279
281
280 ren => sample_f0_A_ren,
282 ren => sample_f0_A_ren,
281 rdata => sample_f0_A_rdata,
283 rdata => sample_f0_A_rdata,
282
284
283 empty => sample_f0_A_empty,
285 empty => sample_f0_A_empty,
284 full => sample_f0_A_full,
286 full => sample_f0_A_full,
285 almost_full => OPEN);
287 almost_full => OPEN);
286
288
287 lppFIFOxN_f0_b : lppFIFOxN
289 lppFIFOxN_f0_b : lppFIFOxN
288 GENERIC MAP (
290 GENERIC MAP (
289 tech => 0,
291 tech => 0,
290 Mem_use => Mem_use,
292 Mem_use => Mem_use,
291 Data_sz => 16,
293 Data_sz => 16,
292 Addr_sz => 8,
294 Addr_sz => 8,
293 FifoCnt => 5)
295 FifoCnt => 5)
294 PORT MAP (
296 PORT MAP (
295 clk => clk,
297 clk => clk,
296 rstn => rstn,
298 rstn => rstn,
297
299
298 ReUse => (OTHERS => '0'),
300 ReUse => (OTHERS => '0'),
299
301
300 wen => sample_f0_B_wen,
302 wen => sample_f0_B_wen,
301 wdata => sample_f0_wdata,
303 wdata => sample_f0_wdata,
302 ren => sample_f0_B_ren,
304 ren => sample_f0_B_ren,
303 rdata => sample_f0_B_rdata,
305 rdata => sample_f0_B_rdata,
304 empty => sample_f0_B_empty,
306 empty => sample_f0_B_empty,
305 full => sample_f0_B_full,
307 full => sample_f0_B_full,
306 almost_full => OPEN);
308 almost_full => OPEN);
307
309
308 lppFIFOxN_f1 : lppFIFOxN
310 lppFIFOxN_f1 : lppFIFOxN
309 GENERIC MAP (
311 GENERIC MAP (
310 tech => 0,
312 tech => 0,
311 Mem_use => Mem_use,
313 Mem_use => Mem_use,
312 Data_sz => 16,
314 Data_sz => 16,
313 Addr_sz => 8,
315 Addr_sz => 8,
314 FifoCnt => 5)
316 FifoCnt => 5)
315 PORT MAP (
317 PORT MAP (
316 clk => clk,
318 clk => clk,
317 rstn => rstn,
319 rstn => rstn,
318
320
319 ReUse => (OTHERS => '0'),
321 ReUse => (OTHERS => '0'),
320
322
321 wen => sample_f1_wen,
323 wen => sample_f1_wen,
322 wdata => sample_f1_wdata,
324 wdata => sample_f1_wdata,
323 ren => sample_f1_ren,
325 ren => sample_f1_ren,
324 rdata => sample_f1_rdata,
326 rdata => sample_f1_rdata,
325 empty => sample_f1_empty,
327 empty => sample_f1_empty,
326 full => sample_f1_full,
328 full => sample_f1_full,
327 almost_full => sample_f1_almost_full);
329 almost_full => sample_f1_almost_full);
328
330
329
331
330 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
332 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
331
333
332 PROCESS (clk, rstn)
334 PROCESS (clk, rstn)
333 BEGIN -- PROCESS
335 BEGIN -- PROCESS
334 IF rstn = '0' THEN -- asynchronous reset (active low)
336 IF rstn = '0' THEN -- asynchronous reset (active low)
335 one_sample_f1_full <= '0';
337 one_sample_f1_full <= '0';
336 error_wen_f1 <= '0';
338 error_wen_f1 <= '0';
337 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
339 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
338 IF sample_f1_full = "00000" THEN
340 IF sample_f1_full = "00000" THEN
339 one_sample_f1_full <= '0';
341 one_sample_f1_full <= '0';
340 ELSE
342 ELSE
341 one_sample_f1_full <= '1';
343 one_sample_f1_full <= '1';
342 END IF;
344 END IF;
343 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
345 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
344 END IF;
346 END IF;
345 END PROCESS;
347 END PROCESS;
346
348
347
349
348 lppFIFOxN_f2 : lppFIFOxN
350 lppFIFOxN_f2 : lppFIFOxN
349 GENERIC MAP (
351 GENERIC MAP (
350 tech => 0,
352 tech => 0,
351 Mem_use => Mem_use,
353 Mem_use => Mem_use,
352 Data_sz => 16,
354 Data_sz => 16,
353 Addr_sz => 8,
355 Addr_sz => 8,
354 FifoCnt => 5)
356 FifoCnt => 5)
355 PORT MAP (
357 PORT MAP (
356 clk => clk,
358 clk => clk,
357 rstn => rstn,
359 rstn => rstn,
358
360
359 ReUse => (OTHERS => '0'),
361 ReUse => (OTHERS => '0'),
360
362
361 wen => sample_f2_wen,
363 wen => sample_f2_wen,
362 wdata => sample_f2_wdata,
364 wdata => sample_f2_wdata,
363 ren => sample_f2_ren,
365 ren => sample_f2_ren,
364 rdata => sample_f2_rdata,
366 rdata => sample_f2_rdata,
365 empty => sample_f2_empty,
367 empty => sample_f2_empty,
366 full => sample_f2_full,
368 full => sample_f2_full,
367 almost_full => OPEN);
369 almost_full => OPEN);
368
370
369
371
370 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
372 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
371
373
372 PROCESS (clk, rstn)
374 PROCESS (clk, rstn)
373 BEGIN -- PROCESS
375 BEGIN -- PROCESS
374 IF rstn = '0' THEN -- asynchronous reset (active low)
376 IF rstn = '0' THEN -- asynchronous reset (active low)
375 one_sample_f2_full <= '0';
377 one_sample_f2_full <= '0';
376 error_wen_f2 <= '0';
378 error_wen_f2 <= '0';
377 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
379 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
378 IF sample_f2_full = "00000" THEN
380 IF sample_f2_full = "00000" THEN
379 one_sample_f2_full <= '0';
381 one_sample_f2_full <= '0';
380 ELSE
382 ELSE
381 one_sample_f2_full <= '1';
383 one_sample_f2_full <= '1';
382 END IF;
384 END IF;
383 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
385 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
384 END IF;
386 END IF;
385 END PROCESS;
387 END PROCESS;
386
388
387 -----------------------------------------------------------------------------
389 -----------------------------------------------------------------------------
388 -- FSM SELECT CHANNEL
390 -- FSM SELECT CHANNEL
389 -----------------------------------------------------------------------------
391 -----------------------------------------------------------------------------
390 PROCESS (clk, rstn)
392 PROCESS (clk, rstn)
391 BEGIN
393 BEGIN
392 IF rstn = '0' THEN
394 IF rstn = '0' THEN
393 state_fsm_select_channel <= IDLE;
395 state_fsm_select_channel <= IDLE;
394 ELSIF clk'EVENT AND clk = '1' THEN
396 ELSIF clk'EVENT AND clk = '1' THEN
395 CASE state_fsm_select_channel IS
397 CASE state_fsm_select_channel IS
396 WHEN IDLE =>
398 WHEN IDLE =>
397 IF sample_f1_full = "11111" THEN
399 IF sample_f1_full = "11111" THEN
398 state_fsm_select_channel <= SWITCH_F1;
400 state_fsm_select_channel <= SWITCH_F1;
399 ELSIF sample_f1_almost_full = "00000" THEN
401 ELSIF sample_f1_almost_full = "00000" THEN
400 IF sample_f0_A_full = "11111" THEN
402 IF sample_f0_A_full = "11111" THEN
401 state_fsm_select_channel <= SWITCH_F0_A;
403 state_fsm_select_channel <= SWITCH_F0_A;
402 ELSIF sample_f0_B_full = "11111" THEN
404 ELSIF sample_f0_B_full = "11111" THEN
403 state_fsm_select_channel <= SWITCH_F0_B;
405 state_fsm_select_channel <= SWITCH_F0_B;
404 ELSIF sample_f2_full = "11111" THEN
406 ELSIF sample_f2_full = "11111" THEN
405 state_fsm_select_channel <= SWITCH_F2;
407 state_fsm_select_channel <= SWITCH_F2;
406 END IF;
408 END IF;
407 END IF;
409 END IF;
408
410
409 WHEN SWITCH_F0_A =>
411 WHEN SWITCH_F0_A =>
410 IF sample_f0_A_empty = "11111" THEN
412 IF sample_f0_A_empty = "11111" THEN
411 state_fsm_select_channel <= IDLE;
413 state_fsm_select_channel <= IDLE;
412 END IF;
414 END IF;
413 WHEN SWITCH_F0_B =>
415 WHEN SWITCH_F0_B =>
414 IF sample_f0_B_empty = "11111" THEN
416 IF sample_f0_B_empty = "11111" THEN
415 state_fsm_select_channel <= IDLE;
417 state_fsm_select_channel <= IDLE;
416 END IF;
418 END IF;
417 WHEN SWITCH_F1 =>
419 WHEN SWITCH_F1 =>
418 IF sample_f1_empty = "11111" THEN
420 IF sample_f1_empty = "11111" THEN
419 state_fsm_select_channel <= IDLE;
421 state_fsm_select_channel <= IDLE;
420 END IF;
422 END IF;
421 WHEN SWITCH_F2 =>
423 WHEN SWITCH_F2 =>
422 IF sample_f2_empty = "11111" THEN
424 IF sample_f2_empty = "11111" THEN
423 state_fsm_select_channel <= IDLE;
425 state_fsm_select_channel <= IDLE;
424 END IF;
426 END IF;
425 WHEN OTHERS => NULL;
427 WHEN OTHERS => NULL;
426 END CASE;
428 END CASE;
427
429
428 END IF;
430 END IF;
429 END PROCESS;
431 END PROCESS;
430
432
431 PROCESS (clk, rstn)
433 PROCESS (clk, rstn)
432 BEGIN
434 BEGIN
433 IF rstn = '0' THEN
435 IF rstn = '0' THEN
434 pre_state_fsm_select_channel <= IDLE;
436 pre_state_fsm_select_channel <= IDLE;
435 ELSIF clk'EVENT AND clk = '1' THEN
437 ELSIF clk'EVENT AND clk = '1' THEN
436 pre_state_fsm_select_channel <= state_fsm_select_channel;
438 pre_state_fsm_select_channel <= state_fsm_select_channel;
437 END IF;
439 END IF;
438 END PROCESS;
440 END PROCESS;
439
441
440
442
441 -----------------------------------------------------------------------------
443 -----------------------------------------------------------------------------
442 -- SWITCH SELECT CHANNEL
444 -- SWITCH SELECT CHANNEL
443 -----------------------------------------------------------------------------
445 -----------------------------------------------------------------------------
444 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
446 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
445 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
447 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
446 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
448 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
447 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
449 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
448 (OTHERS => '1');
450 (OTHERS => '1');
449
451
450 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
452 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
451 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
453 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
452 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
454 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
453 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
455 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
454 (OTHERS => '0');
456 (OTHERS => '0');
455
457
456 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
458 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
457 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
459 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
458 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
460 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
459 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
461 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
460
462
461
463
462 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
464 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
463 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
465 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
464 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
466 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
465 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
467 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
466
468
467
469
468 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
470 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
469 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
471 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
470 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
472 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
471 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
473 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
472
474
473 -----------------------------------------------------------------------------
475 -----------------------------------------------------------------------------
474 -- FSM LOAD FFT
476 -- FSM LOAD FFT
475 -----------------------------------------------------------------------------
477 -----------------------------------------------------------------------------
476
478
477 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
479 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
478
480
479 PROCESS (clk, rstn)
481 PROCESS (clk, rstn)
480 BEGIN
482 BEGIN
481 IF rstn = '0' THEN
483 IF rstn = '0' THEN
482 sample_ren_s <= (OTHERS => '1');
484 sample_ren_s <= (OTHERS => '1');
483 state_fsm_load_FFT <= IDLE;
485 state_fsm_load_FFT <= IDLE;
484 status_MS_input <= (OTHERS => '0');
486 status_MS_input <= (OTHERS => '0');
485 --next_state_fsm_load_FFT <= IDLE;
487 --next_state_fsm_load_FFT <= IDLE;
486 --sample_valid <= '0';
488 --sample_valid <= '0';
487 ELSIF clk'EVENT AND clk = '1' THEN
489 ELSIF clk'EVENT AND clk = '1' THEN
488 CASE state_fsm_load_FFT IS
490 CASE state_fsm_load_FFT IS
489 WHEN IDLE =>
491 WHEN IDLE =>
490 --sample_valid <= '0';
492 --sample_valid <= '0';
491 sample_ren_s <= (OTHERS => '1');
493 sample_ren_s <= (OTHERS => '1');
492 IF sample_full = "11111" AND sample_load = '1' THEN
494 IF sample_full = "11111" AND sample_load = '1' THEN
493 state_fsm_load_FFT <= FIFO_1;
495 state_fsm_load_FFT <= FIFO_1;
494 status_MS_input <= status_channel;
496 status_MS_input <= status_channel;
495 END IF;
497 END IF;
496
498
497 WHEN FIFO_1 =>
499 WHEN FIFO_1 =>
498 sample_ren_s <= "1111" & NOT(sample_load);
500 sample_ren_s <= "1111" & NOT(sample_load);
499 IF sample_empty(0) = '1' THEN
501 IF sample_empty(0) = '1' THEN
500 sample_ren_s <= (OTHERS => '1');
502 sample_ren_s <= (OTHERS => '1');
501 state_fsm_load_FFT <= FIFO_2;
503 state_fsm_load_FFT <= FIFO_2;
502 END IF;
504 END IF;
503
505
504 WHEN FIFO_2 =>
506 WHEN FIFO_2 =>
505 sample_ren_s <= "111" & NOT(sample_load) & '1';
507 sample_ren_s <= "111" & NOT(sample_load) & '1';
506 IF sample_empty(1) = '1' THEN
508 IF sample_empty(1) = '1' THEN
507 sample_ren_s <= (OTHERS => '1');
509 sample_ren_s <= (OTHERS => '1');
508 state_fsm_load_FFT <= FIFO_3;
510 state_fsm_load_FFT <= FIFO_3;
509 END IF;
511 END IF;
510
512
511 WHEN FIFO_3 =>
513 WHEN FIFO_3 =>
512 sample_ren_s <= "11" & NOT(sample_load) & "11";
514 sample_ren_s <= "11" & NOT(sample_load) & "11";
513 IF sample_empty(2) = '1' THEN
515 IF sample_empty(2) = '1' THEN
514 sample_ren_s <= (OTHERS => '1');
516 sample_ren_s <= (OTHERS => '1');
515 state_fsm_load_FFT <= FIFO_4;
517 state_fsm_load_FFT <= FIFO_4;
516 END IF;
518 END IF;
517
519
518 WHEN FIFO_4 =>
520 WHEN FIFO_4 =>
519 sample_ren_s <= '1' & NOT(sample_load) & "111";
521 sample_ren_s <= '1' & NOT(sample_load) & "111";
520 IF sample_empty(3) = '1' THEN
522 IF sample_empty(3) = '1' THEN
521 sample_ren_s <= (OTHERS => '1');
523 sample_ren_s <= (OTHERS => '1');
522 state_fsm_load_FFT <= FIFO_5;
524 state_fsm_load_FFT <= FIFO_5;
523 END IF;
525 END IF;
524
526
525 WHEN FIFO_5 =>
527 WHEN FIFO_5 =>
526 sample_ren_s <= NOT(sample_load) & "1111";
528 sample_ren_s <= NOT(sample_load) & "1111";
527 IF sample_empty(4) = '1' THEN
529 IF sample_empty(4) = '1' THEN
528 sample_ren_s <= (OTHERS => '1');
530 sample_ren_s <= (OTHERS => '1');
529 state_fsm_load_FFT <= IDLE;
531 state_fsm_load_FFT <= IDLE;
530 END IF;
532 END IF;
531 WHEN OTHERS => NULL;
533 WHEN OTHERS => NULL;
532 END CASE;
534 END CASE;
533 END IF;
535 END IF;
534 END PROCESS;
536 END PROCESS;
535
537
536 PROCESS (clk, rstn)
538 PROCESS (clk, rstn)
537 BEGIN
539 BEGIN
538 IF rstn = '0' THEN
540 IF rstn = '0' THEN
539 sample_valid_r <= '0';
541 sample_valid_r <= '0';
540 next_state_fsm_load_FFT <= IDLE;
542 next_state_fsm_load_FFT <= IDLE;
541 ELSIF clk'EVENT AND clk = '1' THEN
543 ELSIF clk'EVENT AND clk = '1' THEN
542 next_state_fsm_load_FFT <= state_fsm_load_FFT;
544 next_state_fsm_load_FFT <= state_fsm_load_FFT;
543 IF sample_ren_s = "11111" THEN
545 IF sample_ren_s = "11111" THEN
544 sample_valid_r <= '0';
546 sample_valid_r <= '0';
545 ELSE
547 ELSE
546 sample_valid_r <= '1';
548 sample_valid_r <= '1';
547 END IF;
549 END IF;
548 END IF;
550 END IF;
549 END PROCESS;
551 END PROCESS;
550
552
551 sample_valid <= sample_valid_r AND sample_load;
553 -- sample_valid <= sample_valid_r AND sample_load;
554 sample_valid <= sample_valid_r AND (sample_load AND (ping_npong AND fft_pong));
552
555
553 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
556 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
554 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
557 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
555 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
558 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
556 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
559 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
557 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
560 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
558
561
559 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
560 -- FFT
563 -- FFT
561 -----------------------------------------------------------------------------
564 -----------------------------------------------------------------------------
562 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
565 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
563 PORT MAP (
566 PORT MAP (
564 clk => clk,
567 clk => clk,
565 rstn => rstn,
568 rstn => rstn,
566 sample_valid => sample_valid,
569 sample_valid => sample_valid,
567 fft_read => fft_read,
570 fft_read => fft_read,
568 sample_data => sample_data,
571 sample_data => sample_data,
569 sample_load => sample_load,
572 sample_load => sample_load,
570 fft_pong => fft_pong,
573 fft_pong => fft_pong,
571 fft_data_im => fft_data_im,
574 fft_data_im => fft_data_im,
572 fft_data_re => fft_data_re,
575 fft_data_re => fft_data_re,
573 fft_data_valid => fft_data_valid,
576 fft_data_valid => fft_data_valid,
574 fft_ready => fft_ready);
577 fft_ready => fft_ready);
575
578
576 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
579 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
577 fft_data_valid & --4
580 fft_data_valid & --4
578 fft_pong & --3
581 fft_pong & --3
579 sample_load & --2
582 sample_load & --2
580 fft_read & --1
583 fft_read & --1
581 sample_valid; --0
584 sample_valid; --0
582
585
586 -----------------------------------------------------------------------------
587 PROCESS (clk, rstn)
588 BEGIN
589 IF rstn = '0' THEN
590 ping_npong <= '0';
591 sample_load_reg <= '0';
592 ELSIF clk'event AND clk = '1' THEN
593 sample_load_reg <= sample_load;
594 IF sample_load_reg = '1' AND sample_load = '0' THEN
595 ping_npong <= NOT ping_npong;
596 END IF;
597 END IF;
598 END PROCESS;
583
599
584 -----------------------------------------------------------------------------
600 -----------------------------------------------------------------------------
585 PROCESS (clk, rstn)
601 PROCESS (clk, rstn)
586 BEGIN
602 BEGIN
587 IF rstn = '0' THEN
603 IF rstn = '0' THEN
588 state_fsm_load_MS_memory <= IDLE;
604 state_fsm_load_MS_memory <= IDLE;
589 current_fifo_load <= "00001";
605 current_fifo_load <= "00001";
590 ELSIF clk'EVENT AND clk = '1' THEN
606 ELSIF clk'EVENT AND clk = '1' THEN
591 CASE state_fsm_load_MS_memory IS
607 CASE state_fsm_load_MS_memory IS
592 WHEN IDLE =>
608 WHEN IDLE =>
593 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
609 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
594 state_fsm_load_MS_memory <= LOAD_FIFO;
610 state_fsm_load_MS_memory <= LOAD_FIFO;
595 END IF;
611 END IF;
596 WHEN LOAD_FIFO =>
612 WHEN LOAD_FIFO =>
597 IF current_fifo_full = '1' THEN
613 IF current_fifo_full = '1' THEN
598 state_fsm_load_MS_memory <= TRASH_FFT;
614 state_fsm_load_MS_memory <= TRASH_FFT;
599 END IF;
615 END IF;
600 WHEN TRASH_FFT =>
616 WHEN TRASH_FFT =>
601 IF fft_ready = '0' THEN
617 IF fft_ready = '0' THEN
602 state_fsm_load_MS_memory <= IDLE;
618 state_fsm_load_MS_memory <= IDLE;
603 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
619 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
604 END IF;
620 END IF;
605 WHEN OTHERS => NULL;
621 WHEN OTHERS => NULL;
606 END CASE;
622 END CASE;
607
623
608 END IF;
624 END IF;
609 END PROCESS;
625 END PROCESS;
610
626
611 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
627 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
612 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
628 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
613 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
629 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
614 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
630 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
615 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
631 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
616
632
617 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
633 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
618 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
634 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
619 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
635 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
620 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
636 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
621 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
637 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
622
638
623 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
639 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
624 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
640 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
625 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
641 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
626 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
642 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
627 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
643 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
628
644
629 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
645 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
630
646
631 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
647 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
632 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
648 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
633 AND state_fsm_load_MS_memory = LOAD_FIFO
649 AND state_fsm_load_MS_memory = LOAD_FIFO
634 AND current_fifo_load(I) = '1'
650 AND current_fifo_load(I) = '1'
635 ELSE '1';
651 ELSE '1';
636 END GENERATE all_fifo;
652 END GENERATE all_fifo;
637
653
638 PROCESS (clk, rstn)
654 PROCESS (clk, rstn)
639 BEGIN
655 BEGIN
640 IF rstn = '0' THEN
656 IF rstn = '0' THEN
641 MEM_IN_SM_wen <= (OTHERS => '1');
657 MEM_IN_SM_wen <= (OTHERS => '1');
642 ELSIF clk'EVENT AND clk = '1' THEN
658 ELSIF clk'EVENT AND clk = '1' THEN
643 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
659 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
644 END IF;
660 END IF;
645 END PROCESS;
661 END PROCESS;
646
662
647 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
663 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
648 (fft_data_im & fft_data_re) &
664 (fft_data_im & fft_data_re) &
649 (fft_data_im & fft_data_re) &
665 (fft_data_im & fft_data_re) &
650 (fft_data_im & fft_data_re) &
666 (fft_data_im & fft_data_re) &
651 (fft_data_im & fft_data_re);
667 (fft_data_im & fft_data_re);
652 -----------------------------------------------------------------------------
668 -----------------------------------------------------------------------------
653
669
654
670
655 -----------------------------------------------------------------------------
671 -----------------------------------------------------------------------------
656 Mem_In_SpectralMatrix : lppFIFOxN
672 Mem_In_SpectralMatrix : lppFIFOxN
657 GENERIC MAP (
673 GENERIC MAP (
658 tech => 0,
674 tech => 0,
659 Mem_use => Mem_use,
675 Mem_use => Mem_use,
660 Data_sz => 32, --16,
676 Data_sz => 32, --16,
661 Addr_sz => 7, --8
677 Addr_sz => 7, --8
662 FifoCnt => 5)
678 FifoCnt => 5)
663 PORT MAP (
679 PORT MAP (
664 clk => clk,
680 clk => clk,
665 rstn => rstn,
681 rstn => rstn,
666
682
667 ReUse => MEM_IN_SM_ReUse,
683 ReUse => MEM_IN_SM_ReUse,
668
684
669 wen => MEM_IN_SM_wen,
685 wen => MEM_IN_SM_wen,
670 wdata => MEM_IN_SM_wData,
686 wdata => MEM_IN_SM_wData,
671
687
672 ren => MEM_IN_SM_ren,
688 ren => MEM_IN_SM_ren,
673 rdata => MEM_IN_SM_rData,
689 rdata => MEM_IN_SM_rData,
674 full => MEM_IN_SM_Full,
690 full => MEM_IN_SM_Full,
675 empty => MEM_IN_SM_Empty,
691 empty => MEM_IN_SM_Empty,
676 almost_full => OPEN);
692 almost_full => OPEN);
677
693
678 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
679
695
680 observation_vector_1(11 DOWNTO 0) <= "0000" &
696 observation_vector_1(11 DOWNTO 0) <= "0000" &
681 SM_correlation_start & --7
697 SM_correlation_start & --7
682 status_MS_input(1 DOWNTO 0)& --6..5
698 status_MS_input(1 DOWNTO 0)& --6..5
683 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
699 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
684
700
685 observation_vector_0(11 DOWNTO 6) <= MEM_IN_SM_locked(0) &
701 observation_vector_0(11 DOWNTO 6) <= MEM_IN_SM_locked(0) &
686 SM_correlation_done & --4
702 SM_correlation_done & --4
687 SM_correlation_auto & --3
703 SM_correlation_auto & --3
688 SM_correlation_start & --2
704 SM_correlation_start & --2
689 status_component(5 DOWNTO 4); --1..0
705 status_component(5 DOWNTO 4); --1..0
690 -----------------------------------------------------------------------------
706 -----------------------------------------------------------------------------
691 MS_control_1 : MS_control
707 MS_control_1 : MS_control
692 PORT MAP (
708 PORT MAP (
693 clk => clk,
709 clk => clk,
694 rstn => rstn,
710 rstn => rstn,
695
711
696 current_status_ms => status_MS_input,
712 current_status_ms => status_MS_input,
697
713
698 fifo_in_lock => MEM_IN_SM_locked,
714 fifo_in_lock => MEM_IN_SM_locked,
699 fifo_in_data => MEM_IN_SM_rdata,
715 fifo_in_data => MEM_IN_SM_rdata,
700 fifo_in_full => MEM_IN_SM_Full,
716 fifo_in_full => MEM_IN_SM_Full,
701 fifo_in_empty => MEM_IN_SM_Empty,
717 fifo_in_empty => MEM_IN_SM_Empty,
702 fifo_in_ren => MEM_IN_SM_ren,
718 fifo_in_ren => MEM_IN_SM_ren,
703 fifo_in_reuse => MEM_IN_SM_ReUse,
719 fifo_in_reuse => MEM_IN_SM_ReUse,
704
720
705 fifo_out_data => SM_in_data,
721 fifo_out_data => SM_in_data,
706 fifo_out_ren => SM_in_ren,
722 fifo_out_ren => SM_in_ren,
707 fifo_out_empty => SM_in_empty,
723 fifo_out_empty => SM_in_empty,
708
724
709 current_status_component => status_component,
725 current_status_component => status_component,
710
726
711 correlation_start => SM_correlation_start,
727 correlation_start => SM_correlation_start,
712 correlation_auto => SM_correlation_auto,
728 correlation_auto => SM_correlation_auto,
713 correlation_done => SM_correlation_done);
729 correlation_done => SM_correlation_done);
714
730
715
731
716 MS_calculation_1 : MS_calculation
732 MS_calculation_1 : MS_calculation
717 PORT MAP (
733 PORT MAP (
718 clk => clk,
734 clk => clk,
719 rstn => rstn,
735 rstn => rstn,
720
736
721 fifo_in_data => SM_in_data,
737 fifo_in_data => SM_in_data,
722 fifo_in_ren => SM_in_ren,
738 fifo_in_ren => SM_in_ren,
723 fifo_in_empty => SM_in_empty,
739 fifo_in_empty => SM_in_empty,
724
740
725 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
741 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
726 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
742 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
727 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
743 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
728
744
729 correlation_start => SM_correlation_start,
745 correlation_start => SM_correlation_start,
730 correlation_auto => SM_correlation_auto,
746 correlation_auto => SM_correlation_auto,
731 correlation_begin => SM_correlation_begin,
747 correlation_begin => SM_correlation_begin,
732 correlation_done => SM_correlation_done);
748 correlation_done => SM_correlation_done);
733
749
734 -----------------------------------------------------------------------------
750 -----------------------------------------------------------------------------
735 PROCESS (clk, rstn)
751 PROCESS (clk, rstn)
736 BEGIN -- PROCESS
752 BEGIN -- PROCESS
737 IF rstn = '0' THEN -- asynchronous reset (active low)
753 IF rstn = '0' THEN -- asynchronous reset (active low)
738 current_matrix_write <= '0';
754 current_matrix_write <= '0';
739 current_matrix_wait_empty <= '1';
755 current_matrix_wait_empty <= '1';
740 status_component_fifo_0 <= (OTHERS => '0');
756 status_component_fifo_0 <= (OTHERS => '0');
741 status_component_fifo_1 <= (OTHERS => '0');
757 status_component_fifo_1 <= (OTHERS => '0');
742 status_component_fifo_0_end <= '0';
758 status_component_fifo_0_end <= '0';
743 status_component_fifo_1_end <= '0';
759 status_component_fifo_1_end <= '0';
744 SM_correlation_done_reg1 <= '0';
760 SM_correlation_done_reg1 <= '0';
745 SM_correlation_done_reg2 <= '0';
761 SM_correlation_done_reg2 <= '0';
746 SM_correlation_done_reg3 <= '0';
762 SM_correlation_done_reg3 <= '0';
747
763
748 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
764 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
749 SM_correlation_done_reg1 <= SM_correlation_done;
765 SM_correlation_done_reg1 <= SM_correlation_done;
750 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
766 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
751 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
767 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
752 status_component_fifo_0_end <= '0';
768 status_component_fifo_0_end <= '0';
753 status_component_fifo_1_end <= '0';
769 status_component_fifo_1_end <= '0';
754 IF SM_correlation_begin = '1' THEN
770 IF SM_correlation_begin = '1' THEN
755 IF current_matrix_write = '0' THEN
771 IF current_matrix_write = '0' THEN
756 status_component_fifo_0 <= status_component;
772 status_component_fifo_0 <= status_component;
757 ELSE
773 ELSE
758 status_component_fifo_1 <= status_component;
774 status_component_fifo_1 <= status_component;
759 END IF;
775 END IF;
760 END IF;
776 END IF;
761
777
762 IF SM_correlation_done_reg3 = '1' THEN
778 IF SM_correlation_done_reg3 = '1' THEN
763 IF current_matrix_write = '0' THEN
779 IF current_matrix_write = '0' THEN
764 status_component_fifo_0_end <= '1';
780 status_component_fifo_0_end <= '1';
765 ELSE
781 ELSE
766 status_component_fifo_1_end <= '1';
782 status_component_fifo_1_end <= '1';
767 END IF;
783 END IF;
768 current_matrix_wait_empty <= '1';
784 current_matrix_wait_empty <= '1';
769 current_matrix_write <= NOT current_matrix_write;
785 current_matrix_write <= NOT current_matrix_write;
770 END IF;
786 END IF;
771
787
772 IF current_matrix_wait_empty <= '1' THEN
788 IF current_matrix_wait_empty <= '1' THEN
773 IF current_matrix_write = '0' THEN
789 IF current_matrix_write = '0' THEN
774 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
790 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
775 ELSE
791 ELSE
776 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
792 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
777 END IF;
793 END IF;
778 END IF;
794 END IF;
779
795
780 END IF;
796 END IF;
781 END PROCESS;
797 END PROCESS;
782
798
783 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
799 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
784 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
800 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
785 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
801 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
786 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
802 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
787 '1' WHEN current_matrix_wait_empty = '1' ELSE
803 '1' WHEN current_matrix_wait_empty = '1' ELSE
788 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
804 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
789 MEM_OUT_SM_Full(1);
805 MEM_OUT_SM_Full(1);
790
806
791 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
807 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
792 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
808 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
793
809
794 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
810 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
795 -----------------------------------------------------------------------------
811 -----------------------------------------------------------------------------
796
812
797 Mem_Out_SpectralMatrix : lppFIFOxN
813 Mem_Out_SpectralMatrix : lppFIFOxN
798 GENERIC MAP (
814 GENERIC MAP (
799 tech => 0,
815 tech => 0,
800 Mem_use => Mem_use,
816 Mem_use => Mem_use,
801 Data_sz => 32,
817 Data_sz => 32,
802 Addr_sz => 8,
818 Addr_sz => 8,
803 FifoCnt => 2)
819 FifoCnt => 2)
804 PORT MAP (
820 PORT MAP (
805 clk => clk,
821 clk => clk,
806 rstn => rstn,
822 rstn => rstn,
807
823
808 ReUse => (OTHERS => '0'),
824 ReUse => (OTHERS => '0'),
809
825
810 wen => MEM_OUT_SM_Write,
826 wen => MEM_OUT_SM_Write,
811 wdata => MEM_OUT_SM_Data_in,
827 wdata => MEM_OUT_SM_Data_in,
812
828
813 ren => MEM_OUT_SM_Read,
829 ren => MEM_OUT_SM_Read,
814 rdata => MEM_OUT_SM_Data_out,
830 rdata => MEM_OUT_SM_Data_out,
815
831
816 full => MEM_OUT_SM_Full,
832 full => MEM_OUT_SM_Full,
817 empty => MEM_OUT_SM_Empty,
833 empty => MEM_OUT_SM_Empty,
818 almost_full => OPEN);
834 almost_full => OPEN);
819
835
820 -----------------------------------------------------------------------------
836 -----------------------------------------------------------------------------
821 -- MEM_OUT_SM_Read <= "00";
837 -- MEM_OUT_SM_Read <= "00";
822 PROCESS (clk, rstn)
838 PROCESS (clk, rstn)
823 BEGIN
839 BEGIN
824 IF rstn = '0' THEN
840 IF rstn = '0' THEN
825 fifo_0_ready <= '0';
841 fifo_0_ready <= '0';
826 fifo_1_ready <= '0';
842 fifo_1_ready <= '0';
827 fifo_ongoing <= '0';
843 fifo_ongoing <= '0';
828 ELSIF clk'EVENT AND clk = '1' THEN
844 ELSIF clk'EVENT AND clk = '1' THEN
829 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
845 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
830 fifo_ongoing <= '1';
846 fifo_ongoing <= '1';
831 fifo_0_ready <= '0';
847 fifo_0_ready <= '0';
832 ELSIF status_component_fifo_0_end = '1' THEN
848 ELSIF status_component_fifo_0_end = '1' THEN
833 fifo_0_ready <= '1';
849 fifo_0_ready <= '1';
834 END IF;
850 END IF;
835
851
836 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
852 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
837 fifo_ongoing <= '0';
853 fifo_ongoing <= '0';
838 fifo_1_ready <= '0';
854 fifo_1_ready <= '0';
839 ELSIF status_component_fifo_1_end = '1' THEN
855 ELSIF status_component_fifo_1_end = '1' THEN
840 fifo_1_ready <= '1';
856 fifo_1_ready <= '1';
841 END IF;
857 END IF;
842
858
843 END IF;
859 END IF;
844 END PROCESS;
860 END PROCESS;
845
861
846 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
862 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
847 '1' WHEN fifo_0_ready = '0' ELSE
863 '1' WHEN fifo_0_ready = '0' ELSE
848 FSM_DMA_fifo_ren;
864 FSM_DMA_fifo_ren;
849
865
850 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
866 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
851 '1' WHEN fifo_1_ready = '0' ELSE
867 '1' WHEN fifo_1_ready = '0' ELSE
852 FSM_DMA_fifo_ren;
868 FSM_DMA_fifo_ren;
853
869
854 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
870 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
855 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
871 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
856 '1';
872 '1';
857
873
858 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
874 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
859 status_component_fifo_1;
875 status_component_fifo_1;
860
876
861 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
877 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
862 MEM_OUT_SM_Data_out(63 DOWNTO 32);
878 MEM_OUT_SM_Data_out(63 DOWNTO 32);
863
879
864 -----------------------------------------------------------------------------
880 -----------------------------------------------------------------------------
865 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
881 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
866 PORT MAP (
882 PORT MAP (
867 HCLK => clk,
883 HCLK => clk,
868 HRESETn => rstn,
884 HRESETn => rstn,
869
885
870 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
886 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
871 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
887 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
872 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
888 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
873 fifo_data => FSM_DMA_fifo_data,
889 fifo_data => FSM_DMA_fifo_data,
874 fifo_empty => FSM_DMA_fifo_empty,
890 fifo_empty => FSM_DMA_fifo_empty,
875 fifo_ren => FSM_DMA_fifo_ren,
891 fifo_ren => FSM_DMA_fifo_ren,
876
892
877 dma_addr => dma_addr,
893 dma_addr => dma_addr,
878 dma_data => dma_data,
894 dma_data => dma_data,
879 dma_valid => dma_valid,
895 dma_valid => dma_valid,
880 dma_valid_burst => dma_valid_burst,
896 dma_valid_burst => dma_valid_burst,
881 dma_ren => dma_ren,
897 dma_ren => dma_ren,
882 dma_done => dma_done,
898 dma_done => dma_done,
883
899
884 ready_matrix_f0 => ready_matrix_f0,
900 ready_matrix_f0 => ready_matrix_f0,
885 ready_matrix_f1 => ready_matrix_f1,
901 ready_matrix_f1 => ready_matrix_f1,
886 ready_matrix_f2 => ready_matrix_f2,
902 ready_matrix_f2 => ready_matrix_f2,
887
903
888 error_bad_component_error => error_bad_component_error,
904 error_bad_component_error => error_bad_component_error,
889 error_buffer_full => error_buffer_full,
905 error_buffer_full => error_buffer_full,
890
906
891 debug_reg => debug_reg,
907 debug_reg => debug_reg,
892 status_ready_matrix_f0 => status_ready_matrix_f0,
908 status_ready_matrix_f0 => status_ready_matrix_f0,
893 status_ready_matrix_f1 => status_ready_matrix_f1,
909 status_ready_matrix_f1 => status_ready_matrix_f1,
894 status_ready_matrix_f2 => status_ready_matrix_f2,
910 status_ready_matrix_f2 => status_ready_matrix_f2,
895
911
896 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
912 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
897 config_active_interruption_onError => config_active_interruption_onError,
913 config_active_interruption_onError => config_active_interruption_onError,
898
914
899 addr_matrix_f0 => addr_matrix_f0,
915 addr_matrix_f0 => addr_matrix_f0,
900 addr_matrix_f1 => addr_matrix_f1,
916 addr_matrix_f1 => addr_matrix_f1,
901 addr_matrix_f2 => addr_matrix_f2,
917 addr_matrix_f2 => addr_matrix_f2,
902
918
903 matrix_time_f0 => matrix_time_f0,
919 matrix_time_f0 => matrix_time_f0,
904 matrix_time_f1 => matrix_time_f1,
920 matrix_time_f1 => matrix_time_f1,
905 matrix_time_f2 => matrix_time_f2
921 matrix_time_f2 => matrix_time_f2
906 );
922 );
907 -----------------------------------------------------------------------------
923 -----------------------------------------------------------------------------
908
924
909
925
910
926
911
927
912
928
913 -----------------------------------------------------------------------------
929 -----------------------------------------------------------------------------
914 -- TIME MANAGMENT
930 -- TIME MANAGMENT
915 -----------------------------------------------------------------------------
931 -----------------------------------------------------------------------------
916 all_time <= coarse_time & fine_time;
932 all_time <= coarse_time & fine_time;
917 --
933 --
918 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
934 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
919 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
935 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
920 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
936 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
921 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
937 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
922
938
923 all_time_reg: FOR I IN 0 TO 3 GENERATE
939 all_time_reg: FOR I IN 0 TO 3 GENERATE
924
940
925 PROCESS (clk, rstn)
941 PROCESS (clk, rstn)
926 BEGIN
942 BEGIN
927 IF rstn = '0' THEN
943 IF rstn = '0' THEN
928 f_empty_reg(I) <= '1';
944 f_empty_reg(I) <= '1';
929 ELSIF clk'event AND clk = '1' THEN
945 ELSIF clk'event AND clk = '1' THEN
930 f_empty_reg(I) <= f_empty(I);
946 f_empty_reg(I) <= f_empty(I);
931 END IF;
947 END IF;
932 END PROCESS;
948 END PROCESS;
933
949
934 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
950 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
935
951
936 s_m_t_m_f0_A : spectral_matrix_time_managment
952 s_m_t_m_f0_A : spectral_matrix_time_managment
937 PORT MAP (
953 PORT MAP (
938 clk => clk,
954 clk => clk,
939 rstn => rstn,
955 rstn => rstn,
940 time_in => all_time,
956 time_in => all_time,
941 update_1 => time_update_f(I),
957 update_1 => time_update_f(I),
942 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
958 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
943 );
959 );
944
960
945 END GENERATE all_time_reg;
961 END GENERATE all_time_reg;
946
962
947 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
963 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
948 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
964 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
949 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
965 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
950 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
966 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
951
967
952 -----------------------------------------------------------------------------
968 -----------------------------------------------------------------------------
953
969
954 END Behavioral;
970 END Behavioral;
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