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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------- |
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19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | -- jean-christophe.pellion@easii-ic.com |
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22 | 22 | ------------------------------------------------------------------------------- |
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23 | 23 | LIBRARY IEEE; |
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24 | 24 | USE IEEE.STD_LOGIC_1164.ALL; |
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25 | 25 | USE ieee.numeric_std.ALL; |
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26 | 26 | |
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27 | 27 | LIBRARY grlib; |
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28 | 28 | USE grlib.amba.ALL; |
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29 | 29 | USE grlib.stdlib.ALL; |
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30 | 30 | USE grlib.devices.ALL; |
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31 | 31 | USE GRLIB.DMA2AHB_Package.ALL; |
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32 | 32 | |
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33 | 33 | LIBRARY lpp; |
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34 | 34 | USE lpp.lpp_waveform_pkg.ALL; |
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35 | 35 | USE lpp.iir_filter.ALL; |
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36 | 36 | USE lpp.lpp_memory.ALL; |
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37 | 37 | |
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38 | 38 | LIBRARY techmap; |
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39 | 39 | USE techmap.gencomp.ALL; |
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40 | 40 | |
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41 | 41 | ENTITY lpp_waveform IS |
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42 | 42 | |
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43 | 43 | GENERIC ( |
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44 | 44 | tech : INTEGER := inferred; |
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45 | 45 | data_size : INTEGER := 96; --16*6 |
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46 | 46 | nb_data_by_buffer_size : INTEGER := 11; |
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47 | 47 | -- nb_word_by_buffer_size : INTEGER := 11; |
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48 | 48 | nb_snapshot_param_size : INTEGER := 11; |
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49 | 49 | delta_vector_size : INTEGER := 20; |
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50 | 50 | delta_vector_size_f0_2 : INTEGER := 3); |
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51 | 51 | |
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52 | 52 | PORT ( |
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53 | 53 | clk : IN STD_LOGIC; |
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54 | 54 | rstn : IN STD_LOGIC; |
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55 | 55 | |
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56 | 56 | ---- AMBA AHB Master Interface |
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57 | 57 | --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO |
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58 | 58 | --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO |
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59 | 59 | |
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60 | 60 | --config |
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61 | 61 | reg_run : IN STD_LOGIC; |
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62 | 62 | reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
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63 | 63 | reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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64 | 64 | reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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65 | 65 | reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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66 | 66 | reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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67 | 67 | reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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68 | 68 | |
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69 | 69 | enable_f0 : IN STD_LOGIC; |
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70 | 70 | enable_f1 : IN STD_LOGIC; |
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71 | 71 | enable_f2 : IN STD_LOGIC; |
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72 | 72 | enable_f3 : IN STD_LOGIC; |
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73 | 73 | |
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74 | 74 | burst_f0 : IN STD_LOGIC; |
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75 | 75 | burst_f1 : IN STD_LOGIC; |
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76 | 76 | burst_f2 : IN STD_LOGIC; |
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77 | 77 | |
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78 | 78 | nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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79 | 79 | -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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80 | 80 | nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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81 | 81 | |
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82 | 82 | status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma |
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83 | 83 | |
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84 | 84 | |
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85 | 85 | -- REG DMA |
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86 | 86 | status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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87 | 87 | addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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88 | 88 | length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0); |
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89 | 89 | |
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90 | 90 | ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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91 | 91 | buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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92 | 92 | error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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93 | 93 | |
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94 | 94 | --------------------------------------------------------------------------- |
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95 | 95 | -- INPUT |
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96 | 96 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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97 | 97 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
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98 | 98 | |
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99 | 99 | --f0 |
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100 | 100 | data_f0_in_valid : IN STD_LOGIC; |
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101 | 101 | data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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102 | 102 | --f1 |
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103 | 103 | data_f1_in_valid : IN STD_LOGIC; |
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104 | 104 | data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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105 | 105 | --f2 |
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106 | 106 | data_f2_in_valid : IN STD_LOGIC; |
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107 | 107 | data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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108 | 108 | --f3 |
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109 | 109 | data_f3_in_valid : IN STD_LOGIC; |
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110 | 110 | data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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111 | 111 | |
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112 | 112 | --------------------------------------------------------------------------- |
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113 | 113 | -- DMA -------------------------------------------------------------------- |
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114 | 114 | |
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115 | 115 | dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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116 | 116 | dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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117 | 117 | dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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118 | 118 | dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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119 | 119 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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120 | 120 | dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0); |
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121 | 121 | dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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122 | 122 | dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0) |
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123 | 123 | |
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124 | 124 | ); |
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125 | 125 | |
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126 | 126 | END lpp_waveform; |
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127 | 127 | |
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128 | 128 | ARCHITECTURE beh OF lpp_waveform IS |
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129 | 129 | SIGNAL start_snapshot_f0 : STD_LOGIC; |
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130 | 130 | SIGNAL start_snapshot_f1 : STD_LOGIC; |
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131 | 131 | SIGNAL start_snapshot_f2 : STD_LOGIC; |
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132 | 132 | |
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133 | 133 | SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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134 | 134 | SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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135 | 135 | SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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136 | 136 | SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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137 | 137 | |
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138 | 138 | SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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139 | 139 | SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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140 | 140 | SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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141 | 141 | SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); |
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142 | 142 | |
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143 | 143 | SIGNAL data_f0_out_valid : STD_LOGIC; |
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144 | 144 | SIGNAL data_f1_out_valid : STD_LOGIC; |
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145 | 145 | SIGNAL data_f2_out_valid : STD_LOGIC; |
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146 | 146 | SIGNAL data_f3_out_valid : STD_LOGIC; |
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147 | 147 | SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); |
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148 | 148 | -- |
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149 | 149 | SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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150 | 150 | SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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151 | 151 | SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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152 | 152 | SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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153 | 153 | SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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154 | 154 | SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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155 | 155 | SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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156 | 156 | SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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157 | 157 | SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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158 | 158 | SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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159 | 159 | SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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160 | 160 | SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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161 | 161 | SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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162 | 162 | -- |
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163 | 163 | SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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164 | 164 | SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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165 | 165 | SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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166 | 166 | SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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167 | 167 | -- |
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168 | 168 | SIGNAL run : STD_LOGIC; |
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169 | 169 | -- |
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170 | 170 | TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); |
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171 | 171 | SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); |
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172 | 172 | SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); |
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173 | 173 | SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); |
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174 | 174 | SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug |
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175 | 175 | SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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176 | 176 | SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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177 | 177 | -- |
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178 | 178 | |
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179 | 179 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b |
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180 | 180 | SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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181 | 181 | SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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182 | 182 | -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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183 | 183 | SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
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184 | 184 | |
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185 | 185 | -- |
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186 | 186 | SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0); |
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187 | 187 | SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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188 | 188 | |
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189 | 189 | SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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190 | 190 | |
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191 | 191 | SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
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192 | 192 | |
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193 | 193 | BEGIN -- beh |
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194 | 194 | |
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195 | 195 | ----------------------------------------------------------------------------- |
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196 | 196 | |
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197 | 197 | lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler |
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198 | 198 | GENERIC MAP ( |
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199 | 199 | delta_vector_size => delta_vector_size, |
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200 | 200 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
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201 | 201 | ) |
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202 | 202 | PORT MAP ( |
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203 | 203 | clk => clk, |
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204 | 204 | rstn => rstn, |
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205 | 205 | reg_run => reg_run, |
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206 | 206 | reg_start_date => reg_start_date, |
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207 | 207 | reg_delta_snapshot => reg_delta_snapshot, |
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208 | 208 | reg_delta_f0 => reg_delta_f0, |
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209 | 209 | reg_delta_f0_2 => reg_delta_f0_2, |
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210 | 210 | reg_delta_f1 => reg_delta_f1, |
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211 | 211 | reg_delta_f2 => reg_delta_f2, |
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212 | 212 | coarse_time => coarse_time(30 DOWNTO 0), |
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213 | 213 | data_f0_valid => data_f0_in_valid, |
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214 | 214 | data_f2_valid => data_f2_in_valid, |
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215 | 215 | start_snapshot_f0 => start_snapshot_f0, |
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216 | 216 | start_snapshot_f1 => start_snapshot_f1, |
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217 | 217 | start_snapshot_f2 => start_snapshot_f2, |
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218 | 218 | wfp_on => run); |
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219 | 219 | |
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220 | 220 | lpp_waveform_snapshot_f0 : lpp_waveform_snapshot |
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221 | 221 | GENERIC MAP ( |
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222 | 222 | data_size => data_size, |
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223 | 223 | nb_snapshot_param_size => nb_snapshot_param_size) |
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224 | 224 | PORT MAP ( |
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225 | 225 | clk => clk, |
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226 | 226 | rstn => rstn, |
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227 | 227 | run => run, |
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228 | 228 | enable => enable_f0, |
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229 | 229 | burst_enable => burst_f0, |
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230 | 230 | nb_snapshot_param => nb_snapshot_param, |
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231 | 231 | start_snapshot => start_snapshot_f0, |
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232 | 232 | data_in => data_f0_in, |
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233 | 233 | data_in_valid => data_f0_in_valid, |
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234 | 234 | data_out => data_f0_out, |
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235 | 235 | data_out_valid => data_f0_out_valid); |
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236 | 236 | |
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237 | 237 | nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; |
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238 | 238 | |
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239 | 239 | lpp_waveform_snapshot_f1 : lpp_waveform_snapshot |
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240 | 240 | GENERIC MAP ( |
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241 | 241 | data_size => data_size, |
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242 | 242 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
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243 | 243 | PORT MAP ( |
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244 | 244 | clk => clk, |
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245 | 245 | rstn => rstn, |
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246 | 246 | run => run, |
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247 | 247 | enable => enable_f1, |
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248 | 248 | burst_enable => burst_f1, |
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249 | 249 | nb_snapshot_param => nb_snapshot_param_more_one, |
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250 | 250 | start_snapshot => start_snapshot_f1, |
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251 | 251 | data_in => data_f1_in, |
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252 | 252 | data_in_valid => data_f1_in_valid, |
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253 | 253 | data_out => data_f1_out, |
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254 | 254 | data_out_valid => data_f1_out_valid); |
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255 | 255 | |
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256 | 256 | lpp_waveform_snapshot_f2 : lpp_waveform_snapshot |
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257 | 257 | GENERIC MAP ( |
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258 | 258 | data_size => data_size, |
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259 | 259 | nb_snapshot_param_size => nb_snapshot_param_size+1) |
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260 | 260 | PORT MAP ( |
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261 | 261 | clk => clk, |
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262 | 262 | rstn => rstn, |
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263 | 263 | run => run, |
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264 | 264 | enable => enable_f2, |
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265 | 265 | burst_enable => burst_f2, |
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266 | 266 | nb_snapshot_param => nb_snapshot_param_more_one, |
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267 | 267 | start_snapshot => start_snapshot_f2, |
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268 | 268 | data_in => data_f2_in, |
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269 | 269 | data_in_valid => data_f2_in_valid, |
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270 | 270 | data_out => data_f2_out, |
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271 | 271 | data_out_valid => data_f2_out_valid); |
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272 | 272 | |
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273 | 273 | lpp_waveform_burst_f3 : lpp_waveform_burst |
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274 | 274 | GENERIC MAP ( |
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275 | 275 | data_size => data_size) |
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276 | 276 | PORT MAP ( |
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277 | 277 | clk => clk, |
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278 | 278 | rstn => rstn, |
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279 | 279 | run => run, |
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280 | 280 | enable => enable_f3, |
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281 | 281 | data_in => data_f3_in, |
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282 | 282 | data_in_valid => data_f3_in_valid, |
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283 | 283 | data_out => data_f3_out, |
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284 | 284 | data_out_valid => data_f3_out_valid); |
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285 | 285 | |
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286 | 286 | ----------------------------------------------------------------------------- |
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287 | 287 | -- DEBUG -- SNAPSHOT OUT |
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288 | 288 | --debug_f0_data_valid <= data_f0_out_valid; |
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289 | 289 | --debug_f0_data <= data_f0_out; |
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290 | 290 | --debug_f1_data_valid <= data_f1_out_valid; |
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291 | 291 | --debug_f1_data <= data_f1_out; |
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292 | 292 | --debug_f2_data_valid <= data_f2_out_valid; |
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293 | 293 | --debug_f2_data <= data_f2_out; |
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294 | 294 | --debug_f3_data_valid <= data_f3_out_valid; |
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295 | 295 | --debug_f3_data <= data_f3_out; |
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296 | 296 | ----------------------------------------------------------------------------- |
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297 | 297 | |
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298 | 298 | PROCESS (clk, rstn) |
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299 | 299 | BEGIN -- PROCESS |
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300 | 300 | IF rstn = '0' THEN -- asynchronous reset (active low) |
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301 | 301 | time_reg1 <= (OTHERS => '0'); |
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302 | 302 | time_reg2 <= (OTHERS => '0'); |
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303 | 303 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
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304 | 304 | time_reg1 <= fine_time & coarse_time; |
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305 | 305 | time_reg2 <= time_reg1; |
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306 | 306 | END IF; |
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307 | 307 | END PROCESS; |
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308 | 308 | |
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309 | 309 | valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; |
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310 | 310 | all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE |
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311 | 311 | lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid |
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312 | 312 | PORT MAP ( |
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313 | 313 | HCLK => clk, |
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314 | 314 | HRESETn => rstn, |
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315 | 315 | run => run, |
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316 | 316 | valid_in => valid_in(I), |
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317 | 317 | ack_in => valid_ack(I), |
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318 | 318 | time_in => time_reg2, -- Todo |
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319 | 319 | valid_out => valid_out(I), |
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320 | 320 | time_out => time_out(I), -- Todo |
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321 | 321 | error => status_new_err(I)); |
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322 | 322 | END GENERATE all_input_valid; |
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323 | 323 | |
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324 | 324 | data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) & |
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325 | 325 | data_f0_out((16*6)-1 DOWNTO 16*5) & |
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326 | 326 | data_f0_out((16*3)-1 DOWNTO 16*2) & |
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327 | 327 | data_f0_out((16*4)-1 DOWNTO 16*3) & |
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328 | 328 | data_f0_out((16*1)-1 DOWNTO 16*0) & |
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329 | 329 | data_f0_out((16*2)-1 DOWNTO 16*1) ; |
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330 | 330 | |
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331 | 331 | data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) & |
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332 | 332 | data_f1_out((16*6)-1 DOWNTO 16*5) & |
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333 | 333 | data_f1_out((16*3)-1 DOWNTO 16*2) & |
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334 | 334 | data_f1_out((16*4)-1 DOWNTO 16*3) & |
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335 | 335 | data_f1_out((16*1)-1 DOWNTO 16*0) & |
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336 | 336 | data_f1_out((16*2)-1 DOWNTO 16*1) ; |
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337 | 337 | |
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338 | 338 | data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) & |
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339 | 339 | data_f2_out((16*6)-1 DOWNTO 16*5) & |
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340 | 340 | data_f2_out((16*3)-1 DOWNTO 16*2) & |
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341 | 341 | data_f2_out((16*4)-1 DOWNTO 16*3) & |
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342 | 342 | data_f2_out((16*1)-1 DOWNTO 16*0) & |
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343 | 343 | data_f2_out((16*2)-1 DOWNTO 16*1) ; |
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344 | 344 | |
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345 | 345 | data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) & |
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346 | 346 | data_f3_out((16*6)-1 DOWNTO 16*5) & |
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347 | 347 | data_f3_out((16*3)-1 DOWNTO 16*2) & |
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348 | 348 | data_f3_out((16*4)-1 DOWNTO 16*3) & |
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349 | 349 | data_f3_out((16*1)-1 DOWNTO 16*0) & |
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350 | 350 | data_f3_out((16*2)-1 DOWNTO 16*1) ; |
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351 | 351 | |
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352 | 352 | all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE |
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353 | 353 | data_out(0, I) <= data_f0_out_swap(I); |
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354 | 354 | data_out(1, I) <= data_f1_out_swap(I); |
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355 | 355 | data_out(2, I) <= data_f2_out_swap(I); |
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356 | 356 | data_out(3, I) <= data_f3_out_swap(I); |
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357 | 357 | END GENERATE all_bit_of_data_out; |
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358 | 358 | |
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359 | 359 | ----------------------------------------------------------------------------- |
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360 | 360 | -- TODO : debug |
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361 | 361 | ----------------------------------------------------------------------------- |
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362 | 362 | all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE |
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363 | 363 | all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE |
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364 | 364 | time_out_2(J, I) <= time_out(J)(I); |
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365 | 365 | END GENERATE all_sample_of_time_out; |
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366 | 366 | END GENERATE all_bit_of_time_out; |
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367 | 367 | |
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368 | 368 | lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter |
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369 | 369 | GENERIC MAP (tech => tech, |
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370 | 370 | nb_data_by_buffer_size => nb_data_by_buffer_size) |
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371 | 371 | PORT MAP ( |
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372 | 372 | clk => clk, |
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373 | 373 | rstn => rstn, |
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374 | 374 | run => run, |
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375 | 375 | nb_data_by_buffer => nb_data_by_buffer, |
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376 | 376 | data_in_valid => valid_out, |
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377 | 377 | data_in_ack => valid_ack, |
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378 | 378 | data_in => data_out, |
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379 | 379 | time_in => time_out_2, |
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380 | 380 | |
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381 | 381 | data_out => wdata, |
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382 | 382 | data_out_wen => data_wen, |
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383 | 383 | full_almost => full_almost, |
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384 | 384 | full => full, |
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385 | 385 | |
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386 | 386 | time_out => arbiter_time_out, |
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387 | 387 | time_out_new => arbiter_time_out_new |
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388 | 388 | |
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389 | 389 | ); |
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390 | 390 | |
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391 | 391 | ----------------------------------------------------------------------------- |
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392 | 392 | ----------------------------------------------------------------------------- |
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393 | 393 | |
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394 | 394 | generate_all_fifo: FOR I IN 0 TO 3 GENERATE |
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395 | 395 | lpp_fifo_1: lpp_fifo |
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396 | 396 | GENERIC MAP ( |
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397 | 397 | tech => tech, |
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398 | 398 | Mem_use => use_RAM, |
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399 | 399 | EMPTY_THRESHOLD_LIMIT => 15, |
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400 | 400 | FULL_THRESHOLD_LIMIT => 3, |
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401 | 401 | DataSz => 32, |
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402 | 402 | AddrSz => 7) |
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403 | 403 | PORT MAP ( |
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404 | 404 | clk => clk, |
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405 | 405 | rstn => rstn, |
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406 | 406 | reUse => '0', |
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407 | 407 | run => run, |
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408 | 408 | ren => data_ren(I), |
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409 | 409 | rdata => s_rdata_v((I+1)*32-1 downto I*32), |
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410 | 410 | wen => data_wen(I), |
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411 | 411 | wdata => wdata, |
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412 | 412 | empty => empty(I), |
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413 | 413 | full => full(I), |
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414 | 414 | full_almost => OPEN, |
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415 | 415 | empty_threshold => empty_almost(I), |
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416 | 416 | full_threshold => full_almost(I) ); |
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417 | 417 | |
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418 | 418 | END GENERATE generate_all_fifo; |
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419 | 419 | |
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420 | 420 | ----------------------------------------------------------------------------- |
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421 | 421 | -- |
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422 | 422 | ----------------------------------------------------------------------------- |
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423 | 423 | |
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424 | 424 | all_channel: FOR I IN 3 DOWNTO 0 GENERATE |
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425 | 425 | |
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426 | 426 | PROCESS (clk, rstn) |
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427 | 427 | BEGIN |
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428 | 428 | IF rstn = '0' THEN |
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429 | 429 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); |
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430 | 430 | ELSIF clk'event AND clk = '1' THEN |
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431 | 431 | IF run = '0' THEN |
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432 | 432 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0'); |
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433 | 433 | ELSE |
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434 | 434 | IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015 |
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435 | 435 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out; |
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436 | 436 | END IF; |
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437 | 437 | END IF; |
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438 | 438 | END IF; |
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439 | 439 | END PROCESS; |
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440 | 440 | |
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441 | 441 | fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE |
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442 | 442 | fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); |
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443 | 443 | |
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444 | 444 | lpp_waveform_fsmdma_I: lpp_waveform_fsmdma |
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445 | 445 | PORT MAP ( |
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446 | 446 | clk => clk, |
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447 | 447 | rstn => rstn, |
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448 | 448 | run => run, |
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449 | 449 | |
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450 | 450 | fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I), |
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451 | 451 | |
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452 | 452 | fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I), |
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453 | 453 | fifo_empty => empty(I), |
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454 | 454 | fifo_empty_threshold => empty_almost(I), |
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455 | 455 | fifo_ren => data_ren(I), |
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456 | 456 | |
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457 | 457 | dma_fifo_valid_burst => dma_fifo_valid_burst(I), |
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458 | 458 | dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I), |
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459 | 459 | dma_fifo_ren => dma_fifo_ren(I), |
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460 | 460 | dma_buffer_new => dma_buffer_new(I), |
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461 | 461 | dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I), |
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462 | 462 | dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I), |
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463 | 463 | dma_buffer_full => dma_buffer_full(I), |
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464 | 464 | dma_buffer_full_err => dma_buffer_full_err(I), |
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465 | 465 | |
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466 | 466 | status_buffer_ready => status_buffer_ready(I), -- TODO |
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467 | 467 | addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO |
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468 | 468 | length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO |
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469 | 469 | ready_buffer => ready_buffer(I), -- TODO |
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470 |
buffer_time => |
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470 | buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO | |
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471 | 471 | error_buffer_full => error_buffer_full(I)); -- TODO |
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472 | ||
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473 | buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I); | |
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472 | 474 | |
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473 | 475 | END GENERATE all_channel; |
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474 | 476 | |
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475 | 477 | |
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476 | 478 | END beh; |
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