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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY grlib;
28 28 USE grlib.amba.ALL;
29 29 USE grlib.stdlib.ALL;
30 30 USE grlib.devices.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32
33 33 LIBRARY lpp;
34 34 USE lpp.lpp_waveform_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.lpp_memory.ALL;
37 37
38 38 LIBRARY techmap;
39 39 USE techmap.gencomp.ALL;
40 40
41 41 ENTITY lpp_waveform IS
42 42
43 43 GENERIC (
44 44 tech : INTEGER := inferred;
45 45 data_size : INTEGER := 96; --16*6
46 46 nb_data_by_buffer_size : INTEGER := 11;
47 47 -- nb_word_by_buffer_size : INTEGER := 11;
48 48 nb_snapshot_param_size : INTEGER := 11;
49 49 delta_vector_size : INTEGER := 20;
50 50 delta_vector_size_f0_2 : INTEGER := 3);
51 51
52 52 PORT (
53 53 clk : IN STD_LOGIC;
54 54 rstn : IN STD_LOGIC;
55 55
56 56 ---- AMBA AHB Master Interface
57 57 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
58 58 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
59 59
60 60 --config
61 61 reg_run : IN STD_LOGIC;
62 62 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 63 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 64 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 65 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
66 66 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67 67 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
68 68
69 69 enable_f0 : IN STD_LOGIC;
70 70 enable_f1 : IN STD_LOGIC;
71 71 enable_f2 : IN STD_LOGIC;
72 72 enable_f3 : IN STD_LOGIC;
73 73
74 74 burst_f0 : IN STD_LOGIC;
75 75 burst_f1 : IN STD_LOGIC;
76 76 burst_f2 : IN STD_LOGIC;
77 77
78 78 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
79 79 -- nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
80 80 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
81 81
82 82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 83
84 84
85 85 -- REG DMA
86 86 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 addr_buffer : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
88 88 length_buffer : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
89 89
90 90 ready_buffer : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
91 91 buffer_time : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
92 92 error_buffer_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
93 93
94 94 ---------------------------------------------------------------------------
95 95 -- INPUT
96 96 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
98 98
99 99 --f0
100 100 data_f0_in_valid : IN STD_LOGIC;
101 101 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
102 102 --f1
103 103 data_f1_in_valid : IN STD_LOGIC;
104 104 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 105 --f2
106 106 data_f2_in_valid : IN STD_LOGIC;
107 107 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 108 --f3
109 109 data_f3_in_valid : IN STD_LOGIC;
110 110 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
111 111
112 112 ---------------------------------------------------------------------------
113 113 -- DMA --------------------------------------------------------------------
114 114
115 115 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
116 116 dma_fifo_data : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 117 dma_fifo_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
118 118 dma_buffer_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
119 119 dma_buffer_addr : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
120 120 dma_buffer_length : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
121 121 dma_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
122 122 dma_buffer_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
123 123
124 124 );
125 125
126 126 END lpp_waveform;
127 127
128 128 ARCHITECTURE beh OF lpp_waveform IS
129 129 SIGNAL start_snapshot_f0 : STD_LOGIC;
130 130 SIGNAL start_snapshot_f1 : STD_LOGIC;
131 131 SIGNAL start_snapshot_f2 : STD_LOGIC;
132 132
133 133 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 134 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 135 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 136 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 137
138 138 SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 139 SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 140 SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 141 SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
142 142
143 143 SIGNAL data_f0_out_valid : STD_LOGIC;
144 144 SIGNAL data_f1_out_valid : STD_LOGIC;
145 145 SIGNAL data_f2_out_valid : STD_LOGIC;
146 146 SIGNAL data_f3_out_valid : STD_LOGIC;
147 147 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
148 148 --
149 149 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 150 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 151 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 152 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
153 153 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
154 154 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 155 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 156 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 157 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 159 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 160 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 161 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 162 --
163 163 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 164 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 165 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 166 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 167 --
168 168 SIGNAL run : STD_LOGIC;
169 169 --
170 170 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
171 171 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
172 172 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
173 173 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
174 174 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
175 175 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
176 176 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
177 177 --
178 178
179 179 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
180 180 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 181 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 182 -- SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 SIGNAL s_rdata_v : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
184 184
185 185 --
186 186 SIGNAL arbiter_time_out : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 187 SIGNAL arbiter_time_out_new : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 188
189 189 SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
190 190
191 191 SIGNAL fifo_buffer_time_s : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
192 192
193 193 BEGIN -- beh
194 194
195 195 -----------------------------------------------------------------------------
196 196
197 197 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
198 198 GENERIC MAP (
199 199 delta_vector_size => delta_vector_size,
200 200 delta_vector_size_f0_2 => delta_vector_size_f0_2
201 201 )
202 202 PORT MAP (
203 203 clk => clk,
204 204 rstn => rstn,
205 205 reg_run => reg_run,
206 206 reg_start_date => reg_start_date,
207 207 reg_delta_snapshot => reg_delta_snapshot,
208 208 reg_delta_f0 => reg_delta_f0,
209 209 reg_delta_f0_2 => reg_delta_f0_2,
210 210 reg_delta_f1 => reg_delta_f1,
211 211 reg_delta_f2 => reg_delta_f2,
212 212 coarse_time => coarse_time(30 DOWNTO 0),
213 213 data_f0_valid => data_f0_in_valid,
214 214 data_f2_valid => data_f2_in_valid,
215 215 start_snapshot_f0 => start_snapshot_f0,
216 216 start_snapshot_f1 => start_snapshot_f1,
217 217 start_snapshot_f2 => start_snapshot_f2,
218 218 wfp_on => run);
219 219
220 220 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
221 221 GENERIC MAP (
222 222 data_size => data_size,
223 223 nb_snapshot_param_size => nb_snapshot_param_size)
224 224 PORT MAP (
225 225 clk => clk,
226 226 rstn => rstn,
227 227 run => run,
228 228 enable => enable_f0,
229 229 burst_enable => burst_f0,
230 230 nb_snapshot_param => nb_snapshot_param,
231 231 start_snapshot => start_snapshot_f0,
232 232 data_in => data_f0_in,
233 233 data_in_valid => data_f0_in_valid,
234 234 data_out => data_f0_out,
235 235 data_out_valid => data_f0_out_valid);
236 236
237 237 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
238 238
239 239 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
240 240 GENERIC MAP (
241 241 data_size => data_size,
242 242 nb_snapshot_param_size => nb_snapshot_param_size+1)
243 243 PORT MAP (
244 244 clk => clk,
245 245 rstn => rstn,
246 246 run => run,
247 247 enable => enable_f1,
248 248 burst_enable => burst_f1,
249 249 nb_snapshot_param => nb_snapshot_param_more_one,
250 250 start_snapshot => start_snapshot_f1,
251 251 data_in => data_f1_in,
252 252 data_in_valid => data_f1_in_valid,
253 253 data_out => data_f1_out,
254 254 data_out_valid => data_f1_out_valid);
255 255
256 256 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
257 257 GENERIC MAP (
258 258 data_size => data_size,
259 259 nb_snapshot_param_size => nb_snapshot_param_size+1)
260 260 PORT MAP (
261 261 clk => clk,
262 262 rstn => rstn,
263 263 run => run,
264 264 enable => enable_f2,
265 265 burst_enable => burst_f2,
266 266 nb_snapshot_param => nb_snapshot_param_more_one,
267 267 start_snapshot => start_snapshot_f2,
268 268 data_in => data_f2_in,
269 269 data_in_valid => data_f2_in_valid,
270 270 data_out => data_f2_out,
271 271 data_out_valid => data_f2_out_valid);
272 272
273 273 lpp_waveform_burst_f3 : lpp_waveform_burst
274 274 GENERIC MAP (
275 275 data_size => data_size)
276 276 PORT MAP (
277 277 clk => clk,
278 278 rstn => rstn,
279 279 run => run,
280 280 enable => enable_f3,
281 281 data_in => data_f3_in,
282 282 data_in_valid => data_f3_in_valid,
283 283 data_out => data_f3_out,
284 284 data_out_valid => data_f3_out_valid);
285 285
286 286 -----------------------------------------------------------------------------
287 287 -- DEBUG -- SNAPSHOT OUT
288 288 --debug_f0_data_valid <= data_f0_out_valid;
289 289 --debug_f0_data <= data_f0_out;
290 290 --debug_f1_data_valid <= data_f1_out_valid;
291 291 --debug_f1_data <= data_f1_out;
292 292 --debug_f2_data_valid <= data_f2_out_valid;
293 293 --debug_f2_data <= data_f2_out;
294 294 --debug_f3_data_valid <= data_f3_out_valid;
295 295 --debug_f3_data <= data_f3_out;
296 296 -----------------------------------------------------------------------------
297 297
298 298 PROCESS (clk, rstn)
299 299 BEGIN -- PROCESS
300 300 IF rstn = '0' THEN -- asynchronous reset (active low)
301 301 time_reg1 <= (OTHERS => '0');
302 302 time_reg2 <= (OTHERS => '0');
303 303 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
304 304 time_reg1 <= fine_time & coarse_time;
305 305 time_reg2 <= time_reg1;
306 306 END IF;
307 307 END PROCESS;
308 308
309 309 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
310 310 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
311 311 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
312 312 PORT MAP (
313 313 HCLK => clk,
314 314 HRESETn => rstn,
315 315 run => run,
316 316 valid_in => valid_in(I),
317 317 ack_in => valid_ack(I),
318 318 time_in => time_reg2, -- Todo
319 319 valid_out => valid_out(I),
320 320 time_out => time_out(I), -- Todo
321 321 error => status_new_err(I));
322 322 END GENERATE all_input_valid;
323 323
324 324 data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
325 325 data_f0_out((16*6)-1 DOWNTO 16*5) &
326 326 data_f0_out((16*3)-1 DOWNTO 16*2) &
327 327 data_f0_out((16*4)-1 DOWNTO 16*3) &
328 328 data_f0_out((16*1)-1 DOWNTO 16*0) &
329 329 data_f0_out((16*2)-1 DOWNTO 16*1) ;
330 330
331 331 data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
332 332 data_f1_out((16*6)-1 DOWNTO 16*5) &
333 333 data_f1_out((16*3)-1 DOWNTO 16*2) &
334 334 data_f1_out((16*4)-1 DOWNTO 16*3) &
335 335 data_f1_out((16*1)-1 DOWNTO 16*0) &
336 336 data_f1_out((16*2)-1 DOWNTO 16*1) ;
337 337
338 338 data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
339 339 data_f2_out((16*6)-1 DOWNTO 16*5) &
340 340 data_f2_out((16*3)-1 DOWNTO 16*2) &
341 341 data_f2_out((16*4)-1 DOWNTO 16*3) &
342 342 data_f2_out((16*1)-1 DOWNTO 16*0) &
343 343 data_f2_out((16*2)-1 DOWNTO 16*1) ;
344 344
345 345 data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
346 346 data_f3_out((16*6)-1 DOWNTO 16*5) &
347 347 data_f3_out((16*3)-1 DOWNTO 16*2) &
348 348 data_f3_out((16*4)-1 DOWNTO 16*3) &
349 349 data_f3_out((16*1)-1 DOWNTO 16*0) &
350 350 data_f3_out((16*2)-1 DOWNTO 16*1) ;
351 351
352 352 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
353 353 data_out(0, I) <= data_f0_out_swap(I);
354 354 data_out(1, I) <= data_f1_out_swap(I);
355 355 data_out(2, I) <= data_f2_out_swap(I);
356 356 data_out(3, I) <= data_f3_out_swap(I);
357 357 END GENERATE all_bit_of_data_out;
358 358
359 359 -----------------------------------------------------------------------------
360 360 -- TODO : debug
361 361 -----------------------------------------------------------------------------
362 362 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
363 363 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
364 364 time_out_2(J, I) <= time_out(J)(I);
365 365 END GENERATE all_sample_of_time_out;
366 366 END GENERATE all_bit_of_time_out;
367 367
368 368 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
369 369 GENERIC MAP (tech => tech,
370 370 nb_data_by_buffer_size => nb_data_by_buffer_size)
371 371 PORT MAP (
372 372 clk => clk,
373 373 rstn => rstn,
374 374 run => run,
375 375 nb_data_by_buffer => nb_data_by_buffer,
376 376 data_in_valid => valid_out,
377 377 data_in_ack => valid_ack,
378 378 data_in => data_out,
379 379 time_in => time_out_2,
380 380
381 381 data_out => wdata,
382 382 data_out_wen => data_wen,
383 383 full_almost => full_almost,
384 384 full => full,
385 385
386 386 time_out => arbiter_time_out,
387 387 time_out_new => arbiter_time_out_new
388 388
389 389 );
390 390
391 391 -----------------------------------------------------------------------------
392 392 -----------------------------------------------------------------------------
393 393
394 394 generate_all_fifo: FOR I IN 0 TO 3 GENERATE
395 395 lpp_fifo_1: lpp_fifo
396 396 GENERIC MAP (
397 397 tech => tech,
398 398 Mem_use => use_RAM,
399 399 EMPTY_THRESHOLD_LIMIT => 15,
400 400 FULL_THRESHOLD_LIMIT => 3,
401 401 DataSz => 32,
402 402 AddrSz => 7)
403 403 PORT MAP (
404 404 clk => clk,
405 405 rstn => rstn,
406 406 reUse => '0',
407 407 run => run,
408 408 ren => data_ren(I),
409 409 rdata => s_rdata_v((I+1)*32-1 downto I*32),
410 410 wen => data_wen(I),
411 411 wdata => wdata,
412 412 empty => empty(I),
413 413 full => full(I),
414 414 full_almost => OPEN,
415 415 empty_threshold => empty_almost(I),
416 416 full_threshold => full_almost(I) );
417 417
418 418 END GENERATE generate_all_fifo;
419 419
420 420 -----------------------------------------------------------------------------
421 421 --
422 422 -----------------------------------------------------------------------------
423 423
424 424 all_channel: FOR I IN 3 DOWNTO 0 GENERATE
425 425
426 426 PROCESS (clk, rstn)
427 427 BEGIN
428 428 IF rstn = '0' THEN
429 429 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
430 430 ELSIF clk'event AND clk = '1' THEN
431 431 IF run = '0' THEN
432 432 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
433 433 ELSE
434 434 IF arbiter_time_out_new(I) = '1' THEN -- modif JC 15-01-2015
435 435 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
436 436 END IF;
437 437 END IF;
438 438 END IF;
439 439 END PROCESS;
440 440
441 441 fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out WHEN arbiter_time_out_new(I) = '1' ELSE
442 442 fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
443 443
444 444 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
445 445 PORT MAP (
446 446 clk => clk,
447 447 rstn => rstn,
448 448 run => run,
449 449
450 450 fifo_buffer_time => fifo_buffer_time_s(48*(I+1)-1 DOWNTO 48*I),
451 451
452 452 fifo_data => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
453 453 fifo_empty => empty(I),
454 454 fifo_empty_threshold => empty_almost(I),
455 455 fifo_ren => data_ren(I),
456 456
457 457 dma_fifo_valid_burst => dma_fifo_valid_burst(I),
458 458 dma_fifo_data => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
459 459 dma_fifo_ren => dma_fifo_ren(I),
460 460 dma_buffer_new => dma_buffer_new(I),
461 461 dma_buffer_addr => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
462 462 dma_buffer_length => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
463 463 dma_buffer_full => dma_buffer_full(I),
464 464 dma_buffer_full_err => dma_buffer_full_err(I),
465 465
466 466 status_buffer_ready => status_buffer_ready(I), -- TODO
467 467 addr_buffer => addr_buffer(32*(I+1)-1 DOWNTO 32*I), -- TODO
468 468 length_buffer => length_buffer,--(26*(I+1)-1 DOWNTO 26*I), -- TODO
469 469 ready_buffer => ready_buffer(I), -- TODO
470 buffer_time => buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
470 buffer_time => OPEN,--buffer_time(48*(I+1)-1 DOWNTO 48*I), -- TODO
471 471 error_buffer_full => error_buffer_full(I)); -- TODO
472
473 buffer_time(48*(I+1)-1 DOWNTO 48*I) <= fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I);
472 474
473 475 END GENERATE all_channel;
474 476
475 477
476 478 END beh;
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