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LPP IIR FILTER v2.0.0...
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26
27 27 package FILTERcfg is
28 28
29 29
30 30
31 31
32 32 --===========================================================|
33 33 --========F I L T E R C O N F I G V A L U E S=============|
34 34 --===========================================================|
35 35 --____________________________
36 36 --Bus Width and chanels number|
37 37 --____________________________|
38 38 constant ChanelsCount : integer := 1;
39 39 constant Sample_SZ : integer := 18;
40 40 constant Coef_SZ : integer := 9;
41 41 constant CoefCntPerCel: integer := 6;
42 constant CoefPerCel: integer := 5;
42 43 constant Cels_count : integer := 5;
43 44 constant virgPos : integer := 7;
44 45 constant Mem_use : integer := 1;
45 46
46 47
47 48
48 49 --============================================================
49 50 -- create each initial values for each coefs ============
50 51 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 52 --============================================================
52 53 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
53 54 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
54 55 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
55 56
56 57 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
57 58 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
58 59 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
59 60
60 61 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
61 62 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
62 63 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
63 64
64 65 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
65 66 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
66 67 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
67 68
68 69 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
69 70 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
70 71 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
71 72
72 constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
73 constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
74 constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
73 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
74 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
75 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
75 76
76 constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
77 constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
78 constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
77 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
78 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
79 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
79 80
80 81
81 82 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
82 83 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
83 84 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
84 85
85 86 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
86 87 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
87 88 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
88 89
89 90 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
90 91 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
91 92 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
92 93
93 94 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
94 95 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
95 96 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
96 97
97 98 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
98 99 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
99 100 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
100 101
101 constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
102 constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
103 constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
104 constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
105 constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
106 constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
102 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
103 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
104 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
105 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
106 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
107 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
107 108
108 109 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
109 110
111 constant CoefsInitValCst_JC : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
112 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
113 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
114 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
115 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
116 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
117
110 118
111 119 end;
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@@ -1,266 +1,290
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
22 LIBRARY ieee;
23 USE ieee.std_logic_1164.ALL;
24 LIBRARY grlib;
25 USE grlib.amba.ALL;
26 USE grlib.stdlib.ALL;
27 USE grlib.devices.ALL;
28 LIBRARY lpp;
29 29
30 30
31 31
32 32
33 package iir_filter is
33 PACKAGE iir_filter IS
34 34
35 35
36 36 --===========================================================|
37 37 --================A L U C O N T R O L======================|
38 38 --===========================================================|
39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
39 CONSTANT IDLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
40 CONSTANT MAC_op : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
41 CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
42 CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
43 CONSTANT clr_mac : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
44 CONSTANT MULT_with_clear_ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
44 45
45 46 --____
46 47 --RAM |
47 48 --____|
48 constant use_RAM : integer := 1;
49 constant use_CEL : integer := 0;
49 CONSTANT use_RAM : INTEGER := 1;
50 CONSTANT use_CEL : INTEGER := 0;
50 51
51 52
52 53 --===========================================================|
53 54 --=============C O E F S ====================================|
54 55 --===========================================================|
55 56 -- create a specific type of data for coefs to avoid errors |
56 57 --===========================================================|
57 58
58 type scaleValT is array(natural range <>) of integer;
59 TYPE scaleValT IS ARRAY(NATURAL RANGE <>) OF INTEGER;
59 60
60 type samplT is array(natural range <>,natural range <>) of std_logic;
61 TYPE samplT IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
61 62
62 type in_IIR_CEL_reg is record
63 config : std_logic_vector(31 downto 0);
64 virgPos : std_logic_vector(4 downto 0);
65 end record;
63 TYPE in_IIR_CEL_reg IS RECORD
64 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 virgPos : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 END RECORD;
66 67
67 type out_IIR_CEL_reg is record
68 config : std_logic_vector(31 downto 0);
69 status : std_logic_vector(31 downto 0);
70 end record;
68 TYPE out_IIR_CEL_reg IS RECORD
69 config : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 status : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 END RECORD;
71 72
72 73
73 component APB_IIR_CEL is
74 generic (
75 tech : integer := 0;
76 pindex : integer := 0;
77 paddr : integer := 0;
78 pmask : integer := 16#fff#;
79 pirq : integer := 0;
80 abits : integer := 8;
81 Sample_SZ : integer := 16;
82 ChanelsCount : integer := 6;
83 Coef_SZ : integer := 9;
84 CoefCntPerCel: integer := 6;
85 Cels_count : integer := 5;
86 virgPos : integer := 7;
87 Mem_use : integer := use_RAM
88 );
89 port (
90 rst : in std_logic;
91 clk : in std_logic;
92 apbi : in apb_slv_in_type;
93 apbo : out apb_slv_out_type;
94 sample_clk : in std_logic;
95 sample_clk_out : out std_logic;
96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
98 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
99 );
100 end component;
74 COMPONENT APB_IIR_CEL IS
75 GENERIC (
76 tech : INTEGER := 0;
77 pindex : INTEGER := 0;
78 paddr : INTEGER := 0;
79 pmask : INTEGER := 16#fff#;
80 pirq : INTEGER := 0;
81 abits : INTEGER := 8;
82 Sample_SZ : INTEGER := 16;
83 ChanelsCount : INTEGER := 6;
84 Coef_SZ : INTEGER := 9;
85 CoefCntPerCel : INTEGER := 6;
86 Cels_count : INTEGER := 5;
87 virgPos : INTEGER := 7;
88 Mem_use : INTEGER := use_RAM
89 );
90 PORT (
91 rst : IN STD_LOGIC;
92 clk : IN STD_LOGIC;
93 apbi : IN apb_slv_in_type;
94 apbo : OUT apb_slv_out_type;
95 sample_clk : IN STD_LOGIC;
96 sample_clk_out : OUT STD_LOGIC;
97 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
98 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
99 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
100 );
101 END COMPONENT;
101 102
102 103
103 component Top_IIR is
104 generic(
105 Sample_SZ : integer := 18;
106 ChanelsCount : integer := 1;
107 Coef_SZ : integer := 9;
108 CoefCntPerCel: integer := 6;
109 Cels_count : integer := 5);
110 port(
111 reset : in std_logic;
112 clk : in std_logic;
113 sample_clk : in std_logic;
114 -- BP : in std_logic;
115 -- BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(15 downto 0);
117 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
118 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
119 );
120 end component;
104 COMPONENT Top_IIR IS
105 GENERIC(
106 Sample_SZ : INTEGER := 18;
107 ChanelsCount : INTEGER := 1;
108 Coef_SZ : INTEGER := 9;
109 CoefCntPerCel : INTEGER := 6;
110 Cels_count : INTEGER := 5);
111 PORT(
112 reset : IN STD_LOGIC;
113 clk : IN STD_LOGIC;
114 sample_clk : IN STD_LOGIC;
115 -- BP : in std_logic;
116 -- BPinput : in std_logic_vector(3 downto 0);
117 LVLinput : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
118 INsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
119 OUTsample : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)
120 );
121 END COMPONENT;
121 122
122
123 COMPONENT IIR_CEL_CTRLR_v2
124 GENERIC (
125 tech : INTEGER;
126 Mem_use : INTEGER;
127 Sample_SZ : INTEGER;
128 Coef_SZ : INTEGER;
129 Coef_Nb : INTEGER;
130 Coef_sel_SZ : INTEGER;
131 Cels_count : INTEGER;
132 ChanelsCount : INTEGER);
133 PORT (
134 rstn : IN STD_LOGIC;
135 clk : IN STD_LOGIC;
136 virg_pos : IN INTEGER;
137 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
138 sample_in_val : IN STD_LOGIC;
139 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 sample_out_val : OUT STD_LOGIC;
141 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
142 END COMPONENT;
143
123 144
124 145 --component FilterCTRLR is
125 146 --port(
126 147 -- reset : in std_logic;
127 148 -- clk : in std_logic;
128 149 -- sample_clk : in std_logic;
129 150 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
130 151 -- sample_in : in samplT;
131 152 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
132 153 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
133 154 --);
134 155 --end component;
135 156
136 157
137 158 --component FILTER_RAM_CTRLR is
138 159 --port(
139 160 -- reset : in std_logic;
140 161 -- clk : in std_logic;
141 162 -- run : in std_logic;
142 163 -- GO_0 : in std_logic;
143 164 -- B_A : in std_logic;
144 165 -- writeForce : in std_logic;
145 166 -- next_blk : in std_logic;
146 167 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
147 168 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
148 169 --);
149 170 --end component;
150 171
151 172
152 component IIR_CEL_CTRLR is
153 generic(
154 tech : integer := 0;
155 Sample_SZ : integer := 16;
156 ChanelsCount : integer := 1;
157 Coef_SZ : integer := 9;
158 CoefCntPerCel: integer := 3;
159 Cels_count : integer := 5;
160 Mem_use : integer := use_RAM
161 );
162 port(
163 reset : in std_logic;
164 clk : in std_logic;
165 sample_clk : in std_logic;
166 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
167 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
168 virg_pos : in integer;
169 GOtest : out std_logic;
170 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
171 );
172 end component;
173
174
175 component RAM is
176 generic(
177 Input_SZ_1 : integer := 8
178 );
179 port( WD : in std_logic_vector(Input_SZ_1-1 downto 0); RD : out
180 std_logic_vector(Input_SZ_1-1 downto 0);WEN, REN : in std_logic;
181 WADDR : in std_logic_vector(7 downto 0); RADDR : in
182 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
183 ) ;
184 end component;
173 COMPONENT IIR_CEL_CTRLR IS
174 GENERIC(
175 tech : INTEGER := 0;
176 Sample_SZ : INTEGER := 16;
177 ChanelsCount : INTEGER := 1;
178 Coef_SZ : INTEGER := 9;
179 CoefCntPerCel : INTEGER := 3;
180 Cels_count : INTEGER := 5;
181 Mem_use : INTEGER := use_RAM
182 );
183 PORT(
184 reset : IN STD_LOGIC;
185 clk : IN STD_LOGIC;
186 sample_clk : IN STD_LOGIC;
187 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
188 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
189 virg_pos : IN INTEGER;
190 GOtest : OUT STD_LOGIC;
191 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
192 );
193 END COMPONENT;
185 194
186 195
187 component RAM_CEL is
188 port( WD : in std_logic_vector(35 downto 0); RD : out
189 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
190 WADDR : in std_logic_vector(7 downto 0); RADDR : in
191 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
192 ) ;
193 end component;
196 COMPONENT RAM IS
197 GENERIC(
198 Input_SZ_1 : INTEGER := 8
199 );
200 PORT(WD : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); RD : OUT
201 STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); WEN, REN : IN STD_LOGIC;
202 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0); RADDR : IN
203 STD_LOGIC_VECTOR(7 DOWNTO 0); RWCLK, RESET : IN STD_LOGIC
204 ) ;
205 END COMPONENT;
206
207 COMPONENT RAM_CEL
208 GENERIC (
209 Sample_SZ : INTEGER);
210 PORT (
211 WD : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
212 RD : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
213 WEN, REN : IN STD_LOGIC;
214 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
215 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
216 RWCLK, RESET : IN STD_LOGIC);
217 END COMPONENT;
194 218
195 component IIR_CEL_FILTER is
196 generic(
197 tech : integer := 0;
198 Sample_SZ : integer := 16;
199 ChanelsCount : integer := 1;
200 Coef_SZ : integer := 9;
201 CoefCntPerCel: integer := 3;
202 Cels_count : integer := 5;
203 Mem_use : integer := use_RAM);
204 port(
205 reset : in std_logic;
206 clk : in std_logic;
207 sample_clk : in std_logic;
208 regs_in : in in_IIR_CEL_reg;
209 regs_out : in out_IIR_CEL_reg;
210 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
211 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
212 GOtest : out std_logic;
213 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
214
215 );
216 end component;
219 COMPONENT IIR_CEL_FILTER IS
220 GENERIC(
221 tech : INTEGER := 0;
222 Sample_SZ : INTEGER := 16;
223 ChanelsCount : INTEGER := 1;
224 Coef_SZ : INTEGER := 9;
225 CoefCntPerCel : INTEGER := 3;
226 Cels_count : INTEGER := 5;
227 Mem_use : INTEGER := use_RAM);
228 PORT(
229 reset : IN STD_LOGIC;
230 clk : IN STD_LOGIC;
231 sample_clk : IN STD_LOGIC;
232 regs_in : IN in_IIR_CEL_reg;
233 regs_out : IN out_IIR_CEL_reg;
234 sample_in : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
235 sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
236 GOtest : OUT STD_LOGIC;
237 coefs : IN STD_LOGIC_VECTOR(Coef_SZ*CoefCntPerCel*Cels_count-1 DOWNTO 0)
238
239 );
240 END COMPONENT;
217 241
218 242
219 component RAM_CTRLR2 is
220 generic(
221 tech : integer := 0;
222 Input_SZ_1 : integer := 16;
223 Mem_use : integer := use_RAM
224 );
225 port(
226 reset : in std_logic;
227 clk : in std_logic;
228 WD_sel : in std_logic;
229 Read : in std_logic;
230 WADDR_sel : in std_logic;
231 count : in std_logic;
232 SVG_ADDR : in std_logic;
233 Write : in std_logic;
234 GO_0 : in std_logic;
235 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
236 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
237 );
238 end component;
243 COMPONENT RAM_CTRLR2 IS
244 GENERIC(
245 tech : INTEGER := 0;
246 Input_SZ_1 : INTEGER := 16;
247 Mem_use : INTEGER := use_RAM
248 );
249 PORT(
250 reset : IN STD_LOGIC;
251 clk : IN STD_LOGIC;
252 WD_sel : IN STD_LOGIC;
253 Read : IN STD_LOGIC;
254 WADDR_sel : IN STD_LOGIC;
255 count : IN STD_LOGIC;
256 SVG_ADDR : IN STD_LOGIC;
257 Write : IN STD_LOGIC;
258 GO_0 : IN STD_LOGIC;
259 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
260 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
261 );
262 END COMPONENT;
239 263
240 component APB_IIR_Filter is
241 generic (
242 tech : integer := 0;
243 pindex : integer := 0;
244 paddr : integer := 0;
245 pmask : integer := 16#fff#;
246 pirq : integer := 0;
247 abits : integer := 8;
248 Sample_SZ : integer := 16;
249 ChanelsCount : integer := 1;
250 Coef_SZ : integer := 9;
251 CoefCntPerCel: integer := 6;
252 Cels_count : integer := 5;
253 virgPos : integer := 3;
254 Mem_use : integer := use_RAM
255 );
256 port (
257 rst : in std_logic;
258 clk : in std_logic;
259 apbi : in apb_slv_in_type;
260 apbo : out apb_slv_out_type;
261 sample_clk_out : out std_logic;
262 GOtest : out std_logic;
263 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
264 );
265 end component;
266 end;
264 COMPONENT APB_IIR_Filter IS
265 GENERIC (
266 tech : INTEGER := 0;
267 pindex : INTEGER := 0;
268 paddr : INTEGER := 0;
269 pmask : INTEGER := 16#fff#;
270 pirq : INTEGER := 0;
271 abits : INTEGER := 8;
272 Sample_SZ : INTEGER := 16;
273 ChanelsCount : INTEGER := 1;
274 Coef_SZ : INTEGER := 9;
275 CoefCntPerCel : INTEGER := 6;
276 Cels_count : INTEGER := 5;
277 virgPos : INTEGER := 3;
278 Mem_use : INTEGER := use_RAM
279 );
280 PORT (
281 rst : IN STD_LOGIC;
282 clk : IN STD_LOGIC;
283 apbi : IN apb_slv_in_type;
284 apbo : OUT apb_slv_out_type;
285 sample_clk_out : OUT STD_LOGIC;
286 GOtest : OUT STD_LOGIC;
287 CoefsInitVal : IN STD_LOGIC_VECTOR((Cels_count*CoefCntPerCel*Coef_SZ)-1 DOWNTO 0) := (OTHERS => '1')
288 );
289 END COMPONENT;
290 END;
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@@ -1,81 +1,77
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
27 --IDLE =0000 MAC =0001 MULT =0010 ADD =0011 CLRMAC =0100
28 --NOT =0101 AND =0110 OR =0111 XOR =1000
29 --SHIFTleft =1001 SHIFTright =1010
30
31 entity ALU is
32 generic(
33 Arith_en : integer := 1;
34 Logic_en : integer := 1;
35 Input_SZ_1 : integer := 16;
36 Input_SZ_2 : integer := 9
37
38 );
39 port(
40 clk : in std_logic;
41 reset : in std_logic;
42 ctrl : in std_logic_vector(3 downto 0);
43 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
44 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
45 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
46 );
47 end entity;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 --IDLE = 0000
28 --MAC = 0001
29 --MULT = 0010 and set MULT in ADD reg
30 --ADD = 0011
31 --CLRMAC = 0100
48 32
49 33
50
51 architecture ar_ALU of ALU is
52
53
54
55 signal clr_MAC : std_logic:='1';
56
57
58 begin
34 ENTITY ALU IS
35 GENERIC(
36 Arith_en : INTEGER := 1;
37 Logic_en : INTEGER := 1;
38 Input_SZ_1 : INTEGER := 16;
39 Input_SZ_2 : INTEGER := 9
59 40
60 clr_MAC <= '1' when ctrl = "0100" else '0';
41 );
42 PORT(
43 clk : IN STD_LOGIC;
44 reset : IN STD_LOGIC;
45 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
47 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
48 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
49 );
50 END ENTITY;
61 51
52 ARCHITECTURE ar_ALU OF ALU IS
62 53
63 arith : if Arith_en = 1 generate
64 MACinst : MAC
65 generic map(Input_SZ_1,Input_SZ_2)
66 port map(clk,reset,clr_MAC,ctrl(1 downto 0),OP1,OP2,RES);
67 end generate;
54 SIGNAL clr_MAC : STD_LOGIC := '1';
55
56 BEGIN
57 clr_MAC <= '1' WHEN ctrl = "0100" OR ctrl = "0101" OR ctrl = "0110" ELSE '0';
68 58
69 end architecture;
59 arith : IF Arith_en = 1 GENERATE
60 MACinst : MAC
61 GENERIC MAP(Input_SZ_1, Input_SZ_2)
62 PORT MAP(clk, reset, clr_MAC, ctrl(1 DOWNTO 0), OP1, OP2, RES);
63 END GENERATE;
64
65 END ARCHITECTURE;
70 66
71 67
72 68
73 69
74 70
75 71
76 72
77 73
78 74
79 75
80 76
81 77
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@@ -1,72 +1,75
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 library lpp;
26 use lpp.general_purpose.all;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
26 USE lpp.general_purpose.ALL;
27 27
28 28
29 29
30 entity Adder is
31 generic(
32 Input_SZ_A : integer := 16;
33 Input_SZ_B : integer := 16
30 ENTITY Adder IS
31 GENERIC(
32 Input_SZ_A : INTEGER := 16;
33 Input_SZ_B : INTEGER := 16
34 34
35 );
36 port(
37 clk : in std_logic;
38 reset : in std_logic;
39 clr : in std_logic;
40 add : in std_logic;
41 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
42 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
43 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
44 );
45 end entity;
35 );
36 PORT(
37 clk : IN STD_LOGIC;
38 reset : IN STD_LOGIC;
39 clr : IN STD_LOGIC;
40 load : IN STD_LOGIC;
41 add : IN STD_LOGIC;
42 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
43 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
44 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
45 );
46 END ENTITY;
46 47
47 48
48 49
49 50
50 architecture ar_Adder of Adder is
51 ARCHITECTURE ar_Adder OF Adder IS
51 52
52 signal REG : std_logic_vector(Input_SZ_A-1 downto 0);
53 signal RESADD : std_logic_vector(Input_SZ_A-1 downto 0);
53 SIGNAL REG : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
54 SIGNAL RESADD : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
54 55
55 begin
56 BEGIN
56 57
57 RES <= REG;
58 RESADD <= std_logic_vector(resize(signed(OP1)+signed(OP2),Input_SZ_A));
58 RES <= REG;
59 RESADD <= STD_LOGIC_VECTOR(resize(SIGNED(OP1)+SIGNED(OP2), Input_SZ_A));
59 60
60 process(clk,reset)
61 begin
62 if reset = '0' then
63 REG <= (others => '0');
64 elsif clk'event and clk ='1' then
65 if clr = '1' then
66 REG <= (others => '0');
67 elsif add = '1' then
68 REG <= RESADD;
69 end if;
70 end if;
71 end process;
72 end ar_Adder;
61 PROCESS(clk, reset)
62 BEGIN
63 IF reset = '0' THEN
64 REG <= (OTHERS => '0');
65 ELSIF clk'EVENT AND clk = '1' then
66 IF clr = '1' THEN
67 REG <= (OTHERS => '0');
68 ELSIF add = '1' THEN
69 REG <= RESADD;
70 ELSIF load = '1' THEN
71 REG <= OP2;
72 END IF;
73 END IF;
74 END PROCESS;
75 END ar_Adder;
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@@ -1,208 +1,241
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
22 --UPDATE
23 -------------------------------------------------------------------------------
24 -- 14-03-2013 - Jean-christophe Pellion
25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 -------------------------------------------------------------------------------
27
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
24 30
25 31
26 32
27 package general_purpose is
33 PACKAGE general_purpose IS
28 34
29 35
30 36
31 component Clk_divider is
32 generic(OSC_freqHz : integer := 50000000;
33 TargetFreq_Hz : integer := 50000);
34 Port ( clk : in STD_LOGIC;
35 reset : in STD_LOGIC;
36 clk_divided : out STD_LOGIC);
37 end component;
37 COMPONENT Clk_divider IS
38 GENERIC(OSC_freqHz : INTEGER := 50000000;
39 TargetFreq_Hz : INTEGER := 50000);
40 PORT (clk : IN STD_LOGIC;
41 reset : IN STD_LOGIC;
42 clk_divided : OUT STD_LOGIC);
43 END COMPONENT;
38 44
39 45
40 component Adder is
41 generic(
42 Input_SZ_A : integer := 16;
43 Input_SZ_B : integer := 16
46 COMPONENT Adder IS
47 GENERIC(
48 Input_SZ_A : INTEGER := 16;
49 Input_SZ_B : INTEGER := 16
44 50
45 );
46 port(
47 clk : in std_logic;
48 reset : in std_logic;
49 clr : in std_logic;
50 add : in std_logic;
51 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
52 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
53 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
54 );
55 end component;
51 );
52 PORT(
53 clk : IN STD_LOGIC;
54 reset : IN STD_LOGIC;
55 clr : IN STD_LOGIC;
56 load : IN STD_LOGIC;
57 add : IN STD_LOGIC;
58 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
59 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
60 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
61 );
62 END COMPONENT;
56 63
57 component ADDRcntr is
58 port(
59 clk : in std_logic;
60 reset : in std_logic;
61 count : in std_logic;
62 clr : in std_logic;
63 Q : out std_logic_vector(7 downto 0)
64 );
65 end component;
64 COMPONENT ADDRcntr IS
65 PORT(
66 clk : IN STD_LOGIC;
67 reset : IN STD_LOGIC;
68 count : IN STD_LOGIC;
69 clr : IN STD_LOGIC;
70 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
71 );
72 END COMPONENT;
66 73
67 component ALU is
68 generic(
69 Arith_en : integer := 1;
70 Logic_en : integer := 1;
71 Input_SZ_1 : integer := 16;
72 Input_SZ_2 : integer := 9
74 COMPONENT ALU IS
75 GENERIC(
76 Arith_en : INTEGER := 1;
77 Logic_en : INTEGER := 1;
78 Input_SZ_1 : INTEGER := 16;
79 Input_SZ_2 : INTEGER := 9
73 80
74 );
75 port(
76 clk : in std_logic;
77 reset : in std_logic;
78 ctrl : in std_logic_vector(3 downto 0);
79 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
80 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
81 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
82 );
83 end component;
81 );
82 PORT(
83 clk : IN STD_LOGIC;
84 reset : IN STD_LOGIC;
85 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
87 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
88 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
89 );
90 END COMPONENT;
84 91
85 92
86 component MAC is
87 generic(
88 Input_SZ_A : integer := 8;
89 Input_SZ_B : integer := 8
93 COMPONENT MAC IS
94 GENERIC(
95 Input_SZ_A : INTEGER := 8;
96 Input_SZ_B : INTEGER := 8
90 97
91 );
92 port(
93 clk : in std_logic;
94 reset : in std_logic;
95 clr_MAC : in std_logic;
96 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
97 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
98 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
99 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
100 );
101 end component;
98 );
99 PORT(
100 clk : IN STD_LOGIC;
101 reset : IN STD_LOGIC;
102 clr_MAC : IN STD_LOGIC;
103 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
104 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
105 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
106 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
107 );
108 END COMPONENT;
102 109
103 110
104 component MAC_CONTROLER is
105 port(
106 ctrl : in std_logic_vector(1 downto 0);
107 MULT : out std_logic;
108 ADD : out std_logic;
109 MACMUX_sel : out std_logic;
110 MACMUX2_sel : out std_logic
111
112 );
113 end component;
111 COMPONENT MAC_CONTROLER IS
112 PORT(
113 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
114 MULT : OUT STD_LOGIC;
115 ADD : OUT STD_LOGIC;
116 LOAD_ADDER : out std_logic;
117 MACMUX_sel : OUT STD_LOGIC;
118 MACMUX2_sel : OUT STD_LOGIC
119 );
120 END COMPONENT;
114 121
115 component MAC_MUX is
116 generic(
117 Input_SZ_A : integer := 16;
118 Input_SZ_B : integer := 16
122 COMPONENT MAC_MUX IS
123 GENERIC(
124 Input_SZ_A : INTEGER := 16;
125 Input_SZ_B : INTEGER := 16
119 126
120 );
121 port(
122 sel : in std_logic;
123 INA1 : in std_logic_vector(Input_SZ_A-1 downto 0);
124 INA2 : in std_logic_vector(Input_SZ_A-1 downto 0);
125 INB1 : in std_logic_vector(Input_SZ_B-1 downto 0);
126 INB2 : in std_logic_vector(Input_SZ_B-1 downto 0);
127 OUTA : out std_logic_vector(Input_SZ_A-1 downto 0);
128 OUTB : out std_logic_vector(Input_SZ_B-1 downto 0)
129 );
130 end component;
127 );
128 PORT(
129 sel : IN STD_LOGIC;
130 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
131 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
132 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
133 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
134 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
135 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
136 );
137 END COMPONENT;
131 138
132 139
133 component MAC_MUX2 is
134 generic(Input_SZ : integer := 16);
135 port(
136 sel : in std_logic;
137 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
138 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
139 RES : out std_logic_vector(Input_SZ-1 downto 0)
140 );
141 end component;
140 COMPONENT MAC_MUX2 IS
141 GENERIC(Input_SZ : INTEGER := 16);
142 PORT(
143 sel : IN STD_LOGIC;
144 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
145 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
146 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
147 );
148 END COMPONENT;
149
150
151 COMPONENT MAC_REG IS
152 GENERIC(size : INTEGER := 16);
153 PORT(
154 reset : IN STD_LOGIC;
155 clk : IN STD_LOGIC;
156 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
157 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
158 );
159 END COMPONENT;
142 160
143 161
144 component MAC_REG is
145 generic(size : integer := 16);
146 port(
147 reset : in std_logic;
148 clk : in std_logic;
149 D : in std_logic_vector(size-1 downto 0);
150 Q : out std_logic_vector(size-1 downto 0)
151 );
152 end component;
162 COMPONENT MUX2 IS
163 GENERIC(Input_SZ : INTEGER := 16);
164 PORT(
165 sel : IN STD_LOGIC;
166 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
167 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
168 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
169 );
170 END COMPONENT;
153 171
172 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
173 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
174
175 COMPONENT MUXN
176 GENERIC (
177 Input_SZ : INTEGER;
178 NbStage : INTEGER);
179 PORT (
180 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
181 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
182 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
183 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
184 END COMPONENT;
154 185
155 component MUX2 is
156 generic(Input_SZ : integer := 16);
157 port(
158 sel : in std_logic;
159 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
160 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
161 RES : out std_logic_vector(Input_SZ-1 downto 0)
162 );
163 end component;
186
164 187
165 component Multiplier is
166 generic(
167 Input_SZ_A : integer := 16;
168 Input_SZ_B : integer := 16
188 COMPONENT Multiplier IS
189 GENERIC(
190 Input_SZ_A : INTEGER := 16;
191 Input_SZ_B : INTEGER := 16
169 192
170 );
171 port(
172 clk : in std_logic;
173 reset : in std_logic;
174 mult : in std_logic;
175 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
176 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
177 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
178 );
179 end component;
193 );
194 PORT(
195 clk : IN STD_LOGIC;
196 reset : IN STD_LOGIC;
197 mult : IN STD_LOGIC;
198 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
199 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
200 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
201 );
202 END COMPONENT;
180 203
181 component REG is
182 generic(size : integer := 16 ; initial_VALUE : integer := 0);
183 port(
184 reset : in std_logic;
185 clk : in std_logic;
186 D : in std_logic_vector(size-1 downto 0);
187 Q : out std_logic_vector(size-1 downto 0)
188 );
189 end component;
204 COMPONENT REG IS
205 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
206 PORT(
207 reset : IN STD_LOGIC;
208 clk : IN STD_LOGIC;
209 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
210 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
211 );
212 END COMPONENT;
190 213
191 214
192 215
193 component RShifter is
194 generic(
195 Input_SZ : integer := 16;
196 shift_SZ : integer := 4
197 );
198 port(
199 clk : in std_logic;
200 reset : in std_logic;
201 shift : in std_logic;
202 OP : in std_logic_vector(Input_SZ-1 downto 0);
203 cnt : in std_logic_vector(shift_SZ-1 downto 0);
204 RES : out std_logic_vector(Input_SZ-1 downto 0)
205 );
206 end component;
216 COMPONENT RShifter IS
217 GENERIC(
218 Input_SZ : INTEGER := 16;
219 shift_SZ : INTEGER := 4
220 );
221 PORT(
222 clk : IN STD_LOGIC;
223 reset : IN STD_LOGIC;
224 shift : IN STD_LOGIC;
225 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
226 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
227 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
228 );
229 END COMPONENT;
207 230
208 end;
231 COMPONENT SYNC_FF
232 GENERIC (
233 NB_FF_OF_SYNC : INTEGER);
234 PORT (
235 clk : IN STD_LOGIC;
236 rstn : IN STD_LOGIC;
237 A : IN STD_LOGIC;
238 A_sync : OUT STD_LOGIC);
239 END COMPONENT;
240
241 END;
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@@ -1,14 +1,16
1 1 ADDRcntr.vhd
2 2 ALU.vhd
3 3 Adder.vhd
4 4 Clk_divider.vhd
5 5 MAC.vhd
6 6 MAC_CONTROLER.vhd
7 7 MAC_MUX.vhd
8 8 MAC_MUX2.vhd
9 9 MAC_REG.vhd
10 10 MUX2.vhd
11 MUXN.vhd
11 12 Multiplier.vhd
12 13 REG.vhd
13 14 Shifter.vhd
15 SYNC_FF.vhd
14 16 general_purpose.vhd
Show file before | Show file after | Hide comments
@@ -1,105 +1,193
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 library lpp;
25 use lpp.lpp_ad_conv.all;
26 use lpp.general_purpose.Clk_divider;
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
30
31 ENTITY ADS7886_drvr IS
32 GENERIC(
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
36 PORT (
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
27 42
28 entity ADS7886_drvr is
29 generic(ChanelCount : integer;
30 clkkHz : integer);
31 Port ( clk : in STD_LOGIC;
32 reset : in STD_LOGIC;
33 smplClk: in STD_LOGIC;
34 DataReady : out std_logic;
35 smpout : out Samples_out(ChanelCount-1 downto 0);
36 AD_in : in AD7688_in(ChanelCount-1 downto 0);
37 AD_out : out AD7688_out);
38 end ADS7886_drvr;
43 -- DATA --
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
51 );
52 END ADS7886_drvr;
39 53
40 architecture ar_ADS7886_drvr of ADS7886_drvr is
41
42 constant convTrigger : integer:= clkkHz*1/1000; --tconv = 1.6Β΅s
54 ARCHITECTURE ar_ADS7886_drvr OF ADS7886_drvr IS
43 55
44 signal i : integer range 0 to convTrigger :=0;
45 signal clk_int : std_logic;
46 signal smplClk_reg : std_logic;
47 signal cnv_int : std_logic;
48 signal smpout_int : Samples_out(ChanelCount-1 downto 0);
49
50
51 begin
56 COMPONENT SYNC_FF
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
52 65
53 66
54 clkdiv: if clkkHz>=20000 generate
55 clkdivider: Clk_divider
56 generic map(clkkHz*1000,19000000)
57 Port map( clk ,reset,clk_int);
58 end generate;
59
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
60 74
61 clknodiv: if clkkHz<20000 generate
62 nodiv: clk_int <= clk;
63 end generate;
75 SIGNAL cnv_run_sync : STD_LOGIC;
76
77 BEGIN
78 -----------------------------------------------------------------------------
79 -- CONV
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
92 ELSE
93 cnv_s <= '0';
94 END IF;
95 ELSE
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
98 END IF;
99 ELSE
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
102 END IF;
103 END IF;
104 END PROCESS;
64 105
65 AD_out.CNV <= cnv_int;
66 AD_out.SCK <= clk_int;
106 cnv <= cnv_s;
107
108 -----------------------------------------------------------------------------
67 109
68 110
69 sckgen: process(clk,reset)
70 begin
71 if reset = '0' then
72 i <= 0;
73 cnv_int <= '0';
74 smplClk_reg <= '0';
75 elsif clk'event and clk = '1' then
76 if smplClk = '1' and smplClk_reg = '0' then
77 if i = convTrigger then
78 smplClk_reg <= '1';
79 i <= 0;
80 cnv_int <= '0';
81 else
82 i <= i+1;
83 cnv_int <= '1';
84 end if;
85 elsif smplClk = '0' and smplClk_reg = '1' then
86 smplClk_reg <= '0';
87 end if;
88 end if;
89 end process;
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
114
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
119 clk => clk,
120 rstn => rstn,
121 A => cnv_s,
122 A_sync => cnv_sync);
123
124 PROCESS (clk, rstn)
125 BEGIN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
133 END PROCESS;
134
135 -----------------------------------------------------------------------------
136
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
141 clk => clk,
142 rstn => rstn,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
90 145
91 146
92 NDMSK: for i in 0 to ChanelCount-1
93 generate
94 smpout(i) <= smpout_int(i) and X"0FFF";
95 end generate;
96
147
148 -----------------------------------------------------------------------------
149 -- DATA
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
161
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
97 169
98 spidrvr: AD7688_spi_if
99 generic map(ChanelCount)
100 Port map(clk_int,reset,cnv_int,DataReady,AD_in,smpout_int);
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 shift_reg(l)(15) <= sdo(l);
173 shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 END LOOP;
175 SCK <= '0';
176 ELSE
177 SCK <= '1';
178 END IF;
101 179
102
180 IF sample_bit_counter = 31 THEN
181 sample_val <= '1';
182 FOR l IN 0 TO ChanelCount-1 LOOP
183 sample(l)(15) <= sdo(l);
184 sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
185 END LOOP;
186 ELSE
187 sample_val <= '0';
188 END IF;
189 END IF;
190 END PROCESS;
191
192 END ar_ADS7886_drvr;
103 193
104 end ar_ADS7886_drvr;
105
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