##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Add debug reg for LFR_MS
pellion -
r313:7171ec567127 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,503 +1,580
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_val : STD_LOGIC;
166 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
167 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
168 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
169 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170
170
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
171 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172
172
173 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 -----------------------------------------------------------------------------
174 -----------------------------------------------------------------------------
174
175
175 BEGIN -- beh
176 BEGIN -- beh
176
177
177 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
178 -- CLK
179 -- CLK
179 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
180
181
181 PROCESS(clk_50)
182 PROCESS(clk_50)
182 BEGIN
183 BEGIN
183 IF clk_50'EVENT AND clk_50 = '1' THEN
184 IF clk_50'EVENT AND clk_50 = '1' THEN
184 clk_50_s <= NOT clk_50_s;
185 clk_50_s <= NOT clk_50_s;
185 END IF;
186 END IF;
186 END PROCESS;
187 END PROCESS;
187
188
188 PROCESS(clk_50_s)
189 PROCESS(clk_50_s)
189 BEGIN
190 BEGIN
190 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
191 clk_25 <= NOT clk_25;
192 clk_25 <= NOT clk_25;
192 END IF;
193 END IF;
193 END PROCESS;
194 END PROCESS;
194
195
195 PROCESS(clk_49)
196 PROCESS(clk_49)
196 BEGIN
197 BEGIN
197 IF clk_49'EVENT AND clk_49 = '1' THEN
198 IF clk_49'EVENT AND clk_49 = '1' THEN
198 clk_24 <= NOT clk_24;
199 clk_24 <= NOT clk_24;
199 END IF;
200 END IF;
200 END PROCESS;
201 END PROCESS;
201
202
202 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
203
204
204 PROCESS (clk_25, reset)
205 PROCESS (clk_25, reset)
205 BEGIN -- PROCESS
206 BEGIN -- PROCESS
206 IF reset = '0' THEN -- asynchronous reset (active low)
207 IF reset = '0' THEN -- asynchronous reset (active low)
207 LED0 <= '0';
208 LED0 <= '0';
208 LED1 <= '0';
209 LED1 <= '0';
209 LED2 <= '0';
210 LED2 <= '0';
210 --IO1 <= '0';
211 --IO1 <= '0';
211 --IO2 <= '1';
212 --IO2 <= '1';
212 --IO3 <= '0';
213 --IO3 <= '0';
213 --IO4 <= '0';
214 --IO4 <= '0';
214 --IO5 <= '0';
215 --IO5 <= '0';
215 --IO6 <= '0';
216 --IO6 <= '0';
216 --IO7 <= '0';
217 --IO7 <= '0';
217 --IO8 <= '0';
218 --IO8 <= '0';
218 --IO9 <= '0';
219 --IO9 <= '0';
219 --IO10 <= '0';
220 --IO10 <= '0';
220 --IO11 <= '0';
221 --IO11 <= '0';
221 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
222 LED0 <= '0';
223 LED0 <= '0';
223 LED1 <= '1';
224 LED1 <= '1';
224 LED2 <= BP0;
225 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
225 --IO1 <= '1';
226 --IO1 <= '1';
226 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
227 --IO3 <= ADC_SDO(0);
228 --IO3 <= ADC_SDO(0);
228 --IO4 <= ADC_SDO(1);
229 --IO4 <= ADC_SDO(1);
229 --IO5 <= ADC_SDO(2);
230 --IO5 <= ADC_SDO(2);
230 --IO6 <= ADC_SDO(3);
231 --IO6 <= ADC_SDO(3);
231 --IO7 <= ADC_SDO(4);
232 --IO7 <= ADC_SDO(4);
232 --IO8 <= ADC_SDO(5);
233 --IO8 <= ADC_SDO(5);
233 --IO9 <= ADC_SDO(6);
234 --IO9 <= ADC_SDO(6);
234 --IO10 <= ADC_SDO(7);
235 --IO10 <= ADC_SDO(7);
235 IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
236 END IF;
237 END IF;
237 END PROCESS;
238 END PROCESS;
238
239
239 PROCESS (clk_24, reset)
240 PROCESS (clk_24, reset)
240 BEGIN -- PROCESS
241 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 IF reset = '0' THEN -- asynchronous reset (active low)
242 I00_s <= '0';
243 I00_s <= '0';
243 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
244 I00_s <= NOT I00_s;
245 I00_s <= NOT I00_s ;
245 END IF;
246 END IF;
246 END PROCESS;
247 END PROCESS;
247 -- IO0 <= I00_s;
248 -- IO0 <= I00_s;
248
249
249 --UARTs
250 --UARTs
250 nCTS1 <= '1';
251 nCTS1 <= '1';
251 nCTS2 <= '1';
252 nCTS2 <= '1';
252 nDCD2 <= '1';
253 nDCD2 <= '1';
253
254
254 --EXT CONNECTOR
255 --EXT CONNECTOR
255
256
256 --SPACE WIRE
257 --SPACE WIRE
257
258
258 leon3_soc_1 : leon3_soc
259 leon3_soc_1 : leon3_soc
259 GENERIC MAP (
260 GENERIC MAP (
260 fabtech => apa3e,
261 fabtech => apa3e,
261 memtech => apa3e,
262 memtech => apa3e,
262 padtech => inferred,
263 padtech => inferred,
263 clktech => inferred,
264 clktech => inferred,
264 disas => 0,
265 disas => 0,
265 dbguart => 0,
266 dbguart => 0,
266 pclow => 2,
267 pclow => 2,
267 clk_freq => 25000,
268 clk_freq => 25000,
268 NB_CPU => 1,
269 NB_CPU => 1,
269 ENABLE_FPU => 1,
270 ENABLE_FPU => 1,
270 FPU_NETLIST => 0,
271 FPU_NETLIST => 0,
271 ENABLE_DSU => 1,
272 ENABLE_DSU => 1,
272 ENABLE_AHB_UART => 1,
273 ENABLE_AHB_UART => 1,
273 ENABLE_APB_UART => 1,
274 ENABLE_APB_UART => 1,
274 ENABLE_IRQMP => 1,
275 ENABLE_IRQMP => 1,
275 ENABLE_GPT => 1,
276 ENABLE_GPT => 1,
276 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_MASTER => NB_AHB_MASTER,
277 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_AHB_SLAVE => NB_AHB_SLAVE,
278 NB_APB_SLAVE => NB_APB_SLAVE)
279 NB_APB_SLAVE => NB_APB_SLAVE)
279 PORT MAP (
280 PORT MAP (
280 clk => clk_25,
281 clk => clk_25,
281 reset => reset,
282 reset => reset,
282 errorn => errorn,
283 errorn => errorn,
283 ahbrxd => TXD1,
284 ahbrxd => TXD1,
284 ahbtxd => RXD1,
285 ahbtxd => RXD1,
285 urxd1 => TXD2,
286 urxd1 => TXD2,
286 utxd1 => RXD2,
287 utxd1 => RXD2,
287 address => SRAM_A,
288 address => SRAM_A,
288 data => SRAM_DQ,
289 data => SRAM_DQ,
289 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE0 => SRAM_nBE(0),
290 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE1 => SRAM_nBE(1),
291 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE2 => SRAM_nBE(2),
292 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_BE3 => SRAM_nBE(3),
293 nSRAM_WE => SRAM_nWE,
294 nSRAM_WE => SRAM_nWE,
294 nSRAM_CE => SRAM_CE,
295 nSRAM_CE => SRAM_CE,
295 nSRAM_OE => SRAM_nOE,
296 nSRAM_OE => SRAM_nOE,
296
297
297 apbi_ext => apbi_ext,
298 apbi_ext => apbi_ext,
298 apbo_ext => apbo_ext,
299 apbo_ext => apbo_ext,
299 ahbi_s_ext => ahbi_s_ext,
300 ahbi_s_ext => ahbi_s_ext,
300 ahbo_s_ext => ahbo_s_ext,
301 ahbo_s_ext => ahbo_s_ext,
301 ahbi_m_ext => ahbi_m_ext,
302 ahbi_m_ext => ahbi_m_ext,
302 ahbo_m_ext => ahbo_m_ext);
303 ahbo_m_ext => ahbo_m_ext);
303
304
304 -------------------------------------------------------------------------------
305 -------------------------------------------------------------------------------
305 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
306 -------------------------------------------------------------------------------
307 -------------------------------------------------------------------------------
307 apb_lfr_time_management_1 : apb_lfr_time_management
308 apb_lfr_time_management_1 : apb_lfr_time_management
308 GENERIC MAP (
309 GENERIC MAP (
309 pindex => 6,
310 pindex => 6,
310 paddr => 6,
311 paddr => 6,
311 pmask => 16#fff#,
312 pmask => 16#fff#,
312 pirq => 12,
313 pirq => 12,
313 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 nb_wait_pediod => 375) -- (49.152/2) /2^16 = 375
314 PORT MAP (
315 PORT MAP (
315 clk25MHz => clk_25,
316 clk25MHz => clk_25,
316 clk49_152MHz => clk_24, -- 49.152MHz/2
317 clk49_152MHz => clk_24, -- 49.152MHz/2
317 resetn => reset,
318 resetn => reset,
318 grspw_tick => swno.tickout,
319 grspw_tick => swno.tickout,
319 apbi => apbi_ext,
320 apbi => apbi_ext,
320 apbo => apbo_ext(6),
321 apbo => apbo_ext(6),
321 coarse_time => coarse_time,
322 coarse_time => coarse_time,
322 fine_time => fine_time);
323 fine_time => fine_time);
323
324
324 -----------------------------------------------------------------------
325 -----------------------------------------------------------------------
325 --- SpaceWire --------------------------------------------------------
326 --- SpaceWire --------------------------------------------------------
326 -----------------------------------------------------------------------
327 -----------------------------------------------------------------------
327
328
328 SPW_EN <= '1';
329 SPW_EN <= '1';
329
330
330 spw_clk <= clk_50_s;
331 spw_clk <= clk_50_s;
331 spw_rxtxclk <= spw_clk;
332 spw_rxtxclk <= spw_clk;
332 spw_rxclkn <= NOT spw_rxtxclk;
333 spw_rxclkn <= NOT spw_rxtxclk;
333
334
334 -- PADS for SPW1
335 -- PADS for SPW1
335 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
336 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 PORT MAP (SPW_NOM_DIN, dtmp(0));
337 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_SIN, stmp(0));
339 PORT MAP (SPW_NOM_SIN, stmp(0));
339 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 PORT MAP (SPW_NOM_DOUT, swno.d(0));
341 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 PORT MAP (SPW_NOM_SOUT, swno.s(0));
343 -- PADS FOR SPW2
344 -- PADS FOR SPW2
344 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
345 PORT MAP (SPW_RED_SIN, dtmp(1));
346 PORT MAP (SPW_RED_SIN, dtmp(1));
346 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_DIN, stmp(1));
348 PORT MAP (SPW_RED_DIN, stmp(1));
348 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 PORT MAP (SPW_RED_DOUT, swno.d(1));
350 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_SOUT, swno.s(1));
352 PORT MAP (SPW_RED_SOUT, swno.s(1));
352
353
353 -- GRSPW PHY
354 -- GRSPW PHY
354 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 --spw1_input: if CFG_SPW_GRSPW = 1 generate
355 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_inputloop : FOR j IN 0 TO 1 GENERATE
356 spw_phy0 : grspw_phy
357 spw_phy0 : grspw_phy
357 GENERIC MAP(
358 GENERIC MAP(
358 tech => apa3e,
359 tech => apa3e,
359 rxclkbuftype => 1,
360 rxclkbuftype => 1,
360 scantest => 0)
361 scantest => 0)
361 PORT MAP(
362 PORT MAP(
362 rxrst => swno.rxrst,
363 rxrst => swno.rxrst,
363 di => dtmp(j),
364 di => dtmp(j),
364 si => stmp(j),
365 si => stmp(j),
365 rxclko => spw_rxclk(j),
366 rxclko => spw_rxclk(j),
366 do => swni.d(j),
367 do => swni.d(j),
367 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 ndo => swni.nd(j*5+4 DOWNTO j*5),
368 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
369 END GENERATE spw_inputloop;
370 END GENERATE spw_inputloop;
370
371
371 -- SPW core
372 -- SPW core
372 sw0 : grspwm GENERIC MAP(
373 sw0 : grspwm GENERIC MAP(
373 tech => apa3e,
374 tech => apa3e,
374 hindex => 1,
375 hindex => 1,
375 pindex => 5,
376 pindex => 5,
376 paddr => 5,
377 paddr => 5,
377 pirq => 11,
378 pirq => 11,
378 sysfreq => 25000, -- CPU_FREQ
379 sysfreq => 25000, -- CPU_FREQ
379 rmap => 1,
380 rmap => 1,
380 rmapcrc => 1,
381 rmapcrc => 1,
381 fifosize1 => 16,
382 fifosize1 => 16,
382 fifosize2 => 16,
383 fifosize2 => 16,
383 rxclkbuftype => 1,
384 rxclkbuftype => 1,
384 rxunaligned => 0,
385 rxunaligned => 0,
385 rmapbufs => 4,
386 rmapbufs => 4,
386 ft => 0,
387 ft => 0,
387 netlist => 0,
388 netlist => 0,
388 ports => 2,
389 ports => 2,
389 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
390 memtech => apa3e,
391 memtech => apa3e,
391 destkey => 2,
392 destkey => 2,
392 spwcore => 1
393 spwcore => 1
393 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
394 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
395 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
396 )
397 )
397 PORT MAP(reset, clk_25, spw_rxclk(0),
398 PORT MAP(reset, clk_25, spw_rxclk(0),
398 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
399 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
400 swni, swno);
401 swni, swno);
401
402
402 swni.tickin <= '0';
403 swni.tickin <= '0';
403 swni.rmapen <= '1';
404 swni.rmapen <= '1';
404 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
405 swni.tickinraw <= '0';
406 swni.tickinraw <= '0';
406 swni.timein <= (OTHERS => '0');
407 swni.timein <= (OTHERS => '0');
407 swni.dcrstval <= (OTHERS => '0');
408 swni.dcrstval <= (OTHERS => '0');
408 swni.timerrstval <= (OTHERS => '0');
409 swni.timerrstval <= (OTHERS => '0');
409
410
410 -------------------------------------------------------------------------------
411 -------------------------------------------------------------------------------
411 -- LFR ------------------------------------------------------------------------
412 -- LFR ------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 -------------------------------------------------------------------------------
413 lpp_lfr_1 : lpp_lfr
414 lpp_lfr_1 : lpp_lfr
414 GENERIC MAP (
415 GENERIC MAP (
415 Mem_use => use_RAM,
416 Mem_use => use_RAM,
416 nb_data_by_buffer_size => 32,
417 nb_data_by_buffer_size => 32,
417 nb_word_by_buffer_size => 30,
418 nb_word_by_buffer_size => 30,
418 nb_snapshot_param_size => 32,
419 nb_snapshot_param_size => 32,
419 delta_vector_size => 32,
420 delta_vector_size => 32,
420 delta_vector_size_f0_2 => 7, -- log2(96)
421 delta_vector_size_f0_2 => 7, -- log2(96)
421 pindex => 15,
422 pindex => 15,
422 paddr => 15,
423 paddr => 15,
423 pmask => 16#fff#,
424 pmask => 16#fff#,
424 pirq_ms => 6,
425 pirq_ms => 6,
425 pirq_wfp => 14,
426 pirq_wfp => 14,
426 hindex => 2,
427 hindex => 2,
427 top_lfr_version => X"000102") -- aa.bb.cc version
428 top_lfr_version => X"000103") -- aa.bb.cc version
428 PORT MAP (
429 PORT MAP (
429 clk => clk_25,
430 clk => clk_25,
430 rstn => reset,
431 rstn => reset,
431 sample_B => sample(2 DOWNTO 0),
432 sample_B => sample(2 DOWNTO 0),
432 sample_E => sample(7 DOWNTO 3),
433 sample_E => sample(7 DOWNTO 3),
433 sample_val => sample_val,
434 sample_val => sample_val,
434 apbi => apbi_ext,
435 apbi => apbi_ext,
435 apbo => apbo_ext(15),
436 apbo => apbo_ext(15),
436 ahbi => ahbi_m_ext,
437 ahbi => ahbi_m_ext,
437 ahbo => ahbo_m_ext(2),
438 ahbo => ahbo_m_ext(2),
438 coarse_time => coarse_time,
439 coarse_time => coarse_time,
439 fine_time => fine_time,
440 fine_time => fine_time,
440 data_shaping_BW => bias_fail_sw_sig);
441 data_shaping_BW => bias_fail_sw_sig,
442 observation_reg => observation_reg);
441
443
442 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
444 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
443 GENERIC MAP(
445 GENERIC MAP(
444 ChannelCount => 8,
446 ChannelCount => 8,
445 SampleNbBits => 14,
447 SampleNbBits => 14,
446 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
448 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
447 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
449 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
448 PORT MAP (
450 PORT MAP (
449 -- CONV
451 -- CONV
450 cnv_clk => clk_24,
452 cnv_clk => clk_24,
451 cnv_rstn => reset,
453 cnv_rstn => reset,
452 cnv => ADC_nCS_sig,
454 cnv => ADC_nCS_sig,
453 -- DATA
455 -- DATA
454 clk => clk_25,
456 clk => clk_25,
455 rstn => reset,
457 rstn => reset,
456 sck => ADC_CLK_sig,
458 sck => ADC_CLK_sig,
457 sdo => ADC_SDO_sig,
459 sdo => ADC_SDO_sig,
458 -- SAMPLE
460 -- SAMPLE
459 sample => sample,
461 sample => sample,
460 sample_val => sample_val);
462 sample_val => sample_val);
461
463
462 IO10 <= ADC_SDO_sig(5);
464 --IO10 <= ADC_SDO_sig(5);
463 IO9 <= ADC_SDO_sig(4);
465 --IO9 <= ADC_SDO_sig(4);
464 IO8 <= ADC_SDO_sig(3);
466 --IO8 <= ADC_SDO_sig(3);
465
467
466 ADC_nCS <= ADC_nCS_sig;
468 ADC_nCS <= ADC_nCS_sig;
467 ADC_CLK <= ADC_CLK_sig;
469 ADC_CLK <= ADC_CLK_sig;
468 ADC_SDO_sig <= ADC_SDO;
470 ADC_SDO_sig <= ADC_SDO;
469
471
470 ----------------------------------------------------------------------
472 ----------------------------------------------------------------------
471 --- GPIO -----------------------------------------------------------
473 --- GPIO -----------------------------------------------------------
472 ----------------------------------------------------------------------
474 ----------------------------------------------------------------------
473
475
474 grgpio0 : grgpio
476 grgpio0 : grgpio
475 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
477 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
476 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
478 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
477
479
478 pio_pad_0 : iopad
480 --pio_pad_0 : iopad
479 GENERIC MAP (tech => CFG_PADTECH)
481 -- GENERIC MAP (tech => CFG_PADTECH)
480 PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
482 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
481 pio_pad_1 : iopad
483 --pio_pad_1 : iopad
482 GENERIC MAP (tech => CFG_PADTECH)
484 -- GENERIC MAP (tech => CFG_PADTECH)
483 PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
485 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
484 pio_pad_2 : iopad
486 --pio_pad_2 : iopad
485 GENERIC MAP (tech => CFG_PADTECH)
487 -- GENERIC MAP (tech => CFG_PADTECH)
486 PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
488 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
487 pio_pad_3 : iopad
489 --pio_pad_3 : iopad
488 GENERIC MAP (tech => CFG_PADTECH)
490 -- GENERIC MAP (tech => CFG_PADTECH)
489 PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
491 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
490 pio_pad_4 : iopad
492 --pio_pad_4 : iopad
491 GENERIC MAP (tech => CFG_PADTECH)
493 -- GENERIC MAP (tech => CFG_PADTECH)
492 PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
494 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
493 pio_pad_5 : iopad
495 --pio_pad_5 : iopad
494 GENERIC MAP (tech => CFG_PADTECH)
496 -- GENERIC MAP (tech => CFG_PADTECH)
495 PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
497 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
496 pio_pad_6 : iopad
498 --pio_pad_6 : iopad
497 GENERIC MAP (tech => CFG_PADTECH)
499 -- GENERIC MAP (tech => CFG_PADTECH)
498 PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
500 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
499 pio_pad_7 : iopad
501 --pio_pad_7 : iopad
500 GENERIC MAP (tech => CFG_PADTECH)
502 -- GENERIC MAP (tech => CFG_PADTECH)
501 PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
503 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
502
504
503 END beh;
505 PROCESS (clk_25, reset)
506 BEGIN -- PROCESS
507 IF reset = '0' THEN -- asynchronous reset (active low)
508 IO0 <= '0';
509 IO1 <= '0';
510 IO2 <= '0';
511 IO3 <= '0';
512 IO4 <= '0';
513 IO5 <= '0';
514 IO6 <= '0';
515 IO7 <= '0';
516 IO8 <= '0';
517 IO9 <= '0';
518 IO10 <= '0';
519 IO11 <= '0';
520 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
521 CASE gpioo.dout(1 DOWNTO 0) IS
522 WHEN "00" =>
523 IO0 <= observation_reg(0 );
524 IO1 <= observation_reg(1 );
525 IO2 <= observation_reg(2 );
526 IO3 <= observation_reg(3 );
527 IO4 <= observation_reg(4 );
528 IO5 <= observation_reg(5 );
529 IO6 <= observation_reg(6 );
530 IO7 <= observation_reg(7 );
531 IO8 <= observation_reg(8 );
532 IO9 <= observation_reg(9 );
533 IO10 <= observation_reg(10);
534 IO11 <= observation_reg(11);
535 WHEN "01" =>
536 IO0 <= observation_reg(0 + 12);
537 IO1 <= observation_reg(1 + 12);
538 IO2 <= observation_reg(2 + 12);
539 IO3 <= observation_reg(3 + 12);
540 IO4 <= observation_reg(4 + 12);
541 IO5 <= observation_reg(5 + 12);
542 IO6 <= observation_reg(6 + 12);
543 IO7 <= observation_reg(7 + 12);
544 IO8 <= observation_reg(8 + 12);
545 IO9 <= observation_reg(9 + 12);
546 IO10 <= observation_reg(10 + 12);
547 IO11 <= observation_reg(11 + 12);
548 WHEN "10" =>
549 IO0 <= observation_reg(0 + 12 + 12);
550 IO1 <= observation_reg(1 + 12 + 12);
551 IO2 <= observation_reg(2 + 12 + 12);
552 IO3 <= observation_reg(3 + 12 + 12);
553 IO4 <= observation_reg(4 + 12 + 12);
554 IO5 <= observation_reg(5 + 12 + 12);
555 IO6 <= observation_reg(6 + 12 + 12);
556 IO7 <= observation_reg(7 + 12 + 12);
557 IO8 <= '0';
558 IO9 <= '0';
559 IO10 <= '0';
560 IO11 <= '0';
561 WHEN "11" =>
562 IO0 <= '0';
563 IO1 <= '0';
564 IO2 <= '0';
565 IO3 <= '0';
566 IO4 <= '0';
567 IO5 <= '0';
568 IO6 <= '0';
569 IO7 <= '0';
570 IO8 <= '0';
571 IO9 <= '0';
572 IO10 <= '0';
573 IO11 <= '0';
574 WHEN OTHERS => NULL;
575 END CASE;
576
577 END IF;
578 END PROCESS;
579
580 END beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,121 +1,121
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM
37 );
37 );
38 PORT(
38 PORT(
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- R/W Ctrl
41 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
42 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
44 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
45 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
48 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
51 );
52 END RAM_CTRLR_v2;
52 END RAM_CTRLR_v2;
53
53
54
54
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
56
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
59 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63
63
64 BEGIN
64 BEGIN
65
65
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 -- RAM
69 -- RAM
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71
71
72 memCEL : IF Mem_use = use_CEL GENERATE
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
74 REN <= NOT ram_read;
75 -- RAMblk : RAM_CEL_N
75 -- RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
76 RAMblk : RAM_CEL_N
77 GENERIC MAP(Input_SZ_1)
77 GENERIC MAP(Input_SZ_1)
78 PORT MAP(
78 PORT MAP(
79 WD => WD,
79 WD => WD,
80 RD => RD,
80 RD => RD,
81 WEN => WEN,
81 WEN => WEN,
82 REN => REN,
82 REN => REN,
83 WADDR => WADDR,
83 WADDR => WADDR,
84 RADDR => RADDR,
84 RADDR => RADDR,
85 RWCLK => clk,
85 RWCLK => clk,
86 RESET => rstn
86 RESET => rstn
87 ) ;
87 ) ;
88 END GENERATE;
88 END GENERATE;
89
89
90 memRAM : IF Mem_use = use_RAM GENERATE
90 memRAM : IF Mem_use = use_RAM GENERATE
91 SRAM : syncram_2p
91 SRAM : syncram_2p
92 GENERIC MAP(tech, 8, Input_SZ_1)
92 GENERIC MAP(tech, 8, Input_SZ_1)
93 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
93 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
94 END GENERATE;
94 END GENERATE;
95
95
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 -- RADDR
97 -- RADDR
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 PROCESS (clk, rstn)
99 PROCESS (clk, rstn)
100 BEGIN -- PROCESS
100 BEGIN -- PROCESS
101 IF rstn = '0' THEN -- asynchronous reset (active low)
101 IF rstn = '0' THEN -- asynchronous reset (active low)
102 counter <= (OTHERS => '0');
102 counter <= (OTHERS => '0');
103 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
103 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
104 IF raddr_rst = '1' THEN
104 IF raddr_rst = '1' THEN
105 counter <= (OTHERS => '0');
105 counter <= (OTHERS => '0');
106 ELSIF raddr_add1 = '1' THEN
106 ELSIF raddr_add1 = '1' THEN
107 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
107 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
108 END IF;
108 END IF;
109 END IF;
109 END IF;
110 END PROCESS;
110 END PROCESS;
111 RADDR <= counter;
111 RADDR <= counter;
112
112
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 -- WADDR
114 -- WADDR
115 -----------------------------------------------------------------------------
115 -----------------------------------------------------------------------------
116 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
116 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
118 STD_LOGIC_VECTOR(UNSIGNED(counter));
119
119
120
120
121 END ar_RAM_CTRLR_v2; No newline at end of file
121 END ar_RAM_CTRLR_v2;
Show file before | Show file after | Hide comments
@@ -1,769 +1,769
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
65
66 --debug
66 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
68 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
70 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
72 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
74 --debug_f3_data_valid : OUT STD_LOGIC;
75
75
76 ---- debug FIFO_IN
76 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
85
86 ----debug FIFO OUT
86 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
95
96 ----debug DMA IN
96 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
105 );
106 END lpp_lfr;
106 END lpp_lfr;
107
107
108 ARCHITECTURE beh OF lpp_lfr IS
108 ARCHITECTURE beh OF lpp_lfr IS
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
109 SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
111 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
116 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
120 --
121 SIGNAL sample_f0_val : STD_LOGIC;
121 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
125 --
125 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
130 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
134
135 -- SM
135 -- SM
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
136 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
156 -- WFP
156 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
166
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
170 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
181
182 SIGNAL run : STD_LOGIC;
182 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
184
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
190 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
196 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
202 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
208
209 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
210 --
210 --
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
215 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
219 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
223 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
227
228 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
229 -- DMA RR
229 -- DMA RR
230 -----------------------------------------------------------------------------
230 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
231 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
236
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
239
240 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
241 -- DMA_REG
241 -- DMA_REG
242 -----------------------------------------------------------------------------
242 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
243 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
245 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
249
250
250
251 -----------------------------------------------------------------------------
251 -----------------------------------------------------------------------------
252 -- DMA
252 -- DMA
253 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
254 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
256 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
261
262 -----------------------------------------------------------------------------
262 -----------------------------------------------------------------------------
263 -- DEBUG
263 -- DEBUG
264 -----------------------------------------------------------------------------
264 -----------------------------------------------------------------------------
265 --
265 --
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
266 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
267 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
268 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
269 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
270
270
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
273 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
274 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
275 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
276 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
277 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
278 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
279
279
280 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
281 -- MS
281 -- MS
282 -----------------------------------------------------------------------------
282 -----------------------------------------------------------------------------
283
283
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
284 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
285 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
286 SIGNAL data_ms_valid : STD_LOGIC;
286 SIGNAL data_ms_valid : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
287 SIGNAL data_ms_valid_burst : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
288 SIGNAL data_ms_ren : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
289 SIGNAL data_ms_done : STD_LOGIC;
290
290
291 BEGIN
291 BEGIN
292
292
293 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
293 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
294 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
294 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
295
295
296 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
296 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
297 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
297 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
298 END GENERATE all_channel;
298 END GENERATE all_channel;
299
299
300 -----------------------------------------------------------------------------
300 -----------------------------------------------------------------------------
301 lpp_lfr_filter_1 : lpp_lfr_filter
301 lpp_lfr_filter_1 : lpp_lfr_filter
302 GENERIC MAP (
302 GENERIC MAP (
303 Mem_use => Mem_use)
303 Mem_use => Mem_use)
304 PORT MAP (
304 PORT MAP (
305 sample => sample_s,
305 sample => sample_s,
306 sample_val => sample_val,
306 sample_val => sample_val,
307 clk => clk,
307 clk => clk,
308 rstn => rstn,
308 rstn => rstn,
309 data_shaping_SP0 => data_shaping_SP0,
309 data_shaping_SP0 => data_shaping_SP0,
310 data_shaping_SP1 => data_shaping_SP1,
310 data_shaping_SP1 => data_shaping_SP1,
311 data_shaping_R0 => data_shaping_R0,
311 data_shaping_R0 => data_shaping_R0,
312 data_shaping_R1 => data_shaping_R1,
312 data_shaping_R1 => data_shaping_R1,
313 sample_f0_val => sample_f0_val,
313 sample_f0_val => sample_f0_val,
314 sample_f1_val => sample_f1_val,
314 sample_f1_val => sample_f1_val,
315 sample_f2_val => sample_f2_val,
315 sample_f2_val => sample_f2_val,
316 sample_f3_val => sample_f3_val,
316 sample_f3_val => sample_f3_val,
317 sample_f0_wdata => sample_f0_data,
317 sample_f0_wdata => sample_f0_data,
318 sample_f1_wdata => sample_f1_data,
318 sample_f1_wdata => sample_f1_data,
319 sample_f2_wdata => sample_f2_data,
319 sample_f2_wdata => sample_f2_data,
320 sample_f3_wdata => sample_f3_data);
320 sample_f3_wdata => sample_f3_data);
321
321
322 -----------------------------------------------------------------------------
322 -----------------------------------------------------------------------------
323 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
323 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
324 GENERIC MAP (
324 GENERIC MAP (
325 nb_data_by_buffer_size => nb_data_by_buffer_size,
325 nb_data_by_buffer_size => nb_data_by_buffer_size,
326 nb_word_by_buffer_size => nb_word_by_buffer_size,
326 nb_word_by_buffer_size => nb_word_by_buffer_size,
327 nb_snapshot_param_size => nb_snapshot_param_size,
327 nb_snapshot_param_size => nb_snapshot_param_size,
328 delta_vector_size => delta_vector_size,
328 delta_vector_size => delta_vector_size,
329 delta_vector_size_f0_2 => delta_vector_size_f0_2,
329 delta_vector_size_f0_2 => delta_vector_size_f0_2,
330 pindex => pindex,
330 pindex => pindex,
331 paddr => paddr,
331 paddr => paddr,
332 pmask => pmask,
332 pmask => pmask,
333 pirq_ms => pirq_ms,
333 pirq_ms => pirq_ms,
334 pirq_wfp => pirq_wfp,
334 pirq_wfp => pirq_wfp,
335 top_lfr_version => top_lfr_version)
335 top_lfr_version => top_lfr_version)
336 PORT MAP (
336 PORT MAP (
337 HCLK => clk,
337 HCLK => clk,
338 HRESETn => rstn,
338 HRESETn => rstn,
339 apbi => apbi,
339 apbi => apbi,
340 apbo => apbo,
340 apbo => apbo,
341 ready_matrix_f0_0 => ready_matrix_f0_0,
341 ready_matrix_f0_0 => ready_matrix_f0_0,
342 ready_matrix_f0_1 => ready_matrix_f0_1,
342 ready_matrix_f0_1 => ready_matrix_f0_1,
343 ready_matrix_f1 => ready_matrix_f1,
343 ready_matrix_f1 => ready_matrix_f1,
344 ready_matrix_f2 => ready_matrix_f2,
344 ready_matrix_f2 => ready_matrix_f2,
345 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
345 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
346 error_bad_component_error => error_bad_component_error,
346 error_bad_component_error => error_bad_component_error,
347 debug_reg => debug_reg,
347 debug_reg => debug_reg,
348 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
348 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
349 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
349 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
350 status_ready_matrix_f1 => status_ready_matrix_f1,
350 status_ready_matrix_f1 => status_ready_matrix_f1,
351 status_ready_matrix_f2 => status_ready_matrix_f2,
351 status_ready_matrix_f2 => status_ready_matrix_f2,
352 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
352 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
353 status_error_bad_component_error => status_error_bad_component_error,
353 status_error_bad_component_error => status_error_bad_component_error,
354 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
354 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
355 config_active_interruption_onError => config_active_interruption_onError,
355 config_active_interruption_onError => config_active_interruption_onError,
356 addr_matrix_f0_0 => addr_matrix_f0_0,
356 addr_matrix_f0_0 => addr_matrix_f0_0,
357 addr_matrix_f0_1 => addr_matrix_f0_1,
357 addr_matrix_f0_1 => addr_matrix_f0_1,
358 addr_matrix_f1 => addr_matrix_f1,
358 addr_matrix_f1 => addr_matrix_f1,
359 addr_matrix_f2 => addr_matrix_f2,
359 addr_matrix_f2 => addr_matrix_f2,
360 status_full => status_full,
360 status_full => status_full,
361 status_full_ack => status_full_ack,
361 status_full_ack => status_full_ack,
362 status_full_err => status_full_err,
362 status_full_err => status_full_err,
363 status_new_err => status_new_err,
363 status_new_err => status_new_err,
364 data_shaping_BW => data_shaping_BW,
364 data_shaping_BW => data_shaping_BW,
365 data_shaping_SP0 => data_shaping_SP0,
365 data_shaping_SP0 => data_shaping_SP0,
366 data_shaping_SP1 => data_shaping_SP1,
366 data_shaping_SP1 => data_shaping_SP1,
367 data_shaping_R0 => data_shaping_R0,
367 data_shaping_R0 => data_shaping_R0,
368 data_shaping_R1 => data_shaping_R1,
368 data_shaping_R1 => data_shaping_R1,
369 delta_snapshot => delta_snapshot,
369 delta_snapshot => delta_snapshot,
370 delta_f0 => delta_f0,
370 delta_f0 => delta_f0,
371 delta_f0_2 => delta_f0_2,
371 delta_f0_2 => delta_f0_2,
372 delta_f1 => delta_f1,
372 delta_f1 => delta_f1,
373 delta_f2 => delta_f2,
373 delta_f2 => delta_f2,
374 nb_data_by_buffer => nb_data_by_buffer,
374 nb_data_by_buffer => nb_data_by_buffer,
375 nb_word_by_buffer => nb_word_by_buffer,
375 nb_word_by_buffer => nb_word_by_buffer,
376 nb_snapshot_param => nb_snapshot_param,
376 nb_snapshot_param => nb_snapshot_param,
377 enable_f0 => enable_f0,
377 enable_f0 => enable_f0,
378 enable_f1 => enable_f1,
378 enable_f1 => enable_f1,
379 enable_f2 => enable_f2,
379 enable_f2 => enable_f2,
380 enable_f3 => enable_f3,
380 enable_f3 => enable_f3,
381 burst_f0 => burst_f0,
381 burst_f0 => burst_f0,
382 burst_f1 => burst_f1,
382 burst_f1 => burst_f1,
383 burst_f2 => burst_f2,
383 burst_f2 => burst_f2,
384 run => run,
384 run => run,
385 addr_data_f0 => addr_data_f0,
385 addr_data_f0 => addr_data_f0,
386 addr_data_f1 => addr_data_f1,
386 addr_data_f1 => addr_data_f1,
387 addr_data_f2 => addr_data_f2,
387 addr_data_f2 => addr_data_f2,
388 addr_data_f3 => addr_data_f3,
388 addr_data_f3 => addr_data_f3,
389 start_date => start_date,
389 start_date => start_date,
390 ---------------------------------------------------------------------------
390 ---------------------------------------------------------------------------
391 debug_reg0 => debug_reg0,
391 debug_reg0 => debug_reg0,
392 debug_reg1 => debug_reg1,
392 debug_reg1 => debug_reg1,
393 debug_reg2 => debug_reg2,
393 debug_reg2 => debug_reg2,
394 debug_reg3 => debug_reg3,
394 debug_reg3 => debug_reg3,
395 debug_reg4 => debug_reg4,
395 debug_reg4 => debug_reg4,
396 debug_reg5 => debug_reg5,
396 debug_reg5 => debug_reg5,
397 debug_reg6 => debug_reg6,
397 debug_reg6 => debug_reg6,
398 debug_reg7 => debug_reg7);
398 debug_reg7 => debug_reg7);
399
399
400 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
400 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
401 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
401 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
402 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
402 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
403 -----------------------------------------------------------------------------
403 -----------------------------------------------------------------------------
404 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
404 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
405 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
405 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
406 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
406 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
407 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
407 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
408
408
409
409
410 -----------------------------------------------------------------------------
410 -----------------------------------------------------------------------------
411 lpp_waveform_1 : lpp_waveform
411 lpp_waveform_1 : lpp_waveform
412 GENERIC MAP (
412 GENERIC MAP (
413 tech => inferred,
413 tech => inferred,
414 data_size => 6*16,
414 data_size => 6*16,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
415 nb_data_by_buffer_size => nb_data_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
416 nb_word_by_buffer_size => nb_word_by_buffer_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
417 nb_snapshot_param_size => nb_snapshot_param_size,
418 delta_vector_size => delta_vector_size,
418 delta_vector_size => delta_vector_size,
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
419 delta_vector_size_f0_2 => delta_vector_size_f0_2
420 )
420 )
421 PORT MAP (
421 PORT MAP (
422 clk => clk,
422 clk => clk,
423 rstn => rstn,
423 rstn => rstn,
424
424
425 reg_run => run,
425 reg_run => run,
426 reg_start_date => start_date,
426 reg_start_date => start_date,
427 reg_delta_snapshot => delta_snapshot,
427 reg_delta_snapshot => delta_snapshot,
428 reg_delta_f0 => delta_f0,
428 reg_delta_f0 => delta_f0,
429 reg_delta_f0_2 => delta_f0_2,
429 reg_delta_f0_2 => delta_f0_2,
430 reg_delta_f1 => delta_f1,
430 reg_delta_f1 => delta_f1,
431 reg_delta_f2 => delta_f2,
431 reg_delta_f2 => delta_f2,
432
432
433 enable_f0 => enable_f0,
433 enable_f0 => enable_f0,
434 enable_f1 => enable_f1,
434 enable_f1 => enable_f1,
435 enable_f2 => enable_f2,
435 enable_f2 => enable_f2,
436 enable_f3 => enable_f3,
436 enable_f3 => enable_f3,
437 burst_f0 => burst_f0,
437 burst_f0 => burst_f0,
438 burst_f1 => burst_f1,
438 burst_f1 => burst_f1,
439 burst_f2 => burst_f2,
439 burst_f2 => burst_f2,
440
440
441 nb_data_by_buffer => nb_data_by_buffer,
441 nb_data_by_buffer => nb_data_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
442 nb_word_by_buffer => nb_word_by_buffer,
443 nb_snapshot_param => nb_snapshot_param,
443 nb_snapshot_param => nb_snapshot_param,
444 status_full => status_full,
444 status_full => status_full,
445 status_full_ack => status_full_ack,
445 status_full_ack => status_full_ack,
446 status_full_err => status_full_err,
446 status_full_err => status_full_err,
447 status_new_err => status_new_err,
447 status_new_err => status_new_err,
448
448
449 coarse_time => coarse_time,
449 coarse_time => coarse_time,
450 fine_time => fine_time,
450 fine_time => fine_time,
451
451
452 --f0
452 --f0
453 addr_data_f0 => addr_data_f0,
453 addr_data_f0 => addr_data_f0,
454 data_f0_in_valid => sample_f0_val,
454 data_f0_in_valid => sample_f0_val,
455 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
455 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
456 --f1
456 --f1
457 addr_data_f1 => addr_data_f1,
457 addr_data_f1 => addr_data_f1,
458 data_f1_in_valid => sample_f1_val,
458 data_f1_in_valid => sample_f1_val,
459 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
459 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
460 --f2
460 --f2
461 addr_data_f2 => addr_data_f2,
461 addr_data_f2 => addr_data_f2,
462 data_f2_in_valid => sample_f2_val,
462 data_f2_in_valid => sample_f2_val,
463 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
463 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
464 --f3
464 --f3
465 addr_data_f3 => addr_data_f3,
465 addr_data_f3 => addr_data_f3,
466 data_f3_in_valid => sample_f3_val,
466 data_f3_in_valid => sample_f3_val,
467 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
467 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
468 -- OUTPUT -- DMA interface
468 -- OUTPUT -- DMA interface
469 --f0
469 --f0
470 data_f0_addr_out => data_f0_addr_out_s,
470 data_f0_addr_out => data_f0_addr_out_s,
471 data_f0_data_out => data_f0_data_out,
471 data_f0_data_out => data_f0_data_out,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
472 data_f0_data_out_valid => data_f0_data_out_valid_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
473 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
474 data_f0_data_out_ren => data_f0_data_out_ren,
474 data_f0_data_out_ren => data_f0_data_out_ren,
475 --f1
475 --f1
476 data_f1_addr_out => data_f1_addr_out_s,
476 data_f1_addr_out => data_f1_addr_out_s,
477 data_f1_data_out => data_f1_data_out,
477 data_f1_data_out => data_f1_data_out,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
478 data_f1_data_out_valid => data_f1_data_out_valid_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
479 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
480 data_f1_data_out_ren => data_f1_data_out_ren,
480 data_f1_data_out_ren => data_f1_data_out_ren,
481 --f2
481 --f2
482 data_f2_addr_out => data_f2_addr_out_s,
482 data_f2_addr_out => data_f2_addr_out_s,
483 data_f2_data_out => data_f2_data_out,
483 data_f2_data_out => data_f2_data_out,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
484 data_f2_data_out_valid => data_f2_data_out_valid_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
485 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
486 data_f2_data_out_ren => data_f2_data_out_ren,
486 data_f2_data_out_ren => data_f2_data_out_ren,
487 --f3
487 --f3
488 data_f3_addr_out => data_f3_addr_out_s,
488 data_f3_addr_out => data_f3_addr_out_s,
489 data_f3_data_out => data_f3_data_out,
489 data_f3_data_out => data_f3_data_out,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
490 data_f3_data_out_valid => data_f3_data_out_valid_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
491 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
492 data_f3_data_out_ren => data_f3_data_out_ren ,
493
493
494 -------------------------------------------------------------------------
494 -------------------------------------------------------------------------
495 observation_reg => observation_reg
495 observation_reg => OPEN --observation_reg
496 ---- debug SNAPSHOT_OUT
496 ---- debug SNAPSHOT_OUT
497 --debug_f0_data => debug_f0_data,
497 --debug_f0_data => debug_f0_data,
498 --debug_f0_data_valid => debug_f0_data_valid ,
498 --debug_f0_data_valid => debug_f0_data_valid ,
499 --debug_f1_data => debug_f1_data ,
499 --debug_f1_data => debug_f1_data ,
500 --debug_f1_data_valid => debug_f1_data_valid,
500 --debug_f1_data_valid => debug_f1_data_valid,
501 --debug_f2_data => debug_f2_data ,
501 --debug_f2_data => debug_f2_data ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
502 --debug_f2_data_valid => debug_f2_data_valid ,
503 --debug_f3_data => debug_f3_data ,
503 --debug_f3_data => debug_f3_data ,
504 --debug_f3_data_valid => debug_f3_data_valid,
504 --debug_f3_data_valid => debug_f3_data_valid,
505
505
506 ---- debug FIFO_IN
506 ---- debug FIFO_IN
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
507 --debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
508 --debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
509 --debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
510 --debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
511 --debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
512 --debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
513 --debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
514 --debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
515
515
516 );
516 );
517
517
518
518
519 -----------------------------------------------------------------------------
519 -----------------------------------------------------------------------------
520 -- DEBUG -- WFP OUT
520 -- DEBUG -- WFP OUT
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
521 --debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
522 --debug_f0_data_fifo_out <= data_f0_data_out;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
523 --debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
524 --debug_f1_data_fifo_out <= data_f1_data_out;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
525 --debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
526 --debug_f2_data_fifo_out <= data_f2_data_out;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
527 --debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
528 --debug_f3_data_fifo_out <= data_f3_data_out;
529 -----------------------------------------------------------------------------
529 -----------------------------------------------------------------------------
530
530
531
531
532 -----------------------------------------------------------------------------
532 -----------------------------------------------------------------------------
533 -- TEMP
533 -- TEMP
534 -----------------------------------------------------------------------------
534 -----------------------------------------------------------------------------
535
535
536 PROCESS (clk, rstn)
536 PROCESS (clk, rstn)
537 BEGIN -- PROCESS
537 BEGIN -- PROCESS
538 IF rstn = '0' THEN -- asynchronous reset (active low)
538 IF rstn = '0' THEN -- asynchronous reset (active low)
539 data_f0_data_out_valid <= '0';
539 data_f0_data_out_valid <= '0';
540 data_f0_data_out_valid_burst <= '0';
540 data_f0_data_out_valid_burst <= '0';
541 data_f1_data_out_valid <= '0';
541 data_f1_data_out_valid <= '0';
542 data_f1_data_out_valid_burst <= '0';
542 data_f1_data_out_valid_burst <= '0';
543 data_f2_data_out_valid <= '0';
543 data_f2_data_out_valid <= '0';
544 data_f2_data_out_valid_burst <= '0';
544 data_f2_data_out_valid_burst <= '0';
545 data_f3_data_out_valid <= '0';
545 data_f3_data_out_valid <= '0';
546 data_f3_data_out_valid_burst <= '0';
546 data_f3_data_out_valid_burst <= '0';
547 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
547 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
548 data_f0_data_out_valid <= data_f0_data_out_valid_s;
548 data_f0_data_out_valid <= data_f0_data_out_valid_s;
549 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
549 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
550 data_f1_data_out_valid <= data_f1_data_out_valid_s;
550 data_f1_data_out_valid <= data_f1_data_out_valid_s;
551 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
551 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
552 data_f2_data_out_valid <= data_f2_data_out_valid_s;
552 data_f2_data_out_valid <= data_f2_data_out_valid_s;
553 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
553 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
554 data_f3_data_out_valid <= data_f3_data_out_valid_s;
554 data_f3_data_out_valid <= data_f3_data_out_valid_s;
555 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
555 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
556 END IF;
556 END IF;
557 END PROCESS;
557 END PROCESS;
558
558
559 data_f0_addr_out <= data_f0_addr_out_s;
559 data_f0_addr_out <= data_f0_addr_out_s;
560 data_f1_addr_out <= data_f1_addr_out_s;
560 data_f1_addr_out <= data_f1_addr_out_s;
561 data_f2_addr_out <= data_f2_addr_out_s;
561 data_f2_addr_out <= data_f2_addr_out_s;
562 data_f3_addr_out <= data_f3_addr_out_s;
562 data_f3_addr_out <= data_f3_addr_out_s;
563
563
564 -----------------------------------------------------------------------------
564 -----------------------------------------------------------------------------
565 -- RoundRobin Selection For DMA
565 -- RoundRobin Selection For DMA
566 -----------------------------------------------------------------------------
566 -----------------------------------------------------------------------------
567
567
568 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
568 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
569 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
569 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
570 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
570 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
571 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
571 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
572
572
573 RR_Arbiter_4_1 : RR_Arbiter_4
573 RR_Arbiter_4_1 : RR_Arbiter_4
574 PORT MAP (
574 PORT MAP (
575 clk => clk,
575 clk => clk,
576 rstn => rstn,
576 rstn => rstn,
577 in_valid => dma_rr_valid,
577 in_valid => dma_rr_valid,
578 out_grant => dma_rr_grant_s);
578 out_grant => dma_rr_grant_s);
579
579
580 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
580 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
581 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
581 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
582 dma_rr_valid_ms(2) <= '0';
582 dma_rr_valid_ms(2) <= '0';
583 dma_rr_valid_ms(3) <= '0';
583 dma_rr_valid_ms(3) <= '0';
584
584
585 RR_Arbiter_4_2 : RR_Arbiter_4
585 RR_Arbiter_4_2 : RR_Arbiter_4
586 PORT MAP (
586 PORT MAP (
587 clk => clk,
587 clk => clk,
588 rstn => rstn,
588 rstn => rstn,
589 in_valid => dma_rr_valid_ms,
589 in_valid => dma_rr_valid_ms,
590 out_grant => dma_rr_grant_ms);
590 out_grant => dma_rr_grant_ms);
591
591
592 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
592 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
593
593
594
594
595 -----------------------------------------------------------------------------
595 -----------------------------------------------------------------------------
596 -- in : dma_rr_grant
596 -- in : dma_rr_grant
597 -- send
597 -- send
598 -- out : dma_sel
598 -- out : dma_sel
599 -- dma_valid_burst
599 -- dma_valid_burst
600 -- dma_sel_valid
600 -- dma_sel_valid
601 -----------------------------------------------------------------------------
601 -----------------------------------------------------------------------------
602 PROCESS (clk, rstn)
602 PROCESS (clk, rstn)
603 BEGIN -- PROCESS
603 BEGIN -- PROCESS
604 IF rstn = '0' THEN -- asynchronous reset (active low)
604 IF rstn = '0' THEN -- asynchronous reset (active low)
605 dma_sel <= (OTHERS => '0');
605 dma_sel <= (OTHERS => '0');
606 dma_send <= '0';
606 dma_send <= '0';
607 dma_valid_burst <= '0';
607 dma_valid_burst <= '0';
608 data_ms_done <= '0';
608 data_ms_done <= '0';
609 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
609 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
610 IF run = '1' THEN
610 IF run = '1' THEN
611 data_ms_done <= '0';
611 data_ms_done <= '0';
612 IF dma_sel = "00000" OR dma_done = '1' THEN
612 IF dma_sel = "00000" OR dma_done = '1' THEN
613 dma_sel <= dma_rr_grant;
613 dma_sel <= dma_rr_grant;
614 IF dma_rr_grant(0) = '1' THEN
614 IF dma_rr_grant(0) = '1' THEN
615 dma_send <= '1';
615 dma_send <= '1';
616 dma_valid_burst <= data_f0_data_out_valid_burst;
616 dma_valid_burst <= data_f0_data_out_valid_burst;
617 dma_sel_valid <= data_f0_data_out_valid;
617 dma_sel_valid <= data_f0_data_out_valid;
618 ELSIF dma_rr_grant(1) = '1' THEN
618 ELSIF dma_rr_grant(1) = '1' THEN
619 dma_send <= '1';
619 dma_send <= '1';
620 dma_valid_burst <= data_f1_data_out_valid_burst;
620 dma_valid_burst <= data_f1_data_out_valid_burst;
621 dma_sel_valid <= data_f1_data_out_valid;
621 dma_sel_valid <= data_f1_data_out_valid;
622 ELSIF dma_rr_grant(2) = '1' THEN
622 ELSIF dma_rr_grant(2) = '1' THEN
623 dma_send <= '1';
623 dma_send <= '1';
624 dma_valid_burst <= data_f2_data_out_valid_burst;
624 dma_valid_burst <= data_f2_data_out_valid_burst;
625 dma_sel_valid <= data_f2_data_out_valid;
625 dma_sel_valid <= data_f2_data_out_valid;
626 ELSIF dma_rr_grant(3) = '1' THEN
626 ELSIF dma_rr_grant(3) = '1' THEN
627 dma_send <= '1';
627 dma_send <= '1';
628 dma_valid_burst <= data_f3_data_out_valid_burst;
628 dma_valid_burst <= data_f3_data_out_valid_burst;
629 dma_sel_valid <= data_f3_data_out_valid;
629 dma_sel_valid <= data_f3_data_out_valid;
630 ELSIF dma_rr_grant(4) = '1' THEN
630 ELSIF dma_rr_grant(4) = '1' THEN
631 dma_send <= '1';
631 dma_send <= '1';
632 dma_valid_burst <= data_ms_valid_burst;
632 dma_valid_burst <= data_ms_valid_burst;
633 dma_sel_valid <= data_ms_valid;
633 dma_sel_valid <= data_ms_valid;
634 END IF;
634 END IF;
635
635
636 IF dma_sel(4) = '1' THEN
636 IF dma_sel(4) = '1' THEN
637 data_ms_done <= '1';
637 data_ms_done <= '1';
638 END IF;
638 END IF;
639 ELSE
639 ELSE
640 dma_sel <= dma_sel;
640 dma_sel <= dma_sel;
641 dma_send <= '0';
641 dma_send <= '0';
642 END IF;
642 END IF;
643 ELSE
643 ELSE
644 data_ms_done <= '0';
644 data_ms_done <= '0';
645 dma_sel <= (OTHERS => '0');
645 dma_sel <= (OTHERS => '0');
646 dma_send <= '0';
646 dma_send <= '0';
647 dma_valid_burst <= '0';
647 dma_valid_burst <= '0';
648 END IF;
648 END IF;
649 END IF;
649 END IF;
650 END PROCESS;
650 END PROCESS;
651
651
652
652
653 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
653 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
654 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
654 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
655 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
655 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
656 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
656 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
657 data_ms_addr;
657 data_ms_addr;
658
658
659 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
659 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
660 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
660 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
661 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
661 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
662 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
662 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
663 data_ms_data;
663 data_ms_data;
664
664
665 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
665 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
666 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
666 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
667 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
667 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
668 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
668 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
669 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
669 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
670
670
671 dma_data_2 <= dma_data;
671 dma_data_2 <= dma_data;
672
672
673
673
674
674
675
675
676
676
677 -----------------------------------------------------------------------------
677 -----------------------------------------------------------------------------
678 -- DEBUG -- DMA IN
678 -- DEBUG -- DMA IN
679 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
679 --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
680 --debug_f0_data_dma_in <= dma_data;
680 --debug_f0_data_dma_in <= dma_data;
681 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
681 --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
682 --debug_f1_data_dma_in <= dma_data;
682 --debug_f1_data_dma_in <= dma_data;
683 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
683 --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
684 --debug_f2_data_dma_in <= dma_data;
684 --debug_f2_data_dma_in <= dma_data;
685 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
685 --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
686 --debug_f3_data_dma_in <= dma_data;
686 --debug_f3_data_dma_in <= dma_data;
687 -----------------------------------------------------------------------------
687 -----------------------------------------------------------------------------
688
688
689 -----------------------------------------------------------------------------
689 -----------------------------------------------------------------------------
690 -- DMA
690 -- DMA
691 -----------------------------------------------------------------------------
691 -----------------------------------------------------------------------------
692 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
692 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
693 GENERIC MAP (
693 GENERIC MAP (
694 tech => inferred,
694 tech => inferred,
695 hindex => hindex)
695 hindex => hindex)
696 PORT MAP (
696 PORT MAP (
697 HCLK => clk,
697 HCLK => clk,
698 HRESETn => rstn,
698 HRESETn => rstn,
699 run => run,
699 run => run,
700 AHB_Master_In => ahbi,
700 AHB_Master_In => ahbi,
701 AHB_Master_Out => ahbo,
701 AHB_Master_Out => ahbo,
702
702
703 send => dma_send,
703 send => dma_send,
704 valid_burst => dma_valid_burst,
704 valid_burst => dma_valid_burst,
705 done => dma_done,
705 done => dma_done,
706 ren => dma_ren,
706 ren => dma_ren,
707 address => dma_address,
707 address => dma_address,
708 data => dma_data_2);
708 data => dma_data_2);
709
709
710 -----------------------------------------------------------------------------
710 -----------------------------------------------------------------------------
711 -- Matrix Spectral
711 -- Matrix Spectral
712 -----------------------------------------------------------------------------
712 -----------------------------------------------------------------------------
713 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
713 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
714 NOT(sample_f0_val) & NOT(sample_f0_val) ;
714 NOT(sample_f0_val) & NOT(sample_f0_val) ;
715 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
715 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
716 NOT(sample_f1_val) & NOT(sample_f1_val) ;
716 NOT(sample_f1_val) & NOT(sample_f1_val) ;
717 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
717 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
718 NOT(sample_f3_val) & NOT(sample_f3_val) ;
718 NOT(sample_f3_val) & NOT(sample_f3_val) ;
719
719
720 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
720 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
721 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
721 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
722 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
722 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
723
723
724 -------------------------------------------------------------------------------
724 -------------------------------------------------------------------------------
725 lpp_lfr_ms_1: lpp_lfr_ms
725 lpp_lfr_ms_1: lpp_lfr_ms
726 GENERIC MAP (
726 GENERIC MAP (
727 Mem_use => Mem_use )
727 Mem_use => Mem_use )
728 PORT MAP (
728 PORT MAP (
729 clk => clk,
729 clk => clk,
730 rstn => rstn,
730 rstn => rstn,
731
731
732 coarse_time => coarse_time,
732 coarse_time => coarse_time,
733 fine_time => fine_time,
733 fine_time => fine_time,
734
734
735 sample_f0_wen => sample_f0_wen,
735 sample_f0_wen => sample_f0_wen,
736 sample_f0_wdata => sample_f0_wdata,
736 sample_f0_wdata => sample_f0_wdata,
737 sample_f1_wen => sample_f1_wen,
737 sample_f1_wen => sample_f1_wen,
738 sample_f1_wdata => sample_f1_wdata,
738 sample_f1_wdata => sample_f1_wdata,
739 sample_f3_wen => sample_f3_wen,
739 sample_f3_wen => sample_f3_wen,
740 sample_f3_wdata => sample_f3_wdata,
740 sample_f3_wdata => sample_f3_wdata,
741
741
742 dma_addr => data_ms_addr, --
742 dma_addr => data_ms_addr, --
743 dma_data => data_ms_data, --
743 dma_data => data_ms_data, --
744 dma_valid => data_ms_valid, --
744 dma_valid => data_ms_valid, --
745 dma_valid_burst => data_ms_valid_burst, --
745 dma_valid_burst => data_ms_valid_burst, --
746 dma_ren => data_ms_ren, --
746 dma_ren => data_ms_ren, --
747 dma_done => data_ms_done, --
747 dma_done => data_ms_done, --
748
748
749 ready_matrix_f0_0 => ready_matrix_f0_0,
749 ready_matrix_f0_0 => ready_matrix_f0_0,
750 ready_matrix_f0_1 => ready_matrix_f0_1,
750 ready_matrix_f0_1 => ready_matrix_f0_1,
751 ready_matrix_f1 => ready_matrix_f1,
751 ready_matrix_f1 => ready_matrix_f1,
752 ready_matrix_f2 => ready_matrix_f2,
752 ready_matrix_f2 => ready_matrix_f2,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
753 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
754 error_bad_component_error => error_bad_component_error,
754 error_bad_component_error => error_bad_component_error,
755 debug_reg => debug_reg,
755 debug_reg => observation_reg,--debug_reg,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
756 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
757 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
758 status_ready_matrix_f1 => status_ready_matrix_f1,
759 status_ready_matrix_f2 => status_ready_matrix_f2,
759 status_ready_matrix_f2 => status_ready_matrix_f2,
760 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
760 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
761 status_error_bad_component_error => status_error_bad_component_error,
761 status_error_bad_component_error => status_error_bad_component_error,
762 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
762 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
763 config_active_interruption_onError => config_active_interruption_onError,
763 config_active_interruption_onError => config_active_interruption_onError,
764 addr_matrix_f0_0 => addr_matrix_f0_0,
764 addr_matrix_f0_0 => addr_matrix_f0_0,
765 addr_matrix_f0_1 => addr_matrix_f0_1,
765 addr_matrix_f0_1 => addr_matrix_f0_1,
766 addr_matrix_f1 => addr_matrix_f1,
766 addr_matrix_f1 => addr_matrix_f1,
767 addr_matrix_f2 => addr_matrix_f2);
767 addr_matrix_f2 => addr_matrix_f2);
768
768
769 END beh;
769 END beh;
General Comments 0
You need to be logged in to leave comments. Login now