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LFR-EQM 2.1.82
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r599:6aaa08019409 simu_with_Leon3
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.sim.ALL;
32 32 USE gaisler.memctrl.ALL;
33 33 USE gaisler.leon3.ALL;
34 34 USE gaisler.uart.ALL;
35 35 USE gaisler.misc.ALL;
36 36 USE gaisler.spacewire.ALL;
37 37 LIBRARY esa;
38 38 USE esa.memoryctrl.ALL;
39 39 LIBRARY lpp;
40 40 USE lpp.lpp_memory.ALL;
41 41 USE lpp.lpp_ad_conv.ALL;
42 42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 44 USE lpp.iir_filter.ALL;
45 45 USE lpp.general_purpose.ALL;
46 46 USE lpp.lpp_lfr_management.ALL;
47 47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 USE lpp.lpp_bootloader_pkg.ALL;
49 49
50 50 --library proasic3l;
51 51 --use proasic3l.all;
52 52
53 53 ENTITY LFR_EQM IS
54 54 GENERIC (
55 55 Mem_use : INTEGER := use_RAM;
56 56 USE_BOOTLOADER : INTEGER := 0;
57 57 USE_ADCDRIVER : INTEGER := 1;
58 58 tech : INTEGER := apa3e;
59 59 tech_leon : INTEGER := apa3e;
60 60 DEBUG_FORCE_DATA_DMA : INTEGER := 0;
61 61 USE_DEBUG_VECTOR : INTEGER := 0
62 62 );
63 63
64 64 PORT (
65 65 clk50MHz : IN STD_ULOGIC;
66 66 clk49_152MHz : IN STD_ULOGIC;
67 67 reset : IN STD_ULOGIC;
68 68
69 69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70 70
71 71 -- TAG --------------------------------------------------------------------
72 72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
73 73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
74 74 -- UART APB ---------------------------------------------------------------
75 75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
76 76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
77 77 -- RAM --------------------------------------------------------------------
78 78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
79 79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80
81 81 nSRAM_MBE : INOUT STD_LOGIC; -- new
82 82 nSRAM_E1 : OUT STD_LOGIC; -- new
83 83 nSRAM_E2 : OUT STD_LOGIC; -- new
84 84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
85 85 nSRAM_W : OUT STD_LOGIC; -- new
86 86 nSRAM_G : OUT STD_LOGIC; -- new
87 87 nSRAM_BUSY : IN STD_LOGIC; -- new
88 88 -- SPW --------------------------------------------------------------------
89 89 spw1_en : OUT STD_LOGIC; -- new
90 90 spw1_din : IN STD_LOGIC;
91 91 spw1_sin : IN STD_LOGIC;
92 92 spw1_dout : OUT STD_LOGIC;
93 93 spw1_sout : OUT STD_LOGIC;
94 94 spw2_en : OUT STD_LOGIC; -- new
95 95 spw2_din : IN STD_LOGIC;
96 96 spw2_sin : IN STD_LOGIC;
97 97 spw2_dout : OUT STD_LOGIC;
98 98 spw2_sout : OUT STD_LOGIC;
99 99 -- ADC --------------------------------------------------------------------
100 100 bias_fail_sw : OUT STD_LOGIC;
101 101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102 ADC_smpclk : OUT STD_LOGIC;
103 103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 104 -- DAC --------------------------------------------------------------------
105 105 DAC_SDO : OUT STD_LOGIC;
106 106 DAC_SCK : OUT STD_LOGIC;
107 107 DAC_SYNC : OUT STD_LOGIC;
108 108 DAC_CAL_EN : OUT STD_LOGIC;
109 109 -- HK ---------------------------------------------------------------------
110 110 HK_smpclk : OUT STD_LOGIC;
111 111 ADC_OEB_bar_HK : OUT STD_LOGIC;
112 112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
113 113 ---------------------------------------------------------------------------
114 114 -- TAG8 : OUT STD_LOGIC
115 115 );
116 116
117 117 END LFR_EQM;
118 118
119 119
120 120 ARCHITECTURE beh OF LFR_EQM IS
121 121
122 122 SIGNAL clk_25 : STD_LOGIC := '0';
123 123 SIGNAL clk_24 : STD_LOGIC := '0';
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
127 127
128 128 -- CONSTANTS
129 129 CONSTANT CFG_PADTECH : INTEGER := inferred;
130 130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
131 131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
132 132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
133 133
134 134 SIGNAL apbi_ext : apb_slv_in_type;
135 135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
136 136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
137 137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
138 138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
139 139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
140 140
141 141 -- Spacewire signals
142 142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
145 145 SIGNAL spw_rxtxclk : STD_ULOGIC;
146 146 SIGNAL spw_rxclkn : STD_ULOGIC;
147 147 SIGNAL spw_clk : STD_LOGIC;
148 148 SIGNAL swni : grspw_in_type;
149 149 SIGNAL swno : grspw_out_type;
150 150
151 151 --GPIO
152 152 SIGNAL gpioi : gpio_in_type;
153 153 SIGNAL gpioo : gpio_out_type;
154 154
155 155 -- AD Converter ADS7886
156 156 SIGNAL sample : Samples14v(8 DOWNTO 0);
157 157 SIGNAL sample_s : Samples(8 DOWNTO 0);
158 158 SIGNAL sample_val : STD_LOGIC;
159 159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
160 160
161 161 -----------------------------------------------------------------------------
162 162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 163
164 164 -----------------------------------------------------------------------------
165 165 SIGNAL rstn_25 : STD_LOGIC;
166 166 SIGNAL rstn_24 : STD_LOGIC;
167 167
168 168 SIGNAL LFR_soft_rstn : STD_LOGIC;
169 169 SIGNAL LFR_rstn : STD_LOGIC;
170 170
171 171 SIGNAL ADC_smpclk_s : STD_LOGIC;
172 172
173 173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 174
175 175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
176 176 SIGNAL clk_25_int : STD_LOGIC := '0';
177 177
178 178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
179 179
180 180 SIGNAL rstn_50 : STD_LOGIC;
181 181 SIGNAL clk_lock : STD_LOGIC;
182 182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184 184
185 185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL ahbrxd: STD_LOGIC;
187 187 SIGNAL ahbtxd: STD_LOGIC;
188 188 SIGNAL urxd1 : STD_LOGIC;
189 189 SIGNAL utxd1 : STD_LOGIC;
190 190 BEGIN -- beh
191 191
192 192 -----------------------------------------------------------------------------
193 193 -- CLK_LOCK
194 194 -----------------------------------------------------------------------------
195 195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
196 196
197 197 PROCESS (clk50MHz_int, rstn_50)
198 198 BEGIN -- PROCESS
199 199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
200 200 clk_lock <= '0';
201 201 clk_busy_counter <= (OTHERS => '0');
202 202 nSRAM_BUSY_reg <= '0';
203 203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
204 204 nSRAM_BUSY_reg <= nSRAM_BUSY;
205 205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
206 206 IF clk_busy_counter = "1111" THEN
207 207 clk_lock <= '1';
208 208 ELSE
209 209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
210 210 END IF;
211 211 END IF;
212 212 END IF;
213 213 END PROCESS;
214 214
215 215 -----------------------------------------------------------------------------
216 216 -- CLK
217 217 -----------------------------------------------------------------------------
218 218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
219 219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
220 220
221 221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
222 222 clk50MHz_int <= clk50MHz;
223 223
224 224 PROCESS(clk50MHz_int)
225 225 BEGIN
226 226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
227 227 --clk_25_int <= NOT clk_25_int;
228 228 clk_25 <= NOT clk_25;
229 229 END IF;
230 230 END PROCESS;
231 231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
232 232
233 233 PROCESS(clk49_152MHz)
234 234 BEGIN
235 235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
236 236 clk_24 <= NOT clk_24;
237 237 END IF;
238 238 END PROCESS;
239 239 -- clk_49 <= clk49_152MHz;
240 240
241 241 -----------------------------------------------------------------------------
242 242 --
243 243 leon3_soc_1 : leon3_soc
244 244 GENERIC MAP (
245 245 fabtech => tech_leon,
246 246 memtech => tech_leon,
247 247 padtech => inferred,
248 248 clktech => inferred,
249 249 disas => 0,
250 250 dbguart => 0,
251 251 pclow => 2,
252 252 clk_freq => 25000,
253 253 IS_RADHARD => 0,
254 254 NB_CPU => 1,
255 255 ENABLE_FPU => 1,
256 256 FPU_NETLIST => 0,
257 257 ENABLE_DSU => 1,
258 258 ENABLE_AHB_UART => 1,
259 259 ENABLE_APB_UART => 1,
260 260 ENABLE_IRQMP => 1,
261 261 ENABLE_GPT => 1,
262 262 NB_AHB_MASTER => NB_AHB_MASTER,
263 263 NB_AHB_SLAVE => NB_AHB_SLAVE,
264 264 NB_APB_SLAVE => NB_APB_SLAVE,
265 265 ADDRESS_SIZE => 19,
266 266 USES_IAP_MEMCTRLR => 1,
267 267 BYPASS_EDAC_MEMCTRLR => '0',
268 268 SRBANKSZ => 8)
269 269 PORT MAP (
270 270 clk => clk_25,
271 271 reset => rstn_25,
272 272 errorn => OPEN,
273 273
274 274 ahbrxd => ahbrxd, -- INPUT
275 275 ahbtxd => ahbtxd, -- OUTPUT
276 276 urxd1 => urxd1, -- INPUT
277 277 utxd1 => utxd1, -- OUTPUT
278 278
279 279 address => address,
280 280 data => data,
281 281 nSRAM_BE0 => OPEN,
282 282 nSRAM_BE1 => OPEN,
283 283 nSRAM_BE2 => OPEN,
284 284 nSRAM_BE3 => OPEN,
285 285 nSRAM_WE => nSRAM_W,
286 286 nSRAM_CE => nSRAM_CE,
287 287 nSRAM_OE => nSRAM_G,
288 288 nSRAM_READY => nSRAM_BUSY,
289 289 SRAM_MBE => nSRAM_MBE,
290 290
291 291 apbi_ext => apbi_ext,
292 292 apbo_ext => apbo_ext,
293 293 ahbi_s_ext => ahbi_s_ext,
294 294 ahbo_s_ext => ahbo_s_ext,
295 295 ahbi_m_ext => ahbi_m_ext,
296 296 ahbo_m_ext => ahbo_m_ext);
297 297
298 298
299 299 nSRAM_E1 <= nSRAM_CE(0);
300 300 nSRAM_E2 <= nSRAM_CE(1);
301 301
302 302 -------------------------------------------------------------------------------
303 303 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
304 304 -------------------------------------------------------------------------------
305 305 apb_lfr_management_1 : apb_lfr_management
306 306 GENERIC MAP (
307 307 tech => tech,
308 308 pindex => 6,
309 309 paddr => 6,
310 310 pmask => 16#fff#,
311 311 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
312 312 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
313 313 PORT MAP (
314 314 clk25MHz => clk_25,
315 315 resetn_25MHz => rstn_25, -- TODO
316 316 --clk24_576MHz => clk_24, -- 49.152MHz/2
317 317 --resetn_24_576MHz => rstn_24, -- TODO
318 318
319 319 grspw_tick => swno.tickout,
320 320 apbi => apbi_ext,
321 321 apbo => apbo_ext(6),
322 322
323 323 HK_sample => sample_s(8),
324 324 HK_val => sample_val,
325 325 HK_sel => HK_SEL,
326 326
327 327 DAC_SDO => DAC_SDO,
328 328 DAC_SCK => DAC_SCK,
329 329 DAC_SYNC => DAC_SYNC,
330 330 DAC_CAL_EN => DAC_CAL_EN,
331 331
332 332 coarse_time => coarse_time,
333 333 fine_time => fine_time,
334 334 LFR_soft_rstn => LFR_soft_rstn
335 335 );
336 336
337 337 -----------------------------------------------------------------------
338 338 --- SpaceWire --------------------------------------------------------
339 339 -----------------------------------------------------------------------
340 340
341 341 ------------------------------------------------------------------------------
342 342 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
343 343 ------------------------------------------------------------------------------
344 344 spw1_en <= '1';
345 345 spw2_en <= '1';
346 346 ------------------------------------------------------------------------------
347 347 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
348 348 ------------------------------------------------------------------------------
349 349
350 350 --spw_clk <= clk50MHz;
351 351 --spw_rxtxclk <= spw_clk;
352 352 --spw_rxclkn <= NOT spw_rxtxclk;
353 353
354 354 -- PADS for SPW1
355 355 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
356 356 PORT MAP (spw1_din, dtmp(0));
357 357 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
358 358 PORT MAP (spw1_sin, stmp(0));
359 359 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
360 360 PORT MAP (spw1_dout, swno.d(0));
361 361 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
362 362 PORT MAP (spw1_sout, swno.s(0));
363 363 -- PADS FOR SPW2
364 364 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 365 PORT MAP (spw2_din, dtmp(1));
366 366 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
367 367 PORT MAP (spw2_sin, stmp(1));
368 368 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
369 369 PORT MAP (spw2_dout, swno.d(1));
370 370 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
371 371 PORT MAP (spw2_sout, swno.s(1));
372 372
373 373 -- GRSPW PHY
374 374 --spw1_input: if CFG_SPW_GRSPW = 1 generate
375 375 spw_inputloop : FOR j IN 0 TO 1 GENERATE
376 376 spw_phy0 : grspw_phy
377 377 GENERIC MAP(
378 378 tech => tech_leon,
379 379 rxclkbuftype => 1,
380 380 scantest => 0)
381 381 PORT MAP(
382 382 rxrst => swno.rxrst,
383 383 di => dtmp(j),
384 384 si => stmp(j),
385 385 rxclko => spw_rxclk(j),
386 386 do => swni.d(j),
387 387 ndo => swni.nd(j*5+4 DOWNTO j*5),
388 388 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
389 389 END GENERATE spw_inputloop;
390 390
391 391 -- SPW core
392 392 sw0 : grspwm GENERIC MAP(
393 393 tech => tech_leon,
394 394 hindex => 1,
395 395 pindex => 5,
396 396 paddr => 5,
397 397 pirq => 11,
398 398 sysfreq => 25000, -- CPU_FREQ
399 399 rmap => 1,
400 400 rmapcrc => 1,
401 401 fifosize1 => 16,
402 402 fifosize2 => 16,
403 403 rxclkbuftype => 1,
404 404 rxunaligned => 0,
405 405 rmapbufs => 4,
406 406 ft => 0,
407 407 netlist => 0,
408 408 ports => 2,
409 409 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
410 410 memtech => tech_leon,
411 411 destkey => 2,
412 412 spwcore => 1
413 413 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
414 414 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
415 415 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
416 416 )
417 417 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
418 418 spw_rxclk(1),
419 419 clk50MHz_int,
420 420 clk50MHz_int,
421 421 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
422 422 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
423 423 swni, swno);
424 424
425 425 swni.tickin <= '0';
426 426 swni.rmapen <= '1';
427 427 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
428 428 swni.tickinraw <= '0';
429 429 swni.timein <= (OTHERS => '0');
430 430 swni.dcrstval <= (OTHERS => '0');
431 431 swni.timerrstval <= (OTHERS => '0');
432 432
433 433 -------------------------------------------------------------------------------
434 434 -- LFR ------------------------------------------------------------------------
435 435 -------------------------------------------------------------------------------
436 436 LFR_rstn <= LFR_soft_rstn AND rstn_25;
437 437
438 438 lpp_lfr_1 : lpp_lfr
439 439 GENERIC MAP (
440 440 Mem_use => Mem_use,
441 441 tech => tech,
442 442 nb_data_by_buffer_size => 32,
443 443 --nb_word_by_buffer_size => 30,
444 444 nb_snapshot_param_size => 32,
445 445 delta_vector_size => 32,
446 446 delta_vector_size_f0_2 => 7, -- log2(96)
447 447 pindex => 15,
448 448 paddr => 15,
449 449 pmask => 16#fff#,
450 450 pirq_ms => 6,
451 451 pirq_wfp => 14,
452 452 hindex => 2,
453 top_lfr_version => X"020151", -- aa.bb.cc version
453 top_lfr_version => X"020152", -- aa.bb.cc version
454 454 -- AA : BOARD NUMBER
455 455 -- 0 => MINI_LFR
456 456 -- 1 => EM
457 457 -- 2 => EQM (with A3PE3000)
458 458 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
459 459 PORT MAP (
460 460 clk => clk_25,
461 461 rstn => LFR_rstn,
462 462 sample_B => sample_s(2 DOWNTO 0),
463 463 sample_E => sample_s(7 DOWNTO 3),
464 464 sample_val => sample_val,
465 465 apbi => apbi_ext,
466 466 apbo => apbo_ext(15),
467 467 ahbi => ahbi_m_ext,
468 468 ahbo => ahbo_m_ext(2),
469 469 coarse_time => coarse_time,
470 470 fine_time => fine_time,
471 471 data_shaping_BW => bias_fail_sw,
472 472 debug_vector => debug_vector,
473 473 debug_vector_ms => OPEN); --,
474 474 --observation_vector_0 => OPEN,
475 475 --observation_vector_1 => OPEN,
476 476 --observation_reg => observation_reg);
477 477
478 478
479 479 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
480 480 sample_s(I) <= sample(I) & '0' & '0';
481 481 END GENERATE all_sample;
482 482 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
483 483
484 484 -----------------------------------------------------------------------------
485 485 --
486 486 -----------------------------------------------------------------------------
487 487 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
488 488 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
489 489 GENERIC MAP (
490 490 ChanelCount => 9,
491 ncycle_cnv_high => 25,
492 ncycle_cnv => 50,
491 ncycle_cnv_high => 12,
492 ncycle_cnv => 25,
493 493 FILTER_ENABLED => 16#FF#)
494 494 PORT MAP (
495 495 cnv_clk => clk_24,
496 496 cnv_rstn => rstn_24,
497 497 cnv => ADC_smpclk_s,
498 498 clk => clk_25,
499 499 rstn => rstn_25,
500 500 ADC_data => ADC_data,
501 501 ADC_nOE => ADC_OEB_bar_CH_s,
502 502 sample => sample,
503 503 sample_val => sample_val);
504 504
505 505 END GENERATE USE_ADCDRIVER_true;
506 506
507 507 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
508 508 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
509 509 GENERIC MAP (
510 510 ChanelCount => 9,
511 511 ncycle_cnv_high => 25,
512 512 ncycle_cnv => 50,
513 513 FILTER_ENABLED => 16#FF#)
514 514 PORT MAP (
515 515 cnv_clk => clk_24,
516 516 cnv_rstn => rstn_24,
517 517 cnv => ADC_smpclk_s,
518 518 clk => clk_25,
519 519 rstn => rstn_25,
520 520 ADC_data => ADC_data,
521 521 ADC_nOE => OPEN,
522 522 sample => OPEN,
523 523 sample_val => sample_val);
524 524
525 525 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
526 526
527 527 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
528 528 ramp_generator_1: ramp_generator
529 529 GENERIC MAP (
530 530 DATA_SIZE => 14,
531 531 VALUE_UNSIGNED_INIT => 2**I,
532 532 VALUE_UNSIGNED_INCR => 0,
533 533 VALUE_UNSIGNED_MASK => 16#3FFF#)
534 534 PORT MAP (
535 535 clk => clk_25,
536 536 rstn => rstn_25,
537 537 new_data => sample_val,
538 538 output_data => sample(I) );
539 539 END GENERATE all_sample;
540 540
541 541
542 542 END GENERATE USE_ADCDRIVER_false;
543 543
544 544
545 545
546 546
547 547 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
548 548
549 549 ADC_smpclk <= ADC_smpclk_s;
550 550 HK_smpclk <= ADC_smpclk_s;
551 551
552 552
553 553 -----------------------------------------------------------------------------
554 554 -- HK
555 555 -----------------------------------------------------------------------------
556 556 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
557 557
558 558 -----------------------------------------------------------------------------
559 559 --
560 560 -----------------------------------------------------------------------------
561 561 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
562 562 lpp_bootloader_1: lpp_bootloader
563 563 GENERIC MAP (
564 564 pindex => 13,
565 565 paddr => 13,
566 566 pmask => 16#fff#,
567 567 hindex => 3,
568 568 haddr => 0,
569 569 hmask => 16#fff#)
570 570 PORT MAP (
571 571 HCLK => clk_25,
572 572 HRESETn => rstn_25,
573 573 apbi => apbi_ext,
574 574 apbo => apbo_ext(13),
575 575 ahbsi => ahbi_s_ext,
576 576 ahbso => ahbo_s_ext(3));
577 577 END GENERATE inst_bootloader;
578 578
579 579 -----------------------------------------------------------------------------
580 580 --
581 581 -----------------------------------------------------------------------------
582 582 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
583 583 PROCESS (clk_25, rstn_25)
584 584 BEGIN -- PROCESS
585 585 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
586 586 TAG <= (OTHERS => '0');
587 587 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
588 588 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
589 589 END IF;
590 590 END PROCESS;
591 591
592 592
593 593 END GENERATE USE_DEBUG_VECTOR_IF;
594 594
595 595 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
596 596 ahbrxd <= TAG(1);
597 597 TAG(3) <= ahbtxd;
598 598 urxd1 <= TAG(2);
599 599 TAG(4) <= utxd1;
600 600 TAG(8) <= nSRAM_BUSY;
601 601 END GENERATE USE_DEBUG_VECTOR_IF2;
602 602
603 603 END beh;
Show file before | Show file after | Hide comments
@@ -1,685 +1,685
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_sim_pkg.ALL;
32 32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.FILTERcfg.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_waveform_pkg.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_top_lfr_pkg.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL;
42 42 USE lpp.general_purpose.ALL;
43 43 --LIBRARY lpp;
44 44 USE lpp.lpp_ad_conv.ALL;
45 45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47 47
48 48 --USE work.debug.ALL;
49 49
50 50 LIBRARY gaisler;
51 51 USE gaisler.libdcom.ALL;
52 52 USE gaisler.sim.ALL;
53 53 USE gaisler.memctrl.ALL;
54 54 USE gaisler.leon3.ALL;
55 55 USE gaisler.uart.ALL;
56 56 USE gaisler.misc.ALL;
57 57 USE gaisler.spacewire.ALL;
58 58
59 59 ENTITY TB IS
60 60
61 61 END TB;
62 62
63 63 ARCHITECTURE beh OF TB IS
64 64 CONSTANT sramfile : STRING := "prom.srec";
65 65 -- CONSTANT sramfile : STRING;
66 66
67 67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68 68
69 69 COMPONENT LFR_EQM
70 70 GENERIC (
71 71 Mem_use : INTEGER;
72 72 USE_BOOTLOADER : INTEGER;
73 73 USE_ADCDRIVER : INTEGER;
74 74 tech : INTEGER;
75 75 tech_leon : INTEGER;
76 76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 77 USE_DEBUG_VECTOR : INTEGER );
78 78 PORT (
79 79 clk50MHz : IN STD_ULOGIC;
80 80 clk49_152MHz : IN STD_ULOGIC;
81 81 reset : IN STD_ULOGIC;
82 82 --TAG1 : IN STD_ULOGIC;
83 83 --TAG3 : OUT STD_ULOGIC;
84 84 --TAG2 : IN STD_ULOGIC;
85 85 --TAG4 : OUT STD_ULOGIC;
86 86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 nSRAM_MBE : INOUT STD_LOGIC;
90 90 nSRAM_E1 : OUT STD_LOGIC;
91 91 nSRAM_E2 : OUT STD_LOGIC;
92 92 nSRAM_W : OUT STD_LOGIC;
93 93 nSRAM_G : OUT STD_LOGIC;
94 94 nSRAM_BUSY : IN STD_LOGIC;
95 95 spw1_en : OUT STD_LOGIC;
96 96 spw1_din : IN STD_LOGIC;
97 97 spw1_sin : IN STD_LOGIC;
98 98 spw1_dout : OUT STD_LOGIC;
99 99 spw1_sout : OUT STD_LOGIC;
100 100 spw2_en : OUT STD_LOGIC;
101 101 spw2_din : IN STD_LOGIC;
102 102 spw2_sin : IN STD_LOGIC;
103 103 spw2_dout : OUT STD_LOGIC;
104 104 spw2_sout : OUT STD_LOGIC;
105 105 bias_fail_sw : OUT STD_LOGIC;
106 106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 107 ADC_smpclk : OUT STD_LOGIC;
108 108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 109 DAC_SDO : OUT STD_LOGIC;
110 110 DAC_SCK : OUT STD_LOGIC;
111 111 DAC_SYNC : OUT STD_LOGIC;
112 112 DAC_CAL_EN : OUT STD_LOGIC;
113 113 HK_smpclk : OUT STD_LOGIC;
114 114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 120 SIGNAL reset : STD_ULOGIC;
121 121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 122 --SIGNAL TAG3 : STD_ULOGIC;
123 123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 124 --SIGNAL TAG4 : STD_ULOGIC;
125 125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 130 SIGNAL nSRAM_W : STD_LOGIC;
131 131 SIGNAL nSRAM_G : STD_LOGIC;
132 132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 133 SIGNAL spw1_en : STD_LOGIC;
134 134 SIGNAL spw1_din : STD_LOGIC := '1';
135 135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 136 SIGNAL spw1_dout : STD_LOGIC;
137 137 SIGNAL spw1_sout : STD_LOGIC;
138 138 SIGNAL spw2_en : STD_LOGIC;
139 139 SIGNAL spw2_din : STD_LOGIC := '1';
140 140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 141 SIGNAL spw2_dout : STD_LOGIC;
142 142 SIGNAL spw2_sout : STD_LOGIC;
143 143 SIGNAL bias_fail_sw : STD_LOGIC;
144 144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 145 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
147 147 SIGNAL ADC_smpclk : STD_LOGIC;
148 148 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
149 149 SIGNAL ADC_data_s : STD_LOGIC_VECTOR(13 DOWNTO 0);
150 150 SIGNAL DAC_SDO : STD_LOGIC;
151 151 SIGNAL DAC_SCK : STD_LOGIC;
152 152 SIGNAL DAC_SYNC : STD_LOGIC;
153 153 SIGNAL DAC_CAL_EN : STD_LOGIC;
154 154 SIGNAL HK_smpclk : STD_LOGIC;
155 155 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
156 156 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
157 157 -- SIGNAL TAG8 : STD_LOGIC;
158 158
159 159 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
160 160 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
161 161 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
162 162 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
163 163 SIGNAL counter_scrub_period : INTEGER;
164 164
165 165
166 166 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
167 167 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
168 168 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
169 169
170 170 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
171 171 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
172 172 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
173 173 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
174 174 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
175 175 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
176 176
177 177 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
178 178 SIGNAL data_message : STRING(1 TO 15) := "---------------";
179 179 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
180 180 SIGNAL TXD1 : STD_LOGIC;
181 181 SIGNAL RXD1 : STD_LOGIC;
182 182
183 183 -----------------------------------------------------------------------------
184 184 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
185 185 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
186 186 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
187 187 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
188 188 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
189 189 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
190 190 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
191 191 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
192 192 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
193 193 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
194 194 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
195 195 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
196 196 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
197 197 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
198 198
199 199
200 200 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
201 201 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
202 202
203 203 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
204 204 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
205 205
206 206 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 207 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 208 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 209 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
210 210
211 211 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
212 212 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
213 213 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
214 214
215 215
216 216 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
217 217 -----------------------------------------------------------------------------
218 218 CONSTANT srambanks : INTEGER := 2;
219 219 CONSTANT sramwidth : INTEGER := 32;
220 220 CONSTANT sramdepth : INTEGER := 19;
221 221 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
222 222 -----------------------------------------------------------------------------
223 223
224 224 BEGIN -- beh
225 225
226 226 LFR_EQM_1 : LFR_EQM
227 227 GENERIC MAP (
228 228 Mem_use => use_RAM,
229 229 USE_BOOTLOADER => 0,
230 230 USE_ADCDRIVER => 1,
231 231 tech => apa3e,
232 232 tech_leon => apa3e,
233 233 DEBUG_FORCE_DATA_DMA => 0,
234 234 USE_DEBUG_VECTOR => 0)
235 235 PORT MAP (
236 236 clk50MHz => clk50MHz, --IN --ok
237 237 clk49_152MHz => clk49_152MHz, --in --ok
238 238 reset => reset, --IN --ok
239 239
240 240 TAG => TAG,
241 241 --TAG1 => TAG1, --in
242 242 --TAG3 => TAG3, --out
243 243 --TAG2 => TAG2, --IN --ok
244 244 --TAG4 => TAG4, --out --ok
245 245
246 246 address => address, --out
247 247 data => data, --inout
248 248 nSRAM_MBE => nSRAM_MBE, --inout
249 249 nSRAM_E1 => nSRAM_E1, --out
250 250 nSRAM_E2 => nSRAM_E2, --out
251 251 nSRAM_W => nSRAM_W, --out
252 252 nSRAM_G => nSRAM_G, --out
253 253 nSRAM_BUSY => nSRAM_BUSY, --in
254 254
255 255 spw1_en => spw1_en, --out --ok
256 256 spw1_din => spw1_din, --in --ok
257 257 spw1_sin => spw1_sin, --in --ok
258 258 spw1_dout => spw1_dout, --out --ok
259 259 spw1_sout => spw1_sout, --out --ok
260 260
261 261 spw2_en => spw2_en, --out --ok
262 262 spw2_din => spw2_din, --in --ok
263 263 spw2_sin => spw2_sin, --in --ok
264 264 spw2_dout => spw2_dout, --out --ok
265 265 spw2_sout => spw2_sout, --out --ok
266 266
267 267 bias_fail_sw => bias_fail_sw, --OUT --ok
268 268
269 269 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
270 270 ADC_smpclk => ADC_smpclk, --out --ok
271 271 ADC_data => ADC_data, --IN --ok
272 272
273 273 DAC_SDO => DAC_SDO, --out --ok
274 274 DAC_SCK => DAC_SCK, --out --ok
275 275 DAC_SYNC => DAC_SYNC, --out --ok
276 276 DAC_CAL_EN => DAC_CAL_EN, --out --ok
277 277
278 278 HK_smpclk => HK_smpclk, --out --ok
279 279 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
280 280 HK_SEL => HK_SEL); --out --ok
281 281
282 282
283 283 -----------------------------------------------------------------------------
284 284 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
285 285 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
286 286 -----------------------------------------------------------------------------
287 287
288 288 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
289 289 TestModule_RHF1401_1 : TestModule_RHF1401
290 290 GENERIC MAP (
291 291 freq => 2400,--24*(I*5+1),
292 292 amplitude => 4000,--8000/(I*5+1),
293 293 impulsion => 0)
294 294 PORT MAP (
295 295 ADC_smpclk => ADC_smpclk,
296 296 ADC_OEB_bar => ADC_OEB_bar_CH_s(I),
297 297 ADC_data => ADC_data_s);
298 298 --ADC_data_s <= "00" & X"190";
299 299 END GENERATE MODULE_RHF1401;
300 300
301 301 ADC_OEB_bar_CH_s <= TRANSPORT ADC_OEB_bar_CH AFTER 10 ns;
302 ADC_data <= TRANSPORT ADC_data_s AFTER 60 ns;
302 ADC_data <= TRANSPORT ADC_data_s AFTER 20 ns;
303 303 -----------------------------------------------------------------------------
304 304 PROCESS (clk50MHz, reset)
305 305 BEGIN -- PROCESS
306 306 IF reset = '0' THEN -- asynchronous reset (active low)
307 307 nSRAM_BUSY <= '1';
308 308 counter_scrub_period <= 0;
309 309 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
310 310 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
311 311 counter_scrub_period <= 0;
312 312 ELSE
313 313 counter_scrub_period <= counter_scrub_period + 1;
314 314 END IF;
315 315
316 316 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
317 317 nSRAM_BUSY <= '1';
318 318 ELSE
319 319 nSRAM_BUSY <= '0';
320 320 END IF;
321 321 END IF;
322 322 END PROCESS;
323 323
324 324 -----------------------------------------------------------------------------
325 325 -- TB
326 326 -----------------------------------------------------------------------------
327 327 TAG(1) <= TXD1;
328 328 TAG(2) <= '1';
329 329 RXD1 <= TAG(3);
330 330
331 331 PROCESS
332 332 CONSTANT txp : TIME := 320 ns;
333 333 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
334 334 BEGIN -- PROCESS
335 335 TXD1 <= '1';
336 336 reset <= '0';
337 337 WAIT FOR 500 ns;
338 338 reset <= '1';
339 339 WAIT FOR 100 us;
340 340 message_simu <= "0 - UART init ";
341 341 UART_INIT(TXD1, txp);
342 342
343 343 ---------------------------------------------------------------------------
344 344 -- LAUNCH leon 3 software
345 345 ---------------------------------------------------------------------------
346 346 message_simu <= "2- GO Leon3....";
347 347
348 348 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
349 349 --Force a debug break
350 350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
351 351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
352 352 --Clear time tag counter
353 353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
354 354 --Clear ASR registers
355 355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
356 356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
357 357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
358 358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
359 359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
360 360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
361 361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
362 362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
363 363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
364 364 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
365 365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
366 366 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
367 367 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
368 368 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
369 369 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
370 370
371 371 IF USE_ESA_MEMCTRL = 1 THEN
372 372 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
373 373 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
374 374 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
375 375 END IF;
376 376
377 377 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
378 378 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
379 379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
380 380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
381 381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
382 382
383 383 --memSet(DSUBASEADDRESS+0x300000,0,1567);
384 384
385 385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
386 386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
387 387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
388 388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
389 389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
390 390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
391 391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
392 392
393 393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
394 394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
395 395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
396 396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
397 397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
398 398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
399 399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
400 400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
401 401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
402 402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
403 403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
404 404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
405 405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
406 406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
407 407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
408 408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
409 409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
410 410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
411 411 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
412 412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
413 413 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
414 414 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
415 415 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
416 416 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
417 417
418 418 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
419 419
420 420 --//Disable interrupts
421 421 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
422 422 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
423 423 -- return false;
424 424 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
425 425 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
426 426 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
427 427
428 428 -- //Set up timer
429 429 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
430 430 --if(APBTIMERBASEADD == (unsigned int)-1)
431 431 -- return false;
432 432 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
433 433 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
434 434 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
435 435
436 436
437 437 ---------------------------------------------------------------------------
438 438 --bool dsu3plugin::setCacheEnable(bool enabled)
439 439 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
440 440 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
441 441 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
442 442 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
443 443 data_read <= data_read_v;
444 444 --if(enabled){
445 445 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
446 446 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
447 447 --}else{
448 448 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
449 449 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
450 450 --}
451 451
452 452
453 453 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
454 454 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
455 455
456 456 ---------------------------------------------------------------------------
457 457 --message_simu <= "1 - UART test ";
458 458 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
459 459 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
460 460 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
461 461 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
462 462 --data_read <= data_read_v;
463 463 --data_message <= "GPIO_data_write";
464 464
465 465 -- UNSET the LFR reset
466 466 message_simu <= "2 - LFR UNRESET";
467 467 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
468 468 --
469 469 message_simu <= "3 - LFR CONFIG ";
470 470 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
471 471 ADDR_BUFFER_MS_F0_0,
472 472 ADDR_BUFFER_MS_F0_1,
473 473 ADDR_BUFFER_MS_F1_0,
474 474 ADDR_BUFFER_MS_F1_1,
475 475 ADDR_BUFFER_MS_F2_0,
476 476 ADDR_BUFFER_MS_F2_1);
477 477
478 478
479 479 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
480 480 LFR_MODE_SBM1,
481 481 X"7FFFFFFF", -- START DATE
482 482
483 483 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
484 484 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
485 485 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
486 486 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
487 487 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
488 488 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
489 489
490 490 ADDR_BASE_LFR,
491 491 ADDR_BUFFER_WFP_F0_0,
492 492 ADDR_BUFFER_WFP_F0_1,
493 493 ADDR_BUFFER_WFP_F1_0,
494 494 ADDR_BUFFER_WFP_F1_1,
495 495 ADDR_BUFFER_WFP_F2_0,
496 496 ADDR_BUFFER_WFP_F2_1,
497 497 ADDR_BUFFER_WFP_F3_0,
498 498 ADDR_BUFFER_WFP_F3_1);
499 499
500 500 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
501 501 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
502 502
503 503
504 504 ---------------------------------------------------------------------------
505 505 -- CONFIG LFR 2
506 506 ---------------------------------------------------------------------------
507 507 --message_simu <= "3 - LFR2 CONFIG";
508 508 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
509 509 -- X"40000000",
510 510 -- X"40001000",
511 511 -- X"40002000",
512 512 -- X"40003000",
513 513 -- X"40004000",
514 514 -- X"40005000");
515 515
516 516
517 517 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
518 518 -- LFR_MODE_SBM1,
519 519 -- X"7FFFFFFF", -- START DATE
520 520
521 521 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
522 522 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
523 523 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
524 524 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
525 525 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
526 526 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
527 527
528 528 -- ADDR_BASE_LFR_2,
529 529 -- X"40006000",
530 530 -- X"40007000",
531 531 -- X"40008000",
532 532 -- X"40009000",
533 533 -- X"4000A000",
534 534 -- X"4000B000",
535 535 -- X"4000C000",
536 536 -- X"4000D000");
537 537
538 538 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
539 539 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
540 540
541 541 ---------------------------------------------------------------------------
542 542 ---------------------------------------------------------------------------
543 543 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
544 544
545 545
546 546 message_simu <= "4 - GO GO GO !!";
547 547 data_message <= "---------------";
548 548 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
549 549 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
550 550
551 551
552 552 data_read_v := (OTHERS => '1');
553 553 READ_STATUS : LOOP
554 554 data_message <= "---------------";
555 555 WAIT FOR 2 ms;
556 556 data_message <= "READ_STATUS_SM_";
557 557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
558 558 --data_message <= "--------------r";
559 559 --data_read <= data_read_v;
560 560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
561 561
562 562 data_message <= "READ_STATUS_WF_";
563 563 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
564 564 --data_message <= "--------------r";
565 565 --data_read <= data_read_v;
566 566 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
567 567 END LOOP READ_STATUS;
568 568
569 569 WAIT;
570 570 END PROCESS;
571 571
572 572
573 573 -----------------------------------------------------------------------------
574 574 PROCESS (nSRAM_W, reset)
575 575 BEGIN -- PROCESS
576 576 IF reset = '0' THEN -- asynchronous reset (active low)
577 577 data_pre_f0 <= X"00020001";
578 578 data_pre_f1 <= X"00020001";
579 579 data_pre_f2 <= X"00020001";
580 580
581 581 addr_pre_f0 <= (OTHERS => '0');
582 582 addr_pre_f1 <= (OTHERS => '0');
583 583 addr_pre_f2 <= (OTHERS => '0');
584 584
585 585 error_wfp <= "000";
586 586 error_wfp_addr <= "000";
587 587
588 588 sample_counter <= (0,0,0);
589 589
590 590 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
591 591 error_wfp <= "000";
592 592 error_wfp_addr <= "000";
593 593 -------------------------------------------------------------------------
594 594 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
595 595 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
596 596
597 597 addr_pre_f0 <= address(13 DOWNTO 0);
598 598 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
599 599 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
600 600 error_wfp_addr(0) <= '1';
601 601 END IF;
602 602 END IF;
603 603
604 604 data_pre_f0 <= data;
605 605 CASE data_pre_f0 IS
606 606 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
607 607 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
608 608 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
609 609 WHEN OTHERS => error_wfp(0) <= '1';
610 610 END CASE;
611 611
612 612
613 613 END IF;
614 614 -------------------------------------------------------------------------
615 615 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
616 616 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
617 617
618 618 addr_pre_f1 <= address(13 DOWNTO 0);
619 619 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
620 620 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
621 621 error_wfp_addr(1) <= '1';
622 622 END IF;
623 623 END IF;
624 624
625 625 data_pre_f1 <= data;
626 626 CASE data_pre_f1 IS
627 627 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
628 628 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
629 629 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
630 630 WHEN OTHERS => error_wfp(1) <= '1';
631 631 END CASE;
632 632
633 633 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
634 634 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
635 635 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
636 636
637 637 END IF;
638 638 -------------------------------------------------------------------------
639 639 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
640 640 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
641 641
642 642 addr_pre_f2 <= address(13 DOWNTO 0);
643 643 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
644 644 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
645 645 error_wfp_addr(2) <= '1';
646 646 END IF;
647 647 END IF;
648 648
649 649 data_pre_f2 <= data;
650 650 CASE data_pre_f2 IS
651 651 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
652 652 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
653 653 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
654 654 WHEN OTHERS => error_wfp(2) <= '1';
655 655 END CASE;
656 656
657 657 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
658 658 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
659 659 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
660 660
661 661 END IF;
662 662 END IF;
663 663 END PROCESS;
664 664 -----------------------------------------------------------------------------
665 665 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
666 666
667 667 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
668 668 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
669 669 sr0 : sram
670 670 GENERIC MAP (
671 671 index => i,
672 672 abits => sramdepth,
673 673 fname => sramfile)
674 674 PORT MAP (
675 675 address,
676 676 data(31-i*8 DOWNTO 24-i*8),
677 677 ramsn(k),
678 678 nSRAM_W,
679 679 nSRAM_G
680 680 );
681 681 END GENERATE;
682 682 END GENERATE;
683 683
684 684 END beh;
685 685
Show file before | Show file after | Hide comments
@@ -1,226 +1,228
1 1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd
2 2 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
3 3 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
4 4 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
5 5 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd
6 6 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
7 7 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
8 8 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd
9 9 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd
10 10 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
11 11 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd
12 12 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
13 13 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd
14 14 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd
15 15 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd
16 16 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
17 17 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd
18 18 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd
19 19 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd
20 20 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd
21 21 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd
22 22 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd
23 23 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd
24 24 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd
25 25 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd
26 26 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd
27 27 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd
28 28 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd
29 29 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd
30 30 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd
31 31 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd
32 32 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd
33 33 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd
34 34 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd
35 35 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd
36 36 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd
37 37 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd
38 38 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd
39 39 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd
40 40 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd
41 41 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd
42 42 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd
43 43 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd
44 44 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd
45 45 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd
46 46 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd
47 47 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd
48 48 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd
49 49 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd
50 50 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
51 51 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd
52 52 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
53 53 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd
54 54 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
55 55 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
56 56 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
57 57 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd
58 58 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd
59 59 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd
60 60 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd
61 61 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd
62 62 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd
63 63 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd
64 64 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd
65 65 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd
66 66 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd
67 67 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd
68 68 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd
69 69 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd
70 70 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd
71 71 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd
72 72 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd
73 73 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd
74 74 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd
75 75 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd
76 76 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd
77 77 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd
78 78 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
79 79 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
80 80 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd
81 81 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd
82 82 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
83 83 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
84 84 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
85 85 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd
86 86 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
87 87 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
88 88 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd
89 89 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
90 90 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd
91 91 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd
92 92 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd
93 93 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd
94 94 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd
95 95 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd
96 96 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd
97 97 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd
98 98 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd
99 99 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd
100 100 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd
101 101 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd
102 102 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd
103 103 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
104 104 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd
105 105 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd
106 106 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
107 107 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd
108 108 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd
109 109 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd
110 110 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd
111 111 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd
112 112 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd
113 113 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd
114 114 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd
115 115 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd
116 116 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd
117 117 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
118 118 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd
119 119 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd
120 120 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd
121 121 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
122 122 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
123 123 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
124 124 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
125 125 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
126 126 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd
127 127 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd
128 128 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd
129 129 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
130 130 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd
131 131 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
132 132 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
133 133 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
134 134 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
135 135 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
136 136 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
137 137 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
138 138 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
139 139 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
140 140 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd
141 141 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd
142 142 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd
143 143 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd
144 144 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
145 145 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd
146 146 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd
147 147 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd
148 148 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd
149 149 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd
150 150 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd
151 151 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd
152 152 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd
153 153 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd
154 154 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
155 155 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd
156 156 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd
157 157 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd
158 158 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
159 159 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd
160 160 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd
161 161 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
162 162 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
163 163 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd
164 164 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd
165 165 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd
166 166 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
167 167 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
168 168 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd
169 169 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd
170 170 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
171 171 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
172 172 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
173 173 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
174 174 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
175 175 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd
176 176 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd
177 177 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd
178 178 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd
179 179 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd
180 180 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
181 181 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd
182 182 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
183 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
184 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
183 185 vcom -quiet -93 -work work LFR-EQM.vhd
184 186 vcom -quiet -93 -work work TB.vhd
185 187
186 188 vsim work.tb
187 189 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0
188 190 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0
189 191 #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0
190 192
191 193 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
192 194 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
193 195 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
194 196 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
195 197
196 198 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
197 199 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
198 200 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
199 201 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
200 202
201 203 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
202 204 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
203 205 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
204 206 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd
205 207
206 208 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd
207 209
208 210 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
209 211 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
210 212 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
211 213 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
212 214 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
213 215 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
214 216 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9
215 217 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9
216 218 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9
217 219 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9
218 220 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9
219 221 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9
220 222 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9
221 223
222 224 log -r *;
223 225 do wave.do ;
224 226 run -all
225 227
226 228
Show file before | Show file after | Hide comments
@@ -1,197 +1,213
1 1 onerror {resume}
2 2 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc
3 3 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA
4 4 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA
5 5 quietly WaveActivateNextPane {} 0
6 add wave -noupdate -group ALL /tb/data_message
7 add wave -noupdate -group ALL /tb/message_simu
8 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 add wave -noupdate -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
14 add wave -noupdate -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
15 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
16 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
17 add wave -noupdate -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
18 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
19 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
20 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
21 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
22 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
23 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
24 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
25 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
26 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
27 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
28 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
29 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
30 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
31 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
32 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
33 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
34 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
35 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
36 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
37 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
38 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
39 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
40 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
41 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
42 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
43 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
44 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
45 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
46 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
47 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
48 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
49 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
50 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
51 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
52 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
53 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
54 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
55 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
56 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
57 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
58 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
59 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
60 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
61 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
62 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
63 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
64 add wave -noupdate -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
65 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1
66 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2
67 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0
68 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1
69 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2
70 add wave -noupdate -group ALL /tb/error_wfp
71 add wave -noupdate -group ALL /tb/error_wfp_addr
72 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
73 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
74 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
75 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
76 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
77 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
78 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
79 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
80 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
81 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
82 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
83 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
84 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi
85 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
86 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
87 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
88 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
89 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
90 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
91 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
92 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
93 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
94 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
95 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
96 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
97 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
98 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
99 add wave -noupdate -group ALL -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
100 add wave -noupdate -group ALL -height 74 -max 326.0 -min 256.0 /tb/sample_counter
101 add wave -noupdate -group ALL /tb/LFR_EQM_1/debug_vector
102 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
103 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/HWDATA
104 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
105 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/DMA_DATA
106 add wave -noupdate -group ALL -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
107 add wave -noupdate -group ALL -label HREADY /tb/LFR_EQM_1/debug_vector(5)
108 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
109 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
110 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
111 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
112 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
113 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
114 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
115 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
116 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6)
117 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5)
118 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4)
119 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3)
120 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2)
121 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1)
122 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0)
123 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
124 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
125 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
126 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
127 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
128 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
129 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
130 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
131 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
132 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
133 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
134 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
135 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
136 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
137 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
138 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
6 add wave -noupdate -expand -group ALL /tb/data_message
7 add wave -noupdate -expand -group ALL /tb/message_simu
8 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 add wave -noupdate -expand -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
14 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
15 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
16 add wave -noupdate -expand -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
17 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
18 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
19 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
20 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
21 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
22 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn
23 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_falling
24 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s
25 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_s_reg
26 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync
27 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_sync_reg
28 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
29 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
30 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
31 add wave -noupdate -expand -group ALL -expand -group ADC -format Analog-Step -height 74 -max 24.0 /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_cycle_counter
32 add wave -noupdate -expand -group ALL -expand -group ADC /tb/LFR_EQM_1/ADC_OEB_bar_HK
33 add wave -noupdate -expand -group ALL -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_OEB_bar_CH(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/ADC_OEB_bar_CH(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_OEB_bar_CH(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_OEB_bar_CH
34 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
35 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
36 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
37 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
38 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
39 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
40 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
41 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
42 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
43 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
44 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
45 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
46 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
47 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
48 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
49 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
50 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
51 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
52 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
53 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
54 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
55 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
56 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
57 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
58 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
59 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
60 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
61 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
62 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
63 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
64 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
65 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
66 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
67 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
68 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
69 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
70 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
71 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
72 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
73 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
74 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
75 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
76 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
77 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
78 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
79 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1
80 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2
81 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0
82 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1
83 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2
84 add wave -noupdate -expand -group ALL /tb/error_wfp
85 add wave -noupdate -expand -group ALL /tb/error_wfp_addr
86 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
87 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
88 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
89 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
90 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
91 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
92 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
93 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
94 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
95 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
96 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
97 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
98 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi
99 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
100 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
101 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
102 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
103 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
104 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
105 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
106 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
107 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
108 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
109 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
110 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
111 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
112 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
113 add wave -noupdate -expand -group ALL -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
114 add wave -noupdate -expand -group ALL -height 74 -max 326.0 -min 256.0 /tb/sample_counter
115 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/debug_vector
116 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
117 add wave -noupdate -expand -group ALL -radix unsigned /tb/LFR_EQM_1/HWDATA
118 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
119 add wave -noupdate -expand -group ALL -radix unsigned /tb/LFR_EQM_1/DMA_DATA
120 add wave -noupdate -expand -group ALL -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
121 add wave -noupdate -expand -group ALL -label HREADY /tb/LFR_EQM_1/debug_vector(5)
122 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
123 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
124 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
125 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
126 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
127 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
128 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
129 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
130 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6)
131 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5)
132 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4)
133 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3)
134 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2)
135 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1)
136 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0)
137 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
138 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
139 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
140 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
141 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
142 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
143 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
144 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
145 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
146 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
147 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
148 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
149 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
150 add wave -noupdate -expand -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
151 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
152 add wave -noupdate -expand -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
139 153 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 15 -max 7517.0 -min -7504.0 -radix decimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) -radix decimal}}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0)(0) {-height 15 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
140 154 add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val
141 155 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in
142 156 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
143 157 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out
144 158 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg
145 159 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg
146 160 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg
147 161 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg
148 162 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg
149 163 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg
150 164 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg
151 165 add wave -noupdate -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 -radix decimal /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg
152 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 74 -max 14061.999999999998 -min -14378.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim
153 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim
166 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(5) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(4) {-format Analog-Step -height 74 -max 14061.999999999998 -min -14378.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(3) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(2) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(1) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim(0) {-format Analog-Step -height 74 -max 15283.999999999998 -min -14020.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data_sim
167 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(5) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(4) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(3) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(2) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(1) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim(0) {-format Analog-Step -height 74 -max 4548.0 -min -4595.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data_sim
154 168 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data_sim
155 169 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(5) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(4) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(3) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(2) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(1) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim(0) {-format Analog-Step -height 75 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data_sim
156 170 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/sample(8) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(7) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(6) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(5) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(4) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(3) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(2) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(1) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal} /tb/LFR_EQM_1/sample(0) {-format Analog-Step -height 40 -max 8000.0 -min -8000.0 -radix hexadecimal}} /tb/LFR_EQM_1/sample
157 171 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/sample_s(8) -radix decimal} {/tb/LFR_EQM_1/sample_s(7) -radix decimal} {/tb/LFR_EQM_1/sample_s(6) -radix decimal} {/tb/LFR_EQM_1/sample_s(5) -radix decimal} {/tb/LFR_EQM_1/sample_s(4) -radix decimal} {/tb/LFR_EQM_1/sample_s(3) -radix decimal} {/tb/LFR_EQM_1/sample_s(2) -radix decimal} {/tb/LFR_EQM_1/sample_s(1) -radix decimal} {/tb/LFR_EQM_1/sample_s(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/sample_s(8) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/sample_s(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/sample_s
158 172 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_in
159 173 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim
160 174 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_data_shaping_out
161 175 add wave -noupdate -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(7) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0
162 176 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
163 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/ADC_data
177 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
164 178 add wave -noupdate /tb/LFR_EQM_1/sample_val
165 179 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/state_GEN_OEn
166 180 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
167 181 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
168 182 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
169 183 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_out
170 184 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/data_wen
171 185 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/wdata
172 186 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_data
173 187 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_fifo_ren
174 188 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/dma_buffer_full
175 189 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/data
176 190 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
177 191 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/address
178 192 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
179 193 add wave -noupdate -expand /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/fifo_ren
194 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
195 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
180 196 TreeUpdate [SetDefaultTree]
181 WaveRestoreCursors {{Cursor 1} {18490143333 ps} 0} {{Cursor 2} {6701210000 ps} 0} {{Cursor 3} {75952890000 ps} 0}
182 quietly wave cursor active 2
183 configure wave -namecolwidth 493
197 WaveRestoreCursors {{Cursor 1} {33906609 ps} 0} {{Cursor 2} {33050000 ps} 0} {{Cursor 3} {42930000 ps} 0} {{Cursor 4} {8300650000 ps} 0}
198 quietly wave cursor active 3
199 configure wave -namecolwidth 619
184 200 configure wave -valuecolwidth 311
185 201 configure wave -justifyvalue left
186 202 configure wave -signalnamewidth 0
187 203 configure wave -snapdistance 10
188 204 configure wave -datasetprefix 0
189 205 configure wave -rowmargin 4
190 206 configure wave -childrowmargin 2
191 207 configure wave -gridoffset 0
192 208 configure wave -gridperiod 1
193 209 configure wave -griddelta 40
194 210 configure wave -timeline 0
195 211 configure wave -timelineunits ns
196 212 update
197 WaveRestoreZoom {1149644925 ps} {6964513425 ps}
213 WaveRestoreZoom {41901608 ps} {45906411 ps}
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@@ -1,249 +1,274
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 12 ncycle_cnv_high : INTEGER := 25;
13 13 ncycle_cnv : INTEGER := 50;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 37 SIGNAL cnv_sync_reg : STD_LOGIC;
38 38 SIGNAL cnv_sync_falling : STD_LOGIC;
39 39
40 40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 41 SIGNAL enable_ADC : STD_LOGIC;
42 42
43 43
44 44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45 45
46 46 SIGNAL channel_counter : INTEGER;
47 47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48 48
49 49 SIGNAL ADC_data_selected : Samples14;
50 50 SIGNAL ADC_data_result : Samples15;
51 51
52 52 SIGNAL sample_counter : INTEGER;
53 53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54 54
55 55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56 56
57 57 -----------------------------------------------------------------------------
58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 2;
59 CONSTANT DATA_CYCLE_VALID : INTEGER := 3;
58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 1;
59 CONSTANT DATA_CYCLE_VALID : INTEGER := 1;
60 60
61 61 -- GEN OutPut Enable
62 62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1;
65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1 ;
66 66 SIGNAL ADC_data_valid : STD_LOGIC;
67 SIGNAL ADC_data_valid_s : STD_LOGIC;
67 68 SIGNAL ADC_data_reg : Samples14;
68 69 -----------------------------------------------------------------------------
69 CONSTANT SAMPLE_DIVISION : INTEGER := 5;
70 SIGNAL sample_val_s : STD_LOGIC;
70 CONSTANT SAMPLE_DIVISION : INTEGER := 10;
71 SIGNAL sample_val_s : STD_LOGIC;
72 SIGNAL sample_val_s2 : STD_LOGIC;
71 73 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
72 74 BEGIN
73 75
74 76
75 77 -----------------------------------------------------------------------------
76 78 -- CNV GEN
77 79 -----------------------------------------------------------------------------
78 80 PROCESS (cnv_clk, cnv_rstn)
79 81 BEGIN -- PROCESS
80 82 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
81 83 cnv_cycle_counter <= 0;
82 84 cnv_s <= '0';
83 85 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
84 86 IF cnv_cycle_counter < ncycle_cnv-1 THEN
85 87 cnv_cycle_counter <= cnv_cycle_counter + 1;
86 88 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
87 89 cnv_s <= '1';
88 90 ELSE
89 91 cnv_s <= '0';
90 92 END IF;
91 93 ELSE
92 94 cnv_s <= '1';
93 95 cnv_cycle_counter <= 0;
94 96 END IF;
95 97 END IF;
96 98 END PROCESS;
97 99
98 100 cnv <= cnv_s;
99 101
100 102 PROCESS (cnv_clk, cnv_rstn)
101 103 BEGIN -- PROCESS
102 104 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
103 105 cnv_s_reg <= '0';
104 106 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
105 107 cnv_s_reg <= cnv_s;
106 108 END IF;
107 109 END PROCESS;
108 110
109 111
110 112 -----------------------------------------------------------------------------
111 113 -- SYNC CNV
112 114 -----------------------------------------------------------------------------
113 115
114 116 SYNC_FF_cnv : SYNC_FF
115 117 GENERIC MAP (
116 118 NB_FF_OF_SYNC => 2)
117 119 PORT MAP (
118 120 clk => clk,
119 121 rstn => rstn,
120 122 A => cnv_s_reg,
121 123 A_sync => cnv_sync);
122 124
123 125 -----------------------------------------------------------------------------
124 126 --
125 127 -----------------------------------------------------------------------------
126 128 PROCESS (clk, rstn)
127 129 BEGIN -- PROCESS
128 130 IF rstn = '0' THEN -- asynchronous reset (active low)
129 131 cnv_sync_reg <= '0';
130 132 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
131 133 cnv_sync_reg <= cnv_sync;
132 134 END IF;
133 135 END PROCESS;
134 136
135 137 cnv_sync_falling <= '1' WHEN cnv_sync = '0' AND cnv_sync_reg = '1' ELSE '0';
136 138
137 139 -----------------------------------------------------------------------------
138 140 -- GEN OutPut Enable
139 141 -----------------------------------------------------------------------------
140 142 PROCESS (clk, rstn)
141 143 BEGIN -- PROCESS
142 144 IF rstn = '0' THEN
143 145 -------------------------------------------------------------------------
144 146 ADC_nOE <= (OTHERS => '1');
145 147 ADC_current <= 0;
146 148 ADC_current_cycle_enabled <= 0;
147 149 state_GEN_OEn <= IDLE;
148 150 -------------------------------------------------------------------------
149 151 ADC_data_reg <= (OTHERS => '0');
150 152 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
151 153 sample_reg(I) <= (OTHERS => '0');
152 154 sample(I) <= (OTHERS => '0');
153 155 END LOOP all_channel_sample_reg_init;
154 156 sample_val <= '0';
155 157 sample_val_s <= '0';
156 158 sample_val_counter <= 0;
157 159 -------------------------------------------------------------------------
158 160 ELSIF clk'event AND clk = '1' THEN
159 161 -------------------------------------------------------------------------
160 162 sample_val_s <= '0';
161 163 ADC_nOE <= (OTHERS => '1');
162 164 CASE state_GEN_OEn IS
163 165 WHEN IDLE =>
164 166 IF cnv_sync_falling = '1' THEN
165 ADC_nOE(0) <= '0';
167 --ADC_nOE(0) <= '1';
166 168 state_GEN_OEn <= GEN_OE;
167 169 ADC_current <= 0;
168 170 ADC_current_cycle_enabled <= 1;
169 171 END IF;
170 172
171 173 WHEN GEN_OE =>
172 174 ADC_nOE(ADC_current) <= '0';
175
173 176 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
174 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
177
178 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
175 179 state_GEN_OEn <= WAIT_CYCLE;
176 180 END IF;
177 181
178 182 WHEN WAIT_CYCLE =>
179 ADC_current_cycle_enabled <= 0;
183 ADC_current_cycle_enabled <= 1;
180 184 IF ADC_current = ChanelCount-1 THEN
181 185 state_GEN_OEn <= IDLE;
182 186 sample_val_s <= '1';
183 187 ELSE
184 188 ADC_current <= ADC_current + 1;
185 189 state_GEN_OEn <= GEN_OE;
186 190 END IF;
187 191 WHEN OTHERS => NULL;
188 192 END CASE;
189 193 -------------------------------------------------------------------------
190 194 ADC_data_reg <= ADC_data;
191 195
192 196 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
193 197 IF ADC_data_valid = '1' AND ADC_current = I THEN
194 198 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
195 199 ELSE
196 200 sample_reg(I) <= sample_reg(I);
197 201 END IF;
198 202 END LOOP all_channel_sample_reg;
199 203 -------------------------------------------------------------------------
200 204 sample_val <= '0';
201 IF sample_val_s = '1' THEN
205 IF sample_val_s2 = '1' THEN
202 206 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
203 207 sample_val_counter <= 0;
204 208 sample_val <= '1'; -- TODO
205 sample <= sample_reg;
209 sample <= sample_reg;
206 210 ELSE
207 211 sample_val_counter <= sample_val_counter + 1;
208 212 sample_val <= '0';
209 213 END IF;
210 214 END IF;
211 215
212 216 END IF;
213 217 END PROCESS;
214 218
215 ADC_data_valid <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID ELSE '0';
219
220 ADC_data_valid_s <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID + 1 ELSE '0';
221
222 REG_ADC_DATA_valid: IF DATA_CYCLE_VALID = OE_NB_CYCLE_ENABLED GENERATE
223 PROCESS (clk, rstn)
224 BEGIN -- PROCESS
225 IF rstn = '0' THEN -- asynchronous reset (active low)
226 ADC_data_valid <= '0';
227 sample_val_s2 <= '0';
228 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
229 ADC_data_valid <= ADC_data_valid_s;
230 sample_val_s2 <= sample_val_s;
231 END IF;
232 END PROCESS;
233
234 END GENERATE REG_ADC_DATA_valid;
235
236 noREG_ADC_DATA_valid: IF DATA_CYCLE_VALID < OE_NB_CYCLE_ENABLED GENERATE
237 ADC_data_valid <= ADC_data_valid_s;
238 sample_val_s2 <= sample_val_s;
239 END GENERATE noREG_ADC_DATA_valid;
240
216 241
217 242 WITH ADC_current SELECT
218 243 ADC_data_selected <= sample_reg(0) WHEN 0,
219 244 sample_reg(1) WHEN 1,
220 245 sample_reg(2) WHEN 2,
221 246 sample_reg(3) WHEN 3,
222 247 sample_reg(4) WHEN 4,
223 248 sample_reg(5) WHEN 5,
224 249 sample_reg(6) WHEN 6,
225 250 sample_reg(7) WHEN 7,
226 251 sample_reg(8) WHEN OTHERS ;
227 252
228 253 ADC_data_result <= std_logic_vector((
229 254 signed( ADC_data_selected(13) & ADC_data_selected) +
230 255 signed( ADC_data_reg(13) & ADC_data_reg)
231 256 ));
232 257
233 258 -- sample <= sample_reg;
234 259
235 260 END ar_top_ad_conv_RHF1401;
236 261
237 262
238 263
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