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EQM debug
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1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4 use IEEE.std_logic_textio.all;
5 5 LIBRARY STD;
6 6 use std.textio.all;
7 7
8 8 LIBRARY grlib;
9 9 USE grlib.stdlib.ALL;
10 10 LIBRARY gaisler;
11 11 USE gaisler.libdcom.ALL;
12 12 USE gaisler.sim.ALL;
13 13 USE gaisler.jtagtst.ALL;
14 14 LIBRARY techmap;
15 15 USE techmap.gencomp.ALL;
16 16
17 17 LIBRARY lpp;
18 18 USE lpp.lpp_sim_pkg.ALL;
19 19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
22 22
23 23
24 24 ENTITY testbench IS
25 25 END;
26 26
27 27 ARCHITECTURE behav OF testbench IS
28 28
29 29 COMPONENT MINI_LFR_top
30 30 PORT (
31 31 clk_50 : IN STD_LOGIC;
32 32 clk_49 : IN STD_LOGIC;
33 33 reset : IN STD_LOGIC;
34 34 BP0 : IN STD_LOGIC;
35 35 BP1 : IN STD_LOGIC;
36 36 LED0 : OUT STD_LOGIC;
37 37 LED1 : OUT STD_LOGIC;
38 38 LED2 : OUT STD_LOGIC;
39 39 TXD1 : IN STD_LOGIC;
40 40 RXD1 : OUT STD_LOGIC;
41 41 nCTS1 : OUT STD_LOGIC;
42 42 nRTS1 : IN STD_LOGIC;
43 43 TXD2 : IN STD_LOGIC;
44 44 RXD2 : OUT STD_LOGIC;
45 45 nCTS2 : OUT STD_LOGIC;
46 46 nDTR2 : IN STD_LOGIC;
47 47 nRTS2 : IN STD_LOGIC;
48 48 nDCD2 : OUT STD_LOGIC;
49 49 IO0 : INOUT STD_LOGIC;
50 50 IO1 : INOUT STD_LOGIC;
51 51 IO2 : INOUT STD_LOGIC;
52 52 IO3 : INOUT STD_LOGIC;
53 53 IO4 : INOUT STD_LOGIC;
54 54 IO5 : INOUT STD_LOGIC;
55 55 IO6 : INOUT STD_LOGIC;
56 56 IO7 : INOUT STD_LOGIC;
57 57 IO8 : INOUT STD_LOGIC;
58 58 IO9 : INOUT STD_LOGIC;
59 59 IO10 : INOUT STD_LOGIC;
60 60 IO11 : INOUT STD_LOGIC;
61 61 SPW_EN : OUT STD_LOGIC;
62 62 SPW_NOM_DIN : IN STD_LOGIC;
63 63 SPW_NOM_SIN : IN STD_LOGIC;
64 64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 66 SPW_RED_DIN : IN STD_LOGIC;
67 67 SPW_RED_SIN : IN STD_LOGIC;
68 68 SPW_RED_DOUT : OUT STD_LOGIC;
69 69 SPW_RED_SOUT : OUT STD_LOGIC;
70 70 ADC_nCS : OUT STD_LOGIC;
71 71 ADC_CLK : OUT STD_LOGIC;
72 72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 73 SRAM_nWE : OUT STD_LOGIC;
74 74 SRAM_CE : OUT STD_LOGIC;
75 75 SRAM_nOE : OUT STD_LOGIC;
76 76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 79 END COMPONENT;
80 80
81 81 -----------------------------------------------------------------------------
82 82 SIGNAL clk_50 : STD_LOGIC := '0';
83 83 SIGNAL clk_49 : STD_LOGIC := '0';
84 84 SIGNAL reset : STD_LOGIC;
85 85 SIGNAL BP0 : STD_LOGIC;
86 86 SIGNAL BP1 : STD_LOGIC;
87 87 SIGNAL LED0 : STD_LOGIC;
88 88 SIGNAL LED1 : STD_LOGIC;
89 89 SIGNAL LED2 : STD_LOGIC;
90 90 SIGNAL TXD1 : STD_LOGIC;
91 91 SIGNAL RXD1 : STD_LOGIC;
92 92 SIGNAL nCTS1 : STD_LOGIC;
93 93 SIGNAL nRTS1 : STD_LOGIC;
94 94 SIGNAL TXD2 : STD_LOGIC;
95 95 SIGNAL RXD2 : STD_LOGIC;
96 96 SIGNAL nCTS2 : STD_LOGIC;
97 97 SIGNAL nDTR2 : STD_LOGIC;
98 98 SIGNAL nRTS2 : STD_LOGIC;
99 99 SIGNAL nDCD2 : STD_LOGIC;
100 100 SIGNAL IO0 : STD_LOGIC;
101 101 SIGNAL IO1 : STD_LOGIC;
102 102 SIGNAL IO2 : STD_LOGIC;
103 103 SIGNAL IO3 : STD_LOGIC;
104 104 SIGNAL IO4 : STD_LOGIC;
105 105 SIGNAL IO5 : STD_LOGIC;
106 106 SIGNAL IO6 : STD_LOGIC;
107 107 SIGNAL IO7 : STD_LOGIC;
108 108 SIGNAL IO8 : STD_LOGIC;
109 109 SIGNAL IO9 : STD_LOGIC;
110 110 SIGNAL IO10 : STD_LOGIC;
111 111 SIGNAL IO11 : STD_LOGIC;
112 112 SIGNAL SPW_EN : STD_LOGIC;
113 113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 121 SIGNAL ADC_nCS : STD_LOGIC;
122 122 SIGNAL ADC_CLK : STD_LOGIC;
123 123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 124 SIGNAL SRAM_nWE : STD_LOGIC;
125 125 SIGNAL SRAM_CE : STD_LOGIC;
126 126 SIGNAL SRAM_nOE : STD_LOGIC;
127 127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 130 -----------------------------------------------------------------------------
131 131
132 132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135 135
136 136
137 137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138 138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
139 139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
140 140
141 141 BEGIN
142 142
143 143 -----------------------------------------------------------------------------
144 144 -- TB
145 145 -----------------------------------------------------------------------------
146 146 PROCESS
147 147 CONSTANT txp : TIME := 320 ns;
148 148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 149 BEGIN -- PROCESS
150 150 TXD1 <= '1';
151 151 reset <= '0';
152 152 WAIT FOR 500 ns;
153 153 reset <= '1';
154 154 WAIT FOR 10000 ns;
155 155 message_simu <= "0 - UART init ";
156 156 UART_INIT(TXD1,txp);
157 157
158 158 message_simu <= "1 - UART test ";
159 159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
160 160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
161 161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
162 162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
163 163 data_read <= data_read_v;
164 164 data_message <= "GPIO_data_write";
165 165
166 166 -- UNSET the LFR reset
167 167 message_simu <= "2 - LFR UNRESET";
168 168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
169 169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
170 170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 171 --
172 172 message_simu <= "3 - LFR CONFIG ";
173 173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
175 175 X"40000000",
176 176 X"40001000",
177 177 X"40002000",
178 178 X"40003000",
179 179 X"40004000",
180 180 X"40005000");
181 181
182 182
183 183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
184 184 LFR_MODE_SBM1,
185 185 X"7FFFFFFF", -- START DATE
186 186
187 187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
188 188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
189 189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
190 190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
191 191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
192 192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
193 193
194 194 ADDR_BASE_LFR,
195 195 X"40006000",
196 196 X"40007000",
197 197 X"40008000",
198 198 X"40009000",
199 199 X"4000A000",
200 200 X"4000B000",
201 201 X"4000C000",
202 202 X"4000D000");
203 203
204 204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
205 205 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
206 206
207 207 message_simu <= "4 - GO GO GO !!";
208 208 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
209 209
210 210 READ_STATUS: LOOP
211 211 WAIT FOR 2 ms;
212 212 data_message <= "READ_NEW_STATUS";
213 213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
214 214 data_read <= data_read_v;
215 215 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
216 216
217 217 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
218 218 data_read <= data_read_v;
219 219 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
220 220 END LOOP READ_STATUS;
221 221
222 222 WAIT;
223 223 END PROCESS;
224 224
225 225 -----------------------------------------------------------------------------
226 226 -- CLOCK
227 227 -----------------------------------------------------------------------------
228 228 clk_50 <= NOT clk_50 AFTER 5 ns;
229 229 clk_49 <= NOT clk_49 AFTER 10172 ps;
230 230
231 231 -----------------------------------------------------------------------------
232 232 -- DON'T CARE
233 233 -----------------------------------------------------------------------------
234 234 BP0 <= '0';
235 235 BP1 <= '0';
236 236 nRTS1 <= '0' ;
237 237
238 238 TXD2 <= '1';
239 239 nRTS2 <= '1';
240 240 nDTR2 <= '1';
241 241
242 242 SPW_NOM_DIN <= '1';
243 243 SPW_NOM_SIN <= '1';
244 244 SPW_RED_DIN <= '1';
245 245 SPW_RED_SIN <= '1';
246 246
247 247 ADC_SDO <= x"AA";
248 248
249 249 SRAM_DQ <= (OTHERS => 'Z');
250 250 --IO0 <= 'Z';
251 251 --IO1 <= 'Z';
252 252 --IO2 <= 'Z';
253 253 --IO3 <= 'Z';
254 254 --IO4 <= 'Z';
255 255 --IO5 <= 'Z';
256 256 --IO6 <= 'Z';
257 257 --IO7 <= 'Z';
258 258 --IO8 <= 'Z';
259 259 --IO9 <= 'Z';
260 260 --IO10 <= 'Z';
261 261 --IO11 <= 'Z';
262 262
263 263 -----------------------------------------------------------------------------
264 264 -- DUT
265 265 -----------------------------------------------------------------------------
266 266 MINI_LFR_top_1: MINI_LFR_top
267 267 PORT MAP (
268 268 clk_50 => clk_50,
269 269 clk_49 => clk_49,
270 270 reset => reset,
271 271
272 272 BP0 => BP0,
273 273 BP1 => BP1,
274 274
275 275 LED0 => LED0,
276 276 LED1 => LED1,
277 277 LED2 => LED2,
278 278
279 279 TXD1 => TXD1,
280 280 RXD1 => RXD1,
281 281 nCTS1 => nCTS1,
282 282 nRTS1 => nRTS1,
283 283
284 284 TXD2 => TXD2,
285 285 RXD2 => RXD2,
286 286 nCTS2 => nCTS2,
287 287 nDTR2 => nDTR2,
288 288 nRTS2 => nRTS2,
289 289 nDCD2 => nDCD2,
290 290
291 291 IO0 => IO0,
292 292 IO1 => IO1,
293 293 IO2 => IO2,
294 294 IO3 => IO3,
295 295 IO4 => IO4,
296 296 IO5 => IO5,
297 297 IO6 => IO6,
298 298 IO7 => IO7,
299 299 IO8 => IO8,
300 300 IO9 => IO9,
301 301 IO10 => IO10,
302 302 IO11 => IO11,
303 303
304 304 SPW_EN => SPW_EN,
305 305 SPW_NOM_DIN => SPW_NOM_DIN,
306 306 SPW_NOM_SIN => SPW_NOM_SIN,
307 307 SPW_NOM_DOUT => SPW_NOM_DOUT,
308 308 SPW_NOM_SOUT => SPW_NOM_SOUT,
309 309 SPW_RED_DIN => SPW_RED_DIN,
310 310 SPW_RED_SIN => SPW_RED_SIN,
311 311 SPW_RED_DOUT => SPW_RED_DOUT,
312 312 SPW_RED_SOUT => SPW_RED_SOUT,
313 313
314 314 ADC_nCS => ADC_nCS,
315 315 ADC_CLK => ADC_CLK,
316 316 ADC_SDO => ADC_SDO,
317 317
318 318 SRAM_nWE => SRAM_nWE,
319 319 SRAM_CE => SRAM_CE,
320 320 SRAM_nOE => SRAM_nOE,
321 321 SRAM_nBE => SRAM_nBE,
322 322 SRAM_A => SRAM_A,
323 323 SRAM_DQ => SRAM_DQ);
324 324
325 325
326 326 END;
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@@ -1,467 +1,467
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.libdcom.ALL;
30 30 USE gaisler.sim.ALL;
31 31 USE gaisler.jtagtst.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 LIBRARY lpp;
35 35 USE lpp.lpp_sim_pkg.ALL;
36 36 USE lpp.lpp_lfr_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
37 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
38 38
39 39 PACKAGE lpp_lfr_sim_pkg IS
40 40
41 41 CONSTANT LFR_MODE_STANDBY : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
42 42 CONSTANT LFR_MODE_NORMAL : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
43 43 CONSTANT LFR_MODE_BURST : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
44 44 CONSTANT LFR_MODE_SBM1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
45 45 CONSTANT LFR_MODE_SBM2 : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
46 46
47 47 PROCEDURE UNRESET_LFR (
48 48 SIGNAL TX : OUT STD_LOGIC;
49 49 CONSTANT tx_period : IN TIME;
50 50 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
51 51 );
52 52
53 53 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
54 54 SIGNAL TX : OUT STD_LOGIC;
55 55 SIGNAL RX : IN STD_LOGIC;
56 56 CONSTANT tx_period : IN TIME;
57 57
58 58 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
59 59 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 63 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
65 65 );
66 66
67 67 PROCEDURE LAUNCH_WAVEFORM_PICKER(
68 68 SIGNAL TX : OUT STD_LOGIC;
69 69 SIGNAL RX : IN STD_LOGIC;
70 70 CONSTANT tx_period : IN TIME;
71 71
72 72 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
73 73 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
76 76 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 77 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
80 80 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81
82 82 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
83 83
84 84 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 86 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 87 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 88 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 91 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
92 92 );
93 93
94 94 -----------------------------------------------------------------------------
95 95 -- SM function
96 96 -----------------------------------------------------------------------------
97 97
98 98 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
99 99 SIGNAL TX : OUT STD_LOGIC;
100 100 SIGNAL RX : IN STD_LOGIC;
101 101 CONSTANT tx_period : IN TIME;
102 102 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
103 103 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
109 109 );
110 110
111 111 PROCEDURE SET_SM_IRQ_onNewMatrix(
112 112 SIGNAL TX : OUT STD_LOGIC;
113 113 SIGNAL RX : IN STD_LOGIC;
114 114 CONSTANT tx_period : IN TIME;
115 115 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
116 116 CONSTANT PARAM_value : IN STD_LOGIC
117 117 );
118 118
119 119 PROCEDURE SET_SM_IRQ_ERROR(
120 120 SIGNAL TX : OUT STD_LOGIC;
121 121 SIGNAL RX : IN STD_LOGIC;
122 122 CONSTANT tx_period : IN TIME;
123 123 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
124 124 CONSTANT PARAM_value : IN STD_LOGIC
125 125 );
126 126
127 127 PROCEDURE RESET_SM_STATUS(
128 128 SIGNAL TX : OUT STD_LOGIC;
129 129 SIGNAL RX : IN STD_LOGIC;
130 130 CONSTANT tx_period : IN TIME;
131 131 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
132 132 );
133 133
134 134 -----------------------------------------------------------------------------
135 135 -- WP function
136 136 -----------------------------------------------------------------------------
137 137
138 138 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
139 139 SIGNAL TX : OUT STD_LOGIC;
140 140 SIGNAL RX : IN STD_LOGIC;
141 141 CONSTANT tx_period : IN TIME;
142 142 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
143 143
144 144 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
145 145 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 146 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 147 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 148 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
149 149 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
150 150
151 151 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
153 153 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
154 154 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
155 155 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 156 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 157 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 158 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
159 159 );
160 160
161 161 PROCEDURE SET_WFP_DATA_SHAPING(
162 162 SIGNAL TX : OUT STD_LOGIC;
163 163 CONSTANT tx_period : IN TIME;
164 164 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
165 165 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0));
166 166
167 167 PROCEDURE RESET_WFP_BURST_ENABLE(
168 168 SIGNAL TX : OUT STD_LOGIC;
169 169 SIGNAL RX : IN STD_LOGIC;
170 170 CONSTANT tx_period : IN TIME;
171 171 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
172 172
173 173 PROCEDURE RESET_WFP_STATUS(
174 174 SIGNAL TX : OUT STD_LOGIC;
175 175 CONSTANT tx_period : IN TIME;
176 176 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8));
177 177
178 178 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
179 179 SIGNAL TX : OUT STD_LOGIC;
180 180 SIGNAL RX : IN STD_LOGIC;
181 181 CONSTANT tx_period : IN TIME;
182 182 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
183 183 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0)
184 184 );
185 185
186 186 END lpp_lfr_sim_pkg;
187 187
188 188
189 189
190 190 PACKAGE BODY lpp_lfr_sim_pkg IS
191 191
192 192 PROCEDURE UNRESET_LFR (
193 193 SIGNAL TX : OUT STD_LOGIC;
194 194 CONSTANT tx_period : IN TIME;
195 195 CONSTANT ADDR_BASE_TIME_MANAGMENT : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
196 196 IS
197 197 BEGIN
198 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
199 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
198 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_MANAGMENT_CONTROL , X"00000000");
199 UART_WRITE(TX,tx_period,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_MANAGMENT_TIME_LOAD , X"00000000");
200 200 END;
201 201
202 202 PROCEDURE LAUNCH_SPECTRAL_MATRIX(
203 203 SIGNAL TX : OUT STD_LOGIC;
204 204 SIGNAL RX : IN STD_LOGIC;
205 205 CONSTANT tx_period : IN TIME;
206 206 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
207 207 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
208 208 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
209 209 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
210 210 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
211 211 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
212 212 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
213 213 )
214 214 IS
215 215 BEGIN
216 216 RESET_SPECTRAL_MATRIX_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
217 217 PARAM_SM_f0_0_addr, PARAM_SM_f0_1_addr, PARAM_SM_f1_0_addr,
218 218 PARAM_SM_f1_1_addr, PARAM_SM_f2_0_addr, PARAM_SM_f2_1_addr);
219 219 SET_SM_IRQ_onNewMatrix (TX,RX,tx_period,ADDR_BASE_LFR,
220 220 '1');
221 221 END;
222 222
223 223
224 224 PROCEDURE LAUNCH_WAVEFORM_PICKER(
225 225 SIGNAL TX : OUT STD_LOGIC;
226 226 SIGNAL RX : IN STD_LOGIC;
227 227 CONSTANT tx_period : IN TIME;
228 228
229 229 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
230 230 CONSTANT TRANSITION_COARSE_TIME : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
231 231
232 232 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
233 233 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
234 234 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
235 235 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
236 236 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
237 237 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
238 238
239 239 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
240 240 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
241 241 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
242 242 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 243 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
244 244 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
245 245 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
246 246 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
247 247 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
248 248 -- CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
249 249 -- CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
250 250 -- CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 251 -- CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 252 -- CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
253 253 -- CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
254 254 )
255 255 IS
256 256 BEGIN
257 257 RESET_WAVEFORM_PICKER_REGS(TX,RX,tx_period,ADDR_BASE_LFR,
258 258 DATA_SHAPING ,
259 259 DELTA_SNAPSHOT,
260 260 DELTA_F0 ,
261 261 DELTA_F0_2 ,
262 262 DELTA_F1 ,
263 263 DELTA_F2 ,
264 264 PARAM_WP_f0_0_addr, PARAM_WP_f0_1_addr,
265 265 PARAM_WP_f1_0_addr, PARAM_WP_f1_1_addr,
266 266 PARAM_WP_f2_0_addr, PARAM_WP_f2_1_addr,
267 267 PARAM_WP_f3_0_addr, PARAM_WP_f3_1_addr);
268 268
269 269 SET_WFP_BURST_ENABLE_REGISTER(TX, RX, tx_period, ADDR_BASE_LFR, LFR_MODE);
270 270
271 271 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, TRANSITION_COARSE_TIME);
272 272
273 273 END;
274 274
275 275
276 276 -----------------------------------------------------------------------------
277 277 -- SM function
278 278 -----------------------------------------------------------------------------
279 279 PROCEDURE RESET_SPECTRAL_MATRIX_REGS(
280 280 SIGNAL TX : OUT STD_LOGIC;
281 281 SIGNAL RX : IN STD_LOGIC;
282 282 CONSTANT tx_period : IN TIME;
283 283 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
284 284 CONSTANT PARAM_SM_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
285 285 CONSTANT PARAM_SM_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
286 286 CONSTANT PARAM_SM_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
287 287 CONSTANT PARAM_SM_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
288 288 CONSTANT PARAM_SM_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
289 289 CONSTANT PARAM_SM_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
290 290 )
291 291 IS
292 292 BEGIN
293 293 SET_SM_IRQ_ERROR (TX,RX,tx_period,ADDR_BASE_LFR,'0');
294 294 SET_SM_IRQ_onNewMatrix(TX,RX,tx_period,ADDR_BASE_LFR,'0');
295 295 RESET_SM_STATUS (TX,RX,tx_period,ADDR_BASE_LFR);
296 296 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR,PARAM_SM_f0_0_addr);
297 297 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F0_1_ADDR,PARAM_SM_f0_1_addr);
298 298 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_0_ADDR,PARAM_SM_f1_0_addr);
299 299 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F1_1_ADDR,PARAM_SM_f1_1_addr);
300 300 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_0_ADDR,PARAM_SM_f2_0_addr);
301 301 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_F2_1_ADDR,PARAM_SM_f2_1_addr);
302 302 UART_WRITE (TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_LENGTH ,X"000000C8");
303 303 END;
304 304
305 305 PROCEDURE SET_SM_IRQ_onNewMatrix(
306 306 SIGNAL TX : OUT STD_LOGIC;
307 307 SIGNAL RX : IN STD_LOGIC;
308 308 CONSTANT tx_period : IN TIME;
309 309 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
310 310 CONSTANT PARAM_value : IN STD_LOGIC
311 311 )
312 312 IS
313 313 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
314 314 BEGIN
315 315 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
316 316 IF PARAM_value = '1' THEN
317 317 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '1' );
318 318 ELSE
319 319 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 1) & '0' );
320 320 END IF;
321 321 END;
322 322
323 323 PROCEDURE SET_SM_IRQ_ERROR(
324 324 SIGNAL TX : OUT STD_LOGIC;
325 325 SIGNAL RX : IN STD_LOGIC;
326 326 CONSTANT tx_period : IN TIME;
327 327 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8) ;
328 328 CONSTANT PARAM_value : IN STD_LOGIC
329 329 )
330 330 IS
331 331 VARIABLE data_read : STD_LOGIC_VECTOR(31 DOWNTO 0);
332 332 BEGIN
333 333 UART_READ(TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG, data_read);
334 334 IF PARAM_value = '1' THEN
335 335 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '1' & data_read(0) );
336 336 ELSE
337 337 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_CONFIG , data_read(31 DOWNTO 2) & '0' & data_read(0) );
338 338 END IF;
339 339 END;
340 340
341 341 PROCEDURE RESET_SM_STATUS(
342 342 SIGNAL TX : OUT STD_LOGIC;
343 343 SIGNAL RX : IN STD_LOGIC;
344 344 CONSTANT tx_period : IN TIME;
345 345 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8)
346 346 )
347 347 IS
348 348 BEGIN
349 349 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, X"000007FF");
350 350 END;
351 351
352 352 -----------------------------------------------------------------------------
353 353 -- WP function
354 354 -----------------------------------------------------------------------------
355 355
356 356 PROCEDURE RESET_WAVEFORM_PICKER_REGS(
357 357 SIGNAL TX : OUT STD_LOGIC;
358 358 SIGNAL RX : IN STD_LOGIC;
359 359 CONSTANT tx_period : IN TIME;
360 360 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
361 361
362 362 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
363 363 CONSTANT DELTA_SNAPSHOT : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
364 364 CONSTANT DELTA_F0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
365 365 CONSTANT DELTA_F0_2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
366 366 CONSTANT DELTA_F1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
367 367 CONSTANT DELTA_F2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
368 368
369 369 CONSTANT PARAM_WP_f0_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
370 370 CONSTANT PARAM_WP_f0_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
371 371 CONSTANT PARAM_WP_f1_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
372 372 CONSTANT PARAM_WP_f1_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
373 373 CONSTANT PARAM_WP_f2_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
374 374 CONSTANT PARAM_WP_f2_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
375 375 CONSTANT PARAM_WP_f3_0_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
376 376 CONSTANT PARAM_WP_f3_1_addr : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
377 377 )
378 378 IS
379 379 BEGIN
380 380 SET_WFP_DATA_SHAPING (TX, tx_period, ADDR_BASE_LFR, DATA_SHAPING);
381 381 RESET_WFP_BURST_ENABLE(TX, RX, tx_period, ADDR_BASE_LFR);
382 382 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_0_ADDR, PARAM_WP_f0_0_addr);
383 383 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F0_1_ADDR, PARAM_WP_f0_1_addr);
384 384 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_0_ADDR, PARAM_WP_f1_0_addr);
385 385 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F1_1_ADDR, PARAM_WP_f1_1_addr);
386 386 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_0_ADDR, PARAM_WP_f2_0_addr);
387 387 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F2_1_ADDR, PARAM_WP_f2_1_addr);
388 388 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_0_ADDR, PARAM_WP_f3_0_addr);
389 389 UART_WRITE (TX, tx_period, ADDR_BASE_LFR & ADDR_LFR_WP_F3_1_ADDR, PARAM_WP_f3_1_addr);
390 390 RESET_WFP_STATUS (TX, tx_period, ADDR_BASE_LFR);
391 391 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTASNAPSHOT, DELTA_SNAPSHOT);
392 392 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0, DELTA_F0);
393 393 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F0_2, DELTA_F0_2);
394 394 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F1, DELTA_F1);
395 395 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DELTA_F2, DELTA_F2);
396 396
397 397 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000A7F");
398 398 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_NBSNAPSHOT, X"00000A80");
399 399 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"7FFFFFFF");
400 400 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"000001F8");
401 401
402 402 END;
403 403
404 404 PROCEDURE SET_WFP_DATA_SHAPING(
405 405 SIGNAL TX : OUT STD_LOGIC;
406 406 CONSTANT tx_period : IN TIME;
407 407 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
408 408 CONSTANT DATA_SHAPING : IN STD_LOGIC_VECTOR(4 DOWNTO 0))
409 409 IS
410 410 BEGIN
411 411 UART_WRITE(TX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_DATASHAPING, X"000000" & "000" & DATA_SHAPING);
412 412 END;
413 413
414 414 PROCEDURE RESET_WFP_BURST_ENABLE(
415 415 SIGNAL TX : OUT STD_LOGIC;
416 416 SIGNAL RX : IN STD_LOGIC;
417 417 CONSTANT tx_period : IN TIME;
418 418 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
419 419 IS
420 420 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
421 421 BEGIN
422 422 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
423 423 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"000000" & data_read_v(7) & "0000000");
424 424 END;
425 425
426 426 PROCEDURE RESET_WFP_STATUS(
427 427 SIGNAL TX : OUT STD_LOGIC;
428 428 CONSTANT tx_period : IN TIME;
429 429 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8))
430 430 IS
431 431 BEGIN
432 432 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, X"0000FFFF");
433 433 END;
434 434
435 435 PROCEDURE SET_WFP_BURST_ENABLE_REGISTER(
436 436 SIGNAL TX : OUT STD_LOGIC;
437 437 SIGNAL RX : IN STD_LOGIC;
438 438 CONSTANT tx_period : IN TIME;
439 439 CONSTANT ADDR_BASE_LFR : IN STD_LOGIC_VECTOR(31 DOWNTO 8);
440 440 CONSTANT LFR_MODE : IN STD_LOGIC_VECTOR(2 DOWNTO 0))
441 441 IS
442 442 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
443 443 BEGIN
444 444 CASE LFR_MODE IS
445 445 WHEN LFR_MODE_STANDBY =>
446 446 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
447 447 WHEN LFR_MODE_NORMAL =>
448 448 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
449 449 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"0000000F");
450 450 WHEN LFR_MODE_BURST =>
451 451 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
452 452 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
453 453 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "11" & data_read_v(1 DOWNTO 0));
454 454 WHEN LFR_MODE_SBM1 =>
455 455 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000020");
456 456 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
457 457 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
458 458 WHEN LFR_MODE_SBM2 =>
459 459 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000040");
460 460 UART_READ (TX,RX,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v);
461 461 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, data_read_v(31 DOWNTO 4) & "1111");
462 462 WHEN OTHERS =>
463 463 UART_WRITE(TX ,tx_period,ADDR_BASE_LFR & ADDR_LFR_WP_CONTROL, X"00000000");
464 464 END CASE;
465 465 END;
466 466
467 467 END lpp_lfr_sim_pkg;
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