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1 AMBA_Peripherals.vhd
2 apb_devices_list.vhd
3
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1 filters.vhd
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1 SOC.vhd
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1 boards.vhd
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1 communication.vhd
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1 data_converters.vhd
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1 AMBA_Peripherals
2 sample_type
3 general_purpose
4 data_converters
5 SOC
6 DSP/filters
7 memory
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1 general_purpose.vhd
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1 memory.vhd
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1 1 # use glob syntax.
2 2 syntax: glob
3 3
4 4 *.tex
5 5 *.html
6 6 *log*
7 7 *.png
8 8 *.dot
9 9 *.css
10 10 *.md5
11 11 *.eps
12 12 *.pdf
13 13 *.toc
14 14 *.map
15 15 *.sty
16 16 *.3
17 17 *.js
18 18 *.aux
19 19 *.idx
20 20 *doc*
21 21 *Doc*
22 *vhdlsyn.txt
23 *dirs.txt
24 22 *.orig
25 23 *.o
26 24 *.a
27 25 *.bin
28 26 *~
29 27 apb_devices_list.h
30 28 apb_devices_list.vhd
31 29 twiddle.vhd
32 30 primitives.vhd
33 31 fftSm.vhd
34 32 fftDp.vhd
35 33 fft_components.vhd
36 34 CoreFFT.vhd
37 35 actram.vhd
38 36 actar.vhd No newline at end of file
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1 1 vendor VENDOR_LPP 19
2 2
3 3 device ROCKET_TM 1
4 4 device otherCore 2
5 5 device LPP_SIMPLE_DIODE 3
6 6 device LPP_MULTI_DIODE 4
7 7 device LPP_LCD_CTRLR 5
8 8 device LPP_UART 6
9 9 device LPP_CNA 7
10 10 device LPP_APB_ADC 8
11 11 device LPP_CHENILLARD 9
12 12 device LPP_IIR_CEL_FILTER 10
13 13 device LPP_FIFO_PID 11
14 14 device LPP_FFT 12
15 15 device LPP_MATRIX 13
16 16 device LPP_DELAY 14
17 17 device LPP_USB 15
18 18 device LPP_BALISE 16
19 device LPP_DMA_TYPE 17
20 device LPP_BOOTLOADER_TYPE 18
21 device LPP_LFR 19
22 device LPP_CLKSETTING 20
23 device LPP_DEBUG_DMA A0
24 device LPP_DEBUG_LFR A1
25 device LPP_DEBUG_LFR_ID A2
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1 1
2 2 ------------------------------------------------------------------------------
3 3 -- This file is a part of the LPP VHDL IP LIBRARY
4 4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 5 --
6 6 -- This program is free software; you can redistribute it and/or modify
7 7 -- it under the terms of the GNU General Public License as published by
8 8 -- the Free Software Foundation; either version 3 of the License, or
9 9 -- (at your option) any later version.
10 10 --
11 11 -- This program is distributed in the hope that it will be useful,
12 12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 14 -- GNU General Public License for more details.
15 15 --
16 16 -- You should have received a copy of the GNU General Public License
17 17 -- along with this program; if not, write to the Free Software
18 18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 19 -------------------------------------------------------------------------------
20 20 -- Author : Jean-christophe Pellion
21 21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 22 -- jean-christophe.pellion@easii-ic.com
23 23 -------------------------------------------------------------------------------
24 24 -- 1.0 - initial version
25 25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 26 -------------------------------------------------------------------------------
27 27 LIBRARY ieee;
28 28 USE ieee.std_logic_1164.ALL;
29 29 USE ieee.numeric_std.ALL;
30 30 LIBRARY grlib;
31 31 USE grlib.amba.ALL;
32 32 USE grlib.stdlib.ALL;
33 33 USE grlib.devices.ALL;
34 34 USE GRLIB.DMA2AHB_Package.ALL;
35 35
36 36 LIBRARY techmap;
37 37 USE techmap.gencomp.ALL;
38 38
39 LIBRARY VHDLIB;
40 USE VHDLIB.apb_devices_list.ALL;
41
39 42 LIBRARY staging;
40 43 USE staging.lpp_dma_pkg_LPP_JCP.ALL;
41 44
42 45
43 46 ENTITY lpp_dma_singleOrBurst_LPP_JCP IS
44 47 GENERIC (
45 48 tech : INTEGER := inferred;
46 49 hindex : INTEGER := 2
47 50 );
48 51 PORT (
49 52 -- AMBA AHB system signals
50 53 HCLK : IN STD_ULOGIC;
51 54 HRESETn : IN STD_ULOGIC;
52 55 --
53 56 run : IN STD_LOGIC;
54 57 -- AMBA AHB Master Interface
55 58 AHB_Master_In : IN AHB_Mst_In_Type;
56 59 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 60 --
58 61 send : IN STD_LOGIC;
59 62 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
60 63 done : OUT STD_LOGIC;
61 64 ren : OUT STD_LOGIC;
62 65 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 66 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 67 --
65 68 debug_dmaout_okay : OUT STD_LOGIC
66 69
67 70 );
68 71 END;
69 72
70 73 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst_LPP_JCP IS
71 74 -----------------------------------------------------------------------------
72 75 SIGNAL DMAIn : DMA_In_Type;
73 76 SIGNAL DMAOut : DMA_OUt_Type;
74 77 -----------------------------------------------------------------------------
75 78 -----------------------------------------------------------------------------
76 79 -- CONTROL
77 80 SIGNAL single_send : STD_LOGIC;
78 81 SIGNAL burst_send : STD_LOGIC;
79 82
80 83 -----------------------------------------------------------------------------
81 84 -- SEND SINGLE MODULE
82 85 SIGNAL single_dmai : DMA_In_Type;
83 86
84 87 SIGNAL single_send_ok : STD_LOGIC;
85 88 SIGNAL single_send_ko : STD_LOGIC;
86 89 SIGNAL single_ren : STD_LOGIC;
87 90 -----------------------------------------------------------------------------
88 91 -- SEND SINGLE MODULE
89 92 SIGNAL burst_dmai : DMA_In_Type;
90 93
91 94 SIGNAL burst_send_ok : STD_LOGIC;
92 95 SIGNAL burst_send_ko : STD_LOGIC;
93 96 SIGNAL burst_ren : STD_LOGIC;
94 97 -----------------------------------------------------------------------------
95 98 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 99 -----------------------------------------------------------------------------
97 100 SIGNAL send_reg : STD_LOGIC;
98 101 SIGNAL send_s : STD_LOGIC;
99 102
100 103
101 104 BEGIN
102 105
103 106 debug_dmaout_okay <= DMAOut.OKAY;
104 107
105 108
106 109 -----------------------------------------------------------------------------
107 110 -- DMA to AHB interface
108 111 DMA2AHB_1 : DMA2AHB
109 112 GENERIC MAP (
110 113 hindex => hindex,
111 114 vendorid => VENDOR_LPP,
112 115 deviceid => 10,
113 116 version => 0,
114 117 syncrst => 1,
115 118 boundary => 1)
116 119 PORT MAP (
117 120 HCLK => HCLK,
118 121 HRESETn => HRESETn,
119 122 DMAIn => DMAIn,
120 123 DMAOut => DMAOut,
121 124
122 125 AHBIn => AHB_Master_In,
123 126 AHBOut => AHB_Master_Out);
124 127 -----------------------------------------------------------------------------
125 128
126 129 -----------------------------------------------------------------------------
127 130 PROCESS (HCLK, HRESETn)
128 131 BEGIN
129 132 IF HRESETn = '0' THEN
130 133 send_reg <= '0';
131 134 ELSIF HCLK'event AND HCLK = '1' THEN
132 135 send_reg <= send;
133 136 END IF;
134 137 END PROCESS;
135 138 send_s <= send_reg;
136 139
137 140 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
138 141 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
139 142
140 143 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
141 144
142 145 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
143 146
144 147 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 148 single_ren;
146 149
147 150
148 151 -----------------------------------------------------------------------------
149 152 -- SEND 1 word by DMA
150 153 -----------------------------------------------------------------------------
151 154 lpp_dma_send_1word_1 : lpp_dma_send_1word_LPP_JCP
152 155 PORT MAP (
153 156 HCLK => HCLK,
154 157 HRESETn => HRESETn,
155 158 DMAIn => single_dmai,
156 159 DMAOut => DMAOut,
157 160
158 161 send => single_send,
159 162 address => address,
160 163 data => data_2_halfword,
161 164 ren => single_ren,
162 165
163 166 send_ok => single_send_ok,
164 167 send_ko => single_send_ko
165 168 );
166 169
167 170 -----------------------------------------------------------------------------
168 171 -- SEND 16 word by DMA (in burst mode)
169 172 -----------------------------------------------------------------------------
170 173 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
171 174
172 175 lpp_dma_send_16word_1 : lpp_dma_send_16word_LPP_JCP
173 176 PORT MAP (
174 177 HCLK => HCLK,
175 178 HRESETn => HRESETn,
176 179 DMAIn => burst_dmai,
177 180 DMAOut => DMAOut,
178 181
179 182 send => burst_send,
180 183 address => address,
181 184 data => data_2_halfword,
182 185 ren => burst_ren,
183 186
184 187 send_ok => burst_send_ok,
185 188 send_ko => burst_send_ko);
186 189
187 190 END Behavioral;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30
31 31 LIBRARY techmap;
32 32 USE techmap.gencomp.ALL;
33 33
34 LIBRARY VHDLIB;
35 USE VHDLIB.apb_devices_list.ALL;
36
34 37 ENTITY lpp_lfr_apbreg_LPP_JCP IS
35 38 GENERIC (
36 39 nb_data_by_buffer_size : INTEGER := 11;
37 40 nb_word_by_buffer_size : INTEGER := 11;
38 41 nb_snapshot_param_size : INTEGER := 11;
39 42 delta_vector_size : INTEGER := 20;
40 43 delta_vector_size_f0_2 : INTEGER := 3;
41 44
42 45 pindex : INTEGER := 4;
43 46 paddr : INTEGER := 4;
44 47 pmask : INTEGER := 16#fff#;
45 48 pirq_ms : INTEGER := 0;
46 49 pirq_wfp : INTEGER := 1;
47 50 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
48 51 PORT (
49 52 -- AMBA AHB system signals
50 53 HCLK : IN STD_ULOGIC;
51 54 HRESETn : IN STD_ULOGIC;
52 55
53 56 -- AMBA APB Slave Interface
54 57 apbi : IN apb_slv_in_type;
55 58 apbo : OUT apb_slv_out_type;
56 59
57 60 ---------------------------------------------------------------------------
58 61 -- Spectral Matrix Reg
59 62 -- IN
60 63 ready_matrix_f0_0 : IN STD_LOGIC;
61 64 ready_matrix_f0_1 : IN STD_LOGIC;
62 65 ready_matrix_f1 : IN STD_LOGIC;
63 66 ready_matrix_f2 : IN STD_LOGIC;
64 67 error_anticipating_empty_fifo : IN STD_LOGIC;
65 68 error_bad_component_error : IN STD_LOGIC;
66 69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
67 70
68 71 -- OUT
69 72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
70 73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
71 74 status_ready_matrix_f1 : OUT STD_LOGIC;
72 75 status_ready_matrix_f2 : OUT STD_LOGIC;
73 76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
74 77 status_error_bad_component_error : OUT STD_LOGIC;
75 78
76 79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
77 80 config_active_interruption_onError : OUT STD_LOGIC;
78 81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 85 ---------------------------------------------------------------------------
83 86 ---------------------------------------------------------------------------
84 87 -- WaveForm picker Reg
85 88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
86 89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
87 90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 92
90 93 -- OUT
91 94 data_shaping_BW : OUT STD_LOGIC;
92 95 data_shaping_SP0 : OUT STD_LOGIC;
93 96 data_shaping_SP1 : OUT STD_LOGIC;
94 97 data_shaping_R0 : OUT STD_LOGIC;
95 98 data_shaping_R1 : OUT STD_LOGIC;
96 99
97 100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
98 101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
99 102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
100 103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
103 106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
104 107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
105 108
106 109 enable_f0 : OUT STD_LOGIC;
107 110 enable_f1 : OUT STD_LOGIC;
108 111 enable_f2 : OUT STD_LOGIC;
109 112 enable_f3 : OUT STD_LOGIC;
110 113
111 114 burst_f0 : OUT STD_LOGIC;
112 115 burst_f1 : OUT STD_LOGIC;
113 116 burst_f2 : OUT STD_LOGIC;
114 117
115 118 run : OUT STD_LOGIC;
116 119
117 120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
122 125 ---------------------------------------------------------------------------
123 126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
125 128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
131 134
132 135 ---------------------------------------------------------------------------
133 136 );
134 137
135 138 END lpp_lfr_apbreg_LPP_JCP;
136 139
137 140 ARCHITECTURE beh OF lpp_lfr_apbreg_LPP_JCP IS
138 141
139 142 CONSTANT REVISION : INTEGER := 1;
140 143
141 144 CONSTANT pconfig : apb_config_type := (
142 145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
143 146 1 => apb_iobar(paddr, pmask));
144 147
145 148 TYPE lpp_SpectralMatrix_regs IS RECORD
146 149 config_active_interruption_onNewMatrix : STD_LOGIC;
147 150 config_active_interruption_onError : STD_LOGIC;
148 151 status_ready_matrix_f0_0 : STD_LOGIC;
149 152 status_ready_matrix_f0_1 : STD_LOGIC;
150 153 status_ready_matrix_f1 : STD_LOGIC;
151 154 status_ready_matrix_f2 : STD_LOGIC;
152 155 status_error_anticipating_empty_fifo : STD_LOGIC;
153 156 status_error_bad_component_error : STD_LOGIC;
154 157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 161 END RECORD;
159 162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
160 163
161 164 TYPE lpp_WaveformPicker_regs IS RECORD
162 165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 168 data_shaping_BW : STD_LOGIC;
166 169 data_shaping_SP0 : STD_LOGIC;
167 170 data_shaping_SP1 : STD_LOGIC;
168 171 data_shaping_R0 : STD_LOGIC;
169 172 data_shaping_R1 : STD_LOGIC;
170 173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
171 174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
172 175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
173 176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
175 178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
176 179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
177 180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
178 181 enable_f0 : STD_LOGIC;
179 182 enable_f1 : STD_LOGIC;
180 183 enable_f2 : STD_LOGIC;
181 184 enable_f3 : STD_LOGIC;
182 185 burst_f0 : STD_LOGIC;
183 186 burst_f1 : STD_LOGIC;
184 187 burst_f2 : STD_LOGIC;
185 188 run : STD_LOGIC;
186 189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
191 194 END RECORD;
192 195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
193 196
194 197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 198
196 199 -----------------------------------------------------------------------------
197 200 -- IRQ
198 201 -----------------------------------------------------------------------------
199 202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
200 203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
201 204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
202 205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
203 206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 207 SIGNAL ored_irq_wfp : STD_LOGIC;
205 208
206 209 BEGIN -- beh
207 210
208 211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
209 212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
210 213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
211 214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
212 215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
213 216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
214 217
215 218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
216 219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
217 220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
218 221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
219 222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
220 223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
221 224
222 225
223 226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
224 227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
225 228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
226 229 data_shaping_R0 <= reg_wp.data_shaping_R0;
227 230 data_shaping_R1 <= reg_wp.data_shaping_R1;
228 231
229 232 delta_snapshot <= reg_wp.delta_snapshot;
230 233 delta_f0 <= reg_wp.delta_f0;
231 234 delta_f0_2 <= reg_wp.delta_f0_2;
232 235 delta_f1 <= reg_wp.delta_f1;
233 236 delta_f2 <= reg_wp.delta_f2;
234 237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
235 238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
236 239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
237 240
238 241 enable_f0 <= reg_wp.enable_f0;
239 242 enable_f1 <= reg_wp.enable_f1;
240 243 enable_f2 <= reg_wp.enable_f2;
241 244 enable_f3 <= reg_wp.enable_f3;
242 245
243 246 burst_f0 <= reg_wp.burst_f0;
244 247 burst_f1 <= reg_wp.burst_f1;
245 248 burst_f2 <= reg_wp.burst_f2;
246 249
247 250 run <= reg_wp.run;
248 251
249 252 addr_data_f0 <= reg_wp.addr_data_f0;
250 253 addr_data_f1 <= reg_wp.addr_data_f1;
251 254 addr_data_f2 <= reg_wp.addr_data_f2;
252 255 addr_data_f3 <= reg_wp.addr_data_f3;
253 256
254 257 start_date <= reg_wp.start_date;
255 258
256 259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
257 260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
258 261 BEGIN -- PROCESS lpp_dma_top
259 262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
260 263 reg_sp.config_active_interruption_onNewMatrix <= '0';
261 264 reg_sp.config_active_interruption_onError <= '0';
262 265 reg_sp.status_ready_matrix_f0_0 <= '0';
263 266 reg_sp.status_ready_matrix_f0_1 <= '0';
264 267 reg_sp.status_ready_matrix_f1 <= '0';
265 268 reg_sp.status_ready_matrix_f2 <= '0';
266 269 reg_sp.status_error_anticipating_empty_fifo <= '0';
267 270 reg_sp.status_error_bad_component_error <= '0';
268 271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
269 272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
270 273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
271 274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
272 275 prdata <= (OTHERS => '0');
273 276
274 277 apbo.pirq <= (OTHERS => '0');
275 278
276 279 status_full_ack <= (OTHERS => '0');
277 280
278 281 reg_wp.data_shaping_BW <= '0';
279 282 reg_wp.data_shaping_SP0 <= '0';
280 283 reg_wp.data_shaping_SP1 <= '0';
281 284 reg_wp.data_shaping_R0 <= '0';
282 285 reg_wp.data_shaping_R1 <= '0';
283 286 reg_wp.enable_f0 <= '0';
284 287 reg_wp.enable_f1 <= '0';
285 288 reg_wp.enable_f2 <= '0';
286 289 reg_wp.enable_f3 <= '0';
287 290 reg_wp.burst_f0 <= '0';
288 291 reg_wp.burst_f1 <= '0';
289 292 reg_wp.burst_f2 <= '0';
290 293 reg_wp.run <= '0';
291 294 reg_wp.addr_data_f0 <= (OTHERS => '0');
292 295 reg_wp.addr_data_f1 <= (OTHERS => '0');
293 296 reg_wp.addr_data_f2 <= (OTHERS => '0');
294 297 reg_wp.addr_data_f3 <= (OTHERS => '0');
295 298 reg_wp.status_full <= (OTHERS => '0');
296 299 reg_wp.status_full_err <= (OTHERS => '0');
297 300 reg_wp.status_new_err <= (OTHERS => '0');
298 301 reg_wp.delta_snapshot <= (OTHERS => '0');
299 302 reg_wp.delta_f0 <= (OTHERS => '0');
300 303 reg_wp.delta_f0_2 <= (OTHERS => '0');
301 304 reg_wp.delta_f1 <= (OTHERS => '0');
302 305 reg_wp.delta_f2 <= (OTHERS => '0');
303 306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
304 307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
305 308 reg_wp.start_date <= (OTHERS => '0');
306 309
307 310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
308 311 status_full_ack <= (OTHERS => '0');
309 312
310 313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
311 314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
312 315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
313 316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
314 317
315 318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
316 319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
317 320 all_status: FOR I IN 3 DOWNTO 0 LOOP
318 321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
319 322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
320 323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
321 324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
322 325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
323 326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
324 327 END LOOP all_status;
325 328
326 329 paddr := "000000";
327 330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
328 331 prdata <= (OTHERS => '0');
329 332 IF apbi.psel(pindex) = '1' THEN
330 333 -- APB DMA READ --
331 334 CASE paddr(7 DOWNTO 2) IS
332 335 --
333 336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
334 337 prdata(1) <= reg_sp.config_active_interruption_onError;
335 338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
336 339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
337 340 prdata(2) <= reg_sp.status_ready_matrix_f1;
338 341 prdata(3) <= reg_sp.status_ready_matrix_f2;
339 342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
340 343 prdata(5) <= reg_sp.status_error_bad_component_error;
341 344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
342 345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
343 346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
344 347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
345 348 WHEN "000110" => prdata <= debug_reg;
346 349 --
347 350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
348 351 prdata(1) <= reg_wp.data_shaping_SP0;
349 352 prdata(2) <= reg_wp.data_shaping_SP1;
350 353 prdata(3) <= reg_wp.data_shaping_R0;
351 354 prdata(4) <= reg_wp.data_shaping_R1;
352 355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
353 356 prdata(1) <= reg_wp.enable_f1;
354 357 prdata(2) <= reg_wp.enable_f2;
355 358 prdata(3) <= reg_wp.enable_f3;
356 359 prdata(4) <= reg_wp.burst_f0;
357 360 prdata(5) <= reg_wp.burst_f1;
358 361 prdata(6) <= reg_wp.burst_f2;
359 362 prdata(7) <= reg_wp.run;
360 363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
361 364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
362 365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
363 366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
364 367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
365 368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
366 369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
367 370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
368 371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
369 372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
370 373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
371 374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
372 375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
373 376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
374 377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
375 378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
376 379 ----------------------------------------------------
377 380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
378 381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
379 382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
380 383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
381 384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
382 385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
383 386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
384 387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
385 388 ----------------------------------------------------
386 389 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
387 390 WHEN OTHERS => NULL;
388 391 END CASE;
389 392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
390 393 -- APB DMA WRITE --
391 394 CASE paddr(7 DOWNTO 2) IS
392 395 --
393 396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
394 397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
395 398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
396 399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
397 400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
398 401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
399 402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
400 403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
401 404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
402 405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
403 406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
404 407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
405 408 --
406 409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
407 410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
408 411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
409 412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
410 413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
411 414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
412 415 reg_wp.enable_f1 <= apbi.pwdata(1);
413 416 reg_wp.enable_f2 <= apbi.pwdata(2);
414 417 reg_wp.enable_f3 <= apbi.pwdata(3);
415 418 reg_wp.burst_f0 <= apbi.pwdata(4);
416 419 reg_wp.burst_f1 <= apbi.pwdata(5);
417 420 reg_wp.burst_f2 <= apbi.pwdata(6);
418 421 reg_wp.run <= apbi.pwdata(7);
419 422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
420 423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
421 424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
422 425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
423 426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
424 427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
425 428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
426 429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
427 430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
428 431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
429 432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
430 433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
431 434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
432 435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
433 436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
436 439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
437 440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
438 441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
439 442 --
440 443 WHEN OTHERS => NULL;
441 444 END CASE;
442 445 END IF;
443 446 END IF;
444 447
445 448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
446 449 ready_matrix_f0_1 OR
447 450 ready_matrix_f1 OR
448 451 ready_matrix_f2)
449 452 )
450 453 OR
451 454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
452 455 error_bad_component_error)
453 456 ));
454 457
455 458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
456 459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
457 460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
458 461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
459 462 -- );
460 463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
461 464
462 465 END IF;
463 466 END PROCESS lpp_lfr_apbreg;
464 467
465 468 apbo.pindex <= pindex;
466 469 apbo.pconfig <= pconfig;
467 470 apbo.prdata <= prdata;
468 471
469 472 -----------------------------------------------------------------------------
470 473 -- IRQ
471 474 -----------------------------------------------------------------------------
472 475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
473 476
474 477 PROCESS (HCLK, HRESETn)
475 478 BEGIN -- PROCESS
476 479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
477 480 irq_wfp_reg <= (OTHERS => '0');
478 481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
479 482 irq_wfp_reg <= irq_wfp_reg_s;
480 483 END IF;
481 484 END PROCESS;
482 485
483 486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
484 487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
485 488 END GENERATE all_irq_wfp;
486 489
487 490 irq_wfp_ZERO <= (OTHERS => '0');
488 491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
489 492
490 END beh;
493 END beh; No newline at end of file
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@@ -1,211 +1,255
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 -------------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30
31 31 LIBRARY staging;
32 32 USE staging.sample_type_LPP_JCP.ALL;
33 33
34 34 PACKAGE lpp_lfr_pkg_LPP_JCP IS
35 35
36 36 COMPONENT lpp_lfr_apbreg_LPP_JCP
37 37 GENERIC (
38 38 nb_data_by_buffer_size : INTEGER;
39 39 nb_word_by_buffer_size : INTEGER;
40 40 nb_snapshot_param_size : INTEGER;
41 41 delta_vector_size : INTEGER;
42 42 delta_vector_size_f0_2 : INTEGER;
43 43 pindex : INTEGER;
44 44 paddr : INTEGER;
45 45 pmask : INTEGER;
46 46 pirq_ms : INTEGER;
47 47 pirq_wfp : INTEGER;
48 48 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 ready_matrix_f0_0 : IN STD_LOGIC;
55 55 ready_matrix_f0_1 : IN STD_LOGIC;
56 56 ready_matrix_f1 : IN STD_LOGIC;
57 57 ready_matrix_f2 : IN STD_LOGIC;
58 58 error_anticipating_empty_fifo : IN STD_LOGIC;
59 59 error_bad_component_error : IN STD_LOGIC;
60 60 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 status_ready_matrix_f0_0 : OUT STD_LOGIC;
62 62 status_ready_matrix_f0_1 : OUT STD_LOGIC;
63 63 status_ready_matrix_f1 : OUT STD_LOGIC;
64 64 status_ready_matrix_f2 : OUT STD_LOGIC;
65 65 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
66 66 status_error_bad_component_error : OUT STD_LOGIC;
67 67 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
68 68 config_active_interruption_onError : OUT STD_LOGIC;
69 69 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 70 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 71 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
74 74 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
75 75 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
76 76 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
77 77 data_shaping_BW : OUT STD_LOGIC;
78 78 data_shaping_SP0 : OUT STD_LOGIC;
79 79 data_shaping_SP1 : OUT STD_LOGIC;
80 80 data_shaping_R0 : OUT STD_LOGIC;
81 81 data_shaping_R1 : OUT STD_LOGIC;
82 82 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
83 83 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
84 84 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
85 85 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 86 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 87 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
88 88 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
89 89 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
90 90 enable_f0 : OUT STD_LOGIC;
91 91 enable_f1 : OUT STD_LOGIC;
92 92 enable_f2 : OUT STD_LOGIC;
93 93 enable_f3 : OUT STD_LOGIC;
94 94 burst_f0 : OUT STD_LOGIC;
95 95 burst_f1 : OUT STD_LOGIC;
96 96 burst_f2 : OUT STD_LOGIC;
97 97 run : OUT STD_LOGIC;
98 98 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 101 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 102 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
103 103 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 104 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 105 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 106 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
111 111 END COMPONENT;
112 112
113 113 -----------------------------------------------------------------------------
114 114 -- lpp_filter
115 115 -----------------------------------------------------------------------------
116 116 COMPONENT lpp_lfr_filter_LPP_JCP
117 117 GENERIC (
118 118 Mem_use : INTEGER);
119 119 PORT (
120 120 sample : IN Samples(7 DOWNTO 0);
121 121 sample_val : IN STD_LOGIC;
122 122 clk : IN STD_LOGIC;
123 123 rstn : IN STD_LOGIC;
124 124 data_shaping_SP0 : IN STD_LOGIC;
125 125 data_shaping_SP1 : IN STD_LOGIC;
126 126 data_shaping_R0 : IN STD_LOGIC;
127 127 data_shaping_R1 : IN STD_LOGIC;
128 128 sample_f0_val : OUT STD_LOGIC;
129 129 sample_f1_val : OUT STD_LOGIC;
130 130 sample_f2_val : OUT STD_LOGIC;
131 131 sample_f3_val : OUT STD_LOGIC;
132 132 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 133 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 134 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 135 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
136 136 END COMPONENT;
137 137
138 138 -----------------------------------------------------------------------------
139 139 -- lpp_waveform
140 140 -----------------------------------------------------------------------------
141 141 COMPONENT lpp_waveform_LPP_JCP
142 142 GENERIC (
143 143 tech : INTEGER;
144 144 data_size : INTEGER;
145 145 nb_data_by_buffer_size : INTEGER;
146 146 nb_word_by_buffer_size : INTEGER;
147 147 nb_snapshot_param_size : INTEGER;
148 148 delta_vector_size : INTEGER;
149 149 delta_vector_size_f0_2 : INTEGER);
150 150 PORT (
151 151 clk : IN STD_LOGIC;
152 152 rstn : IN STD_LOGIC;
153 153 reg_run : IN STD_LOGIC;
154 154 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
155 155 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
156 156 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
157 157 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
158 158 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
159 159 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 160 enable_f0 : IN STD_LOGIC;
161 161 enable_f1 : IN STD_LOGIC;
162 162 enable_f2 : IN STD_LOGIC;
163 163 enable_f3 : IN STD_LOGIC;
164 164 burst_f0 : IN STD_LOGIC;
165 165 burst_f1 : IN STD_LOGIC;
166 166 burst_f2 : IN STD_LOGIC;
167 167 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 168 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 169 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 170 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
171 171 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
172 172 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
173 173 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
174 174 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
176 176 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 177 data_f0_in_valid : IN STD_LOGIC;
178 178 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 179 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
180 180 data_f1_in_valid : IN STD_LOGIC;
181 181 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
182 182 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
183 183 data_f2_in_valid : IN STD_LOGIC;
184 184 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
185 185 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 186 data_f3_in_valid : IN STD_LOGIC;
187 187 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
188 188 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 189 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 190 data_f0_data_out_valid : OUT STD_LOGIC;
191 191 data_f0_data_out_valid_burst : OUT STD_LOGIC;
192 192 data_f0_data_out_ren : IN STD_LOGIC;
193 193 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
194 194 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
195 195 data_f1_data_out_valid : OUT STD_LOGIC;
196 196 data_f1_data_out_valid_burst : OUT STD_LOGIC;
197 197 data_f1_data_out_ren : IN STD_LOGIC;
198 198 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
200 200 data_f2_data_out_valid : OUT STD_LOGIC;
201 201 data_f2_data_out_valid_burst : OUT STD_LOGIC;
202 202 data_f2_data_out_ren : IN STD_LOGIC;
203 203 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
204 204 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
205 205 data_f3_data_out_valid : OUT STD_LOGIC;
206 206 data_f3_data_out_valid_burst : OUT STD_LOGIC;
207 207 data_f3_data_out_ren : IN STD_LOGIC;
208 208 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
209 209 END COMPONENT;
210
211 -----------------------------------------------------------------------------
212 -- lpp_matrix_spectral
213 -----------------------------------------------------------------------------
214 COMPONENT lpp_lfr_ms_LPP_JCP
215 GENERIC (
216 Mem_use : INTEGER);
217 PORT (
218 clk : IN STD_LOGIC;
219 rstn : IN STD_LOGIC;
220 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
222 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
223 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
225 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
226 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
227 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
228 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
229 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
230 dma_valid : OUT STD_LOGIC;
231 dma_valid_burst : OUT STD_LOGIC;
232 dma_ren : IN STD_LOGIC;
233 dma_done : IN STD_LOGIC;
234 ready_matrix_f0_0 : OUT STD_LOGIC;
235 ready_matrix_f0_1 : OUT STD_LOGIC;
236 ready_matrix_f1 : OUT STD_LOGIC;
237 ready_matrix_f2 : OUT STD_LOGIC;
238 error_anticipating_empty_fifo : OUT STD_LOGIC;
239 error_bad_component_error : OUT STD_LOGIC;
240 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 status_ready_matrix_f0_0 : IN STD_LOGIC;
242 status_ready_matrix_f0_1 : IN STD_LOGIC;
243 status_ready_matrix_f1 : IN STD_LOGIC;
244 status_ready_matrix_f2 : IN STD_LOGIC;
245 status_error_anticipating_empty_fifo : IN STD_LOGIC;
246 status_error_bad_component_error : IN STD_LOGIC;
247 config_active_interruption_onNewMatrix : IN STD_LOGIC;
248 config_active_interruption_onError : IN STD_LOGIC;
249 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
250 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
251 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
252 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
253 END COMPONENT;
210 254
211 255 END;
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@@ -1,25 +1,26
1 1 AMBA_Peripherals.vhd
2 2 apb_lfr_time_managment/lpp_lfr_time_management.vhd
3 3 apb_lfr_time_managment/apb_lfr_time_management.vhd
4 4 apb_lfr_time_managment/lfr_time_management.vhd
5 5 apb_lfr_time_managment/lpp_counter.vhd
6 6 lpp_lfr/lpp_lfr_pkg.vhd
7 7 lpp_lfr/lpp_lfr.vhd
8 8 lpp_lfr/lpp_lfr_apbreg.vhd
9 9 lpp_lfr/lpp_filter/FILTERcfg.vhd
10 10 lpp_lfr/lpp_filter/lpp_lfr_filter.vhd
11 11 lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd
12 12 lpp_lfr/lpp_waveform/lpp_waveform.vhd
13 13 lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd
14 14 lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd
15 15 lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd
16 16 lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd
17 17 lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
18 18 lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
19 19 lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd
20 lpp_lfr/lpp_matrix_spectral/lpp_lfr_ms.vhd
20 21 AHB_DMA/lpp_dma_pkg.vhd
21 22 AHB_DMA/lpp_dma_send_1word.vhd
22 23 AHB_DMA/lpp_dma_send_16word.vhd
23 24 AHB_DMA/lpp_dma_singleOrBurst.vhd
24 25
25 26
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@@ -1,77 +1,77
1 1 echo "======================================================================================="
2 2 echo "---------------------------------------------------------------------------------------"
3 3 echo " LPP VHDL APB Devices List Updater "
4 4 echo " Copyright (C) 2010 Laboratory of Plasmas Physic. "
5 5 echo "======================================================================================="
6 6 echo '----------------------------------------------------------------------------------------
7 7 This file is a part of the LPP VHDL IP LIBRARY
8 8 Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
9 9
10 10 This program is free software; you can redistribute it and/or modify
11 11 it under the terms of the GNU General Public License as published by
12 12 the Free Software Foundation; either version 3 of the License, or
13 13 (at your option) any later version.
14 14
15 15 This program is distributed in the hope that it will be useful,
16 16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 18 GNU General Public License for more details.
19 19
20 20 You should have received a copy of the GNU General Public License
21 21 along with this program; if not, write to the Free Software
22 22 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 23 ----------------------------------------------------------------------------------------'
24 24 echo
25 25 echo
26 26 echo
27 27
28 28 LPP_PATCHPATH=`pwd -L`
29 29
30 30 cd $LPP_PATCHPATH/lib/lpp
31 31
32 32
33 33 VHDFileStart=$LPP_PATCHPATH/APB_DEVICES/VHDListSTART
34 34 VHDFileEnd=$LPP_PATCHPATH/APB_DEVICES/VHDListEND
35 35
36 36 CFileStart=$LPP_PATCHPATH/APB_DEVICES/CListSTART
37 37 CFileEnd=$LPP_PATCHPATH/APB_DEVICES/CListEND
38 38
39 39 ListFILE=$LPP_PATCHPATH/APB_DEVICES/apb_devices_list.txt
40 40
41 VHDListFILE=$LPP_PATCHPATH/lib/lpp/lpp_amba/apb_devices_list.vhd
41 VHDListFILE=$LPP_PATCHPATH/lib/VHDLIB/AMBA_Peripherals/apb_devices_list.vhd
42 42 CListFILE=$LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/apb_devices_list.h
43 43
44 44
45 45 cat $VHDFileStart>$VHDListFILE
46 46 cat $CFileStart>$CListFILE
47 47
48 48 grep vendor $ListFILE | sed "s/vendor /constant /" | sed "s/.* /& : amba_vendor_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE
49 49 grep vendor $ListFILE | sed "s/vendor /#define /" | sed "s/.* /& 0x/" >> $CListFILE
50 50
51 51 echo " ">>$VHDListFILE
52 52 echo " ">>$CListFILE
53 53
54 54 grep device $ListFILE | sed "s/device /constant /" | sed "s/.* /& : amba_device_type := 16#/" | sed "s/.*#*/&#;/" >> $VHDListFILE
55 55 grep device $ListFILE | sed "s/device /#define /" | sed "s/.* /& 0x/" >> $CListFILE
56 56
57 57 cat $VHDFileEnd>>$VHDListFILE
58 58 cat $CFileEnd>>$CListFILE
59 59
60 60 sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh vhd $LPP_PATCHPATH/lib/lpp/lpp_amba/
61 61 sh $LPP_PATCHPATH/scripts/GPL_Patcher.sh h $LPP_PATCHPATH/LPP_drivers/libsrc/AMBA/
62 62
63 63 cd $LPP_PATCHPATH
64 64
65 65
66 66
67 67
68 68
69 69
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
Show file before | Show file after | Hide comments
@@ -1,73 +1,73
1 1 echo "======================================================================================="
2 2 echo "---------------------------------------------------------------------------------------"
3 3 echo " LPP's GRLIB GLOBAL PATCHER "
4 4 echo " Copyright (C) 2013 Laboratory of Plasmas Physic. "
5 5 echo "======================================================================================="
6 6 echo '------------------------------------------------------------------------------
7 7 -- This file is a part of the LPP VHDL IP LIBRARY
8 8 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
9 9 --
10 10 -- This program is free software; you can redistribute it and/or modify
11 11 -- it under the terms of the GNU General Public License as published by
12 12 -- the Free Software Foundation; either version 3 of the License, or
13 13 -- (at your option) any later version.
14 14 --
15 15 -- This program is distributed in the hope that it will be useful,
16 16 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
17 17 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 18 -- GNU General Public License for more details.
19 19 --
20 20 -- You should have received a copy of the GNU General Public License
21 21 -- along with this program; if not, write to the Free Software
22 22 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 23 -------------------------------------------------------------------------------'
24 24 echo
25 25 echo
26 26 echo
27 27
28 28
29 29 VHDLIB_LIB_PATH=`pwd -L`
30 30 source $VHDLIB_LIB_PATH/scripts/lpp_bash_functions.sh
31 31 GRLIBPATH=$1
32 32
33 33 if [ -d "$GRLIBPATH" ]; then
34 34 LPP_PATCHPATH=`relpath $GRLIBPATH/lib $VHDLIB_LIB_PATH`
35 35 echo $LPP_PATCHPATH
36 36 if [ -d "$GRLIBPATH/lib" ]; then
37 37 if [ -d "$GRLIBPATH/designs" ]; then
38 38 if [ -d "$GRLIBPATH/boards" ]; then
39 39
40 40 echo "Patch $1/lib/libs.txt..."
41 41 if(grep -q $LPP_PATCHPATH/lib/lpp $1/lib/libs.txt); then
42 42 echo "No need to Patch $1/lib/libs.txt..."
43 43 else
44 echo $LPP_PATCHPATH/lib/lpp >>$1/lib/libs.txt
44 echo $LPP_PATCHPATH/lib/VHDLIB >>$1/lib/libs.txt
45 45 fi
46 46 if(grep -q $LPP_PATCHPATH/lib/staging $1/lib/libs.txt); then
47 47 echo "No need to Patch $1/lib/libs.txt..."
48 48 else
49 49 echo $LPP_PATCHPATH/lib/staging >>$1/lib/libs.txt
50 50 fi
51 51 echo
52 52 echo
53 53 echo
54 54 else
55 55 echo "I can't find GRLIB in $1"
56 56 fi
57 57
58 58 else
59 59 echo "I can't find GRLIB in $1"
60 60 fi
61 61 else
62 62 echo "I can't find GRLIB in $1"
63 63 fi
64 64
65 65 else
66 66 echo "I can't find GRLIB in $1"
67 67 fi
68 68
69 69
70 70
71 71
72 72
73 73
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