##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

MINI-LFR 0.1.38 :...
pellion -
r478:656868b63e61 (MINI-LFR) WFP_MS-0-1-38 JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,714 +1,714
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
180 SIGNAL LFR_rstn : STD_LOGIC;
181
181
182
182
183 SIGNAL rstn_25 : STD_LOGIC;
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
187
187
188 SIGNAL rstn_50 : STD_LOGIC;
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
192
192
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
193 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195
195
196 BEGIN -- beh
196 BEGIN -- beh
197
197
198 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
199 -- CLK
199 -- CLK
200 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
201
201
202 --PROCESS(clk_50)
202 --PROCESS(clk_50)
203 --BEGIN
203 --BEGIN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
204 -- IF clk_50'EVENT AND clk_50 = '1' THEN
205 -- clk_50_s <= NOT clk_50_s;
205 -- clk_50_s <= NOT clk_50_s;
206 -- END IF;
206 -- END IF;
207 --END PROCESS;
207 --END PROCESS;
208
208
209 --PROCESS(clk_50_s)
209 --PROCESS(clk_50_s)
210 --BEGIN
210 --BEGIN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
211 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
212 -- clk_25 <= NOT clk_25;
212 -- clk_25 <= NOT clk_25;
213 -- END IF;
213 -- END IF;
214 --END PROCESS;
214 --END PROCESS;
215
215
216 --PROCESS(clk_49)
216 --PROCESS(clk_49)
217 --BEGIN
217 --BEGIN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
218 -- IF clk_49'EVENT AND clk_49 = '1' THEN
219 -- clk_24 <= NOT clk_24;
219 -- clk_24 <= NOT clk_24;
220 -- END IF;
220 -- END IF;
221 --END PROCESS;
221 --END PROCESS;
222
222
223 --PROCESS(clk_25)
223 --PROCESS(clk_25)
224 --BEGIN
224 --BEGIN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
225 -- IF clk_25'EVENT AND clk_25 = '1' THEN
226 -- rstn_25 <= reset;
226 -- rstn_25 <= reset;
227 -- END IF;
227 -- END IF;
228 --END PROCESS;
228 --END PROCESS;
229
229
230 PROCESS (clk_50, reset)
230 PROCESS (clk_50, reset)
231 BEGIN -- PROCESS
231 BEGIN -- PROCESS
232 IF reset = '0' THEN -- asynchronous reset (active low)
232 IF reset = '0' THEN -- asynchronous reset (active low)
233 clk_50_s <= '0';
233 clk_50_s <= '0';
234 rstn_50 <= '0';
234 rstn_50 <= '0';
235 rstn_50_d1 <= '0';
235 rstn_50_d1 <= '0';
236 rstn_50_d2 <= '0';
236 rstn_50_d2 <= '0';
237 rstn_50_d3 <= '0';
237 rstn_50_d3 <= '0';
238
238
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
239 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
240 clk_50_s <= NOT clk_50_s;
240 clk_50_s <= NOT clk_50_s;
241 rstn_50_d1 <= '1';
241 rstn_50_d1 <= '1';
242 rstn_50_d2 <= rstn_50_d1;
242 rstn_50_d2 <= rstn_50_d1;
243 rstn_50_d3 <= rstn_50_d2;
243 rstn_50_d3 <= rstn_50_d2;
244 rstn_50 <= rstn_50_d3;
244 rstn_50 <= rstn_50_d3;
245 END IF;
245 END IF;
246 END PROCESS;
246 END PROCESS;
247
247
248 PROCESS (clk_50_s, rstn_50)
248 PROCESS (clk_50_s, rstn_50)
249 BEGIN -- PROCESS
249 BEGIN -- PROCESS
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
250 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
251 clk_25 <= '0';
251 clk_25 <= '0';
252 rstn_25 <= '0';
252 rstn_25 <= '0';
253 rstn_25_d1 <= '0';
253 rstn_25_d1 <= '0';
254 rstn_25_d2 <= '0';
254 rstn_25_d2 <= '0';
255 rstn_25_d3 <= '0';
255 rstn_25_d3 <= '0';
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
256 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
257 clk_25 <= NOT clk_25;
257 clk_25 <= NOT clk_25;
258 rstn_25_d1 <= '1';
258 rstn_25_d1 <= '1';
259 rstn_25_d2 <= rstn_25_d1;
259 rstn_25_d2 <= rstn_25_d1;
260 rstn_25_d3 <= rstn_25_d2;
260 rstn_25_d3 <= rstn_25_d2;
261 rstn_25 <= rstn_25_d3;
261 rstn_25 <= rstn_25_d3;
262 END IF;
262 END IF;
263 END PROCESS;
263 END PROCESS;
264
264
265 PROCESS (clk_49, reset)
265 PROCESS (clk_49, reset)
266 BEGIN -- PROCESS
266 BEGIN -- PROCESS
267 IF reset = '0' THEN -- asynchronous reset (active low)
267 IF reset = '0' THEN -- asynchronous reset (active low)
268 clk_24 <= '0';
268 clk_24 <= '0';
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
269 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
270 clk_24 <= NOT clk_24;
270 clk_24 <= NOT clk_24;
271 END IF;
271 END IF;
272 END PROCESS;
272 END PROCESS;
273
273
274 -----------------------------------------------------------------------------
274 -----------------------------------------------------------------------------
275
275
276 PROCESS (clk_25, rstn_25)
276 PROCESS (clk_25, rstn_25)
277 BEGIN -- PROCESS
277 BEGIN -- PROCESS
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
278 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
279 LED0 <= '0';
279 LED0 <= '0';
280 LED1 <= '0';
280 LED1 <= '0';
281 LED2 <= '0';
281 LED2 <= '0';
282 --IO1 <= '0';
282 --IO1 <= '0';
283 --IO2 <= '1';
283 --IO2 <= '1';
284 --IO3 <= '0';
284 --IO3 <= '0';
285 --IO4 <= '0';
285 --IO4 <= '0';
286 --IO5 <= '0';
286 --IO5 <= '0';
287 --IO6 <= '0';
287 --IO6 <= '0';
288 --IO7 <= '0';
288 --IO7 <= '0';
289 --IO8 <= '0';
289 --IO8 <= '0';
290 --IO9 <= '0';
290 --IO9 <= '0';
291 --IO10 <= '0';
291 --IO10 <= '0';
292 --IO11 <= '0';
292 --IO11 <= '0';
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
293 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
294 LED0 <= '0';
294 LED0 <= '0';
295 LED1 <= '1';
295 LED1 <= '1';
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
296 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
297 --IO1 <= '1';
297 --IO1 <= '1';
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
298 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
299 --IO3 <= ADC_SDO(0);
299 --IO3 <= ADC_SDO(0);
300 --IO4 <= ADC_SDO(1);
300 --IO4 <= ADC_SDO(1);
301 --IO5 <= ADC_SDO(2);
301 --IO5 <= ADC_SDO(2);
302 --IO6 <= ADC_SDO(3);
302 --IO6 <= ADC_SDO(3);
303 --IO7 <= ADC_SDO(4);
303 --IO7 <= ADC_SDO(4);
304 --IO8 <= ADC_SDO(5);
304 --IO8 <= ADC_SDO(5);
305 --IO9 <= ADC_SDO(6);
305 --IO9 <= ADC_SDO(6);
306 --IO10 <= ADC_SDO(7);
306 --IO10 <= ADC_SDO(7);
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
307 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
308 END IF;
308 END IF;
309 END PROCESS;
309 END PROCESS;
310
310
311 PROCESS (clk_24, rstn_25)
311 PROCESS (clk_24, rstn_25)
312 BEGIN -- PROCESS
312 BEGIN -- PROCESS
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
313 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
314 I00_s <= '0';
314 I00_s <= '0';
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
315 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
316 I00_s <= NOT I00_s;
316 I00_s <= NOT I00_s;
317 END IF;
317 END IF;
318 END PROCESS;
318 END PROCESS;
319 -- IO0 <= I00_s;
319 -- IO0 <= I00_s;
320
320
321 --UARTs
321 --UARTs
322 nCTS1 <= '1';
322 nCTS1 <= '1';
323 nCTS2 <= '1';
323 nCTS2 <= '1';
324 nDCD2 <= '1';
324 nDCD2 <= '1';
325
325
326 --EXT CONNECTOR
326 --EXT CONNECTOR
327
327
328 --SPACE WIRE
328 --SPACE WIRE
329
329
330 leon3_soc_1 : leon3_soc
330 leon3_soc_1 : leon3_soc
331 GENERIC MAP (
331 GENERIC MAP (
332 fabtech => apa3e,
332 fabtech => apa3e,
333 memtech => apa3e,
333 memtech => apa3e,
334 padtech => inferred,
334 padtech => inferred,
335 clktech => inferred,
335 clktech => inferred,
336 disas => 0,
336 disas => 0,
337 dbguart => 0,
337 dbguart => 0,
338 pclow => 2,
338 pclow => 2,
339 clk_freq => 25000,
339 clk_freq => 25000,
340 NB_CPU => 1,
340 NB_CPU => 1,
341 ENABLE_FPU => 1,
341 ENABLE_FPU => 1,
342 FPU_NETLIST => 0,
342 FPU_NETLIST => 0,
343 ENABLE_DSU => 1,
343 ENABLE_DSU => 1,
344 ENABLE_AHB_UART => 1,
344 ENABLE_AHB_UART => 1,
345 ENABLE_APB_UART => 1,
345 ENABLE_APB_UART => 1,
346 ENABLE_IRQMP => 1,
346 ENABLE_IRQMP => 1,
347 ENABLE_GPT => 1,
347 ENABLE_GPT => 1,
348 NB_AHB_MASTER => NB_AHB_MASTER,
348 NB_AHB_MASTER => NB_AHB_MASTER,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
349 NB_AHB_SLAVE => NB_AHB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
350 NB_APB_SLAVE => NB_APB_SLAVE,
351 ADDRESS_SIZE => 20)
351 ADDRESS_SIZE => 20)
352 PORT MAP (
352 PORT MAP (
353 clk => clk_25,
353 clk => clk_25,
354 reset => rstn_25,
354 reset => rstn_25,
355 errorn => errorn,
355 errorn => errorn,
356 ahbrxd => TXD1,
356 ahbrxd => TXD1,
357 ahbtxd => RXD1,
357 ahbtxd => RXD1,
358 urxd1 => TXD2,
358 urxd1 => TXD2,
359 utxd1 => RXD2,
359 utxd1 => RXD2,
360 address => SRAM_A,
360 address => SRAM_A,
361 data => SRAM_DQ,
361 data => SRAM_DQ,
362 nSRAM_BE0 => SRAM_nBE(0),
362 nSRAM_BE0 => SRAM_nBE(0),
363 nSRAM_BE1 => SRAM_nBE(1),
363 nSRAM_BE1 => SRAM_nBE(1),
364 nSRAM_BE2 => SRAM_nBE(2),
364 nSRAM_BE2 => SRAM_nBE(2),
365 nSRAM_BE3 => SRAM_nBE(3),
365 nSRAM_BE3 => SRAM_nBE(3),
366 nSRAM_WE => SRAM_nWE,
366 nSRAM_WE => SRAM_nWE,
367 nSRAM_CE => SRAM_CE,
367 nSRAM_CE => SRAM_CE,
368 nSRAM_OE => SRAM_nOE,
368 nSRAM_OE => SRAM_nOE,
369
369
370 apbi_ext => apbi_ext,
370 apbi_ext => apbi_ext,
371 apbo_ext => apbo_ext,
371 apbo_ext => apbo_ext,
372 ahbi_s_ext => ahbi_s_ext,
372 ahbi_s_ext => ahbi_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
373 ahbo_s_ext => ahbo_s_ext,
374 ahbi_m_ext => ahbi_m_ext,
374 ahbi_m_ext => ahbi_m_ext,
375 ahbo_m_ext => ahbo_m_ext);
375 ahbo_m_ext => ahbo_m_ext);
376
376
377 -------------------------------------------------------------------------------
377 -------------------------------------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
378 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
379 -------------------------------------------------------------------------------
379 -------------------------------------------------------------------------------
380 apb_lfr_time_management_1 : apb_lfr_time_management
380 apb_lfr_time_management_1 : apb_lfr_time_management
381 GENERIC MAP (
381 GENERIC MAP (
382 pindex => 6,
382 pindex => 6,
383 paddr => 6,
383 paddr => 6,
384 pmask => 16#fff#,
384 pmask => 16#fff#,
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
385 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
386 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
387 PORT MAP (
387 PORT MAP (
388 clk25MHz => clk_25,
388 clk25MHz => clk_25,
389 clk24_576MHz => clk_24, -- 49.152MHz/2
389 clk24_576MHz => clk_24, -- 49.152MHz/2
390 resetn => rstn_25,
390 resetn => rstn_25,
391 grspw_tick => swno.tickout,
391 grspw_tick => swno.tickout,
392 apbi => apbi_ext,
392 apbi => apbi_ext,
393 apbo => apbo_ext(6),
393 apbo => apbo_ext(6),
394 coarse_time => coarse_time,
394 coarse_time => coarse_time,
395 fine_time => fine_time,
395 fine_time => fine_time,
396 LFR_soft_rstn => LFR_soft_rstn
396 LFR_soft_rstn => LFR_soft_rstn
397 );
397 );
398
398
399 -----------------------------------------------------------------------
399 -----------------------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
400 --- SpaceWire --------------------------------------------------------
401 -----------------------------------------------------------------------
401 -----------------------------------------------------------------------
402
402
403 SPW_EN <= '1';
403 SPW_EN <= '1';
404
404
405 spw_clk <= clk_50_s;
405 spw_clk <= clk_50_s;
406 spw_rxtxclk <= spw_clk;
406 spw_rxtxclk <= spw_clk;
407 spw_rxclkn <= NOT spw_rxtxclk;
407 spw_rxclkn <= NOT spw_rxtxclk;
408
408
409 -- PADS for SPW1
409 -- PADS for SPW1
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
410 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
411 PORT MAP (SPW_NOM_DIN, dtmp(0));
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
412 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
413 PORT MAP (SPW_NOM_SIN, stmp(0));
413 PORT MAP (SPW_NOM_SIN, stmp(0));
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
414 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
415 PORT MAP (SPW_NOM_DOUT, swno.d(0));
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
416 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
417 PORT MAP (SPW_NOM_SOUT, swno.s(0));
418 -- PADS FOR SPW2
418 -- PADS FOR SPW2
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
419 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
420 PORT MAP (SPW_RED_SIN, dtmp(1));
420 PORT MAP (SPW_RED_SIN, dtmp(1));
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
421 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
422 PORT MAP (SPW_RED_DIN, stmp(1));
422 PORT MAP (SPW_RED_DIN, stmp(1));
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
423 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
424 PORT MAP (SPW_RED_DOUT, swno.d(1));
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
425 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
426 PORT MAP (SPW_RED_SOUT, swno.s(1));
427
427
428 -- GRSPW PHY
428 -- GRSPW PHY
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
429 --spw1_input: if CFG_SPW_GRSPW = 1 generate
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
430 spw_inputloop : FOR j IN 0 TO 1 GENERATE
431 spw_phy0 : grspw_phy
431 spw_phy0 : grspw_phy
432 GENERIC MAP(
432 GENERIC MAP(
433 tech => apa3e,
433 tech => apa3e,
434 rxclkbuftype => 1,
434 rxclkbuftype => 1,
435 scantest => 0)
435 scantest => 0)
436 PORT MAP(
436 PORT MAP(
437 rxrst => swno.rxrst,
437 rxrst => swno.rxrst,
438 di => dtmp(j),
438 di => dtmp(j),
439 si => stmp(j),
439 si => stmp(j),
440 rxclko => spw_rxclk(j),
440 rxclko => spw_rxclk(j),
441 do => swni.d(j),
441 do => swni.d(j),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
442 ndo => swni.nd(j*5+4 DOWNTO j*5),
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
443 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
444 END GENERATE spw_inputloop;
444 END GENERATE spw_inputloop;
445
445
446 swni.rmapnodeaddr <= (OTHERS => '0');
446 swni.rmapnodeaddr <= (OTHERS => '0');
447
447
448 -- SPW core
448 -- SPW core
449 sw0 : grspwm GENERIC MAP(
449 sw0 : grspwm GENERIC MAP(
450 tech => apa3e,
450 tech => apa3e,
451 hindex => 1,
451 hindex => 1,
452 pindex => 5,
452 pindex => 5,
453 paddr => 5,
453 paddr => 5,
454 pirq => 11,
454 pirq => 11,
455 sysfreq => 25000, -- CPU_FREQ
455 sysfreq => 25000, -- CPU_FREQ
456 rmap => 1,
456 rmap => 1,
457 rmapcrc => 1,
457 rmapcrc => 1,
458 fifosize1 => 16,
458 fifosize1 => 16,
459 fifosize2 => 16,
459 fifosize2 => 16,
460 rxclkbuftype => 1,
460 rxclkbuftype => 1,
461 rxunaligned => 0,
461 rxunaligned => 0,
462 rmapbufs => 4,
462 rmapbufs => 4,
463 ft => 0,
463 ft => 0,
464 netlist => 0,
464 netlist => 0,
465 ports => 2,
465 ports => 2,
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
466 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
467 memtech => apa3e,
467 memtech => apa3e,
468 destkey => 2,
468 destkey => 2,
469 spwcore => 1
469 spwcore => 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
470 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
471 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
472 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
473 )
473 )
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
474 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
475 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
476 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
477 swni, swno);
477 swni, swno);
478
478
479 swni.tickin <= '0';
479 swni.tickin <= '0';
480 swni.rmapen <= '1';
480 swni.rmapen <= '1';
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
481 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
482 swni.tickinraw <= '0';
482 swni.tickinraw <= '0';
483 swni.timein <= (OTHERS => '0');
483 swni.timein <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
484 swni.dcrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
485 swni.timerrstval <= (OTHERS => '0');
486
486
487 -------------------------------------------------------------------------------
487 -------------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
488 -- LFR ------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
489 -------------------------------------------------------------------------------
490
490
491
491
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
492 LFR_rstn <= LFR_soft_rstn AND rstn_25;
493 --LFR_rstn <= rstn_25;
493 --LFR_rstn <= rstn_25;
494
494
495 lpp_lfr_1 : lpp_lfr
495 lpp_lfr_1 : lpp_lfr
496 GENERIC MAP (
496 GENERIC MAP (
497 Mem_use => use_RAM,
497 Mem_use => use_RAM,
498 nb_data_by_buffer_size => 32,
498 nb_data_by_buffer_size => 32,
499 nb_snapshot_param_size => 32,
499 nb_snapshot_param_size => 32,
500 delta_vector_size => 32,
500 delta_vector_size => 32,
501 delta_vector_size_f0_2 => 7, -- log2(96)
501 delta_vector_size_f0_2 => 7, -- log2(96)
502 pindex => 15,
502 pindex => 15,
503 paddr => 15,
503 paddr => 15,
504 pmask => 16#fff#,
504 pmask => 16#fff#,
505 pirq_ms => 6,
505 pirq_ms => 6,
506 pirq_wfp => 14,
506 pirq_wfp => 14,
507 hindex => 2,
507 hindex => 2,
508 top_lfr_version => X"000125") -- aa.bb.cc version
508 top_lfr_version => X"000126") -- aa.bb.cc version
509 PORT MAP (
509 PORT MAP (
510 clk => clk_25,
510 clk => clk_25,
511 rstn => LFR_rstn,
511 rstn => LFR_rstn,
512 sample_B => sample_s(2 DOWNTO 0),
512 sample_B => sample_s(2 DOWNTO 0),
513 sample_E => sample_s(7 DOWNTO 3),
513 sample_E => sample_s(7 DOWNTO 3),
514 sample_val => sample_val,
514 sample_val => sample_val,
515 apbi => apbi_ext,
515 apbi => apbi_ext,
516 apbo => apbo_ext(15),
516 apbo => apbo_ext(15),
517 ahbi => ahbi_m_ext,
517 ahbi => ahbi_m_ext,
518 ahbo => ahbo_m_ext(2),
518 ahbo => ahbo_m_ext(2),
519 coarse_time => coarse_time,
519 coarse_time => coarse_time,
520 fine_time => fine_time,
520 fine_time => fine_time,
521 data_shaping_BW => bias_fail_sw_sig,
521 data_shaping_BW => bias_fail_sw_sig,
522 debug_vector => lfr_debug_vector,
522 debug_vector => lfr_debug_vector,
523 debug_vector_ms => lfr_debug_vector_ms
523 debug_vector_ms => lfr_debug_vector_ms
524 );
524 );
525
525
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
526 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
527 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
528 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
529 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
530 IO0 <= rstn_25;
530 IO0 <= rstn_25;
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
531 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
532 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
533 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
534 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
535 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
536 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
537 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
538
538
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
539 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
540 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
541 END GENERATE all_sample;
541 END GENERATE all_sample;
542
542
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
543 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
544 GENERIC MAP(
544 GENERIC MAP(
545 ChannelCount => 8,
545 ChannelCount => 8,
546 SampleNbBits => 14,
546 SampleNbBits => 14,
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
547 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
548 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
549 PORT MAP (
549 PORT MAP (
550 -- CONV
550 -- CONV
551 cnv_clk => clk_24,
551 cnv_clk => clk_24,
552 cnv_rstn => rstn_25,
552 cnv_rstn => rstn_25,
553 cnv => ADC_nCS_sig,
553 cnv => ADC_nCS_sig,
554 -- DATA
554 -- DATA
555 clk => clk_25,
555 clk => clk_25,
556 rstn => rstn_25,
556 rstn => rstn_25,
557 sck => ADC_CLK_sig,
557 sck => ADC_CLK_sig,
558 sdo => ADC_SDO_sig,
558 sdo => ADC_SDO_sig,
559 -- SAMPLE
559 -- SAMPLE
560 sample => sample,
560 sample => sample,
561 sample_val => sample_val);
561 sample_val => sample_val);
562
562
563 --IO10 <= ADC_SDO_sig(5);
563 --IO10 <= ADC_SDO_sig(5);
564 --IO9 <= ADC_SDO_sig(4);
564 --IO9 <= ADC_SDO_sig(4);
565 --IO8 <= ADC_SDO_sig(3);
565 --IO8 <= ADC_SDO_sig(3);
566
566
567 ADC_nCS <= ADC_nCS_sig;
567 ADC_nCS <= ADC_nCS_sig;
568 ADC_CLK <= ADC_CLK_sig;
568 ADC_CLK <= ADC_CLK_sig;
569 ADC_SDO_sig <= ADC_SDO;
569 ADC_SDO_sig <= ADC_SDO;
570
570
571 ----------------------------------------------------------------------
571 ----------------------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
572 --- GPIO -----------------------------------------------------------
573 ----------------------------------------------------------------------
573 ----------------------------------------------------------------------
574
574
575 grgpio0 : grgpio
575 grgpio0 : grgpio
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
576 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
577 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
578
578
579 gpioi.sig_en <= (OTHERS => '0');
579 gpioi.sig_en <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
580 gpioi.sig_in <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
581 gpioi.din <= (OTHERS => '0');
582 --pio_pad_0 : iopad
582 --pio_pad_0 : iopad
583 -- GENERIC MAP (tech => CFG_PADTECH)
583 -- GENERIC MAP (tech => CFG_PADTECH)
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
584 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
585 --pio_pad_1 : iopad
585 --pio_pad_1 : iopad
586 -- GENERIC MAP (tech => CFG_PADTECH)
586 -- GENERIC MAP (tech => CFG_PADTECH)
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
587 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
588 --pio_pad_2 : iopad
588 --pio_pad_2 : iopad
589 -- GENERIC MAP (tech => CFG_PADTECH)
589 -- GENERIC MAP (tech => CFG_PADTECH)
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
590 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
591 --pio_pad_3 : iopad
591 --pio_pad_3 : iopad
592 -- GENERIC MAP (tech => CFG_PADTECH)
592 -- GENERIC MAP (tech => CFG_PADTECH)
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
593 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
594 --pio_pad_4 : iopad
594 --pio_pad_4 : iopad
595 -- GENERIC MAP (tech => CFG_PADTECH)
595 -- GENERIC MAP (tech => CFG_PADTECH)
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
596 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
597 --pio_pad_5 : iopad
597 --pio_pad_5 : iopad
598 -- GENERIC MAP (tech => CFG_PADTECH)
598 -- GENERIC MAP (tech => CFG_PADTECH)
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
599 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
600 --pio_pad_6 : iopad
600 --pio_pad_6 : iopad
601 -- GENERIC MAP (tech => CFG_PADTECH)
601 -- GENERIC MAP (tech => CFG_PADTECH)
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
602 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
603 --pio_pad_7 : iopad
603 --pio_pad_7 : iopad
604 -- GENERIC MAP (tech => CFG_PADTECH)
604 -- GENERIC MAP (tech => CFG_PADTECH)
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
605 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
606
606
607 PROCESS (clk_25, rstn_25)
607 PROCESS (clk_25, rstn_25)
608 BEGIN -- PROCESS
608 BEGIN -- PROCESS
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
609 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
610 -- --IO0 <= '0';
610 -- --IO0 <= '0';
611 -- IO1 <= '0';
611 -- IO1 <= '0';
612 -- IO2 <= '0';
612 -- IO2 <= '0';
613 -- IO3 <= '0';
613 -- IO3 <= '0';
614 -- IO4 <= '0';
614 -- IO4 <= '0';
615 -- IO5 <= '0';
615 -- IO5 <= '0';
616 -- IO6 <= '0';
616 -- IO6 <= '0';
617 -- IO7 <= '0';
617 -- IO7 <= '0';
618 IO8 <= '0';
618 IO8 <= '0';
619 IO9 <= '0';
619 IO9 <= '0';
620 IO10 <= '0';
620 IO10 <= '0';
621 IO11 <= '0';
621 IO11 <= '0';
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
622 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
623 CASE gpioo.dout(2 DOWNTO 0) IS
623 CASE gpioo.dout(2 DOWNTO 0) IS
624 WHEN "011" =>
624 WHEN "011" =>
625 -- --IO0 <= observation_reg(0 );
625 -- --IO0 <= observation_reg(0 );
626 -- IO1 <= observation_reg(1 );
626 -- IO1 <= observation_reg(1 );
627 -- IO2 <= observation_reg(2 );
627 -- IO2 <= observation_reg(2 );
628 -- IO3 <= observation_reg(3 );
628 -- IO3 <= observation_reg(3 );
629 -- IO4 <= observation_reg(4 );
629 -- IO4 <= observation_reg(4 );
630 -- IO5 <= observation_reg(5 );
630 -- IO5 <= observation_reg(5 );
631 -- IO6 <= observation_reg(6 );
631 -- IO6 <= observation_reg(6 );
632 -- IO7 <= observation_reg(7 );
632 -- IO7 <= observation_reg(7 );
633 IO8 <= observation_reg(8);
633 IO8 <= observation_reg(8);
634 IO9 <= observation_reg(9);
634 IO9 <= observation_reg(9);
635 IO10 <= observation_reg(10);
635 IO10 <= observation_reg(10);
636 IO11 <= observation_reg(11);
636 IO11 <= observation_reg(11);
637 WHEN "001" =>
637 WHEN "001" =>
638 -- --IO0 <= observation_reg(0 + 12);
638 -- --IO0 <= observation_reg(0 + 12);
639 -- IO1 <= observation_reg(1 + 12);
639 -- IO1 <= observation_reg(1 + 12);
640 -- IO2 <= observation_reg(2 + 12);
640 -- IO2 <= observation_reg(2 + 12);
641 -- IO3 <= observation_reg(3 + 12);
641 -- IO3 <= observation_reg(3 + 12);
642 -- IO4 <= observation_reg(4 + 12);
642 -- IO4 <= observation_reg(4 + 12);
643 -- IO5 <= observation_reg(5 + 12);
643 -- IO5 <= observation_reg(5 + 12);
644 -- IO6 <= observation_reg(6 + 12);
644 -- IO6 <= observation_reg(6 + 12);
645 -- IO7 <= observation_reg(7 + 12);
645 -- IO7 <= observation_reg(7 + 12);
646 IO8 <= observation_reg(8 + 12);
646 IO8 <= observation_reg(8 + 12);
647 IO9 <= observation_reg(9 + 12);
647 IO9 <= observation_reg(9 + 12);
648 IO10 <= observation_reg(10 + 12);
648 IO10 <= observation_reg(10 + 12);
649 IO11 <= observation_reg(11 + 12);
649 IO11 <= observation_reg(11 + 12);
650 WHEN "010" =>
650 WHEN "010" =>
651 -- --IO0 <= observation_reg(0 + 12 + 12);
651 -- --IO0 <= observation_reg(0 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
652 -- IO1 <= observation_reg(1 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
653 -- IO2 <= observation_reg(2 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
654 -- IO3 <= observation_reg(3 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
655 -- IO4 <= observation_reg(4 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
656 -- IO5 <= observation_reg(5 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
657 -- IO6 <= observation_reg(6 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
658 -- IO7 <= observation_reg(7 + 12 + 12);
659 IO8 <= '0';
659 IO8 <= '0';
660 IO9 <= '0';
660 IO9 <= '0';
661 IO10 <= '0';
661 IO10 <= '0';
662 IO11 <= '0';
662 IO11 <= '0';
663 WHEN "000" =>
663 WHEN "000" =>
664 -- --IO0 <= observation_vector_0(0 );
664 -- --IO0 <= observation_vector_0(0 );
665 -- IO1 <= observation_vector_0(1 );
665 -- IO1 <= observation_vector_0(1 );
666 -- IO2 <= observation_vector_0(2 );
666 -- IO2 <= observation_vector_0(2 );
667 -- IO3 <= observation_vector_0(3 );
667 -- IO3 <= observation_vector_0(3 );
668 -- IO4 <= observation_vector_0(4 );
668 -- IO4 <= observation_vector_0(4 );
669 -- IO5 <= observation_vector_0(5 );
669 -- IO5 <= observation_vector_0(5 );
670 -- IO6 <= observation_vector_0(6 );
670 -- IO6 <= observation_vector_0(6 );
671 -- IO7 <= observation_vector_0(7 );
671 -- IO7 <= observation_vector_0(7 );
672 IO8 <= observation_vector_0(8);
672 IO8 <= observation_vector_0(8);
673 IO9 <= observation_vector_0(9);
673 IO9 <= observation_vector_0(9);
674 IO10 <= observation_vector_0(10);
674 IO10 <= observation_vector_0(10);
675 IO11 <= observation_vector_0(11);
675 IO11 <= observation_vector_0(11);
676 WHEN "100" =>
676 WHEN "100" =>
677 -- --IO0 <= observation_vector_1(0 );
677 -- --IO0 <= observation_vector_1(0 );
678 -- IO1 <= observation_vector_1(1 );
678 -- IO1 <= observation_vector_1(1 );
679 -- IO2 <= observation_vector_1(2 );
679 -- IO2 <= observation_vector_1(2 );
680 -- IO3 <= observation_vector_1(3 );
680 -- IO3 <= observation_vector_1(3 );
681 -- IO4 <= observation_vector_1(4 );
681 -- IO4 <= observation_vector_1(4 );
682 -- IO5 <= observation_vector_1(5 );
682 -- IO5 <= observation_vector_1(5 );
683 -- IO6 <= observation_vector_1(6 );
683 -- IO6 <= observation_vector_1(6 );
684 -- IO7 <= observation_vector_1(7 );
684 -- IO7 <= observation_vector_1(7 );
685 IO8 <= observation_vector_1(8);
685 IO8 <= observation_vector_1(8);
686 IO9 <= observation_vector_1(9);
686 IO9 <= observation_vector_1(9);
687 IO10 <= observation_vector_1(10);
687 IO10 <= observation_vector_1(10);
688 IO11 <= observation_vector_1(11);
688 IO11 <= observation_vector_1(11);
689 WHEN OTHERS => NULL;
689 WHEN OTHERS => NULL;
690 END CASE;
690 END CASE;
691
691
692 END IF;
692 END IF;
693 END PROCESS;
693 END PROCESS;
694 -----------------------------------------------------------------------------
694 -----------------------------------------------------------------------------
695 --
695 --
696 -----------------------------------------------------------------------------
696 -----------------------------------------------------------------------------
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
697 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
698 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
699 apbo_ext(I) <= apb_none;
699 apbo_ext(I) <= apb_none;
700 END GENERATE apbo_ext_not_used;
700 END GENERATE apbo_ext_not_used;
701 END GENERATE all_apbo_ext;
701 END GENERATE all_apbo_ext;
702
702
703
703
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
704 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
705 ahbo_s_ext(I) <= ahbs_none;
705 ahbo_s_ext(I) <= ahbs_none;
706 END GENERATE all_ahbo_ext;
706 END GENERATE all_ahbo_ext;
707
707
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
708 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
709 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
710 ahbo_m_ext(I) <= ahbm_none;
710 ahbo_m_ext(I) <= ahbm_none;
711 END GENERATE ahbo_m_ext_not_used;
711 END GENERATE ahbo_m_ext_not_used;
712 END GENERATE all_ahbo_m_ext;
712 END GENERATE all_ahbo_m_ext;
713
713
714 END beh;
714 END beh;
Show file before | Show file after | Hide comments
@@ -1,297 +1,296
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
22
22
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT MINI_LFR_top
29 COMPONENT MINI_LFR_top
30 PORT (
30 PORT (
31 clk_50 : IN STD_LOGIC;
31 clk_50 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SRAM_nWE : OUT STD_LOGIC;
73 SRAM_nWE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 END COMPONENT;
79 END COMPONENT;
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL clk_50 : STD_LOGIC := '0';
82 SIGNAL clk_50 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
84 SIGNAL reset : STD_LOGIC;
84 SIGNAL reset : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 SIGNAL SRAM_nWE : STD_LOGIC;
124 SIGNAL SRAM_nWE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131
131
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135
135
136
136
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138
139 SIGNAL data_message : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
140 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
141
140
142 BEGIN
141 BEGIN
143
142
144 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
145 -- TB
144 -- TB
146 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
147 PROCESS
146 PROCESS
148 CONSTANT txp : TIME := 320 ns;
147 CONSTANT txp : TIME := 320 ns;
149 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 BEGIN -- PROCESS
149 BEGIN -- PROCESS
151 TXD1 <= '1';
150 TXD1 <= '1';
152 reset <= '0';
151 reset <= '0';
153 WAIT FOR 500 ns;
152 WAIT FOR 500 ns;
154 reset <= '1';
153 reset <= '1';
155 WAIT FOR 10000 ns;
154 WAIT FOR 10000 ns;
156 message_simu <= "0 - UART init ";
155 message_simu <= "0 - UART init ";
157 UART_INIT(TXD1,txp);
156 UART_INIT(TXD1,txp);
158
157
159 message_simu <= "1 - UART test ";
158 message_simu <= "1 - UART test ";
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
162 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
163 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
164 data_read <= data_read_v;
163 data_read <= data_read_v;
165 data_message <= "GPIO_data_write";
164 data_message <= "GPIO_data_write";
166
165
167 -- UNSET the LFR reset
166 -- UNSET the LFR reset
168 message_simu <= "2 - LFR UNRESET";
167 message_simu <= "2 - LFR UNRESET";
169 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
171 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
172 --
171 --
173 message_simu <= "3 - LFR CONFIG ";
172 message_simu <= "3 - LFR CONFIG ";
174 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
175 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
176 X"40000000",
175 X"40000000",
177 X"40001000",
176 X"40001000",
178 X"40002000",
177 X"40002000",
179 X"40003000",
178 X"40003000",
180 X"40004000",
179 X"40004000",
181 X"40005000");
180 X"40005000");
182 message_simu <= "4 - GO GO GO !!";
181 message_simu <= "4 - GO GO GO !!";
183 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
182 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
184
183
185 READ_STATUS: LOOP
184 READ_STATUS: LOOP
186 WAIT FOR 2 ms;
185 WAIT FOR 2 ms;
187 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
186 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
188 data_read <= data_read_v;
187 data_read <= data_read_v;
189 data_message <= "READ_NEW_STATUS";
188 data_message <= "READ_NEW_STATUS";
190 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
189 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
191 END LOOP READ_STATUS;
190 END LOOP READ_STATUS;
192
191
193 WAIT;
192 WAIT;
194 END PROCESS;
193 END PROCESS;
195
194
196 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
197 -- CLOCK
196 -- CLOCK
198 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
199 clk_50 <= NOT clk_50 AFTER 5 ns;
198 clk_50 <= NOT clk_50 AFTER 5 ns;
200 clk_49 <= NOT clk_49 AFTER 10172 ps;
199 clk_49 <= NOT clk_49 AFTER 10172 ps;
201
200
202 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
203 -- DON'T CARE
202 -- DON'T CARE
204 -----------------------------------------------------------------------------
203 -----------------------------------------------------------------------------
205 BP0 <= '0';
204 BP0 <= '0';
206 BP1 <= '0';
205 BP1 <= '0';
207 nRTS1 <= '0' ;
206 nRTS1 <= '0' ;
208
207
209 TXD2 <= '1';
208 TXD2 <= '1';
210 nRTS2 <= '1';
209 nRTS2 <= '1';
211 nDTR2 <= '1';
210 nDTR2 <= '1';
212
211
213 SPW_NOM_DIN <= '1';
212 SPW_NOM_DIN <= '1';
214 SPW_NOM_SIN <= '1';
213 SPW_NOM_SIN <= '1';
215 SPW_RED_DIN <= '1';
214 SPW_RED_DIN <= '1';
216 SPW_RED_SIN <= '1';
215 SPW_RED_SIN <= '1';
217
216
218 ADC_SDO <= x"AA";
217 ADC_SDO <= x"AA";
219
218
220 SRAM_DQ <= (OTHERS => 'Z');
219 SRAM_DQ <= (OTHERS => 'Z');
221 --IO0 <= 'Z';
220 --IO0 <= 'Z';
222 --IO1 <= 'Z';
221 --IO1 <= 'Z';
223 --IO2 <= 'Z';
222 --IO2 <= 'Z';
224 --IO3 <= 'Z';
223 --IO3 <= 'Z';
225 --IO4 <= 'Z';
224 --IO4 <= 'Z';
226 --IO5 <= 'Z';
225 --IO5 <= 'Z';
227 --IO6 <= 'Z';
226 --IO6 <= 'Z';
228 --IO7 <= 'Z';
227 --IO7 <= 'Z';
229 --IO8 <= 'Z';
228 --IO8 <= 'Z';
230 --IO9 <= 'Z';
229 --IO9 <= 'Z';
231 --IO10 <= 'Z';
230 --IO10 <= 'Z';
232 --IO11 <= 'Z';
231 --IO11 <= 'Z';
233
232
234 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
235 -- DUT
234 -- DUT
236 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
237 MINI_LFR_top_1: MINI_LFR_top
236 MINI_LFR_top_1: MINI_LFR_top
238 PORT MAP (
237 PORT MAP (
239 clk_50 => clk_50,
238 clk_50 => clk_50,
240 clk_49 => clk_49,
239 clk_49 => clk_49,
241 reset => reset,
240 reset => reset,
242
241
243 BP0 => BP0,
242 BP0 => BP0,
244 BP1 => BP1,
243 BP1 => BP1,
245
244
246 LED0 => LED0,
245 LED0 => LED0,
247 LED1 => LED1,
246 LED1 => LED1,
248 LED2 => LED2,
247 LED2 => LED2,
249
248
250 TXD1 => TXD1,
249 TXD1 => TXD1,
251 RXD1 => RXD1,
250 RXD1 => RXD1,
252 nCTS1 => nCTS1,
251 nCTS1 => nCTS1,
253 nRTS1 => nRTS1,
252 nRTS1 => nRTS1,
254
253
255 TXD2 => TXD2,
254 TXD2 => TXD2,
256 RXD2 => RXD2,
255 RXD2 => RXD2,
257 nCTS2 => nCTS2,
256 nCTS2 => nCTS2,
258 nDTR2 => nDTR2,
257 nDTR2 => nDTR2,
259 nRTS2 => nRTS2,
258 nRTS2 => nRTS2,
260 nDCD2 => nDCD2,
259 nDCD2 => nDCD2,
261
260
262 IO0 => IO0,
261 IO0 => IO0,
263 IO1 => IO1,
262 IO1 => IO1,
264 IO2 => IO2,
263 IO2 => IO2,
265 IO3 => IO3,
264 IO3 => IO3,
266 IO4 => IO4,
265 IO4 => IO4,
267 IO5 => IO5,
266 IO5 => IO5,
268 IO6 => IO6,
267 IO6 => IO6,
269 IO7 => IO7,
268 IO7 => IO7,
270 IO8 => IO8,
269 IO8 => IO8,
271 IO9 => IO9,
270 IO9 => IO9,
272 IO10 => IO10,
271 IO10 => IO10,
273 IO11 => IO11,
272 IO11 => IO11,
274
273
275 SPW_EN => SPW_EN,
274 SPW_EN => SPW_EN,
276 SPW_NOM_DIN => SPW_NOM_DIN,
275 SPW_NOM_DIN => SPW_NOM_DIN,
277 SPW_NOM_SIN => SPW_NOM_SIN,
276 SPW_NOM_SIN => SPW_NOM_SIN,
278 SPW_NOM_DOUT => SPW_NOM_DOUT,
277 SPW_NOM_DOUT => SPW_NOM_DOUT,
279 SPW_NOM_SOUT => SPW_NOM_SOUT,
278 SPW_NOM_SOUT => SPW_NOM_SOUT,
280 SPW_RED_DIN => SPW_RED_DIN,
279 SPW_RED_DIN => SPW_RED_DIN,
281 SPW_RED_SIN => SPW_RED_SIN,
280 SPW_RED_SIN => SPW_RED_SIN,
282 SPW_RED_DOUT => SPW_RED_DOUT,
281 SPW_RED_DOUT => SPW_RED_DOUT,
283 SPW_RED_SOUT => SPW_RED_SOUT,
282 SPW_RED_SOUT => SPW_RED_SOUT,
284
283
285 ADC_nCS => ADC_nCS,
284 ADC_nCS => ADC_nCS,
286 ADC_CLK => ADC_CLK,
285 ADC_CLK => ADC_CLK,
287 ADC_SDO => ADC_SDO,
286 ADC_SDO => ADC_SDO,
288
287
289 SRAM_nWE => SRAM_nWE,
288 SRAM_nWE => SRAM_nWE,
290 SRAM_CE => SRAM_CE,
289 SRAM_CE => SRAM_CE,
291 SRAM_nOE => SRAM_nOE,
290 SRAM_nOE => SRAM_nOE,
292 SRAM_nBE => SRAM_nBE,
291 SRAM_nBE => SRAM_nBE,
293 SRAM_A => SRAM_A,
292 SRAM_A => SRAM_A,
294 SRAM_DQ => SRAM_DQ);
293 SRAM_DQ => SRAM_DQ);
295
294
296
295
297 END;
296 END;
Show file before | Show file after | Hide comments
@@ -1,24 +1,46
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/message_simu
3 add wave -noupdate /testbench/message_simu
4 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
4 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -expand -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
5 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
5 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
6 add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing
6 add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing
7 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full
8 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen
9 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_write_error
10 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data
11 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state
12 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data2
13 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data
14 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full_s
15 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s
16 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty
17 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full
18 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data
19 add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen
20 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/rdata
21 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/almost_full
22 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/full
23 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/empty
24 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ren
25 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wdata
26 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wen
27 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/run
28 add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ReUse
7 TreeUpdate [SetDefaultTree]
29 TreeUpdate [SetDefaultTree]
8 WaveRestoreCursors {{Cursor 1} {11527482482 ps} 0}
30 WaveRestoreCursors {{Cursor 1} {63830825000 ps} 0} {{Cursor 2} {126327585000 ps} 0} {{Cursor 3} {188824345000 ps} 0}
9 quietly wave cursor active 1
31 quietly wave cursor active 3
10 configure wave -namecolwidth 539
32 configure wave -namecolwidth 510
11 configure wave -valuecolwidth 100
33 configure wave -valuecolwidth 100
12 configure wave -justifyvalue left
34 configure wave -justifyvalue left
13 configure wave -signalnamewidth 0
35 configure wave -signalnamewidth 0
14 configure wave -snapdistance 10
36 configure wave -snapdistance 10
15 configure wave -datasetprefix 0
37 configure wave -datasetprefix 0
16 configure wave -rowmargin 4
38 configure wave -rowmargin 4
17 configure wave -childrowmargin 2
39 configure wave -childrowmargin 2
18 configure wave -gridoffset 0
40 configure wave -gridoffset 0
19 configure wave -gridperiod 1
41 configure wave -gridperiod 1
20 configure wave -griddelta 40
42 configure wave -griddelta 40
21 configure wave -timeline 0
43 configure wave -timeline 0
22 configure wave -timelineunits ns
44 configure wave -timelineunits ns
23 update
45 update
24 WaveRestoreZoom {0 ps} {61313789250 ps}
46 WaveRestoreZoom {0 ps} {243397377300 ps}
Show file before | Show file after | Hide comments
@@ -1,100 +1,106
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 ENTITY lpp_lfr_ms_reg_head IS
4 ENTITY lpp_lfr_ms_reg_head IS
5
5
6 PORT (
6 PORT (
7 clk : IN STD_LOGIC;
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
9
10 in_wen : IN STD_LOGIC;
10 in_wen : IN STD_LOGIC;
11 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
11 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
12 in_full : IN STD_LOGIC;
12 in_full : IN STD_LOGIC;
13 in_empty : IN STD_LOGIC;
13 in_empty : IN STD_LOGIC;
14
14
15 out_write_error : OUT STD_LOGIC;
15 out_write_error : OUT STD_LOGIC;
16
16
17 out_wen : OUT STD_LOGIC;
17 out_wen : OUT STD_LOGIC;
18 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
18 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
19 out_full : OUT STD_LOGIC
19 out_full : OUT STD_LOGIC
20 );
20 );
21
21
22 END lpp_lfr_ms_reg_head;
22 END lpp_lfr_ms_reg_head;
23
23
24 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
24 ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
25 TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
26 SIGNAL fsm_state : fsm_state_reg_head;
26 SIGNAL fsm_state : fsm_state_reg_head;
27
27
28 SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
28 SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
29 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
29 SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
30 SIGNAL out_wen_s : STD_LOGIC;
30 SIGNAL out_wen_s : STD_LOGIC;
31
32 SIGNAL in_full_s : STD_LOGIC;
31 BEGIN -- Beh
33 BEGIN -- Beh
32
34
33 PROCESS (clk, rstn)
35 PROCESS (clk, rstn)
34 BEGIN
36 BEGIN
35 IF rstn = '0' THEN
37 IF rstn = '0' THEN
36 fsm_state <= REG_EMPTY;
38 fsm_state <= REG_EMPTY;
37 reg_data <= (OTHERS => '0');
39 reg_data <= (OTHERS => '0');
38 reg_data2 <= (OTHERS => '0');
40 reg_data2 <= (OTHERS => '0');
39 out_wen_s <= '1';
41 out_wen_s <= '1';
40 out_write_error <= '0';
42 out_write_error <= '0';
43 in_full_s <= '0';
41 ELSIF clk'event AND clk = '1' THEN
44 ELSIF clk'event AND clk = '1' THEN
45 in_full_s <= in_full;
46
42 out_wen_s <= '1';
47 out_wen_s <= '1';
43 out_write_error <= '0';
48 out_write_error <= '0';
44 CASE fsm_state IS
49 CASE fsm_state IS
45 WHEN REG_EMPTY =>
50 WHEN REG_EMPTY =>
46 reg_data <= in_data;
51 reg_data <= in_data;
47 IF in_wen = '0' AND in_full = '1' THEN
52 IF in_wen = '0' AND in_full_s = '1' THEN
48 fsm_state <= REG_ONE_DATA;
53 fsm_state <= REG_ONE_DATA;
49 END IF;
54 END IF;
50
55
51 WHEN REG_ONE_DATA =>
56 WHEN REG_ONE_DATA =>
52 reg_data2 <= in_data;
57 reg_data2 <= in_data;
53 IF in_wen = '0' AND in_full = '1' THEN
58 IF in_wen = '0' AND in_full_s = '1' THEN
54 fsm_state <= REG_FULL;
59 fsm_state <= REG_FULL;
55 ELSIF in_empty = '1' THEN
60 ELSIF in_empty = '1' THEN
56 out_wen_s <= '0';
61 out_wen_s <= '0';
57 IF in_wen = '0' THEN
62 IF in_wen = '0' THEN
58 reg_data <= in_data;
63 reg_data <= in_data;
59 ELSE
64 ELSE
60 fsm_state <= REG_EMPTY;
65 fsm_state <= REG_EMPTY;
61 END IF;
66 END IF;
62 END IF;
67 END IF;
63
68
64 WHEN REG_FULL =>
69 WHEN REG_FULL =>
65 IF in_empty = '1' THEN
70 IF in_empty = '1' THEN
66 out_wen_s <= '0';
71 out_wen_s <= '0';
67 IF in_wen = '0' THEN
72 IF in_wen = '0' THEN
68 reg_data2 <= in_data;
73 reg_data2 <= in_data;
69 ELSE
74 ELSE
70 fsm_state <= REG_FULL_2;
75 fsm_state <= REG_FULL_2;
71 END IF;
76 END IF;
72 ELSE
77 ELSE
73 IF in_wen = '0' THEN
78 IF in_wen = '0' THEN
74 out_write_error <= '1';
79 out_write_error <= '1';
75 END IF;
80 END IF;
76 END IF;
81 END IF;
77
82
78 WHEN REG_FULL_2 =>
83 WHEN REG_FULL_2 =>
79 out_wen_s <= '0';
84 out_wen_s <= '0';
80 fsm_state <= REG_EMPTY;
85 fsm_state <= REG_EMPTY;
81
86
82 WHEN OTHERS => NULL;
87 WHEN OTHERS => NULL;
83 END CASE;
88 END CASE;
84
89
85 END IF;
90 END IF;
86 END PROCESS;
91 END PROCESS;
87
92
88 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
93 out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s;
89
94
90 out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
95 out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE
91 reg_data WHEN fsm_state = REG_ONE_DATA ELSE
96 reg_data WHEN fsm_state = REG_ONE_DATA ELSE
92 reg_data WHEN fsm_state = REG_FULL_2 ELSE
97 reg_data WHEN fsm_state = REG_FULL_2 ELSE
93 in_data;
98 in_data;
94
99
95 out_wen <= '0' WHEN out_wen_s = '0' ELSE
100 out_wen <= '0' WHEN out_wen_s = '0' ELSE
96 '1' WHEN fsm_state = REG_ONE_DATA ELSE
101 '1' WHEN fsm_state = REG_ONE_DATA ELSE
97 '1' WHEN fsm_state = REG_FULL ELSE
102 '1' WHEN fsm_state = REG_FULL ELSE
103 '1' WHEN in_full_s = '1' ELSE
98 in_wen;
104 in_wen;
99
105
100 END Beh;
106 END Beh;
General Comments 0
You need to be logged in to leave comments. Login now