HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r478:656868b63e61

MINI-LFR 0.1.38 :...

pellion -

r478:656868b63e61 (MINI-LFR) WFP_MS-0-1-38 JC

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r478:656868b63e61

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;  -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
             --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
             --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
             --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
             --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
               --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);  --  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);  --  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);  -- := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL rstn_25    : STD_LOGIC;
               SIGNAL rstn_25_d1 : STD_LOGIC;
               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               SIGNAL rstn_50_d3 : STD_LOGIC;
               SIGNAL lfr_debug_vector    : STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               --PROCESS(clk_50)
               --BEGIN
               --  IF clk_50'EVENT AND clk_50 = '1' THEN
               --    clk_50_s <= NOT clk_50_s;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_50_s)
               --BEGIN
               --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
               --    clk_25 <= NOT clk_25;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_49)
               --BEGIN
               --  IF clk_49'EVENT AND clk_49 = '1' THEN
               --    clk_24 <= NOT clk_24;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_25)
               --BEGIN
               --  IF clk_25'EVENT AND clk_25 = '1' THEN
               --    rstn_25 <= reset;
               --  END IF;
               --END PROCESS;
               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_50_s   <= '0';
                   rstn_50    <= '0';
                   rstn_50_d1 <= '0';
                   rstn_50_d2 <= '0';
                   rstn_50_d3 <= '0';
                 ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s   <= NOT clk_50_s;
                   rstn_50_d1 <= '1';
                   rstn_50_d2 <= rstn_50_d1;
                   rstn_50_d3 <= rstn_50_d2;
                   rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_50_s, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
                   clk_25     <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';
                   rstn_25_d2 <= '0';
                   rstn_25_d3 <= '0';
                 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN  -- rising clock edge
                   clk_25     <= NOT clk_25;
                   rstn_25_d1 <= '1';
                   rstn_25_d2 <= rstn_25_d1;
                   rstn_25_d3 <= rstn_25_d2;
                   rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24 <= '0';
                 ELSIF clk_49'EVENT AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
               --EXT CONNECTOR
               --SPACE WIRE
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE,
                   nSRAM_OE  => SRAM_nOE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex           => 6,
                   paddr            => 6,
                   pmask            => 16#fff#,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz      => clk_25,
                   clk24_576MHz  => clk_24,          -- 49.152MHz/2
                   resetn        => rstn_25,
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                   coarse_time   => coarse_time,
                   fine_time     => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               swni.rmapnodeaddr <= (OTHERS => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               LFR_rstn <= LFR_soft_rstn AND rstn_25;
               --LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,          -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000125")  -- aa.bb.cc version
+                  top_lfr_version        => X"000126")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig,
                   debug_vector    => lfr_debug_vector,
                   debug_vector_ms => lfr_debug_vector_ms
                   );
               observation_reg(11 DOWNTO 0)      <= lfr_debug_vector;
               observation_reg(31 DOWNTO 12)     <= (OTHERS => '0');
               observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
               observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
               IO0                               <= rstn_25;
               IO1                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT data_valid
               IO2                               <= lfr_debug_vector_ms(0);  -- LFR MS FFT ready
               IO3                               <= lfr_debug_vector(0);  -- LFR APBREG error_buffer_full
               IO4                               <= lfr_debug_vector(1);  -- LFR APBREG reg_sp.status_error_buffer_full
               IO5                               <= lfr_debug_vector(8);  -- LFR APBREG  ready_matrix_f2
               IO6                               <= lfr_debug_vector(9);  -- LFR APBREG reg0_ready_matrix_f2
               IO7                               <= lfr_debug_vector(10);  -- LFR APBREG reg0_ready_matrix_f2
               all_sample : FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249)           -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               gpioi.sig_en <= (OTHERS => '0');
               gpioi.sig_in <= (OTHERS => '0');
               gpioi.din    <= (OTHERS => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN               -- asynchronous reset (active low)
                   --    --IO0  <= '0';
                   --    IO1  <= '0';
                   --    IO2  <= '0';
                   --    IO3  <= '0';
                   --    IO4  <= '0';
                   --    IO5  <= '0';
                   --    IO6  <= '0';
                   --    IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(2 DOWNTO 0) IS
                     WHEN "011" =>
                       --        --IO0  <= observation_reg(0 );
                       --        IO1  <= observation_reg(1 );
                       --        IO2  <= observation_reg(2 );
                       --        IO3  <= observation_reg(3 );
                       --        IO4  <= observation_reg(4 );
                       --        IO5  <= observation_reg(5 );
                       --        IO6  <= observation_reg(6 );
                       --        IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8);
                       IO9  <= observation_reg(9);
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "001" =>
                       --        --IO0  <= observation_reg(0  + 12);
                       --        IO1  <= observation_reg(1  + 12);
                       --        IO2  <= observation_reg(2  + 12);
                       --        IO3  <= observation_reg(3  + 12);
                       --        IO4  <= observation_reg(4  + 12);
                       --        IO5  <= observation_reg(5  + 12);
                       --        IO6  <= observation_reg(6  + 12);
                       --        IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8 + 12);
                       IO9  <= observation_reg(9 + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "010" =>
                       --        --IO0  <= observation_reg(0  + 12 + 12);
                       --        IO1  <= observation_reg(1  + 12 + 12);
                       --        IO2  <= observation_reg(2  + 12 + 12);
                       --        IO3  <= observation_reg(3  + 12 + 12);
                       --        IO4  <= observation_reg(4  + 12 + 12);
                       --        IO5  <= observation_reg(5  + 12 + 12);
                       --        IO6  <= observation_reg(6  + 12 + 12);
                       --        IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "000" =>
                       --        --IO0  <= observation_vector_0(0 );
                       --        IO1  <= observation_vector_0(1 );
                       --        IO2  <= observation_vector_0(2 );
                       --        IO3  <= observation_vector_0(3 );
                       --        IO4  <= observation_vector_0(4 );
                       --        IO5  <= observation_vector_0(5 );
                       --        IO6  <= observation_vector_0(6 );
                       --        IO7  <= observation_vector_0(7 );
                       IO8  <= observation_vector_0(8);
                       IO9  <= observation_vector_0(9);
                       IO10 <= observation_vector_0(10);
                       IO11 <= observation_vector_0(11);
                     WHEN "100" =>
                       --        --IO0  <= observation_vector_1(0 );
                       --        IO1  <= observation_vector_1(1 );
                       --        IO2  <= observation_vector_1(2 );
                       --        IO3  <= observation_vector_1(3 );
                       --        IO4  <= observation_vector_1(4 );
                       --        IO5  <= observation_vector_1(5 );
                       --        IO6  <= observation_vector_1(6 );
                       --        IO7  <= observation_vector_1(7 );
                       IO8  <= observation_vector_1(8);
                       IO9  <= observation_vector_1(9);
                       IO10 <= observation_vector_1(10);
                       IO11 <= observation_vector_1(11);
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
                 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
                   apbo_ext(I) <= apb_none;
                 END GENERATE apbo_ext_not_used;
               END GENERATE all_apbo_ext;
               all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
                 ahbo_s_ext(I) <= ahbs_none;
               END GENERATE all_ahbo_ext;
               all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
                 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
                   ahbo_m_ext(I) <= ahbm_none;
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
             END beh;

designs/MINI-LFR_WFP_MS/testbench.vhd 0 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             use IEEE.std_logic_textio.all;
             LIBRARY STD;
             use std.textio.all;
             LIBRARY grlib;
             USE grlib.stdlib.ALL;
             LIBRARY gaisler;
             USE gaisler.libdcom.ALL;
             USE gaisler.sim.ALL;
             USE gaisler.jtagtst.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY lpp;
             USE lpp.lpp_sim_pkg.ALL;
             USE lpp.lpp_lfr_sim_pkg.ALL;
             USE lpp.lpp_lfr_apbreg_pkg.ALL;
             USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
             ENTITY testbench IS
             END;
             ARCHITECTURE behav OF testbench IS
               COMPONENT MINI_LFR_top
                 PORT (
                   clk_50       : IN    STD_LOGIC;
                   clk_49       : IN    STD_LOGIC;
                   reset        : IN    STD_LOGIC;
                   BP0          : IN    STD_LOGIC;
                   BP1          : IN    STD_LOGIC;
                   LED0         : OUT   STD_LOGIC;
                   LED1         : OUT   STD_LOGIC;
                   LED2         : OUT   STD_LOGIC;
                   TXD1         : IN    STD_LOGIC;
                   RXD1         : OUT   STD_LOGIC;
                   nCTS1        : OUT   STD_LOGIC;
                   nRTS1        : IN    STD_LOGIC;
                   TXD2         : IN    STD_LOGIC;
                   RXD2         : OUT   STD_LOGIC;
                   nCTS2        : OUT   STD_LOGIC;
                   nDTR2        : IN    STD_LOGIC;
                   nRTS2        : IN    STD_LOGIC;
                   nDCD2        : OUT   STD_LOGIC;
                   IO0          : INOUT STD_LOGIC;
                   IO1          : INOUT STD_LOGIC;
                   IO2          : INOUT STD_LOGIC;
                   IO3          : INOUT STD_LOGIC;
                   IO4          : INOUT STD_LOGIC;
                   IO5          : INOUT STD_LOGIC;
                   IO6          : INOUT STD_LOGIC;
                   IO7          : INOUT STD_LOGIC;
                   IO8          : INOUT STD_LOGIC;
                   IO9          : INOUT STD_LOGIC;
                   IO10         : INOUT STD_LOGIC;
                   IO11         : INOUT STD_LOGIC;
                   SPW_EN       : OUT   STD_LOGIC;
                   SPW_NOM_DIN  : IN    STD_LOGIC;
                   SPW_NOM_SIN  : IN    STD_LOGIC;
                   SPW_NOM_DOUT : OUT   STD_LOGIC;
                   SPW_NOM_SOUT : OUT   STD_LOGIC;
                   SPW_RED_DIN  : IN    STD_LOGIC;
                   SPW_RED_SIN  : IN    STD_LOGIC;
                   SPW_RED_DOUT : OUT   STD_LOGIC;
                   SPW_RED_SOUT : OUT   STD_LOGIC;
                   ADC_nCS      : OUT   STD_LOGIC;
                   ADC_CLK      : OUT   STD_LOGIC;
                   ADC_SDO      : IN    STD_LOGIC_VECTOR(7 DOWNTO 0);
                   SRAM_nWE     : OUT   STD_LOGIC;
                   SRAM_CE      : OUT   STD_LOGIC;
                   SRAM_nOE     : OUT   STD_LOGIC;
                   SRAM_nBE     : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                   SRAM_A       : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                   SRAM_DQ      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               SIGNAL clk_50 : STD_LOGIC := '0';
               SIGNAL clk_49 : STD_LOGIC := '0';
               SIGNAL reset        : STD_LOGIC;
               SIGNAL BP0          : STD_LOGIC;
               SIGNAL BP1          : STD_LOGIC;
               SIGNAL LED0         : STD_LOGIC;
               SIGNAL LED1         : STD_LOGIC;
               SIGNAL LED2         : STD_LOGIC;
               SIGNAL TXD1         : STD_LOGIC;
               SIGNAL RXD1         : STD_LOGIC;
               SIGNAL nCTS1        : STD_LOGIC;
               SIGNAL nRTS1        : STD_LOGIC;
               SIGNAL TXD2         : STD_LOGIC;
               SIGNAL RXD2         : STD_LOGIC;
               SIGNAL nCTS2        : STD_LOGIC;
               SIGNAL nDTR2        : STD_LOGIC;
               SIGNAL nRTS2        : STD_LOGIC;
               SIGNAL nDCD2        : STD_LOGIC;
               SIGNAL IO0          : STD_LOGIC;
               SIGNAL IO1          : STD_LOGIC;
               SIGNAL IO2          : STD_LOGIC;
               SIGNAL IO3          : STD_LOGIC;
               SIGNAL IO4          : STD_LOGIC;
               SIGNAL IO5          : STD_LOGIC;
               SIGNAL IO6          : STD_LOGIC;
               SIGNAL IO7          : STD_LOGIC;
               SIGNAL IO8          : STD_LOGIC;
               SIGNAL IO9          : STD_LOGIC;
               SIGNAL IO10         : STD_LOGIC;
               SIGNAL IO11         : STD_LOGIC;
               SIGNAL SPW_EN       : STD_LOGIC;
               SIGNAL SPW_NOM_DIN  : STD_LOGIC;
               SIGNAL SPW_NOM_SIN  : STD_LOGIC;
               SIGNAL SPW_NOM_DOUT : STD_LOGIC;
               SIGNAL SPW_NOM_SOUT : STD_LOGIC;
               SIGNAL SPW_RED_DIN  : STD_LOGIC;
               SIGNAL SPW_RED_SIN  : STD_LOGIC;
               SIGNAL SPW_RED_DOUT : STD_LOGIC;
               SIGNAL SPW_RED_SOUT : STD_LOGIC;
               SIGNAL ADC_nCS      : STD_LOGIC;
               SIGNAL ADC_CLK      : STD_LOGIC;
               SIGNAL ADC_SDO      : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL SRAM_nWE     : STD_LOGIC;
               SIGNAL SRAM_CE      : STD_LOGIC;
               SIGNAL SRAM_nOE     : STD_LOGIC;
               SIGNAL SRAM_nBE     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL SRAM_A       : STD_LOGIC_VECTOR(19 DOWNTO 0);
               SIGNAL SRAM_DQ      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               CONSTANT ADDR_BASE_LFR            : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
               CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
               CONSTANT ADDR_BASE_GPIO           : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
               SIGNAL message_simu : STRING(1 TO 15) := "---------------";
               SIGNAL data_message : STRING(1 TO 15) := "---------------";
               SIGNAL data_read    : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
             BEGIN
               -----------------------------------------------------------------------------
               -- TB
               -----------------------------------------------------------------------------
               PROCESS
                 CONSTANT txp : TIME := 320 ns;
                 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
               BEGIN  -- PROCESS
                 TXD1  <= '1';
                 reset <= '0';
                 WAIT FOR 500 ns;
                 reset <= '1';
                 WAIT FOR 10000 ns;
                 message_simu <= "0 - UART init  ";
                 UART_INIT(TXD1,txp);
                 message_simu <= "1 - UART test  ";
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
                 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
                 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
                 data_read    <= data_read_v;
                 data_message <= "GPIO_data_write";
                 -- UNSET the LFR reset
                 message_simu <= "2 - LFR UNRESET";
                 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
                 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL   , X"00000000");
                 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
                 --
                 message_simu <= "3 - LFR CONFIG ";
                 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
                 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
                                        X"40000000",
                                        X"40001000",
                                        X"40002000",
                                        X"40003000",
                                        X"40004000",
                                        X"40005000");
                 message_simu <= "4 - GO GO GO !!";
                 UART_WRITE            (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
                 READ_STATUS: LOOP
                   WAIT FOR 2 ms;
                   UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
                   data_read    <= data_read_v;
                   data_message <= "READ_NEW_STATUS";
                   UART_WRITE(TXD1,    txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
                 END LOOP READ_STATUS;
                 WAIT;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- CLOCK
               -----------------------------------------------------------------------------
               clk_50    <= NOT clk_50 AFTER 5 ns;
               clk_49    <= NOT clk_49 AFTER 10172 ps;
               -----------------------------------------------------------------------------
               -- DON'T CARE
               -----------------------------------------------------------------------------
               BP0   <= '0';
               BP1   <= '0';
               nRTS1 <= '0' ;
               TXD2  <= '1';
               nRTS2 <= '1';
               nDTR2 <= '1';
               SPW_NOM_DIN  <= '1';
               SPW_NOM_SIN  <= '1';
               SPW_RED_DIN  <= '1';
               SPW_RED_SIN  <= '1';
               ADC_SDO      <= x"AA";
               SRAM_DQ      <= (OTHERS => 'Z');
               --IO0          <= 'Z';
               --IO1          <= 'Z';
               --IO2          <= 'Z';
               --IO3          <= 'Z';
               --IO4          <= 'Z';
               --IO5          <= 'Z';
               --IO6          <= 'Z';
               --IO7          <= 'Z';
               --IO8          <= 'Z';
               --IO9          <= 'Z';
               --IO10         <= 'Z';
               --IO11         <= 'Z';
               -----------------------------------------------------------------------------
               -- DUT
               -----------------------------------------------------------------------------
               MINI_LFR_top_1: MINI_LFR_top
                 PORT MAP (
                   clk_50       => clk_50,
                   clk_49       => clk_49,
                   reset        => reset,
                   BP0          => BP0,
                   BP1          => BP1,
                   LED0         => LED0,
                   LED1         => LED1,
                   LED2         => LED2,
                   TXD1         => TXD1,
                   RXD1         => RXD1,
                   nCTS1        => nCTS1,
                   nRTS1        => nRTS1,
                   TXD2         => TXD2,
                   RXD2         => RXD2,
                   nCTS2        => nCTS2,
                   nDTR2        => nDTR2,
                   nRTS2        => nRTS2,
                   nDCD2        => nDCD2,
                   IO0          => IO0,
                   IO1          => IO1,
                   IO2          => IO2,
                   IO3          => IO3,
                   IO4          => IO4,
                   IO5          => IO5,
                   IO6          => IO6,
                   IO7          => IO7,
                   IO8          => IO8,
                   IO9          => IO9,
                   IO10         => IO10,
                   IO11         => IO11,
                   SPW_EN       => SPW_EN,
                   SPW_NOM_DIN  => SPW_NOM_DIN,
                   SPW_NOM_SIN  => SPW_NOM_SIN,
                   SPW_NOM_DOUT => SPW_NOM_DOUT,
                   SPW_NOM_SOUT => SPW_NOM_SOUT,
                   SPW_RED_DIN  => SPW_RED_DIN,
                   SPW_RED_SIN  => SPW_RED_SIN,
                   SPW_RED_DOUT => SPW_RED_DOUT,
                   SPW_RED_SOUT => SPW_RED_SOUT,
                   ADC_nCS      => ADC_nCS,
                   ADC_CLK      => ADC_CLK,
                   ADC_SDO      => ADC_SDO,
                   SRAM_nWE     => SRAM_nWE,
                   SRAM_CE      => SRAM_CE,
                   SRAM_nOE     => SRAM_nOE,
                   SRAM_nBE     => SRAM_nBE,
                   SRAM_A       => SRAM_A,
                   SRAM_DQ      => SRAM_DQ);
             END;

designs/MINI-LFR_WFP_MS/wave.do +27 -5

             onerror {resume}
             quietly WaveActivateNextPane {} 0
             add wave -noupdate /testbench/message_simu
-            add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
+            add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -expand -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
             add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
             add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_write_error
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data2
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full_s
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data
+            add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/rdata
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/almost_full
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/full
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/empty
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ren
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wdata
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wen
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/run
+            add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ReUse
             TreeUpdate [SetDefaultTree]
-            WaveRestoreCursors {{Cursor 1} {11527482482 ps} 0}
+            WaveRestoreCursors {{Cursor 1} {63830825000 ps} 0} {{Cursor 2} {126327585000 ps} 0} {{Cursor 3} {188824345000 ps} 0}
-            quietly wave cursor active 1
+            quietly wave cursor active 3
-            configure wave -namecolwidth 539
+            configure wave -namecolwidth 510
             configure wave -valuecolwidth 100
             configure wave -justifyvalue left
             configure wave -signalnamewidth 0
             configure wave -snapdistance 10
             configure wave -datasetprefix 0
             configure wave -rowmargin 4
             configure wave -childrowmargin 2
             configure wave -gridoffset 0
             configure wave -gridperiod 1
             configure wave -griddelta 40
             configure wave -timeline 0
             configure wave -timelineunits ns
             update
-            WaveRestoreZoom {0 ps} {61313789250 ps}
+            WaveRestoreZoom {0 ps} {243397377300 ps}

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +1 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
                 Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 run  : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
                 dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
                 dma_buffer_new      : OUT STD_LOGIC;                      --TODOx
                 dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
                 dma_buffer_full     : IN  STD_LOGIC;                      --TODO
                 dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
                 -- Reg out
                 ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
             --    error_bad_component_error : OUT STD_LOGIC;                  -- TODO
                 error_buffer_full         : OUT STD_LOGIC;                  -- TODO
                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
                 addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 length_matrix_f0                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f1                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f2                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);  -- TODO
                 ---------------------------------------------------------------------------
                 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
             --  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
               SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
             --  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
               SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read                 : STD_LOGIC;
               SIGNAL fft_pong                 : STD_LOGIC;
               SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid           : STD_LOGIC;
               SIGNAL fft_ready                : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty       : STD_LOGIC;
               SIGNAL current_fifo_locked      : STD_LOGIC;
               SIGNAL current_fifo_full        : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
               SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_correlation_start     : STD_LOGIC;
               SIGNAL SM_correlation_auto      : STD_LOGIC;
               SIGNAL SM_correlation_done      : STD_LOGIC;
               SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
               SIGNAL SM_correlation_begin     : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
               SIGNAL current_matrix_write      : STD_LOGIC;
               SIGNAL current_matrix_wait_empty : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_0_ready              : STD_LOGIC;
               SIGNAL fifo_1_ready              : STD_LOGIC;
               SIGNAL fifo_ongoing              : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty_Threshold    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
               SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_reg_f    : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --SIGNAL time_update_f0_A : STD_LOGIC;
               --SIGNAL time_update_f0_B : STD_LOGIC;
               --SIGNAL time_update_f1   : STD_LOGIC;
               --SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
               SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
               SIGNAL fft_ready_reg         : STD_LOGIC;
               SIGNAL fft_ready_rising_down : STD_LOGIC;
               SIGNAL sample_load_reg         : STD_LOGIC;
               SIGNAL sample_load_rising_down : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_f1_wen_head     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_head_in  : STD_LOGIC;
               SIGNAL sample_f1_wen_head_out : STD_LOGIC;
               SIGNAL sample_f1_full_head_in : STD_LOGIC;
               SIGNAL sample_f1_full_head_out : STD_LOGIC;
               SIGNAL sample_f1_empty_head_in : STD_LOGIC;
               SIGNAL sample_f1_wdata_head   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL ongoing : STD_LOGIC;
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_f0_wen_s <= (OTHERS => '1');
                   sample_f1_wen_s <= (OTHERS => '1');
                   sample_f2_wen_s <= (OTHERS => '1');
                   ongoing <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF ongoing = '1' THEN
                     sample_f0_wen_s <= sample_f0_wen;
                     sample_f1_wen_s <= sample_f1_wen;
                     sample_f2_wen_s <= sample_f2_wen;
                   ELSE
                     IF start_date = coarse_time(30 DOWNTO 0) THEN
                       ongoing <= '1';
                     END IF;
                     sample_f0_wen_s <= (OTHERS => '1');
                     sample_f1_wen_s <= (OTHERS => '1');
                     sample_f2_wen_s <= (OTHERS => '1');
                   END IF;
                 END IF;
               END PROCESS;
               error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen_s,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen   => sample_f0_A_wen,
                   wdata => sample_f0_wdata,
                   ren   => sample_f0_A_ren,
                   rdata => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               -- sample_f1_wen   in
               -- sample_f1_wdata in
               -- sample_f1_full  OUT
-              sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen_s   = "00000" ELSE '1';
+              sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1';
               sample_f1_full_head_in  <= '0' WHEN sample_f1_full  = "00000" ELSE '1';
               sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
               lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   in_wen   => sample_f1_wen_head_in,
                   in_data  => sample_f1_wdata,
                   in_full  => sample_f1_full_head_in,
                   in_empty => sample_f1_empty_head_in,
                   out_write_error => error_wen_f1,
                   out_wen  => sample_f1_wen_head_out,
                   out_data => sample_f1_wdata_head,
                   out_full => sample_f1_full_head_out);
               sample_f1_wen_head    <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f1_wen_head,
                   wdata       => sample_f1_wdata_head,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   --error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f2_wen_s,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
                   select_channel <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
                         select_channel <= "10";
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
                           select_channel <= "00";
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
                           select_channel <= "01";
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
                           select_channel <= "11";
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                         select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   select_channel_reg <= (OTHERS => '0');
                   --pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_channel_reg <= select_channel;
                   --pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
               --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
               --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
               --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
               --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
                               sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
                               sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
                             sample_ren_s    WHEN sample_load = '1' ELSE
                             (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
                   select_fifo        <= "000";
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
                         select_fifo <= "000";
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
                         select_fifo <= "001";
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
                         select_fifo <= "010";
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
                         select_fifo <= "011";
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
                         select_fifo <= "100";
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
                         select_fifo <= "000";
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
                   select_fifo_reg <= (OTHERS => '0');
                   --next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   select_fifo_reg <= select_fifo;
                   --next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
               --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
               --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
               --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
               --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
               --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
                              sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
                              sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
                              sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_valid   => sample_valid,
                   fft_read       => fft_read,
                   sample_data    => sample_data,
                   sample_load    => sample_load,
                   fft_pong       => fft_pong,
                   fft_data_im    => fft_data_im,
                   fft_data_re    => fft_data_re,
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
               debug_vector(0) <= fft_data_valid;
               debug_vector(1) <= fft_ready;
               debug_vector(11 DOWNTO 2) <= (OTHERS => '0');
               -----------------------------------------------------------------------------
               fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
               sample_load_rising_down <= sample_load_reg AND NOT sample_load;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fft_ready_reg     <= '0';
                   sample_load_reg   <= '0';
                   fft_ongoing_counter <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   fft_ready_reg    <= fft_ready;
                   sample_load_reg  <= sample_load;
                   IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
                     fft_ongoing_counter <= '0';
             --        CASE fft_ongoing_counter IS
             --          WHEN "01" => fft_ongoing_counter <= "00";
             ----          WHEN "10" => fft_ongoing_counter <= "01";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
                     fft_ongoing_counter <= '1';
             --        CASE fft_ongoing_counter IS
             --          WHEN "00" => fft_ongoing_counter <= "01";
             ----          WHEN "01" => fft_ongoing_counter <= "10";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load        <= "00001";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                    MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                    MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                    MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                    MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
                 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                       AND state_fsm_load_MS_memory = LOAD_FIFO
                                       AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,                    --16,
                   Addr_sz => 7,                     --8
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   run   => (OTHERS => '1'),
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren         => MEM_IN_SM_ren,
                   rdata       => MEM_IN_SM_rData,
                   full        => MEM_IN_SM_Full,
                   empty       => MEM_IN_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               MS_control_1 : MS_control
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   current_status_ms => status_MS_input,
                   fifo_in_lock  => MEM_IN_SM_locked,
                   fifo_in_data  => MEM_IN_SM_rdata,
                   fifo_in_full  => MEM_IN_SM_Full,
                   fifo_in_empty => MEM_IN_SM_Empty,
                   fifo_in_ren   => MEM_IN_SM_ren,
                   fifo_in_reuse => MEM_IN_SM_ReUse,
                   fifo_out_data  => SM_in_data,
                   fifo_out_ren   => SM_in_ren,
                   fifo_out_empty => SM_in_empty,
                   current_status_component => status_component,
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_done  => SM_correlation_done);
               MS_calculation_1 : MS_calculation
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   fifo_in_data  => SM_in_data,
                   fifo_in_ren   => SM_in_ren,
                   fifo_in_empty => SM_in_empty,
                   fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
                   fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
                   fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_begin => SM_correlation_begin,
                   correlation_done  => SM_correlation_done);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_matrix_write        <= '0';
                   current_matrix_wait_empty   <= '1';
                   status_component_fifo_0     <= (OTHERS => '0');
                   status_component_fifo_1     <= (OTHERS => '0');
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   SM_correlation_done_reg1    <= '0';
                   SM_correlation_done_reg2    <= '0';
                   SM_correlation_done_reg3    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   SM_correlation_done_reg1    <= SM_correlation_done;
                   SM_correlation_done_reg2    <= SM_correlation_done_reg1;
                   SM_correlation_done_reg3    <= SM_correlation_done_reg2;
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0 <= status_component(53 DOWNTO 4);
                     ELSE
                       status_component_fifo_1 <= status_component(53 DOWNTO 4);
                     END IF;
                   END IF;
                   IF SM_correlation_done_reg3 = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0_end <= '1';
                     ELSE
                       status_component_fifo_1_end <= '1';
                     END IF;
                     current_matrix_wait_empty <= '1';
                     current_matrix_write      <= NOT current_matrix_write;
                   END IF;
                   IF current_matrix_wait_empty <= '1' THEN
                     IF current_matrix_write = '0' THEN
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
                     ELSE
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
                                    '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                                    '1'                WHEN current_matrix_wait_empty = '1' ELSE
                                    MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                                    MEM_OUT_SM_Full(1);
               MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
               MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
               MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
               -----------------------------------------------------------------------------
               --Mem_Out_SpectralMatrix : lppFIFOxN
               --  GENERIC MAP (
               --    tech    => 0,
               --    Mem_use => Mem_use,
               --    Data_sz => 32,
               --    Addr_sz => 8,
               --    FifoCnt => 2)
               --  PORT MAP (
               --    clk  => clk,
               --    rstn => rstn,
               --    ReUse => (OTHERS => '0'),
               --    run   => (OTHERS => '1'),
               --    wen   => MEM_OUT_SM_Write,
               --    wdata => MEM_OUT_SM_Data_in,
               --    ren   => MEM_OUT_SM_Read,
               --    rdata => MEM_OUT_SM_Data_out,
               --    full        => MEM_OUT_SM_Full,
               --    empty       => MEM_OUT_SM_Empty,
               --    almost_full => OPEN);
               all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
                 Mem_Out_SpectralMatrix_I: lpp_fifo
                   GENERIC MAP (
                     tech                  => 0,
                     Mem_use               => Mem_use,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 1,
                     DataSz                => 32,
                     AddrSz                => 8)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => MEM_OUT_SM_Read(I),
                     rdata           => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
                     wen             => MEM_OUT_SM_Write(I),
                     wdata           => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
                     empty           => MEM_OUT_SM_Empty(I),
                     full            => MEM_OUT_SM_Full(I),
                     full_almost     => OPEN,
                     empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
                     full_threshold  => OPEN);
               END GENERATE all_Mem_Out_SpectralMatrix;
               -----------------------------------------------------------------------------
             --  MEM_OUT_SM_Read <= "00";
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fifo_0_ready <= '0';
                   fifo_1_ready <= '0';
                   fifo_ongoing <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
                     fifo_ongoing <= '1';
                     fifo_0_ready <= '0';
                   ELSIF status_component_fifo_0_end = '1' THEN
                     fifo_0_ready <= '1';
                   END IF;
                   IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
                     fifo_ongoing <= '0';
                     fifo_1_ready <= '0';
                   ELSIF status_component_fifo_1_end = '1' THEN
                     fifo_1_ready <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                                     '1' WHEN fifo_0_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
                                     '1' WHEN fifo_1_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
                                     MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                                     '1';
               FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
                                      status_component_fifo_1;
               FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
                                    MEM_OUT_SM_Data_out(63 DOWNTO 32);
               FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1'  ELSE
                                               MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1'  ELSE
                                               '1';
               -----------------------------------------------------------------------------
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),       --IN
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),       --IN
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),      --IN
               --    fifo_data             => FSM_DMA_fifo_data,                     --IN
               --    fifo_empty            => FSM_DMA_fifo_empty,                    --IN
               --    fifo_empty_threshold  => FSM_DMA_fifo_empty_threshold,          --IN
               --    fifo_ren              => FSM_DMA_fifo_ren,                      --OUT
               lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   fifo_matrix_type       => FSM_DMA_fifo_status(5 DOWNTO 4),
                   fifo_matrix_time       => FSM_DMA_fifo_status(53 DOWNTO 6),
                   fifo_data              => FSM_DMA_fifo_data,
                   fifo_empty             => FSM_DMA_fifo_empty,
                   fifo_empty_threshold   => FSM_DMA_fifo_empty_threshold,
                   fifo_ren               => FSM_DMA_fifo_ren,
                   dma_fifo_valid_burst   => dma_fifo_burst_valid,
                   dma_fifo_data          => dma_fifo_data,
                   dma_fifo_ren           => dma_fifo_ren,
                   dma_buffer_new         => dma_buffer_new,
                   dma_buffer_addr        => dma_buffer_addr,
                   dma_buffer_length      => dma_buffer_length,
                   dma_buffer_full        => dma_buffer_full,
                   dma_buffer_full_err    => dma_buffer_full_err,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0       => length_matrix_f0,
                   length_matrix_f1       => length_matrix_f1,
                   length_matrix_f2       => length_matrix_f2,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   matrix_time_f0         => matrix_time_f0,
                   matrix_time_f1         => matrix_time_f1,
                   matrix_time_f2         => matrix_time_f2,
                   error_buffer_full      => error_buffer_full);
               --dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
               --dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
               --dma_buffer_new      : OUT STD_LOGIC;                      --TODO
               --dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
               --dma_buffer_full     : IN  STD_LOGIC;                      --TODO
               --dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
               ---- Reg out
               --ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
               --error_bad_component_error : OUT STD_LOGIC;                  -- TODO
               --error_buffer_full         : OUT STD_LOGIC;                  -- TODO
               ---- Reg In
               --status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
               --addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
               --  PORT MAP (
               --    HCLK    => clk,
               --    HRESETn => rstn,
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
               --    fifo_data             => FSM_DMA_fifo_data,
               --    fifo_empty            => FSM_DMA_fifo_empty,
               --    fifo_ren              => FSM_DMA_fifo_ren,
               --    dma_addr        => dma_addr,
               --    dma_data        => dma_data,
               --    dma_valid       => dma_valid,
               --    dma_valid_burst => dma_valid_burst,
               --    dma_ren         => dma_ren,
               --    dma_done        => dma_done,
               --    ready_matrix_f0 => ready_matrix_f0,
               --    ready_matrix_f1 => ready_matrix_f1,
               --    ready_matrix_f2 => ready_matrix_f2,
               --    error_bad_component_error => error_bad_component_error,
               --    error_buffer_full         => error_buffer_full,
               --    debug_reg              => debug_reg,
               --    status_ready_matrix_f0 => status_ready_matrix_f0,
               --    status_ready_matrix_f1 => status_ready_matrix_f1,
               --    status_ready_matrix_f2 => status_ready_matrix_f2,
               --    config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
               --    config_active_interruption_onError     => config_active_interruption_onError,
               --    addr_matrix_f0 => addr_matrix_f0,
               --    addr_matrix_f1 => addr_matrix_f1,
               --    addr_matrix_f2 => addr_matrix_f2,
               --    matrix_time_f0 => matrix_time_f0,
               --    matrix_time_f1 => matrix_time_f1,
               --    matrix_time_f2 => matrix_time_f2
               --    );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
               all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
               f_empty(2) <= '1' WHEN sample_f1_empty   = "11111" ELSE '0';
               f_empty(3) <= '1' WHEN sample_f2_empty   = "11111" ELSE '0';
               all_time_reg: FOR I IN 0 TO 3 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     f_empty_reg(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN
                     f_empty_reg(I) <= f_empty(I);
                   END IF;
                 END PROCESS;
                 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
                 s_m_t_m_f0_A : spectral_matrix_time_managment
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
                     time_in  => all_time,
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_time_reg;
               time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
               time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
               time_reg_f1   <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
               time_reg_f2   <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_ms_reg_head.vhd +10 -4

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             ENTITY lpp_lfr_ms_reg_head IS
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 in_wen   : IN STD_LOGIC;
                 in_data  : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                 in_full  : IN STD_LOGIC;
                 in_empty : IN STD_LOGIC;
                 out_write_error : OUT STD_LOGIC;
                 out_wen  : OUT STD_LOGIC;
                 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                 out_full : OUT STD_LOGIC
                 );
             END lpp_lfr_ms_reg_head;
             ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS
               TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2);
               SIGNAL fsm_state : fsm_state_reg_head;
               SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
               SIGNAL reg_data  : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
               SIGNAL out_wen_s : STD_LOGIC;
+              SIGNAL in_full_s : STD_LOGIC;
             BEGIN  -- Beh
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fsm_state       <= REG_EMPTY;
                   reg_data        <= (OTHERS => '0');
                   reg_data2       <= (OTHERS => '0');
                   out_wen_s       <= '1';
                   out_write_error <= '0';
+                  in_full_s <= '0';
                 ELSIF clk'event AND clk = '1' THEN
+                  in_full_s <= in_full;
                   out_wen_s <= '1';
                   out_write_error <= '0';
                   CASE fsm_state IS
                     WHEN REG_EMPTY =>
                       reg_data <= in_data;
-                      IF in_wen = '0' AND in_full = '1' THEN
+                      IF in_wen = '0' AND in_full_s = '1' THEN
                         fsm_state <= REG_ONE_DATA;
                       END IF;
                     WHEN REG_ONE_DATA =>
                       reg_data2 <= in_data;
-                      IF in_wen = '0' AND in_full = '1' THEN
+                      IF in_wen = '0' AND in_full_s = '1' THEN
                         fsm_state <= REG_FULL;
                       ELSIF in_empty = '1' THEN
                         out_wen_s <= '0';
                         IF in_wen = '0' THEN
                           reg_data <= in_data;
                         ELSE
                           fsm_state <= REG_EMPTY;
                         END IF;
                       END IF;
                     WHEN REG_FULL =>
                       IF in_empty = '1' THEN
                         out_wen_s <= '0';
                         IF in_wen = '0' THEN
                           reg_data2 <= in_data;
                         ELSE
                           fsm_state <= REG_FULL_2;
                         END IF;
                       ELSE
                         IF in_wen = '0' THEN
                           out_write_error <= '1';
                         END IF;
                       END IF;
                     WHEN REG_FULL_2 =>
                       out_wen_s <= '0';
                       fsm_state <= REG_EMPTY;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
-              out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full;
+              out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s;
               out_data <= reg_data2 WHEN fsm_state = REG_FULL     ELSE
                           reg_data  WHEN fsm_state = REG_ONE_DATA ELSE
                           reg_data  WHEN fsm_state = REG_FULL_2 ELSE
                           in_data;
               out_wen  <= '0' WHEN out_wen_s = '0'          ELSE
                           '1' WHEN fsm_state = REG_ONE_DATA ELSE
                           '1' WHEN fsm_state = REG_FULL     ELSE
-                          in_wen;
+                          '1' WHEN in_full_s = '1'          ELSE
+                          in_wen;
             END Beh;

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