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1 | ------------------------------------------------------------------------------ |
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1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
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4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
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5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
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6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
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7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
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8 | -- (at your option) any later version. | |
9 | -- |
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9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
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10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
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13 | -- GNU General Public License for more details. | |
14 | -- |
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14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
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15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
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16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
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18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Jean-christophe Pellion |
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19 | -- Author : Jean-christophe Pellion | |
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------- |
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21 | ------------------------------------------------------------------------------- | |
22 | LIBRARY IEEE; |
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22 | LIBRARY IEEE; | |
23 | USE IEEE.numeric_std.ALL; |
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23 | USE IEEE.numeric_std.ALL; | |
24 | USE IEEE.std_logic_1164.ALL; |
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24 | USE IEEE.std_logic_1164.ALL; | |
25 | LIBRARY grlib; |
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25 | LIBRARY grlib; | |
26 | USE grlib.amba.ALL; |
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26 | USE grlib.amba.ALL; | |
27 | USE grlib.stdlib.ALL; |
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27 | USE grlib.stdlib.ALL; | |
28 | LIBRARY techmap; |
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28 | LIBRARY techmap; | |
29 | USE techmap.gencomp.ALL; |
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29 | USE techmap.gencomp.ALL; | |
30 | LIBRARY gaisler; |
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30 | LIBRARY gaisler; | |
31 | USE gaisler.memctrl.ALL; |
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31 | USE gaisler.memctrl.ALL; | |
32 | USE gaisler.leon3.ALL; |
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32 | USE gaisler.leon3.ALL; | |
33 | USE gaisler.uart.ALL; |
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33 | USE gaisler.uart.ALL; | |
34 | USE gaisler.misc.ALL; |
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34 | USE gaisler.misc.ALL; | |
35 | USE gaisler.spacewire.ALL; |
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35 | USE gaisler.spacewire.ALL; | |
36 | LIBRARY esa; |
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36 | LIBRARY esa; | |
37 | USE esa.memoryctrl.ALL; |
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37 | USE esa.memoryctrl.ALL; | |
38 | LIBRARY lpp; |
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38 | LIBRARY lpp; | |
39 | USE lpp.lpp_memory.ALL; |
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39 | USE lpp.lpp_memory.ALL; | |
40 | USE lpp.lpp_ad_conv.ALL; |
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40 | USE lpp.lpp_ad_conv.ALL; | |
41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib | |
42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
43 | USE lpp.iir_filter.ALL; |
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43 | USE lpp.iir_filter.ALL; | |
44 | USE lpp.general_purpose.ALL; |
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44 | USE lpp.general_purpose.ALL; | |
45 | USE lpp.lpp_lfr_time_management.ALL; |
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45 | USE lpp.lpp_lfr_time_management.ALL; | |
46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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46 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
47 |
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47 | |||
48 | ENTITY MINI_LFR_top IS |
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48 | ENTITY MINI_LFR_top IS | |
49 |
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49 | |||
50 | PORT ( |
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50 | PORT ( | |
51 | clk_50 : IN STD_LOGIC; |
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51 | clk_50 : IN STD_LOGIC; | |
52 | clk_49 : IN STD_LOGIC; |
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52 | clk_49 : IN STD_LOGIC; | |
53 | reset : IN STD_LOGIC; |
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53 | reset : IN STD_LOGIC; | |
54 | --BPs |
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54 | --BPs | |
55 | BP0 : IN STD_LOGIC; |
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55 | BP0 : IN STD_LOGIC; | |
56 | BP1 : IN STD_LOGIC; |
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56 | BP1 : IN STD_LOGIC; | |
57 | --LEDs |
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57 | --LEDs | |
58 | LED0 : OUT STD_LOGIC; |
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58 | LED0 : OUT STD_LOGIC; | |
59 | LED1 : OUT STD_LOGIC; |
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59 | LED1 : OUT STD_LOGIC; | |
60 | LED2 : OUT STD_LOGIC; |
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60 | LED2 : OUT STD_LOGIC; | |
61 | --UARTs |
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61 | --UARTs | |
62 | TXD1 : IN STD_LOGIC; |
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62 | TXD1 : IN STD_LOGIC; | |
63 | RXD1 : OUT STD_LOGIC; |
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63 | RXD1 : OUT STD_LOGIC; | |
64 | nCTS1 : OUT STD_LOGIC; |
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64 | nCTS1 : OUT STD_LOGIC; | |
65 | nRTS1 : IN STD_LOGIC; |
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65 | nRTS1 : IN STD_LOGIC; | |
66 |
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66 | |||
67 | TXD2 : IN STD_LOGIC; |
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67 | TXD2 : IN STD_LOGIC; | |
68 | RXD2 : OUT STD_LOGIC; |
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68 | RXD2 : OUT STD_LOGIC; | |
69 | nCTS2 : OUT STD_LOGIC; |
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69 | nCTS2 : OUT STD_LOGIC; | |
70 | nDTR2 : IN STD_LOGIC; |
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70 | nDTR2 : IN STD_LOGIC; | |
71 | nRTS2 : IN STD_LOGIC; |
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71 | nRTS2 : IN STD_LOGIC; | |
72 | nDCD2 : OUT STD_LOGIC; |
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72 | nDCD2 : OUT STD_LOGIC; | |
73 |
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73 | |||
74 | --EXT CONNECTOR |
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74 | --EXT CONNECTOR | |
75 | IO0 : INOUT STD_LOGIC; |
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75 | IO0 : INOUT STD_LOGIC; | |
76 | IO1 : INOUT STD_LOGIC; |
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76 | IO1 : INOUT STD_LOGIC; | |
77 | IO2 : INOUT STD_LOGIC; |
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77 | IO2 : INOUT STD_LOGIC; | |
78 | IO3 : INOUT STD_LOGIC; |
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78 | IO3 : INOUT STD_LOGIC; | |
79 | IO4 : INOUT STD_LOGIC; |
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79 | IO4 : INOUT STD_LOGIC; | |
80 | IO5 : INOUT STD_LOGIC; |
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80 | IO5 : INOUT STD_LOGIC; | |
81 | IO6 : INOUT STD_LOGIC; |
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81 | IO6 : INOUT STD_LOGIC; | |
82 | IO7 : INOUT STD_LOGIC; |
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82 | IO7 : INOUT STD_LOGIC; | |
83 | IO8 : INOUT STD_LOGIC; |
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83 | IO8 : INOUT STD_LOGIC; | |
84 | IO9 : INOUT STD_LOGIC; |
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84 | IO9 : INOUT STD_LOGIC; | |
85 | IO10 : INOUT STD_LOGIC; |
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85 | IO10 : INOUT STD_LOGIC; | |
86 | IO11 : INOUT STD_LOGIC; |
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86 | IO11 : INOUT STD_LOGIC; | |
87 |
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87 | |||
88 | --SPACE WIRE |
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88 | --SPACE WIRE | |
89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
91 | SPW_NOM_SIN : IN STD_LOGIC; |
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91 | SPW_NOM_SIN : IN STD_LOGIC; | |
92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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92 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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93 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
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94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
95 | SPW_RED_SIN : IN STD_LOGIC; |
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95 | SPW_RED_SIN : IN STD_LOGIC; | |
96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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96 | SPW_RED_DOUT : OUT STD_LOGIC; | |
97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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97 | SPW_RED_SOUT : OUT STD_LOGIC; | |
98 | -- MINI LFR ADC INPUTS |
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98 | -- MINI LFR ADC INPUTS | |
99 | ADC_nCS : OUT STD_LOGIC; |
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99 | ADC_nCS : OUT STD_LOGIC; | |
100 | ADC_CLK : OUT STD_LOGIC; |
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100 | ADC_CLK : OUT STD_LOGIC; | |
101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
102 |
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102 | |||
103 | -- SRAM |
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103 | -- SRAM | |
104 | SRAM_nWE : OUT STD_LOGIC; |
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104 | SRAM_nWE : OUT STD_LOGIC; | |
105 | SRAM_CE : OUT STD_LOGIC; |
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105 | SRAM_CE : OUT STD_LOGIC; | |
106 | SRAM_nOE : OUT STD_LOGIC; |
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106 | SRAM_nOE : OUT STD_LOGIC; | |
107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) | |
110 | ); |
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110 | ); | |
111 |
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111 | |||
112 | END MINI_LFR_top; |
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112 | END MINI_LFR_top; | |
113 |
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113 | |||
114 |
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114 | |||
115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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115 | ARCHITECTURE beh OF MINI_LFR_top IS | |
116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
118 | SIGNAL clk_24 : STD_LOGIC := '0'; |
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118 | SIGNAL clk_24 : STD_LOGIC := '0'; | |
119 | ----------------------------------------------------------------------------- |
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119 | ----------------------------------------------------------------------------- | |
120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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120 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
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121 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
122 | -- |
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122 | -- | |
123 | SIGNAL errorn : STD_LOGIC; |
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123 | SIGNAL errorn : STD_LOGIC; | |
124 | -- UART AHB --------------------------------------------------------------- |
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124 | -- UART AHB --------------------------------------------------------------- | |
125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
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125 | -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
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126 | -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
127 |
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127 | |||
128 | -- UART APB --------------------------------------------------------------- |
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128 | -- UART APB --------------------------------------------------------------- | |
129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
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129 | -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
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130 | -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
131 | -- |
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131 | -- | |
132 | SIGNAL I00_s : STD_LOGIC; |
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132 | SIGNAL I00_s : STD_LOGIC; | |
133 |
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133 | |||
134 | -- CONSTANTS |
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134 | -- CONSTANTS | |
135 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
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135 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
136 | -- |
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136 | -- | |
137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
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137 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; | |
139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
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139 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
140 |
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140 | |||
141 | SIGNAL apbi_ext : apb_slv_in_type; |
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141 | SIGNAL apbi_ext : apb_slv_in_type; | |
142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); |
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142 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none); | |
143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
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143 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); |
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144 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none); | |
145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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145 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); |
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146 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none); | |
147 |
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147 | |||
148 | -- Spacewire signals |
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148 | -- Spacewire signals | |
149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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149 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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150 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
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151 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
152 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
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152 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
153 | SIGNAL spw_rxclkn : STD_ULOGIC; |
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153 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
154 | SIGNAL spw_clk : STD_LOGIC; |
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154 | SIGNAL spw_clk : STD_LOGIC; | |
155 | SIGNAL swni : grspw_in_type; |
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155 | SIGNAL swni : grspw_in_type; | |
156 | SIGNAL swno : grspw_out_type; |
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156 | SIGNAL swno : grspw_out_type; | |
157 | -- SIGNAL clkmn : STD_ULOGIC; |
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157 | -- SIGNAL clkmn : STD_ULOGIC; | |
158 | -- SIGNAL txclk : STD_ULOGIC; |
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158 | -- SIGNAL txclk : STD_ULOGIC; | |
159 |
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159 | |||
160 | --GPIO |
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160 | --GPIO | |
161 | SIGNAL gpioi : gpio_in_type; |
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161 | SIGNAL gpioi : gpio_in_type; | |
162 | SIGNAL gpioo : gpio_out_type; |
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162 | SIGNAL gpioo : gpio_out_type; | |
163 |
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163 | |||
164 | -- AD Converter ADS7886 |
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164 | -- AD Converter ADS7886 | |
165 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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165 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
166 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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166 | SIGNAL sample_s : Samples(7 DOWNTO 0); | |
167 | SIGNAL sample_val : STD_LOGIC; |
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167 | SIGNAL sample_val : STD_LOGIC; | |
168 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
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168 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
169 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
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169 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
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170 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
171 |
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171 | |||
172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
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172 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
173 |
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173 | |||
174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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174 | SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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175 | SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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176 | SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
177 | ----------------------------------------------------------------------------- |
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177 | ----------------------------------------------------------------------------- | |
178 |
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178 | |||
179 | SIGNAL LFR_soft_rstn : STD_LOGIC; |
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179 | SIGNAL LFR_soft_rstn : STD_LOGIC; | |
180 | SIGNAL LFR_rstn : STD_LOGIC; |
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180 | SIGNAL LFR_rstn : STD_LOGIC; | |
181 |
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181 | |||
182 |
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182 | |||
183 | SIGNAL rstn_25 : STD_LOGIC; |
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183 | SIGNAL rstn_25 : STD_LOGIC; | |
184 | SIGNAL rstn_25_d1 : STD_LOGIC; |
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184 | SIGNAL rstn_25_d1 : STD_LOGIC; | |
185 | SIGNAL rstn_25_d2 : STD_LOGIC; |
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185 | SIGNAL rstn_25_d2 : STD_LOGIC; | |
186 | SIGNAL rstn_25_d3 : STD_LOGIC; |
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186 | SIGNAL rstn_25_d3 : STD_LOGIC; | |
187 |
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187 | |||
188 | SIGNAL rstn_50 : STD_LOGIC; |
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188 | SIGNAL rstn_50 : STD_LOGIC; | |
189 | SIGNAL rstn_50_d1 : STD_LOGIC; |
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189 | SIGNAL rstn_50_d1 : STD_LOGIC; | |
190 | SIGNAL rstn_50_d2 : STD_LOGIC; |
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190 | SIGNAL rstn_50_d2 : STD_LOGIC; | |
191 | SIGNAL rstn_50_d3 : STD_LOGIC; |
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191 | SIGNAL rstn_50_d3 : STD_LOGIC; | |
192 |
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192 | |||
193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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193 | SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); |
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194 | SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
195 |
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195 | |||
196 | BEGIN -- beh |
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196 | BEGIN -- beh | |
197 |
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197 | |||
198 | ----------------------------------------------------------------------------- |
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198 | ----------------------------------------------------------------------------- | |
199 | -- CLK |
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199 | -- CLK | |
200 | ----------------------------------------------------------------------------- |
|
200 | ----------------------------------------------------------------------------- | |
201 |
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201 | |||
202 | --PROCESS(clk_50) |
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202 | --PROCESS(clk_50) | |
203 | --BEGIN |
|
203 | --BEGIN | |
204 | -- IF clk_50'EVENT AND clk_50 = '1' THEN |
|
204 | -- IF clk_50'EVENT AND clk_50 = '1' THEN | |
205 | -- clk_50_s <= NOT clk_50_s; |
|
205 | -- clk_50_s <= NOT clk_50_s; | |
206 | -- END IF; |
|
206 | -- END IF; | |
207 | --END PROCESS; |
|
207 | --END PROCESS; | |
208 |
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208 | |||
209 | --PROCESS(clk_50_s) |
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209 | --PROCESS(clk_50_s) | |
210 | --BEGIN |
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210 | --BEGIN | |
211 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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211 | -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN | |
212 | -- clk_25 <= NOT clk_25; |
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212 | -- clk_25 <= NOT clk_25; | |
213 | -- END IF; |
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213 | -- END IF; | |
214 | --END PROCESS; |
|
214 | --END PROCESS; | |
215 |
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215 | |||
216 | --PROCESS(clk_49) |
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216 | --PROCESS(clk_49) | |
217 | --BEGIN |
|
217 | --BEGIN | |
218 | -- IF clk_49'EVENT AND clk_49 = '1' THEN |
|
218 | -- IF clk_49'EVENT AND clk_49 = '1' THEN | |
219 | -- clk_24 <= NOT clk_24; |
|
219 | -- clk_24 <= NOT clk_24; | |
220 | -- END IF; |
|
220 | -- END IF; | |
221 | --END PROCESS; |
|
221 | --END PROCESS; | |
222 |
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222 | |||
223 | --PROCESS(clk_25) |
|
223 | --PROCESS(clk_25) | |
224 | --BEGIN |
|
224 | --BEGIN | |
225 | -- IF clk_25'EVENT AND clk_25 = '1' THEN |
|
225 | -- IF clk_25'EVENT AND clk_25 = '1' THEN | |
226 | -- rstn_25 <= reset; |
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226 | -- rstn_25 <= reset; | |
227 | -- END IF; |
|
227 | -- END IF; | |
228 | --END PROCESS; |
|
228 | --END PROCESS; | |
229 |
|
229 | |||
230 | PROCESS (clk_50, reset) |
|
230 | PROCESS (clk_50, reset) | |
231 | BEGIN -- PROCESS |
|
231 | BEGIN -- PROCESS | |
232 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
232 | IF reset = '0' THEN -- asynchronous reset (active low) | |
233 | clk_50_s <= '0'; |
|
233 | clk_50_s <= '0'; | |
234 | rstn_50 <= '0'; |
|
234 | rstn_50 <= '0'; | |
235 | rstn_50_d1 <= '0'; |
|
235 | rstn_50_d1 <= '0'; | |
236 | rstn_50_d2 <= '0'; |
|
236 | rstn_50_d2 <= '0'; | |
237 | rstn_50_d3 <= '0'; |
|
237 | rstn_50_d3 <= '0'; | |
238 |
|
238 | |||
239 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge |
|
239 | ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge | |
240 | clk_50_s <= NOT clk_50_s; |
|
240 | clk_50_s <= NOT clk_50_s; | |
241 | rstn_50_d1 <= '1'; |
|
241 | rstn_50_d1 <= '1'; | |
242 | rstn_50_d2 <= rstn_50_d1; |
|
242 | rstn_50_d2 <= rstn_50_d1; | |
243 | rstn_50_d3 <= rstn_50_d2; |
|
243 | rstn_50_d3 <= rstn_50_d2; | |
244 | rstn_50 <= rstn_50_d3; |
|
244 | rstn_50 <= rstn_50_d3; | |
245 | END IF; |
|
245 | END IF; | |
246 | END PROCESS; |
|
246 | END PROCESS; | |
247 |
|
247 | |||
248 | PROCESS (clk_50_s, rstn_50) |
|
248 | PROCESS (clk_50_s, rstn_50) | |
249 | BEGIN -- PROCESS |
|
249 | BEGIN -- PROCESS | |
250 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) |
|
250 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |
251 | clk_25 <= '0'; |
|
251 | clk_25 <= '0'; | |
252 | rstn_25 <= '0'; |
|
252 | rstn_25 <= '0'; | |
253 | rstn_25_d1 <= '0'; |
|
253 | rstn_25_d1 <= '0'; | |
254 | rstn_25_d2 <= '0'; |
|
254 | rstn_25_d2 <= '0'; | |
255 | rstn_25_d3 <= '0'; |
|
255 | rstn_25_d3 <= '0'; | |
256 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge |
|
256 | ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge | |
257 | clk_25 <= NOT clk_25; |
|
257 | clk_25 <= NOT clk_25; | |
258 | rstn_25_d1 <= '1'; |
|
258 | rstn_25_d1 <= '1'; | |
259 | rstn_25_d2 <= rstn_25_d1; |
|
259 | rstn_25_d2 <= rstn_25_d1; | |
260 | rstn_25_d3 <= rstn_25_d2; |
|
260 | rstn_25_d3 <= rstn_25_d2; | |
261 | rstn_25 <= rstn_25_d3; |
|
261 | rstn_25 <= rstn_25_d3; | |
262 | END IF; |
|
262 | END IF; | |
263 | END PROCESS; |
|
263 | END PROCESS; | |
264 |
|
264 | |||
265 | PROCESS (clk_49, reset) |
|
265 | PROCESS (clk_49, reset) | |
266 | BEGIN -- PROCESS |
|
266 | BEGIN -- PROCESS | |
267 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
267 | IF reset = '0' THEN -- asynchronous reset (active low) | |
268 | clk_24 <= '0'; |
|
268 | clk_24 <= '0'; | |
269 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
269 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
270 | clk_24 <= NOT clk_24; |
|
270 | clk_24 <= NOT clk_24; | |
271 | END IF; |
|
271 | END IF; | |
272 | END PROCESS; |
|
272 | END PROCESS; | |
273 |
|
273 | |||
274 | ----------------------------------------------------------------------------- |
|
274 | ----------------------------------------------------------------------------- | |
275 |
|
275 | |||
276 | PROCESS (clk_25, rstn_25) |
|
276 | PROCESS (clk_25, rstn_25) | |
277 | BEGIN -- PROCESS |
|
277 | BEGIN -- PROCESS | |
278 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
278 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
279 | LED0 <= '0'; |
|
279 | LED0 <= '0'; | |
280 | LED1 <= '0'; |
|
280 | LED1 <= '0'; | |
281 | LED2 <= '0'; |
|
281 | LED2 <= '0'; | |
282 | --IO1 <= '0'; |
|
282 | --IO1 <= '0'; | |
283 | --IO2 <= '1'; |
|
283 | --IO2 <= '1'; | |
284 | --IO3 <= '0'; |
|
284 | --IO3 <= '0'; | |
285 | --IO4 <= '0'; |
|
285 | --IO4 <= '0'; | |
286 | --IO5 <= '0'; |
|
286 | --IO5 <= '0'; | |
287 | --IO6 <= '0'; |
|
287 | --IO6 <= '0'; | |
288 | --IO7 <= '0'; |
|
288 | --IO7 <= '0'; | |
289 | --IO8 <= '0'; |
|
289 | --IO8 <= '0'; | |
290 | --IO9 <= '0'; |
|
290 | --IO9 <= '0'; | |
291 | --IO10 <= '0'; |
|
291 | --IO10 <= '0'; | |
292 | --IO11 <= '0'; |
|
292 | --IO11 <= '0'; | |
293 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
293 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
294 | LED0 <= '0'; |
|
294 | LED0 <= '0'; | |
295 | LED1 <= '1'; |
|
295 | LED1 <= '1'; | |
296 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
296 | LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
297 | --IO1 <= '1'; |
|
297 | --IO1 <= '1'; | |
298 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
298 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; | |
299 | --IO3 <= ADC_SDO(0); |
|
299 | --IO3 <= ADC_SDO(0); | |
300 | --IO4 <= ADC_SDO(1); |
|
300 | --IO4 <= ADC_SDO(1); | |
301 | --IO5 <= ADC_SDO(2); |
|
301 | --IO5 <= ADC_SDO(2); | |
302 | --IO6 <= ADC_SDO(3); |
|
302 | --IO6 <= ADC_SDO(3); | |
303 | --IO7 <= ADC_SDO(4); |
|
303 | --IO7 <= ADC_SDO(4); | |
304 | --IO8 <= ADC_SDO(5); |
|
304 | --IO8 <= ADC_SDO(5); | |
305 | --IO9 <= ADC_SDO(6); |
|
305 | --IO9 <= ADC_SDO(6); | |
306 | --IO10 <= ADC_SDO(7); |
|
306 | --IO10 <= ADC_SDO(7); | |
307 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
307 | --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
308 | END IF; |
|
308 | END IF; | |
309 | END PROCESS; |
|
309 | END PROCESS; | |
310 |
|
310 | |||
311 | PROCESS (clk_24, rstn_25) |
|
311 | PROCESS (clk_24, rstn_25) | |
312 | BEGIN -- PROCESS |
|
312 | BEGIN -- PROCESS | |
313 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
313 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
314 | I00_s <= '0'; |
|
314 | I00_s <= '0'; | |
315 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge |
|
315 | ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge | |
316 | I00_s <= NOT I00_s; |
|
316 | I00_s <= NOT I00_s; | |
317 | END IF; |
|
317 | END IF; | |
318 | END PROCESS; |
|
318 | END PROCESS; | |
319 | -- IO0 <= I00_s; |
|
319 | -- IO0 <= I00_s; | |
320 |
|
320 | |||
321 | --UARTs |
|
321 | --UARTs | |
322 | nCTS1 <= '1'; |
|
322 | nCTS1 <= '1'; | |
323 | nCTS2 <= '1'; |
|
323 | nCTS2 <= '1'; | |
324 | nDCD2 <= '1'; |
|
324 | nDCD2 <= '1'; | |
325 |
|
325 | |||
326 | --EXT CONNECTOR |
|
326 | --EXT CONNECTOR | |
327 |
|
327 | |||
328 | --SPACE WIRE |
|
328 | --SPACE WIRE | |
329 |
|
329 | |||
330 | leon3_soc_1 : leon3_soc |
|
330 | leon3_soc_1 : leon3_soc | |
331 | GENERIC MAP ( |
|
331 | GENERIC MAP ( | |
332 | fabtech => apa3e, |
|
332 | fabtech => apa3e, | |
333 | memtech => apa3e, |
|
333 | memtech => apa3e, | |
334 | padtech => inferred, |
|
334 | padtech => inferred, | |
335 | clktech => inferred, |
|
335 | clktech => inferred, | |
336 | disas => 0, |
|
336 | disas => 0, | |
337 | dbguart => 0, |
|
337 | dbguart => 0, | |
338 | pclow => 2, |
|
338 | pclow => 2, | |
339 | clk_freq => 25000, |
|
339 | clk_freq => 25000, | |
340 | NB_CPU => 1, |
|
340 | NB_CPU => 1, | |
341 | ENABLE_FPU => 1, |
|
341 | ENABLE_FPU => 1, | |
342 | FPU_NETLIST => 0, |
|
342 | FPU_NETLIST => 0, | |
343 | ENABLE_DSU => 1, |
|
343 | ENABLE_DSU => 1, | |
344 | ENABLE_AHB_UART => 1, |
|
344 | ENABLE_AHB_UART => 1, | |
345 | ENABLE_APB_UART => 1, |
|
345 | ENABLE_APB_UART => 1, | |
346 | ENABLE_IRQMP => 1, |
|
346 | ENABLE_IRQMP => 1, | |
347 | ENABLE_GPT => 1, |
|
347 | ENABLE_GPT => 1, | |
348 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
348 | NB_AHB_MASTER => NB_AHB_MASTER, | |
349 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
349 | NB_AHB_SLAVE => NB_AHB_SLAVE, | |
350 | NB_APB_SLAVE => NB_APB_SLAVE, |
|
350 | NB_APB_SLAVE => NB_APB_SLAVE, | |
351 | ADDRESS_SIZE => 20) |
|
351 | ADDRESS_SIZE => 20) | |
352 | PORT MAP ( |
|
352 | PORT MAP ( | |
353 | clk => clk_25, |
|
353 | clk => clk_25, | |
354 | reset => rstn_25, |
|
354 | reset => rstn_25, | |
355 | errorn => errorn, |
|
355 | errorn => errorn, | |
356 | ahbrxd => TXD1, |
|
356 | ahbrxd => TXD1, | |
357 | ahbtxd => RXD1, |
|
357 | ahbtxd => RXD1, | |
358 | urxd1 => TXD2, |
|
358 | urxd1 => TXD2, | |
359 | utxd1 => RXD2, |
|
359 | utxd1 => RXD2, | |
360 | address => SRAM_A, |
|
360 | address => SRAM_A, | |
361 | data => SRAM_DQ, |
|
361 | data => SRAM_DQ, | |
362 | nSRAM_BE0 => SRAM_nBE(0), |
|
362 | nSRAM_BE0 => SRAM_nBE(0), | |
363 | nSRAM_BE1 => SRAM_nBE(1), |
|
363 | nSRAM_BE1 => SRAM_nBE(1), | |
364 | nSRAM_BE2 => SRAM_nBE(2), |
|
364 | nSRAM_BE2 => SRAM_nBE(2), | |
365 | nSRAM_BE3 => SRAM_nBE(3), |
|
365 | nSRAM_BE3 => SRAM_nBE(3), | |
366 | nSRAM_WE => SRAM_nWE, |
|
366 | nSRAM_WE => SRAM_nWE, | |
367 | nSRAM_CE => SRAM_CE, |
|
367 | nSRAM_CE => SRAM_CE, | |
368 | nSRAM_OE => SRAM_nOE, |
|
368 | nSRAM_OE => SRAM_nOE, | |
369 |
|
369 | |||
370 | apbi_ext => apbi_ext, |
|
370 | apbi_ext => apbi_ext, | |
371 | apbo_ext => apbo_ext, |
|
371 | apbo_ext => apbo_ext, | |
372 | ahbi_s_ext => ahbi_s_ext, |
|
372 | ahbi_s_ext => ahbi_s_ext, | |
373 | ahbo_s_ext => ahbo_s_ext, |
|
373 | ahbo_s_ext => ahbo_s_ext, | |
374 | ahbi_m_ext => ahbi_m_ext, |
|
374 | ahbi_m_ext => ahbi_m_ext, | |
375 | ahbo_m_ext => ahbo_m_ext); |
|
375 | ahbo_m_ext => ahbo_m_ext); | |
376 |
|
376 | |||
377 | ------------------------------------------------------------------------------- |
|
377 | ------------------------------------------------------------------------------- | |
378 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
378 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- | |
379 | ------------------------------------------------------------------------------- |
|
379 | ------------------------------------------------------------------------------- | |
380 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
380 | apb_lfr_time_management_1 : apb_lfr_time_management | |
381 | GENERIC MAP ( |
|
381 | GENERIC MAP ( | |
382 | pindex => 6, |
|
382 | pindex => 6, | |
383 | paddr => 6, |
|
383 | paddr => 6, | |
384 | pmask => 16#fff#, |
|
384 | pmask => 16#fff#, | |
385 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 |
|
385 | FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374 | |
386 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set |
|
386 | NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set | |
387 | PORT MAP ( |
|
387 | PORT MAP ( | |
388 | clk25MHz => clk_25, |
|
388 | clk25MHz => clk_25, | |
389 | clk24_576MHz => clk_24, -- 49.152MHz/2 |
|
389 | clk24_576MHz => clk_24, -- 49.152MHz/2 | |
390 | resetn => rstn_25, |
|
390 | resetn => rstn_25, | |
391 | grspw_tick => swno.tickout, |
|
391 | grspw_tick => swno.tickout, | |
392 | apbi => apbi_ext, |
|
392 | apbi => apbi_ext, | |
393 | apbo => apbo_ext(6), |
|
393 | apbo => apbo_ext(6), | |
394 | coarse_time => coarse_time, |
|
394 | coarse_time => coarse_time, | |
395 | fine_time => fine_time, |
|
395 | fine_time => fine_time, | |
396 | LFR_soft_rstn => LFR_soft_rstn |
|
396 | LFR_soft_rstn => LFR_soft_rstn | |
397 | ); |
|
397 | ); | |
398 |
|
398 | |||
399 | ----------------------------------------------------------------------- |
|
399 | ----------------------------------------------------------------------- | |
400 | --- SpaceWire -------------------------------------------------------- |
|
400 | --- SpaceWire -------------------------------------------------------- | |
401 | ----------------------------------------------------------------------- |
|
401 | ----------------------------------------------------------------------- | |
402 |
|
402 | |||
403 | SPW_EN <= '1'; |
|
403 | SPW_EN <= '1'; | |
404 |
|
404 | |||
405 | spw_clk <= clk_50_s; |
|
405 | spw_clk <= clk_50_s; | |
406 | spw_rxtxclk <= spw_clk; |
|
406 | spw_rxtxclk <= spw_clk; | |
407 | spw_rxclkn <= NOT spw_rxtxclk; |
|
407 | spw_rxclkn <= NOT spw_rxtxclk; | |
408 |
|
408 | |||
409 | -- PADS for SPW1 |
|
409 | -- PADS for SPW1 | |
410 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
410 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
411 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
411 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
412 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
412 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
413 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
413 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
414 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
414 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
415 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
415 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
416 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
416 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
417 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
417 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
418 | -- PADS FOR SPW2 |
|
418 | -- PADS FOR SPW2 | |
419 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
419 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
420 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
420 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
421 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
421 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
422 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
422 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
423 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
423 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
424 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
424 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
425 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
425 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
426 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
426 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
427 |
|
427 | |||
428 | -- GRSPW PHY |
|
428 | -- GRSPW PHY | |
429 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
429 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
430 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
430 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
431 | spw_phy0 : grspw_phy |
|
431 | spw_phy0 : grspw_phy | |
432 | GENERIC MAP( |
|
432 | GENERIC MAP( | |
433 | tech => apa3e, |
|
433 | tech => apa3e, | |
434 | rxclkbuftype => 1, |
|
434 | rxclkbuftype => 1, | |
435 | scantest => 0) |
|
435 | scantest => 0) | |
436 | PORT MAP( |
|
436 | PORT MAP( | |
437 | rxrst => swno.rxrst, |
|
437 | rxrst => swno.rxrst, | |
438 | di => dtmp(j), |
|
438 | di => dtmp(j), | |
439 | si => stmp(j), |
|
439 | si => stmp(j), | |
440 | rxclko => spw_rxclk(j), |
|
440 | rxclko => spw_rxclk(j), | |
441 | do => swni.d(j), |
|
441 | do => swni.d(j), | |
442 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
442 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
443 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
443 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
444 | END GENERATE spw_inputloop; |
|
444 | END GENERATE spw_inputloop; | |
445 |
|
445 | |||
446 | swni.rmapnodeaddr <= (OTHERS => '0'); |
|
446 | swni.rmapnodeaddr <= (OTHERS => '0'); | |
447 |
|
447 | |||
448 | -- SPW core |
|
448 | -- SPW core | |
449 | sw0 : grspwm GENERIC MAP( |
|
449 | sw0 : grspwm GENERIC MAP( | |
450 | tech => apa3e, |
|
450 | tech => apa3e, | |
451 | hindex => 1, |
|
451 | hindex => 1, | |
452 | pindex => 5, |
|
452 | pindex => 5, | |
453 | paddr => 5, |
|
453 | paddr => 5, | |
454 | pirq => 11, |
|
454 | pirq => 11, | |
455 | sysfreq => 25000, -- CPU_FREQ |
|
455 | sysfreq => 25000, -- CPU_FREQ | |
456 | rmap => 1, |
|
456 | rmap => 1, | |
457 | rmapcrc => 1, |
|
457 | rmapcrc => 1, | |
458 | fifosize1 => 16, |
|
458 | fifosize1 => 16, | |
459 | fifosize2 => 16, |
|
459 | fifosize2 => 16, | |
460 | rxclkbuftype => 1, |
|
460 | rxclkbuftype => 1, | |
461 | rxunaligned => 0, |
|
461 | rxunaligned => 0, | |
462 | rmapbufs => 4, |
|
462 | rmapbufs => 4, | |
463 | ft => 0, |
|
463 | ft => 0, | |
464 | netlist => 0, |
|
464 | netlist => 0, | |
465 | ports => 2, |
|
465 | ports => 2, | |
466 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
466 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
467 | memtech => apa3e, |
|
467 | memtech => apa3e, | |
468 | destkey => 2, |
|
468 | destkey => 2, | |
469 | spwcore => 1 |
|
469 | spwcore => 1 | |
470 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
470 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
471 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
471 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
472 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
472 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
473 | ) |
|
473 | ) | |
474 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), |
|
474 | PORT MAP(rstn_25, clk_25, spw_rxclk(0), | |
475 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
475 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
476 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
476 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
477 | swni, swno); |
|
477 | swni, swno); | |
478 |
|
478 | |||
479 | swni.tickin <= '0'; |
|
479 | swni.tickin <= '0'; | |
480 | swni.rmapen <= '1'; |
|
480 | swni.rmapen <= '1'; | |
481 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
481 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
482 | swni.tickinraw <= '0'; |
|
482 | swni.tickinraw <= '0'; | |
483 | swni.timein <= (OTHERS => '0'); |
|
483 | swni.timein <= (OTHERS => '0'); | |
484 | swni.dcrstval <= (OTHERS => '0'); |
|
484 | swni.dcrstval <= (OTHERS => '0'); | |
485 | swni.timerrstval <= (OTHERS => '0'); |
|
485 | swni.timerrstval <= (OTHERS => '0'); | |
486 |
|
486 | |||
487 | ------------------------------------------------------------------------------- |
|
487 | ------------------------------------------------------------------------------- | |
488 | -- LFR ------------------------------------------------------------------------ |
|
488 | -- LFR ------------------------------------------------------------------------ | |
489 | ------------------------------------------------------------------------------- |
|
489 | ------------------------------------------------------------------------------- | |
490 |
|
490 | |||
491 |
|
491 | |||
492 | LFR_rstn <= LFR_soft_rstn AND rstn_25; |
|
492 | LFR_rstn <= LFR_soft_rstn AND rstn_25; | |
493 | --LFR_rstn <= rstn_25; |
|
493 | --LFR_rstn <= rstn_25; | |
494 |
|
494 | |||
495 | lpp_lfr_1 : lpp_lfr |
|
495 | lpp_lfr_1 : lpp_lfr | |
496 | GENERIC MAP ( |
|
496 | GENERIC MAP ( | |
497 | Mem_use => use_RAM, |
|
497 | Mem_use => use_RAM, | |
498 | nb_data_by_buffer_size => 32, |
|
498 | nb_data_by_buffer_size => 32, | |
499 | nb_snapshot_param_size => 32, |
|
499 | nb_snapshot_param_size => 32, | |
500 | delta_vector_size => 32, |
|
500 | delta_vector_size => 32, | |
501 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
501 | delta_vector_size_f0_2 => 7, -- log2(96) | |
502 | pindex => 15, |
|
502 | pindex => 15, | |
503 | paddr => 15, |
|
503 | paddr => 15, | |
504 | pmask => 16#fff#, |
|
504 | pmask => 16#fff#, | |
505 | pirq_ms => 6, |
|
505 | pirq_ms => 6, | |
506 | pirq_wfp => 14, |
|
506 | pirq_wfp => 14, | |
507 | hindex => 2, |
|
507 | hindex => 2, | |
508 |
top_lfr_version => X"00012 |
|
508 | top_lfr_version => X"000126") -- aa.bb.cc version | |
509 | PORT MAP ( |
|
509 | PORT MAP ( | |
510 | clk => clk_25, |
|
510 | clk => clk_25, | |
511 | rstn => LFR_rstn, |
|
511 | rstn => LFR_rstn, | |
512 | sample_B => sample_s(2 DOWNTO 0), |
|
512 | sample_B => sample_s(2 DOWNTO 0), | |
513 | sample_E => sample_s(7 DOWNTO 3), |
|
513 | sample_E => sample_s(7 DOWNTO 3), | |
514 | sample_val => sample_val, |
|
514 | sample_val => sample_val, | |
515 | apbi => apbi_ext, |
|
515 | apbi => apbi_ext, | |
516 | apbo => apbo_ext(15), |
|
516 | apbo => apbo_ext(15), | |
517 | ahbi => ahbi_m_ext, |
|
517 | ahbi => ahbi_m_ext, | |
518 | ahbo => ahbo_m_ext(2), |
|
518 | ahbo => ahbo_m_ext(2), | |
519 | coarse_time => coarse_time, |
|
519 | coarse_time => coarse_time, | |
520 | fine_time => fine_time, |
|
520 | fine_time => fine_time, | |
521 | data_shaping_BW => bias_fail_sw_sig, |
|
521 | data_shaping_BW => bias_fail_sw_sig, | |
522 | debug_vector => lfr_debug_vector, |
|
522 | debug_vector => lfr_debug_vector, | |
523 | debug_vector_ms => lfr_debug_vector_ms |
|
523 | debug_vector_ms => lfr_debug_vector_ms | |
524 | ); |
|
524 | ); | |
525 |
|
525 | |||
526 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; |
|
526 | observation_reg(11 DOWNTO 0) <= lfr_debug_vector; | |
527 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); |
|
527 | observation_reg(31 DOWNTO 12) <= (OTHERS => '0'); | |
528 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; |
|
528 | observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector; | |
529 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; |
|
529 | observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector; | |
530 | IO0 <= rstn_25; |
|
530 | IO0 <= rstn_25; | |
531 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid |
|
531 | IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid | |
532 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready |
|
532 | IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready | |
533 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full |
|
533 | IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full | |
534 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full |
|
534 | IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full | |
535 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 |
|
535 | IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2 | |
536 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 |
|
536 | IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2 | |
537 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 |
|
537 | IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2 | |
538 |
|
538 | |||
539 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE |
|
539 | all_sample : FOR I IN 7 DOWNTO 0 GENERATE | |
540 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; |
|
540 | sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0'; | |
541 | END GENERATE all_sample; |
|
541 | END GENERATE all_sample; | |
542 |
|
542 | |||
543 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
543 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
544 | GENERIC MAP( |
|
544 | GENERIC MAP( | |
545 | ChannelCount => 8, |
|
545 | ChannelCount => 8, | |
546 | SampleNbBits => 14, |
|
546 | SampleNbBits => 14, | |
547 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 |
|
547 | ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5 | |
548 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 |
|
548 | ncycle_cnv => 249) -- 49 152 000 / 98304 /2 | |
549 | PORT MAP ( |
|
549 | PORT MAP ( | |
550 | -- CONV |
|
550 | -- CONV | |
551 | cnv_clk => clk_24, |
|
551 | cnv_clk => clk_24, | |
552 | cnv_rstn => rstn_25, |
|
552 | cnv_rstn => rstn_25, | |
553 | cnv => ADC_nCS_sig, |
|
553 | cnv => ADC_nCS_sig, | |
554 | -- DATA |
|
554 | -- DATA | |
555 | clk => clk_25, |
|
555 | clk => clk_25, | |
556 | rstn => rstn_25, |
|
556 | rstn => rstn_25, | |
557 | sck => ADC_CLK_sig, |
|
557 | sck => ADC_CLK_sig, | |
558 | sdo => ADC_SDO_sig, |
|
558 | sdo => ADC_SDO_sig, | |
559 | -- SAMPLE |
|
559 | -- SAMPLE | |
560 | sample => sample, |
|
560 | sample => sample, | |
561 | sample_val => sample_val); |
|
561 | sample_val => sample_val); | |
562 |
|
562 | |||
563 | --IO10 <= ADC_SDO_sig(5); |
|
563 | --IO10 <= ADC_SDO_sig(5); | |
564 | --IO9 <= ADC_SDO_sig(4); |
|
564 | --IO9 <= ADC_SDO_sig(4); | |
565 | --IO8 <= ADC_SDO_sig(3); |
|
565 | --IO8 <= ADC_SDO_sig(3); | |
566 |
|
566 | |||
567 | ADC_nCS <= ADC_nCS_sig; |
|
567 | ADC_nCS <= ADC_nCS_sig; | |
568 | ADC_CLK <= ADC_CLK_sig; |
|
568 | ADC_CLK <= ADC_CLK_sig; | |
569 | ADC_SDO_sig <= ADC_SDO; |
|
569 | ADC_SDO_sig <= ADC_SDO; | |
570 |
|
570 | |||
571 | ---------------------------------------------------------------------- |
|
571 | ---------------------------------------------------------------------- | |
572 | --- GPIO ----------------------------------------------------------- |
|
572 | --- GPIO ----------------------------------------------------------- | |
573 | ---------------------------------------------------------------------- |
|
573 | ---------------------------------------------------------------------- | |
574 |
|
574 | |||
575 | grgpio0 : grgpio |
|
575 | grgpio0 : grgpio | |
576 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
576 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
577 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
577 | PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
578 |
|
578 | |||
579 | gpioi.sig_en <= (OTHERS => '0'); |
|
579 | gpioi.sig_en <= (OTHERS => '0'); | |
580 | gpioi.sig_in <= (OTHERS => '0'); |
|
580 | gpioi.sig_in <= (OTHERS => '0'); | |
581 | gpioi.din <= (OTHERS => '0'); |
|
581 | gpioi.din <= (OTHERS => '0'); | |
582 | --pio_pad_0 : iopad |
|
582 | --pio_pad_0 : iopad | |
583 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
583 | -- GENERIC MAP (tech => CFG_PADTECH) | |
584 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
584 | -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
585 | --pio_pad_1 : iopad |
|
585 | --pio_pad_1 : iopad | |
586 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
586 | -- GENERIC MAP (tech => CFG_PADTECH) | |
587 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
587 | -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
588 | --pio_pad_2 : iopad |
|
588 | --pio_pad_2 : iopad | |
589 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
589 | -- GENERIC MAP (tech => CFG_PADTECH) | |
590 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
590 | -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
591 | --pio_pad_3 : iopad |
|
591 | --pio_pad_3 : iopad | |
592 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
592 | -- GENERIC MAP (tech => CFG_PADTECH) | |
593 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
593 | -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
594 | --pio_pad_4 : iopad |
|
594 | --pio_pad_4 : iopad | |
595 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
595 | -- GENERIC MAP (tech => CFG_PADTECH) | |
596 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
596 | -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
597 | --pio_pad_5 : iopad |
|
597 | --pio_pad_5 : iopad | |
598 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
598 | -- GENERIC MAP (tech => CFG_PADTECH) | |
599 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
599 | -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
600 | --pio_pad_6 : iopad |
|
600 | --pio_pad_6 : iopad | |
601 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
601 | -- GENERIC MAP (tech => CFG_PADTECH) | |
602 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
602 | -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
603 | --pio_pad_7 : iopad |
|
603 | --pio_pad_7 : iopad | |
604 | -- GENERIC MAP (tech => CFG_PADTECH) |
|
604 | -- GENERIC MAP (tech => CFG_PADTECH) | |
605 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
605 | -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
606 |
|
606 | |||
607 | PROCESS (clk_25, rstn_25) |
|
607 | PROCESS (clk_25, rstn_25) | |
608 | BEGIN -- PROCESS |
|
608 | BEGIN -- PROCESS | |
609 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) |
|
609 | IF rstn_25 = '0' THEN -- asynchronous reset (active low) | |
610 | -- --IO0 <= '0'; |
|
610 | -- --IO0 <= '0'; | |
611 | -- IO1 <= '0'; |
|
611 | -- IO1 <= '0'; | |
612 | -- IO2 <= '0'; |
|
612 | -- IO2 <= '0'; | |
613 | -- IO3 <= '0'; |
|
613 | -- IO3 <= '0'; | |
614 | -- IO4 <= '0'; |
|
614 | -- IO4 <= '0'; | |
615 | -- IO5 <= '0'; |
|
615 | -- IO5 <= '0'; | |
616 | -- IO6 <= '0'; |
|
616 | -- IO6 <= '0'; | |
617 | -- IO7 <= '0'; |
|
617 | -- IO7 <= '0'; | |
618 | IO8 <= '0'; |
|
618 | IO8 <= '0'; | |
619 | IO9 <= '0'; |
|
619 | IO9 <= '0'; | |
620 | IO10 <= '0'; |
|
620 | IO10 <= '0'; | |
621 | IO11 <= '0'; |
|
621 | IO11 <= '0'; | |
622 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
622 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
623 | CASE gpioo.dout(2 DOWNTO 0) IS |
|
623 | CASE gpioo.dout(2 DOWNTO 0) IS | |
624 | WHEN "011" => |
|
624 | WHEN "011" => | |
625 | -- --IO0 <= observation_reg(0 ); |
|
625 | -- --IO0 <= observation_reg(0 ); | |
626 | -- IO1 <= observation_reg(1 ); |
|
626 | -- IO1 <= observation_reg(1 ); | |
627 | -- IO2 <= observation_reg(2 ); |
|
627 | -- IO2 <= observation_reg(2 ); | |
628 | -- IO3 <= observation_reg(3 ); |
|
628 | -- IO3 <= observation_reg(3 ); | |
629 | -- IO4 <= observation_reg(4 ); |
|
629 | -- IO4 <= observation_reg(4 ); | |
630 | -- IO5 <= observation_reg(5 ); |
|
630 | -- IO5 <= observation_reg(5 ); | |
631 | -- IO6 <= observation_reg(6 ); |
|
631 | -- IO6 <= observation_reg(6 ); | |
632 | -- IO7 <= observation_reg(7 ); |
|
632 | -- IO7 <= observation_reg(7 ); | |
633 | IO8 <= observation_reg(8); |
|
633 | IO8 <= observation_reg(8); | |
634 | IO9 <= observation_reg(9); |
|
634 | IO9 <= observation_reg(9); | |
635 | IO10 <= observation_reg(10); |
|
635 | IO10 <= observation_reg(10); | |
636 | IO11 <= observation_reg(11); |
|
636 | IO11 <= observation_reg(11); | |
637 | WHEN "001" => |
|
637 | WHEN "001" => | |
638 | -- --IO0 <= observation_reg(0 + 12); |
|
638 | -- --IO0 <= observation_reg(0 + 12); | |
639 | -- IO1 <= observation_reg(1 + 12); |
|
639 | -- IO1 <= observation_reg(1 + 12); | |
640 | -- IO2 <= observation_reg(2 + 12); |
|
640 | -- IO2 <= observation_reg(2 + 12); | |
641 | -- IO3 <= observation_reg(3 + 12); |
|
641 | -- IO3 <= observation_reg(3 + 12); | |
642 | -- IO4 <= observation_reg(4 + 12); |
|
642 | -- IO4 <= observation_reg(4 + 12); | |
643 | -- IO5 <= observation_reg(5 + 12); |
|
643 | -- IO5 <= observation_reg(5 + 12); | |
644 | -- IO6 <= observation_reg(6 + 12); |
|
644 | -- IO6 <= observation_reg(6 + 12); | |
645 | -- IO7 <= observation_reg(7 + 12); |
|
645 | -- IO7 <= observation_reg(7 + 12); | |
646 | IO8 <= observation_reg(8 + 12); |
|
646 | IO8 <= observation_reg(8 + 12); | |
647 | IO9 <= observation_reg(9 + 12); |
|
647 | IO9 <= observation_reg(9 + 12); | |
648 | IO10 <= observation_reg(10 + 12); |
|
648 | IO10 <= observation_reg(10 + 12); | |
649 | IO11 <= observation_reg(11 + 12); |
|
649 | IO11 <= observation_reg(11 + 12); | |
650 | WHEN "010" => |
|
650 | WHEN "010" => | |
651 | -- --IO0 <= observation_reg(0 + 12 + 12); |
|
651 | -- --IO0 <= observation_reg(0 + 12 + 12); | |
652 | -- IO1 <= observation_reg(1 + 12 + 12); |
|
652 | -- IO1 <= observation_reg(1 + 12 + 12); | |
653 | -- IO2 <= observation_reg(2 + 12 + 12); |
|
653 | -- IO2 <= observation_reg(2 + 12 + 12); | |
654 | -- IO3 <= observation_reg(3 + 12 + 12); |
|
654 | -- IO3 <= observation_reg(3 + 12 + 12); | |
655 | -- IO4 <= observation_reg(4 + 12 + 12); |
|
655 | -- IO4 <= observation_reg(4 + 12 + 12); | |
656 | -- IO5 <= observation_reg(5 + 12 + 12); |
|
656 | -- IO5 <= observation_reg(5 + 12 + 12); | |
657 | -- IO6 <= observation_reg(6 + 12 + 12); |
|
657 | -- IO6 <= observation_reg(6 + 12 + 12); | |
658 | -- IO7 <= observation_reg(7 + 12 + 12); |
|
658 | -- IO7 <= observation_reg(7 + 12 + 12); | |
659 | IO8 <= '0'; |
|
659 | IO8 <= '0'; | |
660 | IO9 <= '0'; |
|
660 | IO9 <= '0'; | |
661 | IO10 <= '0'; |
|
661 | IO10 <= '0'; | |
662 | IO11 <= '0'; |
|
662 | IO11 <= '0'; | |
663 | WHEN "000" => |
|
663 | WHEN "000" => | |
664 | -- --IO0 <= observation_vector_0(0 ); |
|
664 | -- --IO0 <= observation_vector_0(0 ); | |
665 | -- IO1 <= observation_vector_0(1 ); |
|
665 | -- IO1 <= observation_vector_0(1 ); | |
666 | -- IO2 <= observation_vector_0(2 ); |
|
666 | -- IO2 <= observation_vector_0(2 ); | |
667 | -- IO3 <= observation_vector_0(3 ); |
|
667 | -- IO3 <= observation_vector_0(3 ); | |
668 | -- IO4 <= observation_vector_0(4 ); |
|
668 | -- IO4 <= observation_vector_0(4 ); | |
669 | -- IO5 <= observation_vector_0(5 ); |
|
669 | -- IO5 <= observation_vector_0(5 ); | |
670 | -- IO6 <= observation_vector_0(6 ); |
|
670 | -- IO6 <= observation_vector_0(6 ); | |
671 | -- IO7 <= observation_vector_0(7 ); |
|
671 | -- IO7 <= observation_vector_0(7 ); | |
672 | IO8 <= observation_vector_0(8); |
|
672 | IO8 <= observation_vector_0(8); | |
673 | IO9 <= observation_vector_0(9); |
|
673 | IO9 <= observation_vector_0(9); | |
674 | IO10 <= observation_vector_0(10); |
|
674 | IO10 <= observation_vector_0(10); | |
675 | IO11 <= observation_vector_0(11); |
|
675 | IO11 <= observation_vector_0(11); | |
676 | WHEN "100" => |
|
676 | WHEN "100" => | |
677 | -- --IO0 <= observation_vector_1(0 ); |
|
677 | -- --IO0 <= observation_vector_1(0 ); | |
678 | -- IO1 <= observation_vector_1(1 ); |
|
678 | -- IO1 <= observation_vector_1(1 ); | |
679 | -- IO2 <= observation_vector_1(2 ); |
|
679 | -- IO2 <= observation_vector_1(2 ); | |
680 | -- IO3 <= observation_vector_1(3 ); |
|
680 | -- IO3 <= observation_vector_1(3 ); | |
681 | -- IO4 <= observation_vector_1(4 ); |
|
681 | -- IO4 <= observation_vector_1(4 ); | |
682 | -- IO5 <= observation_vector_1(5 ); |
|
682 | -- IO5 <= observation_vector_1(5 ); | |
683 | -- IO6 <= observation_vector_1(6 ); |
|
683 | -- IO6 <= observation_vector_1(6 ); | |
684 | -- IO7 <= observation_vector_1(7 ); |
|
684 | -- IO7 <= observation_vector_1(7 ); | |
685 | IO8 <= observation_vector_1(8); |
|
685 | IO8 <= observation_vector_1(8); | |
686 | IO9 <= observation_vector_1(9); |
|
686 | IO9 <= observation_vector_1(9); | |
687 | IO10 <= observation_vector_1(10); |
|
687 | IO10 <= observation_vector_1(10); | |
688 | IO11 <= observation_vector_1(11); |
|
688 | IO11 <= observation_vector_1(11); | |
689 | WHEN OTHERS => NULL; |
|
689 | WHEN OTHERS => NULL; | |
690 | END CASE; |
|
690 | END CASE; | |
691 |
|
691 | |||
692 | END IF; |
|
692 | END IF; | |
693 | END PROCESS; |
|
693 | END PROCESS; | |
694 | ----------------------------------------------------------------------------- |
|
694 | ----------------------------------------------------------------------------- | |
695 | -- |
|
695 | -- | |
696 | ----------------------------------------------------------------------------- |
|
696 | ----------------------------------------------------------------------------- | |
697 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE |
|
697 | all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE | |
698 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE |
|
698 | apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE | |
699 | apbo_ext(I) <= apb_none; |
|
699 | apbo_ext(I) <= apb_none; | |
700 | END GENERATE apbo_ext_not_used; |
|
700 | END GENERATE apbo_ext_not_used; | |
701 | END GENERATE all_apbo_ext; |
|
701 | END GENERATE all_apbo_ext; | |
702 |
|
702 | |||
703 |
|
703 | |||
704 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE |
|
704 | all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE | |
705 | ahbo_s_ext(I) <= ahbs_none; |
|
705 | ahbo_s_ext(I) <= ahbs_none; | |
706 | END GENERATE all_ahbo_ext; |
|
706 | END GENERATE all_ahbo_ext; | |
707 |
|
707 | |||
708 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE |
|
708 | all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE | |
709 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE |
|
709 | ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE | |
710 | ahbo_m_ext(I) <= ahbm_none; |
|
710 | ahbo_m_ext(I) <= ahbm_none; | |
711 | END GENERATE ahbo_m_ext_not_used; |
|
711 | END GENERATE ahbo_m_ext_not_used; | |
712 | END GENERATE all_ahbo_m_ext; |
|
712 | END GENERATE all_ahbo_m_ext; | |
713 |
|
713 | |||
714 | END beh; |
|
714 | END beh; |
@@ -1,297 +1,296 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 | use IEEE.std_logic_textio.all; |
|
4 | use IEEE.std_logic_textio.all; | |
5 | LIBRARY STD; |
|
5 | LIBRARY STD; | |
6 | use std.textio.all; |
|
6 | use std.textio.all; | |
7 |
|
7 | |||
8 | LIBRARY grlib; |
|
8 | LIBRARY grlib; | |
9 | USE grlib.stdlib.ALL; |
|
9 | USE grlib.stdlib.ALL; | |
10 | LIBRARY gaisler; |
|
10 | LIBRARY gaisler; | |
11 | USE gaisler.libdcom.ALL; |
|
11 | USE gaisler.libdcom.ALL; | |
12 | USE gaisler.sim.ALL; |
|
12 | USE gaisler.sim.ALL; | |
13 | USE gaisler.jtagtst.ALL; |
|
13 | USE gaisler.jtagtst.ALL; | |
14 | LIBRARY techmap; |
|
14 | LIBRARY techmap; | |
15 | USE techmap.gencomp.ALL; |
|
15 | USE techmap.gencomp.ALL; | |
16 |
|
16 | |||
17 | LIBRARY lpp; |
|
17 | LIBRARY lpp; | |
18 | USE lpp.lpp_sim_pkg.ALL; |
|
18 | USE lpp.lpp_sim_pkg.ALL; | |
19 | USE lpp.lpp_lfr_sim_pkg.ALL; |
|
19 | USE lpp.lpp_lfr_sim_pkg.ALL; | |
20 | USE lpp.lpp_lfr_apbreg_pkg.ALL; |
|
20 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |
21 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; |
|
21 | USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL; | |
22 |
|
22 | |||
23 |
|
23 | |||
24 | ENTITY testbench IS |
|
24 | ENTITY testbench IS | |
25 | END; |
|
25 | END; | |
26 |
|
26 | |||
27 | ARCHITECTURE behav OF testbench IS |
|
27 | ARCHITECTURE behav OF testbench IS | |
28 |
|
28 | |||
29 | COMPONENT MINI_LFR_top |
|
29 | COMPONENT MINI_LFR_top | |
30 | PORT ( |
|
30 | PORT ( | |
31 | clk_50 : IN STD_LOGIC; |
|
31 | clk_50 : IN STD_LOGIC; | |
32 | clk_49 : IN STD_LOGIC; |
|
32 | clk_49 : IN STD_LOGIC; | |
33 | reset : IN STD_LOGIC; |
|
33 | reset : IN STD_LOGIC; | |
34 | BP0 : IN STD_LOGIC; |
|
34 | BP0 : IN STD_LOGIC; | |
35 | BP1 : IN STD_LOGIC; |
|
35 | BP1 : IN STD_LOGIC; | |
36 | LED0 : OUT STD_LOGIC; |
|
36 | LED0 : OUT STD_LOGIC; | |
37 | LED1 : OUT STD_LOGIC; |
|
37 | LED1 : OUT STD_LOGIC; | |
38 | LED2 : OUT STD_LOGIC; |
|
38 | LED2 : OUT STD_LOGIC; | |
39 | TXD1 : IN STD_LOGIC; |
|
39 | TXD1 : IN STD_LOGIC; | |
40 | RXD1 : OUT STD_LOGIC; |
|
40 | RXD1 : OUT STD_LOGIC; | |
41 | nCTS1 : OUT STD_LOGIC; |
|
41 | nCTS1 : OUT STD_LOGIC; | |
42 | nRTS1 : IN STD_LOGIC; |
|
42 | nRTS1 : IN STD_LOGIC; | |
43 | TXD2 : IN STD_LOGIC; |
|
43 | TXD2 : IN STD_LOGIC; | |
44 | RXD2 : OUT STD_LOGIC; |
|
44 | RXD2 : OUT STD_LOGIC; | |
45 | nCTS2 : OUT STD_LOGIC; |
|
45 | nCTS2 : OUT STD_LOGIC; | |
46 | nDTR2 : IN STD_LOGIC; |
|
46 | nDTR2 : IN STD_LOGIC; | |
47 | nRTS2 : IN STD_LOGIC; |
|
47 | nRTS2 : IN STD_LOGIC; | |
48 | nDCD2 : OUT STD_LOGIC; |
|
48 | nDCD2 : OUT STD_LOGIC; | |
49 | IO0 : INOUT STD_LOGIC; |
|
49 | IO0 : INOUT STD_LOGIC; | |
50 | IO1 : INOUT STD_LOGIC; |
|
50 | IO1 : INOUT STD_LOGIC; | |
51 | IO2 : INOUT STD_LOGIC; |
|
51 | IO2 : INOUT STD_LOGIC; | |
52 | IO3 : INOUT STD_LOGIC; |
|
52 | IO3 : INOUT STD_LOGIC; | |
53 | IO4 : INOUT STD_LOGIC; |
|
53 | IO4 : INOUT STD_LOGIC; | |
54 | IO5 : INOUT STD_LOGIC; |
|
54 | IO5 : INOUT STD_LOGIC; | |
55 | IO6 : INOUT STD_LOGIC; |
|
55 | IO6 : INOUT STD_LOGIC; | |
56 | IO7 : INOUT STD_LOGIC; |
|
56 | IO7 : INOUT STD_LOGIC; | |
57 | IO8 : INOUT STD_LOGIC; |
|
57 | IO8 : INOUT STD_LOGIC; | |
58 | IO9 : INOUT STD_LOGIC; |
|
58 | IO9 : INOUT STD_LOGIC; | |
59 | IO10 : INOUT STD_LOGIC; |
|
59 | IO10 : INOUT STD_LOGIC; | |
60 | IO11 : INOUT STD_LOGIC; |
|
60 | IO11 : INOUT STD_LOGIC; | |
61 | SPW_EN : OUT STD_LOGIC; |
|
61 | SPW_EN : OUT STD_LOGIC; | |
62 | SPW_NOM_DIN : IN STD_LOGIC; |
|
62 | SPW_NOM_DIN : IN STD_LOGIC; | |
63 | SPW_NOM_SIN : IN STD_LOGIC; |
|
63 | SPW_NOM_SIN : IN STD_LOGIC; | |
64 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
64 | SPW_NOM_DOUT : OUT STD_LOGIC; | |
65 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
65 | SPW_NOM_SOUT : OUT STD_LOGIC; | |
66 | SPW_RED_DIN : IN STD_LOGIC; |
|
66 | SPW_RED_DIN : IN STD_LOGIC; | |
67 | SPW_RED_SIN : IN STD_LOGIC; |
|
67 | SPW_RED_SIN : IN STD_LOGIC; | |
68 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
68 | SPW_RED_DOUT : OUT STD_LOGIC; | |
69 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
69 | SPW_RED_SOUT : OUT STD_LOGIC; | |
70 | ADC_nCS : OUT STD_LOGIC; |
|
70 | ADC_nCS : OUT STD_LOGIC; | |
71 | ADC_CLK : OUT STD_LOGIC; |
|
71 | ADC_CLK : OUT STD_LOGIC; | |
72 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
72 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
73 | SRAM_nWE : OUT STD_LOGIC; |
|
73 | SRAM_nWE : OUT STD_LOGIC; | |
74 | SRAM_CE : OUT STD_LOGIC; |
|
74 | SRAM_CE : OUT STD_LOGIC; | |
75 | SRAM_nOE : OUT STD_LOGIC; |
|
75 | SRAM_nOE : OUT STD_LOGIC; | |
76 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
76 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
77 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
77 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
78 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); |
|
78 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)); | |
79 | END COMPONENT; |
|
79 | END COMPONENT; | |
80 |
|
80 | |||
81 | ----------------------------------------------------------------------------- |
|
81 | ----------------------------------------------------------------------------- | |
82 | SIGNAL clk_50 : STD_LOGIC := '0'; |
|
82 | SIGNAL clk_50 : STD_LOGIC := '0'; | |
83 | SIGNAL clk_49 : STD_LOGIC := '0'; |
|
83 | SIGNAL clk_49 : STD_LOGIC := '0'; | |
84 | SIGNAL reset : STD_LOGIC; |
|
84 | SIGNAL reset : STD_LOGIC; | |
85 | SIGNAL BP0 : STD_LOGIC; |
|
85 | SIGNAL BP0 : STD_LOGIC; | |
86 | SIGNAL BP1 : STD_LOGIC; |
|
86 | SIGNAL BP1 : STD_LOGIC; | |
87 | SIGNAL LED0 : STD_LOGIC; |
|
87 | SIGNAL LED0 : STD_LOGIC; | |
88 | SIGNAL LED1 : STD_LOGIC; |
|
88 | SIGNAL LED1 : STD_LOGIC; | |
89 | SIGNAL LED2 : STD_LOGIC; |
|
89 | SIGNAL LED2 : STD_LOGIC; | |
90 | SIGNAL TXD1 : STD_LOGIC; |
|
90 | SIGNAL TXD1 : STD_LOGIC; | |
91 | SIGNAL RXD1 : STD_LOGIC; |
|
91 | SIGNAL RXD1 : STD_LOGIC; | |
92 | SIGNAL nCTS1 : STD_LOGIC; |
|
92 | SIGNAL nCTS1 : STD_LOGIC; | |
93 | SIGNAL nRTS1 : STD_LOGIC; |
|
93 | SIGNAL nRTS1 : STD_LOGIC; | |
94 | SIGNAL TXD2 : STD_LOGIC; |
|
94 | SIGNAL TXD2 : STD_LOGIC; | |
95 | SIGNAL RXD2 : STD_LOGIC; |
|
95 | SIGNAL RXD2 : STD_LOGIC; | |
96 | SIGNAL nCTS2 : STD_LOGIC; |
|
96 | SIGNAL nCTS2 : STD_LOGIC; | |
97 | SIGNAL nDTR2 : STD_LOGIC; |
|
97 | SIGNAL nDTR2 : STD_LOGIC; | |
98 | SIGNAL nRTS2 : STD_LOGIC; |
|
98 | SIGNAL nRTS2 : STD_LOGIC; | |
99 | SIGNAL nDCD2 : STD_LOGIC; |
|
99 | SIGNAL nDCD2 : STD_LOGIC; | |
100 | SIGNAL IO0 : STD_LOGIC; |
|
100 | SIGNAL IO0 : STD_LOGIC; | |
101 | SIGNAL IO1 : STD_LOGIC; |
|
101 | SIGNAL IO1 : STD_LOGIC; | |
102 | SIGNAL IO2 : STD_LOGIC; |
|
102 | SIGNAL IO2 : STD_LOGIC; | |
103 | SIGNAL IO3 : STD_LOGIC; |
|
103 | SIGNAL IO3 : STD_LOGIC; | |
104 | SIGNAL IO4 : STD_LOGIC; |
|
104 | SIGNAL IO4 : STD_LOGIC; | |
105 | SIGNAL IO5 : STD_LOGIC; |
|
105 | SIGNAL IO5 : STD_LOGIC; | |
106 | SIGNAL IO6 : STD_LOGIC; |
|
106 | SIGNAL IO6 : STD_LOGIC; | |
107 | SIGNAL IO7 : STD_LOGIC; |
|
107 | SIGNAL IO7 : STD_LOGIC; | |
108 | SIGNAL IO8 : STD_LOGIC; |
|
108 | SIGNAL IO8 : STD_LOGIC; | |
109 | SIGNAL IO9 : STD_LOGIC; |
|
109 | SIGNAL IO9 : STD_LOGIC; | |
110 | SIGNAL IO10 : STD_LOGIC; |
|
110 | SIGNAL IO10 : STD_LOGIC; | |
111 | SIGNAL IO11 : STD_LOGIC; |
|
111 | SIGNAL IO11 : STD_LOGIC; | |
112 | SIGNAL SPW_EN : STD_LOGIC; |
|
112 | SIGNAL SPW_EN : STD_LOGIC; | |
113 | SIGNAL SPW_NOM_DIN : STD_LOGIC; |
|
113 | SIGNAL SPW_NOM_DIN : STD_LOGIC; | |
114 | SIGNAL SPW_NOM_SIN : STD_LOGIC; |
|
114 | SIGNAL SPW_NOM_SIN : STD_LOGIC; | |
115 | SIGNAL SPW_NOM_DOUT : STD_LOGIC; |
|
115 | SIGNAL SPW_NOM_DOUT : STD_LOGIC; | |
116 | SIGNAL SPW_NOM_SOUT : STD_LOGIC; |
|
116 | SIGNAL SPW_NOM_SOUT : STD_LOGIC; | |
117 | SIGNAL SPW_RED_DIN : STD_LOGIC; |
|
117 | SIGNAL SPW_RED_DIN : STD_LOGIC; | |
118 | SIGNAL SPW_RED_SIN : STD_LOGIC; |
|
118 | SIGNAL SPW_RED_SIN : STD_LOGIC; | |
119 | SIGNAL SPW_RED_DOUT : STD_LOGIC; |
|
119 | SIGNAL SPW_RED_DOUT : STD_LOGIC; | |
120 | SIGNAL SPW_RED_SOUT : STD_LOGIC; |
|
120 | SIGNAL SPW_RED_SOUT : STD_LOGIC; | |
121 | SIGNAL ADC_nCS : STD_LOGIC; |
|
121 | SIGNAL ADC_nCS : STD_LOGIC; | |
122 | SIGNAL ADC_CLK : STD_LOGIC; |
|
122 | SIGNAL ADC_CLK : STD_LOGIC; | |
123 | SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
123 | SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
124 | SIGNAL SRAM_nWE : STD_LOGIC; |
|
124 | SIGNAL SRAM_nWE : STD_LOGIC; | |
125 | SIGNAL SRAM_CE : STD_LOGIC; |
|
125 | SIGNAL SRAM_CE : STD_LOGIC; | |
126 | SIGNAL SRAM_nOE : STD_LOGIC; |
|
126 | SIGNAL SRAM_nOE : STD_LOGIC; | |
127 | SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
127 | SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
128 | SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
128 | SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0); | |
129 | SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
129 | SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
130 | ----------------------------------------------------------------------------- |
|
130 | ----------------------------------------------------------------------------- | |
131 |
|
131 | |||
132 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; |
|
132 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; | |
133 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; |
|
133 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; | |
134 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; |
|
134 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; | |
135 |
|
135 | |||
136 |
|
136 | |||
137 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; |
|
137 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; | |
138 |
|
||||
139 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; |
|
138 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; | |
140 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); |
|
139 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); | |
141 |
|
140 | |||
142 | BEGIN |
|
141 | BEGIN | |
143 |
|
142 | |||
144 | ----------------------------------------------------------------------------- |
|
143 | ----------------------------------------------------------------------------- | |
145 | -- TB |
|
144 | -- TB | |
146 | ----------------------------------------------------------------------------- |
|
145 | ----------------------------------------------------------------------------- | |
147 | PROCESS |
|
146 | PROCESS | |
148 | CONSTANT txp : TIME := 320 ns; |
|
147 | CONSTANT txp : TIME := 320 ns; | |
149 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
148 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
150 | BEGIN -- PROCESS |
|
149 | BEGIN -- PROCESS | |
151 | TXD1 <= '1'; |
|
150 | TXD1 <= '1'; | |
152 | reset <= '0'; |
|
151 | reset <= '0'; | |
153 | WAIT FOR 500 ns; |
|
152 | WAIT FOR 500 ns; | |
154 | reset <= '1'; |
|
153 | reset <= '1'; | |
155 | WAIT FOR 10000 ns; |
|
154 | WAIT FOR 10000 ns; | |
156 | message_simu <= "0 - UART init "; |
|
155 | message_simu <= "0 - UART init "; | |
157 | UART_INIT(TXD1,txp); |
|
156 | UART_INIT(TXD1,txp); | |
158 |
|
157 | |||
159 | message_simu <= "1 - UART test "; |
|
158 | message_simu <= "1 - UART test "; | |
160 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); |
|
159 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF"); | |
161 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); |
|
160 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A"); | |
162 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); |
|
161 | UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B"); | |
163 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); |
|
162 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v); | |
164 | data_read <= data_read_v; |
|
163 | data_read <= data_read_v; | |
165 | data_message <= "GPIO_data_write"; |
|
164 | data_message <= "GPIO_data_write"; | |
166 |
|
165 | |||
167 | -- UNSET the LFR reset |
|
166 | -- UNSET the LFR reset | |
168 | message_simu <= "2 - LFR UNRESET"; |
|
167 | message_simu <= "2 - LFR UNRESET"; | |
169 | UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); |
|
168 | UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT); | |
170 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); |
|
169 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000"); | |
171 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); |
|
170 | --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000"); | |
172 | -- |
|
171 | -- | |
173 | message_simu <= "3 - LFR CONFIG "; |
|
172 | message_simu <= "3 - LFR CONFIG "; | |
174 | --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); |
|
173 | --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B"); | |
175 | LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, |
|
174 | LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR, | |
176 | X"40000000", |
|
175 | X"40000000", | |
177 | X"40001000", |
|
176 | X"40001000", | |
178 | X"40002000", |
|
177 | X"40002000", | |
179 | X"40003000", |
|
178 | X"40003000", | |
180 | X"40004000", |
|
179 | X"40004000", | |
181 | X"40005000"); |
|
180 | X"40005000"); | |
182 | message_simu <= "4 - GO GO GO !!"; |
|
181 | message_simu <= "4 - GO GO GO !!"; | |
183 | UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); |
|
182 | UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000"); | |
184 |
|
183 | |||
185 | READ_STATUS: LOOP |
|
184 | READ_STATUS: LOOP | |
186 | WAIT FOR 2 ms; |
|
185 | WAIT FOR 2 ms; | |
187 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); |
|
186 | UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
188 | data_read <= data_read_v; |
|
187 | data_read <= data_read_v; | |
189 | data_message <= "READ_NEW_STATUS"; |
|
188 | data_message <= "READ_NEW_STATUS"; | |
190 | UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); |
|
189 | UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v); | |
191 | END LOOP READ_STATUS; |
|
190 | END LOOP READ_STATUS; | |
192 |
|
191 | |||
193 | WAIT; |
|
192 | WAIT; | |
194 | END PROCESS; |
|
193 | END PROCESS; | |
195 |
|
194 | |||
196 | ----------------------------------------------------------------------------- |
|
195 | ----------------------------------------------------------------------------- | |
197 | -- CLOCK |
|
196 | -- CLOCK | |
198 | ----------------------------------------------------------------------------- |
|
197 | ----------------------------------------------------------------------------- | |
199 | clk_50 <= NOT clk_50 AFTER 5 ns; |
|
198 | clk_50 <= NOT clk_50 AFTER 5 ns; | |
200 | clk_49 <= NOT clk_49 AFTER 10172 ps; |
|
199 | clk_49 <= NOT clk_49 AFTER 10172 ps; | |
201 |
|
200 | |||
202 | ----------------------------------------------------------------------------- |
|
201 | ----------------------------------------------------------------------------- | |
203 | -- DON'T CARE |
|
202 | -- DON'T CARE | |
204 | ----------------------------------------------------------------------------- |
|
203 | ----------------------------------------------------------------------------- | |
205 | BP0 <= '0'; |
|
204 | BP0 <= '0'; | |
206 | BP1 <= '0'; |
|
205 | BP1 <= '0'; | |
207 | nRTS1 <= '0' ; |
|
206 | nRTS1 <= '0' ; | |
208 |
|
207 | |||
209 | TXD2 <= '1'; |
|
208 | TXD2 <= '1'; | |
210 | nRTS2 <= '1'; |
|
209 | nRTS2 <= '1'; | |
211 | nDTR2 <= '1'; |
|
210 | nDTR2 <= '1'; | |
212 |
|
211 | |||
213 | SPW_NOM_DIN <= '1'; |
|
212 | SPW_NOM_DIN <= '1'; | |
214 | SPW_NOM_SIN <= '1'; |
|
213 | SPW_NOM_SIN <= '1'; | |
215 | SPW_RED_DIN <= '1'; |
|
214 | SPW_RED_DIN <= '1'; | |
216 | SPW_RED_SIN <= '1'; |
|
215 | SPW_RED_SIN <= '1'; | |
217 |
|
216 | |||
218 | ADC_SDO <= x"AA"; |
|
217 | ADC_SDO <= x"AA"; | |
219 |
|
218 | |||
220 | SRAM_DQ <= (OTHERS => 'Z'); |
|
219 | SRAM_DQ <= (OTHERS => 'Z'); | |
221 | --IO0 <= 'Z'; |
|
220 | --IO0 <= 'Z'; | |
222 | --IO1 <= 'Z'; |
|
221 | --IO1 <= 'Z'; | |
223 | --IO2 <= 'Z'; |
|
222 | --IO2 <= 'Z'; | |
224 | --IO3 <= 'Z'; |
|
223 | --IO3 <= 'Z'; | |
225 | --IO4 <= 'Z'; |
|
224 | --IO4 <= 'Z'; | |
226 | --IO5 <= 'Z'; |
|
225 | --IO5 <= 'Z'; | |
227 | --IO6 <= 'Z'; |
|
226 | --IO6 <= 'Z'; | |
228 | --IO7 <= 'Z'; |
|
227 | --IO7 <= 'Z'; | |
229 | --IO8 <= 'Z'; |
|
228 | --IO8 <= 'Z'; | |
230 | --IO9 <= 'Z'; |
|
229 | --IO9 <= 'Z'; | |
231 | --IO10 <= 'Z'; |
|
230 | --IO10 <= 'Z'; | |
232 | --IO11 <= 'Z'; |
|
231 | --IO11 <= 'Z'; | |
233 |
|
232 | |||
234 | ----------------------------------------------------------------------------- |
|
233 | ----------------------------------------------------------------------------- | |
235 | -- DUT |
|
234 | -- DUT | |
236 | ----------------------------------------------------------------------------- |
|
235 | ----------------------------------------------------------------------------- | |
237 | MINI_LFR_top_1: MINI_LFR_top |
|
236 | MINI_LFR_top_1: MINI_LFR_top | |
238 | PORT MAP ( |
|
237 | PORT MAP ( | |
239 | clk_50 => clk_50, |
|
238 | clk_50 => clk_50, | |
240 | clk_49 => clk_49, |
|
239 | clk_49 => clk_49, | |
241 | reset => reset, |
|
240 | reset => reset, | |
242 |
|
241 | |||
243 | BP0 => BP0, |
|
242 | BP0 => BP0, | |
244 | BP1 => BP1, |
|
243 | BP1 => BP1, | |
245 |
|
244 | |||
246 | LED0 => LED0, |
|
245 | LED0 => LED0, | |
247 | LED1 => LED1, |
|
246 | LED1 => LED1, | |
248 | LED2 => LED2, |
|
247 | LED2 => LED2, | |
249 |
|
248 | |||
250 | TXD1 => TXD1, |
|
249 | TXD1 => TXD1, | |
251 | RXD1 => RXD1, |
|
250 | RXD1 => RXD1, | |
252 | nCTS1 => nCTS1, |
|
251 | nCTS1 => nCTS1, | |
253 | nRTS1 => nRTS1, |
|
252 | nRTS1 => nRTS1, | |
254 |
|
253 | |||
255 | TXD2 => TXD2, |
|
254 | TXD2 => TXD2, | |
256 | RXD2 => RXD2, |
|
255 | RXD2 => RXD2, | |
257 | nCTS2 => nCTS2, |
|
256 | nCTS2 => nCTS2, | |
258 | nDTR2 => nDTR2, |
|
257 | nDTR2 => nDTR2, | |
259 | nRTS2 => nRTS2, |
|
258 | nRTS2 => nRTS2, | |
260 | nDCD2 => nDCD2, |
|
259 | nDCD2 => nDCD2, | |
261 |
|
260 | |||
262 | IO0 => IO0, |
|
261 | IO0 => IO0, | |
263 | IO1 => IO1, |
|
262 | IO1 => IO1, | |
264 | IO2 => IO2, |
|
263 | IO2 => IO2, | |
265 | IO3 => IO3, |
|
264 | IO3 => IO3, | |
266 | IO4 => IO4, |
|
265 | IO4 => IO4, | |
267 | IO5 => IO5, |
|
266 | IO5 => IO5, | |
268 | IO6 => IO6, |
|
267 | IO6 => IO6, | |
269 | IO7 => IO7, |
|
268 | IO7 => IO7, | |
270 | IO8 => IO8, |
|
269 | IO8 => IO8, | |
271 | IO9 => IO9, |
|
270 | IO9 => IO9, | |
272 | IO10 => IO10, |
|
271 | IO10 => IO10, | |
273 | IO11 => IO11, |
|
272 | IO11 => IO11, | |
274 |
|
273 | |||
275 | SPW_EN => SPW_EN, |
|
274 | SPW_EN => SPW_EN, | |
276 | SPW_NOM_DIN => SPW_NOM_DIN, |
|
275 | SPW_NOM_DIN => SPW_NOM_DIN, | |
277 | SPW_NOM_SIN => SPW_NOM_SIN, |
|
276 | SPW_NOM_SIN => SPW_NOM_SIN, | |
278 | SPW_NOM_DOUT => SPW_NOM_DOUT, |
|
277 | SPW_NOM_DOUT => SPW_NOM_DOUT, | |
279 | SPW_NOM_SOUT => SPW_NOM_SOUT, |
|
278 | SPW_NOM_SOUT => SPW_NOM_SOUT, | |
280 | SPW_RED_DIN => SPW_RED_DIN, |
|
279 | SPW_RED_DIN => SPW_RED_DIN, | |
281 | SPW_RED_SIN => SPW_RED_SIN, |
|
280 | SPW_RED_SIN => SPW_RED_SIN, | |
282 | SPW_RED_DOUT => SPW_RED_DOUT, |
|
281 | SPW_RED_DOUT => SPW_RED_DOUT, | |
283 | SPW_RED_SOUT => SPW_RED_SOUT, |
|
282 | SPW_RED_SOUT => SPW_RED_SOUT, | |
284 |
|
283 | |||
285 | ADC_nCS => ADC_nCS, |
|
284 | ADC_nCS => ADC_nCS, | |
286 | ADC_CLK => ADC_CLK, |
|
285 | ADC_CLK => ADC_CLK, | |
287 | ADC_SDO => ADC_SDO, |
|
286 | ADC_SDO => ADC_SDO, | |
288 |
|
287 | |||
289 | SRAM_nWE => SRAM_nWE, |
|
288 | SRAM_nWE => SRAM_nWE, | |
290 | SRAM_CE => SRAM_CE, |
|
289 | SRAM_CE => SRAM_CE, | |
291 | SRAM_nOE => SRAM_nOE, |
|
290 | SRAM_nOE => SRAM_nOE, | |
292 | SRAM_nBE => SRAM_nBE, |
|
291 | SRAM_nBE => SRAM_nBE, | |
293 | SRAM_A => SRAM_A, |
|
292 | SRAM_A => SRAM_A, | |
294 | SRAM_DQ => SRAM_DQ); |
|
293 | SRAM_DQ => SRAM_DQ); | |
295 |
|
294 | |||
296 |
|
295 | |||
297 | END; |
|
296 | END; |
@@ -1,24 +1,46 | |||||
1 | onerror {resume} |
|
1 | onerror {resume} | |
2 | quietly WaveActivateNextPane {} 0 |
|
2 | quietly WaveActivateNextPane {} 0 | |
3 | add wave -noupdate /testbench/message_simu |
|
3 | add wave -noupdate /testbench/message_simu | |
4 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp |
|
4 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -expand -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |
5 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp |
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5 | add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |
6 | add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing |
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6 | add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing | |
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7 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_full | |||
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8 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen | |||
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9 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_write_error | |||
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10 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_data | |||
|
11 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/fsm_state | |||
|
12 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data2 | |||
|
13 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/reg_data | |||
|
14 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full_s | |||
|
15 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/out_wen_s | |||
|
16 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_empty | |||
|
17 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_full | |||
|
18 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_data | |||
|
19 | add wave -noupdate -expand -group FIFO_f1_REG_HEAD /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lpp_lfr_ms_reg_head_1/in_wen | |||
|
20 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/rdata | |||
|
21 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/almost_full | |||
|
22 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/full | |||
|
23 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/empty | |||
|
24 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ren | |||
|
25 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wdata | |||
|
26 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/wen | |||
|
27 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/run | |||
|
28 | add wave -noupdate -expand -group FIFO_f1 /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/lppFIFOxN_f1/ReUse | |||
7 | TreeUpdate [SetDefaultTree] |
|
29 | TreeUpdate [SetDefaultTree] | |
8 | WaveRestoreCursors {{Cursor 1} {11527482482 ps} 0} |
|
30 | WaveRestoreCursors {{Cursor 1} {63830825000 ps} 0} {{Cursor 2} {126327585000 ps} 0} {{Cursor 3} {188824345000 ps} 0} | |
9 |
quietly wave cursor active |
|
31 | quietly wave cursor active 3 | |
10 |
configure wave -namecolwidth 5 |
|
32 | configure wave -namecolwidth 510 | |
11 | configure wave -valuecolwidth 100 |
|
33 | configure wave -valuecolwidth 100 | |
12 | configure wave -justifyvalue left |
|
34 | configure wave -justifyvalue left | |
13 | configure wave -signalnamewidth 0 |
|
35 | configure wave -signalnamewidth 0 | |
14 | configure wave -snapdistance 10 |
|
36 | configure wave -snapdistance 10 | |
15 | configure wave -datasetprefix 0 |
|
37 | configure wave -datasetprefix 0 | |
16 | configure wave -rowmargin 4 |
|
38 | configure wave -rowmargin 4 | |
17 | configure wave -childrowmargin 2 |
|
39 | configure wave -childrowmargin 2 | |
18 | configure wave -gridoffset 0 |
|
40 | configure wave -gridoffset 0 | |
19 | configure wave -gridperiod 1 |
|
41 | configure wave -gridperiod 1 | |
20 | configure wave -griddelta 40 |
|
42 | configure wave -griddelta 40 | |
21 | configure wave -timeline 0 |
|
43 | configure wave -timeline 0 | |
22 | configure wave -timelineunits ns |
|
44 | configure wave -timelineunits ns | |
23 | update |
|
45 | update | |
24 |
WaveRestoreZoom {0 ps} { |
|
46 | WaveRestoreZoom {0 ps} {243397377300 ps} |
@@ -1,1214 +1,1214 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 | USE ieee.numeric_std.ALL; |
|
3 | USE ieee.numeric_std.ALL; | |
4 |
|
4 | |||
5 |
|
5 | |||
6 | LIBRARY lpp; |
|
6 | LIBRARY lpp; | |
7 | USE lpp.lpp_memory.ALL; |
|
7 | USE lpp.lpp_memory.ALL; | |
8 | USE lpp.iir_filter.ALL; |
|
8 | USE lpp.iir_filter.ALL; | |
9 | USE lpp.spectral_matrix_package.ALL; |
|
9 | USE lpp.spectral_matrix_package.ALL; | |
10 | USE lpp.lpp_dma_pkg.ALL; |
|
10 | USE lpp.lpp_dma_pkg.ALL; | |
11 | USE lpp.lpp_Header.ALL; |
|
11 | USE lpp.lpp_Header.ALL; | |
12 | USE lpp.lpp_matrix.ALL; |
|
12 | USE lpp.lpp_matrix.ALL; | |
13 | USE lpp.lpp_matrix.ALL; |
|
13 | USE lpp.lpp_matrix.ALL; | |
14 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | USE lpp.lpp_lfr_pkg.ALL; | |
15 | USE lpp.lpp_fft.ALL; |
|
15 | USE lpp.lpp_fft.ALL; | |
16 | USE lpp.fft_components.ALL; |
|
16 | USE lpp.fft_components.ALL; | |
17 |
|
17 | |||
18 | ENTITY lpp_lfr_ms IS |
|
18 | ENTITY lpp_lfr_ms IS | |
19 | GENERIC ( |
|
19 | GENERIC ( | |
20 | Mem_use : INTEGER := use_RAM |
|
20 | Mem_use : INTEGER := use_RAM | |
21 | ); |
|
21 | ); | |
22 | PORT ( |
|
22 | PORT ( | |
23 | clk : IN STD_LOGIC; |
|
23 | clk : IN STD_LOGIC; | |
24 | rstn : IN STD_LOGIC; |
|
24 | rstn : IN STD_LOGIC; | |
25 | run : IN STD_LOGIC; |
|
25 | run : IN STD_LOGIC; | |
26 |
|
26 | |||
27 | --------------------------------------------------------------------------- |
|
27 | --------------------------------------------------------------------------- | |
28 | -- DATA INPUT |
|
28 | -- DATA INPUT | |
29 | --------------------------------------------------------------------------- |
|
29 | --------------------------------------------------------------------------- | |
30 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
30 | start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); | |
31 | -- TIME |
|
31 | -- TIME | |
32 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
|
32 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo | |
33 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
|
33 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo | |
34 | -- |
|
34 | -- | |
35 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
35 | sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
36 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
36 | sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
37 | -- |
|
37 | -- | |
38 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
38 | sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
39 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
39 | sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
40 | -- |
|
40 | -- | |
41 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
41 | sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0); | |
42 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
42 | sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
43 |
|
43 | |||
44 | --------------------------------------------------------------------------- |
|
44 | --------------------------------------------------------------------------- | |
45 | -- DMA |
|
45 | -- DMA | |
46 | --------------------------------------------------------------------------- |
|
46 | --------------------------------------------------------------------------- | |
47 | dma_fifo_burst_valid: OUT STD_LOGIC; --TODO |
|
47 | dma_fifo_burst_valid: OUT STD_LOGIC; --TODO | |
48 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
48 | dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
49 | dma_fifo_ren : IN STD_LOGIC; --TODO |
|
49 | dma_fifo_ren : IN STD_LOGIC; --TODO | |
50 | dma_buffer_new : OUT STD_LOGIC; --TODOx |
|
50 | dma_buffer_new : OUT STD_LOGIC; --TODOx | |
51 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
51 | dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
52 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO |
|
52 | dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO | |
53 | dma_buffer_full : IN STD_LOGIC; --TODO |
|
53 | dma_buffer_full : IN STD_LOGIC; --TODO | |
54 | dma_buffer_full_err : IN STD_LOGIC; --TODO |
|
54 | dma_buffer_full_err : IN STD_LOGIC; --TODO | |
55 |
|
55 | |||
56 | -- Reg out |
|
56 | -- Reg out | |
57 | ready_matrix_f0 : OUT STD_LOGIC; -- TODO |
|
57 | ready_matrix_f0 : OUT STD_LOGIC; -- TODO | |
58 | ready_matrix_f1 : OUT STD_LOGIC; -- TODO |
|
58 | ready_matrix_f1 : OUT STD_LOGIC; -- TODO | |
59 | ready_matrix_f2 : OUT STD_LOGIC; -- TODO |
|
59 | ready_matrix_f2 : OUT STD_LOGIC; -- TODO | |
60 | -- error_bad_component_error : OUT STD_LOGIC; -- TODO |
|
60 | -- error_bad_component_error : OUT STD_LOGIC; -- TODO | |
61 | error_buffer_full : OUT STD_LOGIC; -- TODO |
|
61 | error_buffer_full : OUT STD_LOGIC; -- TODO | |
62 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
62 | error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0); | |
63 |
|
63 | |||
64 | -- Reg In |
|
64 | -- Reg In | |
65 | status_ready_matrix_f0 : IN STD_LOGIC; -- TODO |
|
65 | status_ready_matrix_f0 : IN STD_LOGIC; -- TODO | |
66 | status_ready_matrix_f1 : IN STD_LOGIC; -- TODO |
|
66 | status_ready_matrix_f1 : IN STD_LOGIC; -- TODO | |
67 | status_ready_matrix_f2 : IN STD_LOGIC; -- TODO |
|
67 | status_ready_matrix_f2 : IN STD_LOGIC; -- TODO | |
68 |
|
68 | |||
69 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
69 | addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
70 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
70 | addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
71 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
71 | addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
72 |
|
72 | |||
73 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
73 | length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
74 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
74 | length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
75 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO |
|
75 | length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO | |
76 |
|
76 | |||
77 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
77 | matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
78 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
78 | matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
79 | matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
80 | --------------------------------------------------------------------------- |
|
80 | --------------------------------------------------------------------------- | |
81 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
81 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
82 | ); |
|
82 | ); | |
83 | END; |
|
83 | END; | |
84 |
|
84 | |||
85 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS |
|
85 | ARCHITECTURE Behavioral OF lpp_lfr_ms IS | |
86 |
|
86 | |||
87 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
87 | SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
88 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
88 | SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
89 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
89 | SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
90 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
90 | SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
91 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
91 | SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
92 |
|
92 | |||
93 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
93 | SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
94 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
94 | SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
95 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
95 | SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
96 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
96 | SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
97 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
97 | SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
98 |
|
98 | |||
99 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
99 | SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
100 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
100 | SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
101 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
101 | SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
102 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
102 | SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
103 |
|
103 | |||
104 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
104 | SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
105 |
|
105 | |||
106 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
106 | SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
107 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
107 | SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
108 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
108 | SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
109 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
109 | SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
110 |
|
110 | |||
111 | SIGNAL error_wen_f0 : STD_LOGIC; |
|
111 | SIGNAL error_wen_f0 : STD_LOGIC; | |
112 | SIGNAL error_wen_f1 : STD_LOGIC; |
|
112 | SIGNAL error_wen_f1 : STD_LOGIC; | |
113 | SIGNAL error_wen_f2 : STD_LOGIC; |
|
113 | SIGNAL error_wen_f2 : STD_LOGIC; | |
114 |
|
114 | |||
115 | SIGNAL one_sample_f1_full : STD_LOGIC; |
|
115 | SIGNAL one_sample_f1_full : STD_LOGIC; | |
116 | SIGNAL one_sample_f1_wen : STD_LOGIC; |
|
116 | SIGNAL one_sample_f1_wen : STD_LOGIC; | |
117 | SIGNAL one_sample_f2_full : STD_LOGIC; |
|
117 | SIGNAL one_sample_f2_full : STD_LOGIC; | |
118 | SIGNAL one_sample_f2_wen : STD_LOGIC; |
|
118 | SIGNAL one_sample_f2_wen : STD_LOGIC; | |
119 |
|
119 | |||
120 | ----------------------------------------------------------------------------- |
|
120 | ----------------------------------------------------------------------------- | |
121 | -- FSM / SWITCH SELECT CHANNEL |
|
121 | -- FSM / SWITCH SELECT CHANNEL | |
122 | ----------------------------------------------------------------------------- |
|
122 | ----------------------------------------------------------------------------- | |
123 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); |
|
123 | TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2); | |
124 | SIGNAL state_fsm_select_channel : fsm_select_channel; |
|
124 | SIGNAL state_fsm_select_channel : fsm_select_channel; | |
125 | -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel; |
|
125 | -- SIGNAL pre_state_fsm_select_channel : fsm_select_channel; | |
126 | SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
126 | SIGNAL select_channel : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
127 | SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
127 | SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
128 |
|
128 | |||
129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
129 | SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
130 | SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
131 | SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
132 | SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
133 |
|
133 | |||
134 | ----------------------------------------------------------------------------- |
|
134 | ----------------------------------------------------------------------------- | |
135 | -- FSM LOAD FFT |
|
135 | -- FSM LOAD FFT | |
136 | ----------------------------------------------------------------------------- |
|
136 | ----------------------------------------------------------------------------- | |
137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); |
|
137 | TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); | |
138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; |
|
138 | SIGNAL state_fsm_load_FFT : fsm_load_FFT; | |
139 | -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; |
|
139 | -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; | |
140 | SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
140 | SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
141 | SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0); |
|
141 | SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0); | |
142 |
|
142 | |||
143 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
143 | SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
144 | SIGNAL sample_load : STD_LOGIC; |
|
144 | SIGNAL sample_load : STD_LOGIC; | |
145 | SIGNAL sample_valid : STD_LOGIC; |
|
145 | SIGNAL sample_valid : STD_LOGIC; | |
146 | SIGNAL sample_valid_r : STD_LOGIC; |
|
146 | SIGNAL sample_valid_r : STD_LOGIC; | |
147 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
147 | SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
148 |
|
148 | |||
149 |
|
149 | |||
150 | ----------------------------------------------------------------------------- |
|
150 | ----------------------------------------------------------------------------- | |
151 | -- FFT |
|
151 | -- FFT | |
152 | ----------------------------------------------------------------------------- |
|
152 | ----------------------------------------------------------------------------- | |
153 | SIGNAL fft_read : STD_LOGIC; |
|
153 | SIGNAL fft_read : STD_LOGIC; | |
154 | SIGNAL fft_pong : STD_LOGIC; |
|
154 | SIGNAL fft_pong : STD_LOGIC; | |
155 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
155 | SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
156 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
156 | SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
157 | SIGNAL fft_data_valid : STD_LOGIC; |
|
157 | SIGNAL fft_data_valid : STD_LOGIC; | |
158 | SIGNAL fft_ready : STD_LOGIC; |
|
158 | SIGNAL fft_ready : STD_LOGIC; | |
159 | ----------------------------------------------------------------------------- |
|
159 | ----------------------------------------------------------------------------- | |
160 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
160 | -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
161 | ----------------------------------------------------------------------------- |
|
161 | ----------------------------------------------------------------------------- | |
162 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); |
|
162 | TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT); | |
163 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; |
|
163 | SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory; | |
164 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
164 | SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
165 | SIGNAL current_fifo_empty : STD_LOGIC; |
|
165 | SIGNAL current_fifo_empty : STD_LOGIC; | |
166 | SIGNAL current_fifo_locked : STD_LOGIC; |
|
166 | SIGNAL current_fifo_locked : STD_LOGIC; | |
167 | SIGNAL current_fifo_full : STD_LOGIC; |
|
167 | SIGNAL current_fifo_full : STD_LOGIC; | |
168 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
168 | SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
169 |
|
169 | |||
170 | ----------------------------------------------------------------------------- |
|
170 | ----------------------------------------------------------------------------- | |
171 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
171 | SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
172 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
172 | SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
173 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
173 | SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
174 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
174 | SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
175 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
175 | SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
176 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); |
|
176 | SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0); | |
177 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
177 | SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
178 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
178 | SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
179 | ----------------------------------------------------------------------------- |
|
179 | ----------------------------------------------------------------------------- | |
180 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); |
|
180 | SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0); | |
181 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
181 | SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
182 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
182 | SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
183 |
|
183 | |||
184 | SIGNAL SM_correlation_start : STD_LOGIC; |
|
184 | SIGNAL SM_correlation_start : STD_LOGIC; | |
185 | SIGNAL SM_correlation_auto : STD_LOGIC; |
|
185 | SIGNAL SM_correlation_auto : STD_LOGIC; | |
186 | SIGNAL SM_correlation_done : STD_LOGIC; |
|
186 | SIGNAL SM_correlation_done : STD_LOGIC; | |
187 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; |
|
187 | SIGNAL SM_correlation_done_reg1 : STD_LOGIC; | |
188 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; |
|
188 | SIGNAL SM_correlation_done_reg2 : STD_LOGIC; | |
189 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; |
|
189 | SIGNAL SM_correlation_done_reg3 : STD_LOGIC; | |
190 | SIGNAL SM_correlation_begin : STD_LOGIC; |
|
190 | SIGNAL SM_correlation_begin : STD_LOGIC; | |
191 |
|
191 | |||
192 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; |
|
192 | SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC; | |
193 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
193 | SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
194 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; |
|
194 | SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC; | |
195 |
|
195 | |||
196 | SIGNAL current_matrix_write : STD_LOGIC; |
|
196 | SIGNAL current_matrix_write : STD_LOGIC; | |
197 | SIGNAL current_matrix_wait_empty : STD_LOGIC; |
|
197 | SIGNAL current_matrix_wait_empty : STD_LOGIC; | |
198 | ----------------------------------------------------------------------------- |
|
198 | ----------------------------------------------------------------------------- | |
199 | SIGNAL fifo_0_ready : STD_LOGIC; |
|
199 | SIGNAL fifo_0_ready : STD_LOGIC; | |
200 | SIGNAL fifo_1_ready : STD_LOGIC; |
|
200 | SIGNAL fifo_1_ready : STD_LOGIC; | |
201 | SIGNAL fifo_ongoing : STD_LOGIC; |
|
201 | SIGNAL fifo_ongoing : STD_LOGIC; | |
202 |
|
202 | |||
203 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; |
|
203 | SIGNAL FSM_DMA_fifo_ren : STD_LOGIC; | |
204 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; |
|
204 | SIGNAL FSM_DMA_fifo_empty : STD_LOGIC; | |
205 | SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; |
|
205 | SIGNAL FSM_DMA_fifo_empty_threshold : STD_LOGIC; | |
206 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
206 | SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
207 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4); |
|
207 | SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
208 | ----------------------------------------------------------------------------- |
|
208 | ----------------------------------------------------------------------------- | |
209 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
209 | SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
210 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
210 | SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
211 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
211 | SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
212 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); |
|
212 | SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0); | |
213 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
213 | SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
214 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
214 | SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
215 | SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
215 | SIGNAL MEM_OUT_SM_Empty_Threshold : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
216 |
|
216 | |||
217 | ----------------------------------------------------------------------------- |
|
217 | ----------------------------------------------------------------------------- | |
218 | -- TIME REG & INFOs |
|
218 | -- TIME REG & INFOs | |
219 | ----------------------------------------------------------------------------- |
|
219 | ----------------------------------------------------------------------------- | |
220 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
220 | SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
221 |
|
221 | |||
222 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
222 | SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
223 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
223 | SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
224 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
224 | SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
225 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
225 | SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
226 |
|
226 | |||
227 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
227 | SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
228 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
228 | SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
229 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
229 | SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
230 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
230 | SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
231 |
|
231 | |||
232 | --SIGNAL time_update_f0_A : STD_LOGIC; |
|
232 | --SIGNAL time_update_f0_A : STD_LOGIC; | |
233 | --SIGNAL time_update_f0_B : STD_LOGIC; |
|
233 | --SIGNAL time_update_f0_B : STD_LOGIC; | |
234 | --SIGNAL time_update_f1 : STD_LOGIC; |
|
234 | --SIGNAL time_update_f1 : STD_LOGIC; | |
235 | --SIGNAL time_update_f2 : STD_LOGIC; |
|
235 | --SIGNAL time_update_f2 : STD_LOGIC; | |
236 | -- |
|
236 | -- | |
237 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
237 | SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
238 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); |
|
238 | SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0); | |
239 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); |
|
239 | SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0); | |
240 |
|
240 | |||
241 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4); |
|
241 | SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
242 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4); |
|
242 | SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 4); | |
243 | SIGNAL status_component_fifo_0_end : STD_LOGIC; |
|
243 | SIGNAL status_component_fifo_0_end : STD_LOGIC; | |
244 | SIGNAL status_component_fifo_1_end : STD_LOGIC; |
|
244 | SIGNAL status_component_fifo_1_end : STD_LOGIC; | |
245 | ----------------------------------------------------------------------------- |
|
245 | ----------------------------------------------------------------------------- | |
246 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); |
|
246 | SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0); | |
247 |
|
247 | |||
248 | SIGNAL fft_ready_reg : STD_LOGIC; |
|
248 | SIGNAL fft_ready_reg : STD_LOGIC; | |
249 | SIGNAL fft_ready_rising_down : STD_LOGIC; |
|
249 | SIGNAL fft_ready_rising_down : STD_LOGIC; | |
250 |
|
250 | |||
251 | SIGNAL sample_load_reg : STD_LOGIC; |
|
251 | SIGNAL sample_load_reg : STD_LOGIC; | |
252 | SIGNAL sample_load_rising_down : STD_LOGIC; |
|
252 | SIGNAL sample_load_rising_down : STD_LOGIC; | |
253 |
|
253 | |||
254 | ----------------------------------------------------------------------------- |
|
254 | ----------------------------------------------------------------------------- | |
255 | SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
255 | SIGNAL sample_f1_wen_head : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
256 | SIGNAL sample_f1_wen_head_in : STD_LOGIC; |
|
256 | SIGNAL sample_f1_wen_head_in : STD_LOGIC; | |
257 | SIGNAL sample_f1_wen_head_out : STD_LOGIC; |
|
257 | SIGNAL sample_f1_wen_head_out : STD_LOGIC; | |
258 | SIGNAL sample_f1_full_head_in : STD_LOGIC; |
|
258 | SIGNAL sample_f1_full_head_in : STD_LOGIC; | |
259 | SIGNAL sample_f1_full_head_out : STD_LOGIC; |
|
259 | SIGNAL sample_f1_full_head_out : STD_LOGIC; | |
260 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; |
|
260 | SIGNAL sample_f1_empty_head_in : STD_LOGIC; | |
261 |
|
261 | |||
262 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
|
262 | SIGNAL sample_f1_wdata_head : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
263 | ----------------------------------------------------------------------------- |
|
263 | ----------------------------------------------------------------------------- | |
264 | SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
264 | SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
265 | SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
265 | SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
266 | SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); |
|
266 | SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
267 | SIGNAL ongoing : STD_LOGIC; |
|
267 | SIGNAL ongoing : STD_LOGIC; | |
268 |
|
268 | |||
269 | BEGIN |
|
269 | BEGIN | |
270 |
|
270 | |||
271 | PROCESS (clk, rstn) |
|
271 | PROCESS (clk, rstn) | |
272 | BEGIN -- PROCESS |
|
272 | BEGIN -- PROCESS | |
273 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
273 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
274 | sample_f0_wen_s <= (OTHERS => '1'); |
|
274 | sample_f0_wen_s <= (OTHERS => '1'); | |
275 | sample_f1_wen_s <= (OTHERS => '1'); |
|
275 | sample_f1_wen_s <= (OTHERS => '1'); | |
276 | sample_f2_wen_s <= (OTHERS => '1'); |
|
276 | sample_f2_wen_s <= (OTHERS => '1'); | |
277 | ongoing <= '0'; |
|
277 | ongoing <= '0'; | |
278 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
278 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |
279 | IF ongoing = '1' THEN |
|
279 | IF ongoing = '1' THEN | |
280 | sample_f0_wen_s <= sample_f0_wen; |
|
280 | sample_f0_wen_s <= sample_f0_wen; | |
281 | sample_f1_wen_s <= sample_f1_wen; |
|
281 | sample_f1_wen_s <= sample_f1_wen; | |
282 | sample_f2_wen_s <= sample_f2_wen; |
|
282 | sample_f2_wen_s <= sample_f2_wen; | |
283 | ELSE |
|
283 | ELSE | |
284 | IF start_date = coarse_time(30 DOWNTO 0) THEN |
|
284 | IF start_date = coarse_time(30 DOWNTO 0) THEN | |
285 | ongoing <= '1'; |
|
285 | ongoing <= '1'; | |
286 | END IF; |
|
286 | END IF; | |
287 | sample_f0_wen_s <= (OTHERS => '1'); |
|
287 | sample_f0_wen_s <= (OTHERS => '1'); | |
288 | sample_f1_wen_s <= (OTHERS => '1'); |
|
288 | sample_f1_wen_s <= (OTHERS => '1'); | |
289 | sample_f2_wen_s <= (OTHERS => '1'); |
|
289 | sample_f2_wen_s <= (OTHERS => '1'); | |
290 | END IF; |
|
290 | END IF; | |
291 | END IF; |
|
291 | END IF; | |
292 | END PROCESS; |
|
292 | END PROCESS; | |
293 |
|
293 | |||
294 |
|
294 | |||
295 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; |
|
295 | error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0; | |
296 |
|
296 | |||
297 |
|
297 | |||
298 | switch_f0_inst : spectral_matrix_switch_f0 |
|
298 | switch_f0_inst : spectral_matrix_switch_f0 | |
299 | PORT MAP ( |
|
299 | PORT MAP ( | |
300 | clk => clk, |
|
300 | clk => clk, | |
301 | rstn => rstn, |
|
301 | rstn => rstn, | |
302 |
|
302 | |||
303 | sample_wen => sample_f0_wen_s, |
|
303 | sample_wen => sample_f0_wen_s, | |
304 |
|
304 | |||
305 | fifo_A_empty => sample_f0_A_empty, |
|
305 | fifo_A_empty => sample_f0_A_empty, | |
306 | fifo_A_full => sample_f0_A_full, |
|
306 | fifo_A_full => sample_f0_A_full, | |
307 | fifo_A_wen => sample_f0_A_wen, |
|
307 | fifo_A_wen => sample_f0_A_wen, | |
308 |
|
308 | |||
309 | fifo_B_empty => sample_f0_B_empty, |
|
309 | fifo_B_empty => sample_f0_B_empty, | |
310 | fifo_B_full => sample_f0_B_full, |
|
310 | fifo_B_full => sample_f0_B_full, | |
311 | fifo_B_wen => sample_f0_B_wen, |
|
311 | fifo_B_wen => sample_f0_B_wen, | |
312 |
|
312 | |||
313 | error_wen => error_wen_f0); -- TODO |
|
313 | error_wen => error_wen_f0); -- TODO | |
314 |
|
314 | |||
315 | ----------------------------------------------------------------------------- |
|
315 | ----------------------------------------------------------------------------- | |
316 | -- FIFO IN |
|
316 | -- FIFO IN | |
317 | ----------------------------------------------------------------------------- |
|
317 | ----------------------------------------------------------------------------- | |
318 | lppFIFOxN_f0_a : lppFIFOxN |
|
318 | lppFIFOxN_f0_a : lppFIFOxN | |
319 | GENERIC MAP ( |
|
319 | GENERIC MAP ( | |
320 | tech => 0, |
|
320 | tech => 0, | |
321 | Mem_use => Mem_use, |
|
321 | Mem_use => Mem_use, | |
322 | Data_sz => 16, |
|
322 | Data_sz => 16, | |
323 | Addr_sz => 8, |
|
323 | Addr_sz => 8, | |
324 | FifoCnt => 5) |
|
324 | FifoCnt => 5) | |
325 | PORT MAP ( |
|
325 | PORT MAP ( | |
326 | clk => clk, |
|
326 | clk => clk, | |
327 | rstn => rstn, |
|
327 | rstn => rstn, | |
328 |
|
328 | |||
329 | ReUse => (OTHERS => '0'), |
|
329 | ReUse => (OTHERS => '0'), | |
330 |
|
330 | |||
331 | run => (OTHERS => '1'), |
|
331 | run => (OTHERS => '1'), | |
332 |
|
332 | |||
333 | wen => sample_f0_A_wen, |
|
333 | wen => sample_f0_A_wen, | |
334 | wdata => sample_f0_wdata, |
|
334 | wdata => sample_f0_wdata, | |
335 |
|
335 | |||
336 | ren => sample_f0_A_ren, |
|
336 | ren => sample_f0_A_ren, | |
337 | rdata => sample_f0_A_rdata, |
|
337 | rdata => sample_f0_A_rdata, | |
338 |
|
338 | |||
339 | empty => sample_f0_A_empty, |
|
339 | empty => sample_f0_A_empty, | |
340 | full => sample_f0_A_full, |
|
340 | full => sample_f0_A_full, | |
341 | almost_full => OPEN); |
|
341 | almost_full => OPEN); | |
342 |
|
342 | |||
343 | lppFIFOxN_f0_b : lppFIFOxN |
|
343 | lppFIFOxN_f0_b : lppFIFOxN | |
344 | GENERIC MAP ( |
|
344 | GENERIC MAP ( | |
345 | tech => 0, |
|
345 | tech => 0, | |
346 | Mem_use => Mem_use, |
|
346 | Mem_use => Mem_use, | |
347 | Data_sz => 16, |
|
347 | Data_sz => 16, | |
348 | Addr_sz => 8, |
|
348 | Addr_sz => 8, | |
349 | FifoCnt => 5) |
|
349 | FifoCnt => 5) | |
350 | PORT MAP ( |
|
350 | PORT MAP ( | |
351 | clk => clk, |
|
351 | clk => clk, | |
352 | rstn => rstn, |
|
352 | rstn => rstn, | |
353 |
|
353 | |||
354 | ReUse => (OTHERS => '0'), |
|
354 | ReUse => (OTHERS => '0'), | |
355 | run => (OTHERS => '1'), |
|
355 | run => (OTHERS => '1'), | |
356 |
|
356 | |||
357 | wen => sample_f0_B_wen, |
|
357 | wen => sample_f0_B_wen, | |
358 | wdata => sample_f0_wdata, |
|
358 | wdata => sample_f0_wdata, | |
359 | ren => sample_f0_B_ren, |
|
359 | ren => sample_f0_B_ren, | |
360 | rdata => sample_f0_B_rdata, |
|
360 | rdata => sample_f0_B_rdata, | |
361 | empty => sample_f0_B_empty, |
|
361 | empty => sample_f0_B_empty, | |
362 | full => sample_f0_B_full, |
|
362 | full => sample_f0_B_full, | |
363 | almost_full => OPEN); |
|
363 | almost_full => OPEN); | |
364 |
|
364 | |||
365 | ----------------------------------------------------------------------------- |
|
365 | ----------------------------------------------------------------------------- | |
366 | -- sample_f1_wen in |
|
366 | -- sample_f1_wen in | |
367 | -- sample_f1_wdata in |
|
367 | -- sample_f1_wdata in | |
368 | -- sample_f1_full OUT |
|
368 | -- sample_f1_full OUT | |
369 |
|
369 | |||
370 |
sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s |
|
370 | sample_f1_wen_head_in <= '0' WHEN sample_f1_wen_s = "00000" ELSE '1'; | |
371 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; |
|
371 | sample_f1_full_head_in <= '0' WHEN sample_f1_full = "00000" ELSE '1'; | |
372 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
372 | sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
373 |
|
373 | |||
374 | lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head |
|
374 | lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head | |
375 | PORT MAP ( |
|
375 | PORT MAP ( | |
376 | clk => clk, |
|
376 | clk => clk, | |
377 | rstn => rstn, |
|
377 | rstn => rstn, | |
378 | in_wen => sample_f1_wen_head_in, |
|
378 | in_wen => sample_f1_wen_head_in, | |
379 | in_data => sample_f1_wdata, |
|
379 | in_data => sample_f1_wdata, | |
380 | in_full => sample_f1_full_head_in, |
|
380 | in_full => sample_f1_full_head_in, | |
381 | in_empty => sample_f1_empty_head_in, |
|
381 | in_empty => sample_f1_empty_head_in, | |
382 | out_write_error => error_wen_f1, |
|
382 | out_write_error => error_wen_f1, | |
383 | out_wen => sample_f1_wen_head_out, |
|
383 | out_wen => sample_f1_wen_head_out, | |
384 | out_data => sample_f1_wdata_head, |
|
384 | out_data => sample_f1_wdata_head, | |
385 | out_full => sample_f1_full_head_out); |
|
385 | out_full => sample_f1_full_head_out); | |
386 |
|
386 | |||
387 | sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; |
|
387 | sample_f1_wen_head <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out; | |
388 |
|
388 | |||
389 |
|
389 | |||
390 | lppFIFOxN_f1 : lppFIFOxN |
|
390 | lppFIFOxN_f1 : lppFIFOxN | |
391 | GENERIC MAP ( |
|
391 | GENERIC MAP ( | |
392 | tech => 0, |
|
392 | tech => 0, | |
393 | Mem_use => Mem_use, |
|
393 | Mem_use => Mem_use, | |
394 | Data_sz => 16, |
|
394 | Data_sz => 16, | |
395 | Addr_sz => 8, |
|
395 | Addr_sz => 8, | |
396 | FifoCnt => 5) |
|
396 | FifoCnt => 5) | |
397 | PORT MAP ( |
|
397 | PORT MAP ( | |
398 | clk => clk, |
|
398 | clk => clk, | |
399 | rstn => rstn, |
|
399 | rstn => rstn, | |
400 |
|
400 | |||
401 | ReUse => (OTHERS => '0'), |
|
401 | ReUse => (OTHERS => '0'), | |
402 | run => (OTHERS => '1'), |
|
402 | run => (OTHERS => '1'), | |
403 |
|
403 | |||
404 | wen => sample_f1_wen_head, |
|
404 | wen => sample_f1_wen_head, | |
405 | wdata => sample_f1_wdata_head, |
|
405 | wdata => sample_f1_wdata_head, | |
406 | ren => sample_f1_ren, |
|
406 | ren => sample_f1_ren, | |
407 | rdata => sample_f1_rdata, |
|
407 | rdata => sample_f1_rdata, | |
408 | empty => sample_f1_empty, |
|
408 | empty => sample_f1_empty, | |
409 | full => sample_f1_full, |
|
409 | full => sample_f1_full, | |
410 | almost_full => sample_f1_almost_full); |
|
410 | almost_full => sample_f1_almost_full); | |
411 |
|
411 | |||
412 |
|
412 | |||
413 | one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1'; |
|
413 | one_sample_f1_wen <= '0' WHEN sample_f1_wen_head = "11111" ELSE '1'; | |
414 |
|
414 | |||
415 | PROCESS (clk, rstn) |
|
415 | PROCESS (clk, rstn) | |
416 | BEGIN -- PROCESS |
|
416 | BEGIN -- PROCESS | |
417 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
417 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
418 | one_sample_f1_full <= '0'; |
|
418 | one_sample_f1_full <= '0'; | |
419 | --error_wen_f1 <= '0'; |
|
419 | --error_wen_f1 <= '0'; | |
420 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
420 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
421 | IF sample_f1_full_head_out = '0' THEN |
|
421 | IF sample_f1_full_head_out = '0' THEN | |
422 | one_sample_f1_full <= '0'; |
|
422 | one_sample_f1_full <= '0'; | |
423 | ELSE |
|
423 | ELSE | |
424 | one_sample_f1_full <= '1'; |
|
424 | one_sample_f1_full <= '1'; | |
425 | END IF; |
|
425 | END IF; | |
426 | --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; |
|
426 | --error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full; | |
427 | END IF; |
|
427 | END IF; | |
428 | END PROCESS; |
|
428 | END PROCESS; | |
429 |
|
429 | |||
430 | ----------------------------------------------------------------------------- |
|
430 | ----------------------------------------------------------------------------- | |
431 |
|
431 | |||
432 |
|
432 | |||
433 | lppFIFOxN_f2 : lppFIFOxN |
|
433 | lppFIFOxN_f2 : lppFIFOxN | |
434 | GENERIC MAP ( |
|
434 | GENERIC MAP ( | |
435 | tech => 0, |
|
435 | tech => 0, | |
436 | Mem_use => Mem_use, |
|
436 | Mem_use => Mem_use, | |
437 | Data_sz => 16, |
|
437 | Data_sz => 16, | |
438 | Addr_sz => 8, |
|
438 | Addr_sz => 8, | |
439 | FifoCnt => 5) |
|
439 | FifoCnt => 5) | |
440 | PORT MAP ( |
|
440 | PORT MAP ( | |
441 | clk => clk, |
|
441 | clk => clk, | |
442 | rstn => rstn, |
|
442 | rstn => rstn, | |
443 |
|
443 | |||
444 | ReUse => (OTHERS => '0'), |
|
444 | ReUse => (OTHERS => '0'), | |
445 | run => (OTHERS => '1'), |
|
445 | run => (OTHERS => '1'), | |
446 |
|
446 | |||
447 | wen => sample_f2_wen_s, |
|
447 | wen => sample_f2_wen_s, | |
448 | wdata => sample_f2_wdata, |
|
448 | wdata => sample_f2_wdata, | |
449 | ren => sample_f2_ren, |
|
449 | ren => sample_f2_ren, | |
450 | rdata => sample_f2_rdata, |
|
450 | rdata => sample_f2_rdata, | |
451 | empty => sample_f2_empty, |
|
451 | empty => sample_f2_empty, | |
452 | full => sample_f2_full, |
|
452 | full => sample_f2_full, | |
453 | almost_full => OPEN); |
|
453 | almost_full => OPEN); | |
454 |
|
454 | |||
455 |
|
455 | |||
456 | one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1'; |
|
456 | one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1'; | |
457 |
|
457 | |||
458 | PROCESS (clk, rstn) |
|
458 | PROCESS (clk, rstn) | |
459 | BEGIN -- PROCESS |
|
459 | BEGIN -- PROCESS | |
460 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
460 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
461 | one_sample_f2_full <= '0'; |
|
461 | one_sample_f2_full <= '0'; | |
462 | error_wen_f2 <= '0'; |
|
462 | error_wen_f2 <= '0'; | |
463 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
463 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
464 | IF sample_f2_full = "00000" THEN |
|
464 | IF sample_f2_full = "00000" THEN | |
465 | one_sample_f2_full <= '0'; |
|
465 | one_sample_f2_full <= '0'; | |
466 | ELSE |
|
466 | ELSE | |
467 | one_sample_f2_full <= '1'; |
|
467 | one_sample_f2_full <= '1'; | |
468 | END IF; |
|
468 | END IF; | |
469 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; |
|
469 | error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full; | |
470 | END IF; |
|
470 | END IF; | |
471 | END PROCESS; |
|
471 | END PROCESS; | |
472 |
|
472 | |||
473 | ----------------------------------------------------------------------------- |
|
473 | ----------------------------------------------------------------------------- | |
474 | -- FSM SELECT CHANNEL |
|
474 | -- FSM SELECT CHANNEL | |
475 | ----------------------------------------------------------------------------- |
|
475 | ----------------------------------------------------------------------------- | |
476 | PROCESS (clk, rstn) |
|
476 | PROCESS (clk, rstn) | |
477 | BEGIN |
|
477 | BEGIN | |
478 | IF rstn = '0' THEN |
|
478 | IF rstn = '0' THEN | |
479 | state_fsm_select_channel <= IDLE; |
|
479 | state_fsm_select_channel <= IDLE; | |
480 | select_channel <= (OTHERS => '0'); |
|
480 | select_channel <= (OTHERS => '0'); | |
481 | ELSIF clk'EVENT AND clk = '1' THEN |
|
481 | ELSIF clk'EVENT AND clk = '1' THEN | |
482 | CASE state_fsm_select_channel IS |
|
482 | CASE state_fsm_select_channel IS | |
483 | WHEN IDLE => |
|
483 | WHEN IDLE => | |
484 | IF sample_f1_full = "11111" THEN |
|
484 | IF sample_f1_full = "11111" THEN | |
485 | state_fsm_select_channel <= SWITCH_F1; |
|
485 | state_fsm_select_channel <= SWITCH_F1; | |
486 | select_channel <= "10"; |
|
486 | select_channel <= "10"; | |
487 | ELSIF sample_f1_almost_full = "00000" THEN |
|
487 | ELSIF sample_f1_almost_full = "00000" THEN | |
488 | IF sample_f0_A_full = "11111" THEN |
|
488 | IF sample_f0_A_full = "11111" THEN | |
489 | state_fsm_select_channel <= SWITCH_F0_A; |
|
489 | state_fsm_select_channel <= SWITCH_F0_A; | |
490 | select_channel <= "00"; |
|
490 | select_channel <= "00"; | |
491 | ELSIF sample_f0_B_full = "11111" THEN |
|
491 | ELSIF sample_f0_B_full = "11111" THEN | |
492 | state_fsm_select_channel <= SWITCH_F0_B; |
|
492 | state_fsm_select_channel <= SWITCH_F0_B; | |
493 | select_channel <= "01"; |
|
493 | select_channel <= "01"; | |
494 | ELSIF sample_f2_full = "11111" THEN |
|
494 | ELSIF sample_f2_full = "11111" THEN | |
495 | state_fsm_select_channel <= SWITCH_F2; |
|
495 | state_fsm_select_channel <= SWITCH_F2; | |
496 | select_channel <= "11"; |
|
496 | select_channel <= "11"; | |
497 | END IF; |
|
497 | END IF; | |
498 | END IF; |
|
498 | END IF; | |
499 |
|
499 | |||
500 | WHEN SWITCH_F0_A => |
|
500 | WHEN SWITCH_F0_A => | |
501 | IF sample_f0_A_empty = "11111" THEN |
|
501 | IF sample_f0_A_empty = "11111" THEN | |
502 | state_fsm_select_channel <= IDLE; |
|
502 | state_fsm_select_channel <= IDLE; | |
503 | select_channel <= (OTHERS => '0'); |
|
503 | select_channel <= (OTHERS => '0'); | |
504 | END IF; |
|
504 | END IF; | |
505 | WHEN SWITCH_F0_B => |
|
505 | WHEN SWITCH_F0_B => | |
506 | IF sample_f0_B_empty = "11111" THEN |
|
506 | IF sample_f0_B_empty = "11111" THEN | |
507 | state_fsm_select_channel <= IDLE; |
|
507 | state_fsm_select_channel <= IDLE; | |
508 | select_channel <= (OTHERS => '0'); |
|
508 | select_channel <= (OTHERS => '0'); | |
509 | END IF; |
|
509 | END IF; | |
510 | WHEN SWITCH_F1 => |
|
510 | WHEN SWITCH_F1 => | |
511 | IF sample_f1_empty = "11111" THEN |
|
511 | IF sample_f1_empty = "11111" THEN | |
512 | state_fsm_select_channel <= IDLE; |
|
512 | state_fsm_select_channel <= IDLE; | |
513 | select_channel <= (OTHERS => '0'); |
|
513 | select_channel <= (OTHERS => '0'); | |
514 | END IF; |
|
514 | END IF; | |
515 | WHEN SWITCH_F2 => |
|
515 | WHEN SWITCH_F2 => | |
516 | IF sample_f2_empty = "11111" THEN |
|
516 | IF sample_f2_empty = "11111" THEN | |
517 | state_fsm_select_channel <= IDLE; |
|
517 | state_fsm_select_channel <= IDLE; | |
518 | select_channel <= (OTHERS => '0'); |
|
518 | select_channel <= (OTHERS => '0'); | |
519 | END IF; |
|
519 | END IF; | |
520 | WHEN OTHERS => NULL; |
|
520 | WHEN OTHERS => NULL; | |
521 | END CASE; |
|
521 | END CASE; | |
522 |
|
522 | |||
523 | END IF; |
|
523 | END IF; | |
524 | END PROCESS; |
|
524 | END PROCESS; | |
525 |
|
525 | |||
526 | PROCESS (clk, rstn) |
|
526 | PROCESS (clk, rstn) | |
527 | BEGIN |
|
527 | BEGIN | |
528 | IF rstn = '0' THEN |
|
528 | IF rstn = '0' THEN | |
529 | select_channel_reg <= (OTHERS => '0'); |
|
529 | select_channel_reg <= (OTHERS => '0'); | |
530 | --pre_state_fsm_select_channel <= IDLE; |
|
530 | --pre_state_fsm_select_channel <= IDLE; | |
531 | ELSIF clk'EVENT AND clk = '1' THEN |
|
531 | ELSIF clk'EVENT AND clk = '1' THEN | |
532 | select_channel_reg <= select_channel; |
|
532 | select_channel_reg <= select_channel; | |
533 | --pre_state_fsm_select_channel <= state_fsm_select_channel; |
|
533 | --pre_state_fsm_select_channel <= state_fsm_select_channel; | |
534 | END IF; |
|
534 | END IF; | |
535 | END PROCESS; |
|
535 | END PROCESS; | |
536 |
|
536 | |||
537 |
|
537 | |||
538 | ----------------------------------------------------------------------------- |
|
538 | ----------------------------------------------------------------------------- | |
539 | -- SWITCH SELECT CHANNEL |
|
539 | -- SWITCH SELECT CHANNEL | |
540 | ----------------------------------------------------------------------------- |
|
540 | ----------------------------------------------------------------------------- | |
541 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
541 | sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
542 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
542 | sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
543 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
543 | sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
544 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
544 | sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
545 | (OTHERS => '1'); |
|
545 | (OTHERS => '1'); | |
546 |
|
546 | |||
547 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
547 | sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
548 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
548 | sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
549 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
549 | sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
550 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
550 | sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
551 | (OTHERS => '0'); |
|
551 | (OTHERS => '0'); | |
552 |
|
552 | |||
553 | --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE |
|
553 | --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE | |
554 | -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE |
|
554 | -- sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE | |
555 | -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE |
|
555 | -- sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE | |
556 | -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
556 | -- sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
557 | sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE |
|
557 | sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE | |
558 | sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE |
|
558 | sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE | |
559 | sample_f1_rdata WHEN select_channel_reg = "10" ELSE |
|
559 | sample_f1_rdata WHEN select_channel_reg = "10" ELSE | |
560 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE |
|
560 | sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE | |
561 |
|
561 | |||
562 |
|
562 | |||
563 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); |
|
563 | sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1'); | |
564 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); |
|
564 | sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1'); | |
565 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); |
|
565 | sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1'); | |
566 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); |
|
566 | sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1'); | |
567 |
|
567 | |||
568 |
|
568 | |||
569 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE |
|
569 | status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE | |
570 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE |
|
570 | time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE | |
571 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE |
|
571 | time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE | |
572 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 |
|
572 | time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2 | |
573 |
|
573 | |||
574 | ----------------------------------------------------------------------------- |
|
574 | ----------------------------------------------------------------------------- | |
575 | -- FSM LOAD FFT |
|
575 | -- FSM LOAD FFT | |
576 | ----------------------------------------------------------------------------- |
|
576 | ----------------------------------------------------------------------------- | |
577 |
|
577 | |||
578 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE |
|
578 | sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE | |
579 | sample_ren_s WHEN sample_load = '1' ELSE |
|
579 | sample_ren_s WHEN sample_load = '1' ELSE | |
580 | (OTHERS => '1'); |
|
580 | (OTHERS => '1'); | |
581 |
|
581 | |||
582 | PROCESS (clk, rstn) |
|
582 | PROCESS (clk, rstn) | |
583 | BEGIN |
|
583 | BEGIN | |
584 | IF rstn = '0' THEN |
|
584 | IF rstn = '0' THEN | |
585 | sample_ren_s <= (OTHERS => '1'); |
|
585 | sample_ren_s <= (OTHERS => '1'); | |
586 | state_fsm_load_FFT <= IDLE; |
|
586 | state_fsm_load_FFT <= IDLE; | |
587 | status_MS_input <= (OTHERS => '0'); |
|
587 | status_MS_input <= (OTHERS => '0'); | |
588 | select_fifo <= "000"; |
|
588 | select_fifo <= "000"; | |
589 | --next_state_fsm_load_FFT <= IDLE; |
|
589 | --next_state_fsm_load_FFT <= IDLE; | |
590 | --sample_valid <= '0'; |
|
590 | --sample_valid <= '0'; | |
591 | ELSIF clk'EVENT AND clk = '1' THEN |
|
591 | ELSIF clk'EVENT AND clk = '1' THEN | |
592 | CASE state_fsm_load_FFT IS |
|
592 | CASE state_fsm_load_FFT IS | |
593 | WHEN IDLE => |
|
593 | WHEN IDLE => | |
594 | --sample_valid <= '0'; |
|
594 | --sample_valid <= '0'; | |
595 | sample_ren_s <= (OTHERS => '1'); |
|
595 | sample_ren_s <= (OTHERS => '1'); | |
596 | IF sample_full = "11111" AND sample_load = '1' THEN |
|
596 | IF sample_full = "11111" AND sample_load = '1' THEN | |
597 | state_fsm_load_FFT <= FIFO_1; |
|
597 | state_fsm_load_FFT <= FIFO_1; | |
598 | status_MS_input <= status_channel; |
|
598 | status_MS_input <= status_channel; | |
599 | select_fifo <= "000"; |
|
599 | select_fifo <= "000"; | |
600 | END IF; |
|
600 | END IF; | |
601 |
|
601 | |||
602 | WHEN FIFO_1 => |
|
602 | WHEN FIFO_1 => | |
603 | sample_ren_s <= "1111" & NOT(sample_load); |
|
603 | sample_ren_s <= "1111" & NOT(sample_load); | |
604 | IF sample_empty(0) = '1' THEN |
|
604 | IF sample_empty(0) = '1' THEN | |
605 | sample_ren_s <= (OTHERS => '1'); |
|
605 | sample_ren_s <= (OTHERS => '1'); | |
606 | state_fsm_load_FFT <= FIFO_2; |
|
606 | state_fsm_load_FFT <= FIFO_2; | |
607 | select_fifo <= "001"; |
|
607 | select_fifo <= "001"; | |
608 | END IF; |
|
608 | END IF; | |
609 |
|
609 | |||
610 | WHEN FIFO_2 => |
|
610 | WHEN FIFO_2 => | |
611 | sample_ren_s <= "111" & NOT(sample_load) & '1'; |
|
611 | sample_ren_s <= "111" & NOT(sample_load) & '1'; | |
612 | IF sample_empty(1) = '1' THEN |
|
612 | IF sample_empty(1) = '1' THEN | |
613 | sample_ren_s <= (OTHERS => '1'); |
|
613 | sample_ren_s <= (OTHERS => '1'); | |
614 | state_fsm_load_FFT <= FIFO_3; |
|
614 | state_fsm_load_FFT <= FIFO_3; | |
615 | select_fifo <= "010"; |
|
615 | select_fifo <= "010"; | |
616 | END IF; |
|
616 | END IF; | |
617 |
|
617 | |||
618 | WHEN FIFO_3 => |
|
618 | WHEN FIFO_3 => | |
619 | sample_ren_s <= "11" & NOT(sample_load) & "11"; |
|
619 | sample_ren_s <= "11" & NOT(sample_load) & "11"; | |
620 | IF sample_empty(2) = '1' THEN |
|
620 | IF sample_empty(2) = '1' THEN | |
621 | sample_ren_s <= (OTHERS => '1'); |
|
621 | sample_ren_s <= (OTHERS => '1'); | |
622 | state_fsm_load_FFT <= FIFO_4; |
|
622 | state_fsm_load_FFT <= FIFO_4; | |
623 | select_fifo <= "011"; |
|
623 | select_fifo <= "011"; | |
624 | END IF; |
|
624 | END IF; | |
625 |
|
625 | |||
626 | WHEN FIFO_4 => |
|
626 | WHEN FIFO_4 => | |
627 | sample_ren_s <= '1' & NOT(sample_load) & "111"; |
|
627 | sample_ren_s <= '1' & NOT(sample_load) & "111"; | |
628 | IF sample_empty(3) = '1' THEN |
|
628 | IF sample_empty(3) = '1' THEN | |
629 | sample_ren_s <= (OTHERS => '1'); |
|
629 | sample_ren_s <= (OTHERS => '1'); | |
630 | state_fsm_load_FFT <= FIFO_5; |
|
630 | state_fsm_load_FFT <= FIFO_5; | |
631 | select_fifo <= "100"; |
|
631 | select_fifo <= "100"; | |
632 | END IF; |
|
632 | END IF; | |
633 |
|
633 | |||
634 | WHEN FIFO_5 => |
|
634 | WHEN FIFO_5 => | |
635 | sample_ren_s <= NOT(sample_load) & "1111"; |
|
635 | sample_ren_s <= NOT(sample_load) & "1111"; | |
636 | IF sample_empty(4) = '1' THEN |
|
636 | IF sample_empty(4) = '1' THEN | |
637 | sample_ren_s <= (OTHERS => '1'); |
|
637 | sample_ren_s <= (OTHERS => '1'); | |
638 | state_fsm_load_FFT <= IDLE; |
|
638 | state_fsm_load_FFT <= IDLE; | |
639 | select_fifo <= "000"; |
|
639 | select_fifo <= "000"; | |
640 | END IF; |
|
640 | END IF; | |
641 | WHEN OTHERS => NULL; |
|
641 | WHEN OTHERS => NULL; | |
642 | END CASE; |
|
642 | END CASE; | |
643 | END IF; |
|
643 | END IF; | |
644 | END PROCESS; |
|
644 | END PROCESS; | |
645 |
|
645 | |||
646 | PROCESS (clk, rstn) |
|
646 | PROCESS (clk, rstn) | |
647 | BEGIN |
|
647 | BEGIN | |
648 | IF rstn = '0' THEN |
|
648 | IF rstn = '0' THEN | |
649 | sample_valid_r <= '0'; |
|
649 | sample_valid_r <= '0'; | |
650 | select_fifo_reg <= (OTHERS => '0'); |
|
650 | select_fifo_reg <= (OTHERS => '0'); | |
651 | --next_state_fsm_load_FFT <= IDLE; |
|
651 | --next_state_fsm_load_FFT <= IDLE; | |
652 | ELSIF clk'EVENT AND clk = '1' THEN |
|
652 | ELSIF clk'EVENT AND clk = '1' THEN | |
653 | select_fifo_reg <= select_fifo; |
|
653 | select_fifo_reg <= select_fifo; | |
654 | --next_state_fsm_load_FFT <= state_fsm_load_FFT; |
|
654 | --next_state_fsm_load_FFT <= state_fsm_load_FFT; | |
655 | IF sample_ren_s = "11111" THEN |
|
655 | IF sample_ren_s = "11111" THEN | |
656 | sample_valid_r <= '0'; |
|
656 | sample_valid_r <= '0'; | |
657 | ELSE |
|
657 | ELSE | |
658 | sample_valid_r <= '1'; |
|
658 | sample_valid_r <= '1'; | |
659 | END IF; |
|
659 | END IF; | |
660 | END IF; |
|
660 | END IF; | |
661 | END PROCESS; |
|
661 | END PROCESS; | |
662 |
|
662 | |||
663 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; |
|
663 | sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load; | |
664 |
|
664 | |||
665 | --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE |
|
665 | --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE | |
666 | -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE |
|
666 | -- sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE | |
667 | -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE |
|
667 | -- sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE | |
668 | -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE |
|
668 | -- sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE | |
669 | -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
669 | -- sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
670 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE |
|
670 | sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE | |
671 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE |
|
671 | sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE | |
672 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE |
|
672 | sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE | |
673 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE |
|
673 | sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011" ELSE | |
674 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE |
|
674 | sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE | |
675 |
|
675 | |||
676 | ----------------------------------------------------------------------------- |
|
676 | ----------------------------------------------------------------------------- | |
677 | -- FFT |
|
677 | -- FFT | |
678 | ----------------------------------------------------------------------------- |
|
678 | ----------------------------------------------------------------------------- | |
679 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT |
|
679 | lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT | |
680 | PORT MAP ( |
|
680 | PORT MAP ( | |
681 | clk => clk, |
|
681 | clk => clk, | |
682 | rstn => rstn, |
|
682 | rstn => rstn, | |
683 | sample_valid => sample_valid, |
|
683 | sample_valid => sample_valid, | |
684 | fft_read => fft_read, |
|
684 | fft_read => fft_read, | |
685 | sample_data => sample_data, |
|
685 | sample_data => sample_data, | |
686 | sample_load => sample_load, |
|
686 | sample_load => sample_load, | |
687 | fft_pong => fft_pong, |
|
687 | fft_pong => fft_pong, | |
688 | fft_data_im => fft_data_im, |
|
688 | fft_data_im => fft_data_im, | |
689 | fft_data_re => fft_data_re, |
|
689 | fft_data_re => fft_data_re, | |
690 | fft_data_valid => fft_data_valid, |
|
690 | fft_data_valid => fft_data_valid, | |
691 | fft_ready => fft_ready); |
|
691 | fft_ready => fft_ready); | |
692 |
|
692 | |||
693 | debug_vector(0) <= fft_data_valid; |
|
693 | debug_vector(0) <= fft_data_valid; | |
694 | debug_vector(1) <= fft_ready; |
|
694 | debug_vector(1) <= fft_ready; | |
695 | debug_vector(11 DOWNTO 2) <= (OTHERS => '0'); |
|
695 | debug_vector(11 DOWNTO 2) <= (OTHERS => '0'); | |
696 |
|
696 | |||
697 |
|
697 | |||
698 | ----------------------------------------------------------------------------- |
|
698 | ----------------------------------------------------------------------------- | |
699 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; |
|
699 | fft_ready_rising_down <= fft_ready_reg AND NOT fft_ready; | |
700 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; |
|
700 | sample_load_rising_down <= sample_load_reg AND NOT sample_load; | |
701 |
|
701 | |||
702 | PROCESS (clk, rstn) |
|
702 | PROCESS (clk, rstn) | |
703 | BEGIN |
|
703 | BEGIN | |
704 | IF rstn = '0' THEN |
|
704 | IF rstn = '0' THEN | |
705 | fft_ready_reg <= '0'; |
|
705 | fft_ready_reg <= '0'; | |
706 | sample_load_reg <= '0'; |
|
706 | sample_load_reg <= '0'; | |
707 |
|
707 | |||
708 | fft_ongoing_counter <= '0'; |
|
708 | fft_ongoing_counter <= '0'; | |
709 | ELSIF clk'event AND clk = '1' THEN |
|
709 | ELSIF clk'event AND clk = '1' THEN | |
710 | fft_ready_reg <= fft_ready; |
|
710 | fft_ready_reg <= fft_ready; | |
711 | sample_load_reg <= sample_load; |
|
711 | sample_load_reg <= sample_load; | |
712 |
|
712 | |||
713 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN |
|
713 | IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN | |
714 | fft_ongoing_counter <= '0'; |
|
714 | fft_ongoing_counter <= '0'; | |
715 |
|
715 | |||
716 | -- CASE fft_ongoing_counter IS |
|
716 | -- CASE fft_ongoing_counter IS | |
717 | -- WHEN "01" => fft_ongoing_counter <= "00"; |
|
717 | -- WHEN "01" => fft_ongoing_counter <= "00"; | |
718 | ---- WHEN "10" => fft_ongoing_counter <= "01"; |
|
718 | ---- WHEN "10" => fft_ongoing_counter <= "01"; | |
719 | -- WHEN OTHERS => NULL; |
|
719 | -- WHEN OTHERS => NULL; | |
720 | -- END CASE; |
|
720 | -- END CASE; | |
721 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN |
|
721 | ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN | |
722 | fft_ongoing_counter <= '1'; |
|
722 | fft_ongoing_counter <= '1'; | |
723 | -- CASE fft_ongoing_counter IS |
|
723 | -- CASE fft_ongoing_counter IS | |
724 | -- WHEN "00" => fft_ongoing_counter <= "01"; |
|
724 | -- WHEN "00" => fft_ongoing_counter <= "01"; | |
725 | ---- WHEN "01" => fft_ongoing_counter <= "10"; |
|
725 | ---- WHEN "01" => fft_ongoing_counter <= "10"; | |
726 | -- WHEN OTHERS => NULL; |
|
726 | -- WHEN OTHERS => NULL; | |
727 | -- END CASE; |
|
727 | -- END CASE; | |
728 | END IF; |
|
728 | END IF; | |
729 |
|
729 | |||
730 | END IF; |
|
730 | END IF; | |
731 | END PROCESS; |
|
731 | END PROCESS; | |
732 |
|
732 | |||
733 | ----------------------------------------------------------------------------- |
|
733 | ----------------------------------------------------------------------------- | |
734 | PROCESS (clk, rstn) |
|
734 | PROCESS (clk, rstn) | |
735 | BEGIN |
|
735 | BEGIN | |
736 | IF rstn = '0' THEN |
|
736 | IF rstn = '0' THEN | |
737 | state_fsm_load_MS_memory <= IDLE; |
|
737 | state_fsm_load_MS_memory <= IDLE; | |
738 | current_fifo_load <= "00001"; |
|
738 | current_fifo_load <= "00001"; | |
739 | ELSIF clk'EVENT AND clk = '1' THEN |
|
739 | ELSIF clk'EVENT AND clk = '1' THEN | |
740 | CASE state_fsm_load_MS_memory IS |
|
740 | CASE state_fsm_load_MS_memory IS | |
741 | WHEN IDLE => |
|
741 | WHEN IDLE => | |
742 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN |
|
742 | IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN | |
743 | state_fsm_load_MS_memory <= LOAD_FIFO; |
|
743 | state_fsm_load_MS_memory <= LOAD_FIFO; | |
744 | END IF; |
|
744 | END IF; | |
745 | WHEN LOAD_FIFO => |
|
745 | WHEN LOAD_FIFO => | |
746 | IF current_fifo_full = '1' THEN |
|
746 | IF current_fifo_full = '1' THEN | |
747 | state_fsm_load_MS_memory <= TRASH_FFT; |
|
747 | state_fsm_load_MS_memory <= TRASH_FFT; | |
748 | END IF; |
|
748 | END IF; | |
749 | WHEN TRASH_FFT => |
|
749 | WHEN TRASH_FFT => | |
750 | IF fft_ready = '0' THEN |
|
750 | IF fft_ready = '0' THEN | |
751 | state_fsm_load_MS_memory <= IDLE; |
|
751 | state_fsm_load_MS_memory <= IDLE; | |
752 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); |
|
752 | current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4); | |
753 | END IF; |
|
753 | END IF; | |
754 | WHEN OTHERS => NULL; |
|
754 | WHEN OTHERS => NULL; | |
755 | END CASE; |
|
755 | END CASE; | |
756 |
|
756 | |||
757 | END IF; |
|
757 | END IF; | |
758 | END PROCESS; |
|
758 | END PROCESS; | |
759 |
|
759 | |||
760 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE |
|
760 | current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE | |
761 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE |
|
761 | MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE | |
762 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE |
|
762 | MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE | |
763 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE |
|
763 | MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE | |
764 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
764 | MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
765 |
|
765 | |||
766 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE |
|
766 | current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE | |
767 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE |
|
767 | MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE | |
768 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE |
|
768 | MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE | |
769 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE |
|
769 | MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE | |
770 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
770 | MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
771 |
|
771 | |||
772 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE |
|
772 | current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE | |
773 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE |
|
773 | MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE | |
774 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE |
|
774 | MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE | |
775 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE |
|
775 | MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE | |
776 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE |
|
776 | MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE | |
777 |
|
777 | |||
778 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; |
|
778 | fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1'; | |
779 |
|
779 | |||
780 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE |
|
780 | all_fifo : FOR I IN 4 DOWNTO 0 GENERATE | |
781 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' |
|
781 | MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1' | |
782 | AND state_fsm_load_MS_memory = LOAD_FIFO |
|
782 | AND state_fsm_load_MS_memory = LOAD_FIFO | |
783 | AND current_fifo_load(I) = '1' |
|
783 | AND current_fifo_load(I) = '1' | |
784 | ELSE '1'; |
|
784 | ELSE '1'; | |
785 | END GENERATE all_fifo; |
|
785 | END GENERATE all_fifo; | |
786 |
|
786 | |||
787 | PROCESS (clk, rstn) |
|
787 | PROCESS (clk, rstn) | |
788 | BEGIN |
|
788 | BEGIN | |
789 | IF rstn = '0' THEN |
|
789 | IF rstn = '0' THEN | |
790 | MEM_IN_SM_wen <= (OTHERS => '1'); |
|
790 | MEM_IN_SM_wen <= (OTHERS => '1'); | |
791 | ELSIF clk'EVENT AND clk = '1' THEN |
|
791 | ELSIF clk'EVENT AND clk = '1' THEN | |
792 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; |
|
792 | MEM_IN_SM_wen <= MEM_IN_SM_wen_s; | |
793 | END IF; |
|
793 | END IF; | |
794 | END PROCESS; |
|
794 | END PROCESS; | |
795 |
|
795 | |||
796 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & |
|
796 | MEM_IN_SM_wData <= (fft_data_im & fft_data_re) & | |
797 | (fft_data_im & fft_data_re) & |
|
797 | (fft_data_im & fft_data_re) & | |
798 | (fft_data_im & fft_data_re) & |
|
798 | (fft_data_im & fft_data_re) & | |
799 | (fft_data_im & fft_data_re) & |
|
799 | (fft_data_im & fft_data_re) & | |
800 | (fft_data_im & fft_data_re); |
|
800 | (fft_data_im & fft_data_re); | |
801 | ----------------------------------------------------------------------------- |
|
801 | ----------------------------------------------------------------------------- | |
802 |
|
802 | |||
803 |
|
803 | |||
804 | ----------------------------------------------------------------------------- |
|
804 | ----------------------------------------------------------------------------- | |
805 | Mem_In_SpectralMatrix : lppFIFOxN |
|
805 | Mem_In_SpectralMatrix : lppFIFOxN | |
806 | GENERIC MAP ( |
|
806 | GENERIC MAP ( | |
807 | tech => 0, |
|
807 | tech => 0, | |
808 | Mem_use => Mem_use, |
|
808 | Mem_use => Mem_use, | |
809 | Data_sz => 32, --16, |
|
809 | Data_sz => 32, --16, | |
810 | Addr_sz => 7, --8 |
|
810 | Addr_sz => 7, --8 | |
811 | FifoCnt => 5) |
|
811 | FifoCnt => 5) | |
812 | PORT MAP ( |
|
812 | PORT MAP ( | |
813 | clk => clk, |
|
813 | clk => clk, | |
814 | rstn => rstn, |
|
814 | rstn => rstn, | |
815 |
|
815 | |||
816 | ReUse => MEM_IN_SM_ReUse, |
|
816 | ReUse => MEM_IN_SM_ReUse, | |
817 | run => (OTHERS => '1'), |
|
817 | run => (OTHERS => '1'), | |
818 |
|
818 | |||
819 | wen => MEM_IN_SM_wen, |
|
819 | wen => MEM_IN_SM_wen, | |
820 | wdata => MEM_IN_SM_wData, |
|
820 | wdata => MEM_IN_SM_wData, | |
821 |
|
821 | |||
822 | ren => MEM_IN_SM_ren, |
|
822 | ren => MEM_IN_SM_ren, | |
823 | rdata => MEM_IN_SM_rData, |
|
823 | rdata => MEM_IN_SM_rData, | |
824 | full => MEM_IN_SM_Full, |
|
824 | full => MEM_IN_SM_Full, | |
825 | empty => MEM_IN_SM_Empty, |
|
825 | empty => MEM_IN_SM_Empty, | |
826 | almost_full => OPEN); |
|
826 | almost_full => OPEN); | |
827 |
|
827 | |||
828 |
|
828 | |||
829 | ----------------------------------------------------------------------------- |
|
829 | ----------------------------------------------------------------------------- | |
830 | MS_control_1 : MS_control |
|
830 | MS_control_1 : MS_control | |
831 | PORT MAP ( |
|
831 | PORT MAP ( | |
832 | clk => clk, |
|
832 | clk => clk, | |
833 | rstn => rstn, |
|
833 | rstn => rstn, | |
834 |
|
834 | |||
835 | current_status_ms => status_MS_input, |
|
835 | current_status_ms => status_MS_input, | |
836 |
|
836 | |||
837 | fifo_in_lock => MEM_IN_SM_locked, |
|
837 | fifo_in_lock => MEM_IN_SM_locked, | |
838 | fifo_in_data => MEM_IN_SM_rdata, |
|
838 | fifo_in_data => MEM_IN_SM_rdata, | |
839 | fifo_in_full => MEM_IN_SM_Full, |
|
839 | fifo_in_full => MEM_IN_SM_Full, | |
840 | fifo_in_empty => MEM_IN_SM_Empty, |
|
840 | fifo_in_empty => MEM_IN_SM_Empty, | |
841 | fifo_in_ren => MEM_IN_SM_ren, |
|
841 | fifo_in_ren => MEM_IN_SM_ren, | |
842 | fifo_in_reuse => MEM_IN_SM_ReUse, |
|
842 | fifo_in_reuse => MEM_IN_SM_ReUse, | |
843 |
|
843 | |||
844 | fifo_out_data => SM_in_data, |
|
844 | fifo_out_data => SM_in_data, | |
845 | fifo_out_ren => SM_in_ren, |
|
845 | fifo_out_ren => SM_in_ren, | |
846 | fifo_out_empty => SM_in_empty, |
|
846 | fifo_out_empty => SM_in_empty, | |
847 |
|
847 | |||
848 | current_status_component => status_component, |
|
848 | current_status_component => status_component, | |
849 |
|
849 | |||
850 | correlation_start => SM_correlation_start, |
|
850 | correlation_start => SM_correlation_start, | |
851 | correlation_auto => SM_correlation_auto, |
|
851 | correlation_auto => SM_correlation_auto, | |
852 | correlation_done => SM_correlation_done); |
|
852 | correlation_done => SM_correlation_done); | |
853 |
|
853 | |||
854 |
|
854 | |||
855 | MS_calculation_1 : MS_calculation |
|
855 | MS_calculation_1 : MS_calculation | |
856 | PORT MAP ( |
|
856 | PORT MAP ( | |
857 | clk => clk, |
|
857 | clk => clk, | |
858 | rstn => rstn, |
|
858 | rstn => rstn, | |
859 |
|
859 | |||
860 | fifo_in_data => SM_in_data, |
|
860 | fifo_in_data => SM_in_data, | |
861 | fifo_in_ren => SM_in_ren, |
|
861 | fifo_in_ren => SM_in_ren, | |
862 | fifo_in_empty => SM_in_empty, |
|
862 | fifo_in_empty => SM_in_empty, | |
863 |
|
863 | |||
864 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO |
|
864 | fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO | |
865 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO |
|
865 | fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO | |
866 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO |
|
866 | fifo_out_full => MEM_OUT_SM_Full_s, -- TODO | |
867 |
|
867 | |||
868 | correlation_start => SM_correlation_start, |
|
868 | correlation_start => SM_correlation_start, | |
869 | correlation_auto => SM_correlation_auto, |
|
869 | correlation_auto => SM_correlation_auto, | |
870 | correlation_begin => SM_correlation_begin, |
|
870 | correlation_begin => SM_correlation_begin, | |
871 | correlation_done => SM_correlation_done); |
|
871 | correlation_done => SM_correlation_done); | |
872 |
|
872 | |||
873 | ----------------------------------------------------------------------------- |
|
873 | ----------------------------------------------------------------------------- | |
874 | PROCESS (clk, rstn) |
|
874 | PROCESS (clk, rstn) | |
875 | BEGIN -- PROCESS |
|
875 | BEGIN -- PROCESS | |
876 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
876 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
877 | current_matrix_write <= '0'; |
|
877 | current_matrix_write <= '0'; | |
878 | current_matrix_wait_empty <= '1'; |
|
878 | current_matrix_wait_empty <= '1'; | |
879 | status_component_fifo_0 <= (OTHERS => '0'); |
|
879 | status_component_fifo_0 <= (OTHERS => '0'); | |
880 | status_component_fifo_1 <= (OTHERS => '0'); |
|
880 | status_component_fifo_1 <= (OTHERS => '0'); | |
881 | status_component_fifo_0_end <= '0'; |
|
881 | status_component_fifo_0_end <= '0'; | |
882 | status_component_fifo_1_end <= '0'; |
|
882 | status_component_fifo_1_end <= '0'; | |
883 | SM_correlation_done_reg1 <= '0'; |
|
883 | SM_correlation_done_reg1 <= '0'; | |
884 | SM_correlation_done_reg2 <= '0'; |
|
884 | SM_correlation_done_reg2 <= '0'; | |
885 | SM_correlation_done_reg3 <= '0'; |
|
885 | SM_correlation_done_reg3 <= '0'; | |
886 |
|
886 | |||
887 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
887 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |
888 | SM_correlation_done_reg1 <= SM_correlation_done; |
|
888 | SM_correlation_done_reg1 <= SM_correlation_done; | |
889 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; |
|
889 | SM_correlation_done_reg2 <= SM_correlation_done_reg1; | |
890 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; |
|
890 | SM_correlation_done_reg3 <= SM_correlation_done_reg2; | |
891 | status_component_fifo_0_end <= '0'; |
|
891 | status_component_fifo_0_end <= '0'; | |
892 | status_component_fifo_1_end <= '0'; |
|
892 | status_component_fifo_1_end <= '0'; | |
893 | IF SM_correlation_begin = '1' THEN |
|
893 | IF SM_correlation_begin = '1' THEN | |
894 | IF current_matrix_write = '0' THEN |
|
894 | IF current_matrix_write = '0' THEN | |
895 | status_component_fifo_0 <= status_component(53 DOWNTO 4); |
|
895 | status_component_fifo_0 <= status_component(53 DOWNTO 4); | |
896 | ELSE |
|
896 | ELSE | |
897 | status_component_fifo_1 <= status_component(53 DOWNTO 4); |
|
897 | status_component_fifo_1 <= status_component(53 DOWNTO 4); | |
898 | END IF; |
|
898 | END IF; | |
899 | END IF; |
|
899 | END IF; | |
900 |
|
900 | |||
901 | IF SM_correlation_done_reg3 = '1' THEN |
|
901 | IF SM_correlation_done_reg3 = '1' THEN | |
902 | IF current_matrix_write = '0' THEN |
|
902 | IF current_matrix_write = '0' THEN | |
903 | status_component_fifo_0_end <= '1'; |
|
903 | status_component_fifo_0_end <= '1'; | |
904 | ELSE |
|
904 | ELSE | |
905 | status_component_fifo_1_end <= '1'; |
|
905 | status_component_fifo_1_end <= '1'; | |
906 | END IF; |
|
906 | END IF; | |
907 | current_matrix_wait_empty <= '1'; |
|
907 | current_matrix_wait_empty <= '1'; | |
908 | current_matrix_write <= NOT current_matrix_write; |
|
908 | current_matrix_write <= NOT current_matrix_write; | |
909 | END IF; |
|
909 | END IF; | |
910 |
|
910 | |||
911 | IF current_matrix_wait_empty <= '1' THEN |
|
911 | IF current_matrix_wait_empty <= '1' THEN | |
912 | IF current_matrix_write = '0' THEN |
|
912 | IF current_matrix_write = '0' THEN | |
913 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); |
|
913 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0); | |
914 | ELSE |
|
914 | ELSE | |
915 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); |
|
915 | current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1); | |
916 | END IF; |
|
916 | END IF; | |
917 | END IF; |
|
917 | END IF; | |
918 |
|
918 | |||
919 | END IF; |
|
919 | END IF; | |
920 | END PROCESS; |
|
920 | END PROCESS; | |
921 |
|
921 | |||
922 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE |
|
922 | MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE | |
923 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE |
|
923 | '1' WHEN SM_correlation_done_reg1 = '1' ELSE | |
924 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE |
|
924 | '1' WHEN SM_correlation_done_reg2 = '1' ELSE | |
925 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE |
|
925 | '1' WHEN SM_correlation_done_reg3 = '1' ELSE | |
926 | '1' WHEN current_matrix_wait_empty = '1' ELSE |
|
926 | '1' WHEN current_matrix_wait_empty = '1' ELSE | |
927 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE |
|
927 | MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE | |
928 | MEM_OUT_SM_Full(1); |
|
928 | MEM_OUT_SM_Full(1); | |
929 |
|
929 | |||
930 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; |
|
930 | MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1'; | |
931 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; |
|
931 | MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1'; | |
932 |
|
932 | |||
933 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; |
|
933 | MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s; | |
934 | ----------------------------------------------------------------------------- |
|
934 | ----------------------------------------------------------------------------- | |
935 |
|
935 | |||
936 | --Mem_Out_SpectralMatrix : lppFIFOxN |
|
936 | --Mem_Out_SpectralMatrix : lppFIFOxN | |
937 | -- GENERIC MAP ( |
|
937 | -- GENERIC MAP ( | |
938 | -- tech => 0, |
|
938 | -- tech => 0, | |
939 | -- Mem_use => Mem_use, |
|
939 | -- Mem_use => Mem_use, | |
940 | -- Data_sz => 32, |
|
940 | -- Data_sz => 32, | |
941 | -- Addr_sz => 8, |
|
941 | -- Addr_sz => 8, | |
942 | -- FifoCnt => 2) |
|
942 | -- FifoCnt => 2) | |
943 | -- PORT MAP ( |
|
943 | -- PORT MAP ( | |
944 | -- clk => clk, |
|
944 | -- clk => clk, | |
945 | -- rstn => rstn, |
|
945 | -- rstn => rstn, | |
946 |
|
946 | |||
947 | -- ReUse => (OTHERS => '0'), |
|
947 | -- ReUse => (OTHERS => '0'), | |
948 | -- run => (OTHERS => '1'), |
|
948 | -- run => (OTHERS => '1'), | |
949 |
|
949 | |||
950 | -- wen => MEM_OUT_SM_Write, |
|
950 | -- wen => MEM_OUT_SM_Write, | |
951 | -- wdata => MEM_OUT_SM_Data_in, |
|
951 | -- wdata => MEM_OUT_SM_Data_in, | |
952 |
|
952 | |||
953 | -- ren => MEM_OUT_SM_Read, |
|
953 | -- ren => MEM_OUT_SM_Read, | |
954 | -- rdata => MEM_OUT_SM_Data_out, |
|
954 | -- rdata => MEM_OUT_SM_Data_out, | |
955 |
|
955 | |||
956 | -- full => MEM_OUT_SM_Full, |
|
956 | -- full => MEM_OUT_SM_Full, | |
957 | -- empty => MEM_OUT_SM_Empty, |
|
957 | -- empty => MEM_OUT_SM_Empty, | |
958 | -- almost_full => OPEN); |
|
958 | -- almost_full => OPEN); | |
959 |
|
959 | |||
960 |
|
960 | |||
961 | all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE |
|
961 | all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE | |
962 | Mem_Out_SpectralMatrix_I: lpp_fifo |
|
962 | Mem_Out_SpectralMatrix_I: lpp_fifo | |
963 | GENERIC MAP ( |
|
963 | GENERIC MAP ( | |
964 | tech => 0, |
|
964 | tech => 0, | |
965 | Mem_use => Mem_use, |
|
965 | Mem_use => Mem_use, | |
966 | EMPTY_THRESHOLD_LIMIT => 15, |
|
966 | EMPTY_THRESHOLD_LIMIT => 15, | |
967 | FULL_THRESHOLD_LIMIT => 1, |
|
967 | FULL_THRESHOLD_LIMIT => 1, | |
968 | DataSz => 32, |
|
968 | DataSz => 32, | |
969 | AddrSz => 8) |
|
969 | AddrSz => 8) | |
970 | PORT MAP ( |
|
970 | PORT MAP ( | |
971 | clk => clk, |
|
971 | clk => clk, | |
972 | rstn => rstn, |
|
972 | rstn => rstn, | |
973 | reUse => '0', |
|
973 | reUse => '0', | |
974 | run => run, |
|
974 | run => run, | |
975 |
|
975 | |||
976 | ren => MEM_OUT_SM_Read(I), |
|
976 | ren => MEM_OUT_SM_Read(I), | |
977 | rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i), |
|
977 | rdata => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i), | |
978 |
|
978 | |||
979 | wen => MEM_OUT_SM_Write(I), |
|
979 | wen => MEM_OUT_SM_Write(I), | |
980 | wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i), |
|
980 | wdata => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i), | |
981 |
|
981 | |||
982 | empty => MEM_OUT_SM_Empty(I), |
|
982 | empty => MEM_OUT_SM_Empty(I), | |
983 | full => MEM_OUT_SM_Full(I), |
|
983 | full => MEM_OUT_SM_Full(I), | |
984 | full_almost => OPEN, |
|
984 | full_almost => OPEN, | |
985 | empty_threshold => MEM_OUT_SM_Empty_Threshold(I), |
|
985 | empty_threshold => MEM_OUT_SM_Empty_Threshold(I), | |
986 |
|
986 | |||
987 | full_threshold => OPEN); |
|
987 | full_threshold => OPEN); | |
988 |
|
988 | |||
989 | END GENERATE all_Mem_Out_SpectralMatrix; |
|
989 | END GENERATE all_Mem_Out_SpectralMatrix; | |
990 |
|
990 | |||
991 | ----------------------------------------------------------------------------- |
|
991 | ----------------------------------------------------------------------------- | |
992 | -- MEM_OUT_SM_Read <= "00"; |
|
992 | -- MEM_OUT_SM_Read <= "00"; | |
993 | PROCESS (clk, rstn) |
|
993 | PROCESS (clk, rstn) | |
994 | BEGIN |
|
994 | BEGIN | |
995 | IF rstn = '0' THEN |
|
995 | IF rstn = '0' THEN | |
996 | fifo_0_ready <= '0'; |
|
996 | fifo_0_ready <= '0'; | |
997 | fifo_1_ready <= '0'; |
|
997 | fifo_1_ready <= '0'; | |
998 | fifo_ongoing <= '0'; |
|
998 | fifo_ongoing <= '0'; | |
999 | ELSIF clk'EVENT AND clk = '1' THEN |
|
999 | ELSIF clk'EVENT AND clk = '1' THEN | |
1000 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN |
|
1000 | IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN | |
1001 | fifo_ongoing <= '1'; |
|
1001 | fifo_ongoing <= '1'; | |
1002 | fifo_0_ready <= '0'; |
|
1002 | fifo_0_ready <= '0'; | |
1003 | ELSIF status_component_fifo_0_end = '1' THEN |
|
1003 | ELSIF status_component_fifo_0_end = '1' THEN | |
1004 | fifo_0_ready <= '1'; |
|
1004 | fifo_0_ready <= '1'; | |
1005 | END IF; |
|
1005 | END IF; | |
1006 |
|
1006 | |||
1007 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN |
|
1007 | IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN | |
1008 | fifo_ongoing <= '0'; |
|
1008 | fifo_ongoing <= '0'; | |
1009 | fifo_1_ready <= '0'; |
|
1009 | fifo_1_ready <= '0'; | |
1010 | ELSIF status_component_fifo_1_end = '1' THEN |
|
1010 | ELSIF status_component_fifo_1_end = '1' THEN | |
1011 | fifo_1_ready <= '1'; |
|
1011 | fifo_1_ready <= '1'; | |
1012 | END IF; |
|
1012 | END IF; | |
1013 |
|
1013 | |||
1014 | END IF; |
|
1014 | END IF; | |
1015 | END PROCESS; |
|
1015 | END PROCESS; | |
1016 |
|
1016 | |||
1017 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE |
|
1017 | MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE | |
1018 | '1' WHEN fifo_0_ready = '0' ELSE |
|
1018 | '1' WHEN fifo_0_ready = '0' ELSE | |
1019 | FSM_DMA_fifo_ren; |
|
1019 | FSM_DMA_fifo_ren; | |
1020 |
|
1020 | |||
1021 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE |
|
1021 | MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE | |
1022 | '1' WHEN fifo_1_ready = '0' ELSE |
|
1022 | '1' WHEN fifo_1_ready = '0' ELSE | |
1023 | FSM_DMA_fifo_ren; |
|
1023 | FSM_DMA_fifo_ren; | |
1024 |
|
1024 | |||
1025 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
1025 | FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
1026 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
1026 | MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
1027 | '1'; |
|
1027 | '1'; | |
1028 |
|
1028 | |||
1029 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE |
|
1029 | FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE | |
1030 | status_component_fifo_1; |
|
1030 | status_component_fifo_1; | |
1031 |
|
1031 | |||
1032 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE |
|
1032 | FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE | |
1033 | MEM_OUT_SM_Data_out(63 DOWNTO 32); |
|
1033 | MEM_OUT_SM_Data_out(63 DOWNTO 32); | |
1034 |
|
1034 | |||
1035 |
|
1035 | |||
1036 | FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE |
|
1036 | FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE | |
1037 | MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE |
|
1037 | MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE | |
1038 | '1'; |
|
1038 | '1'; | |
1039 |
|
1039 | |||
1040 | ----------------------------------------------------------------------------- |
|
1040 | ----------------------------------------------------------------------------- | |
1041 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN |
|
1041 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), --IN | |
1042 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN |
|
1042 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), --IN | |
1043 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN |
|
1043 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), --IN | |
1044 | -- fifo_data => FSM_DMA_fifo_data, --IN |
|
1044 | -- fifo_data => FSM_DMA_fifo_data, --IN | |
1045 | -- fifo_empty => FSM_DMA_fifo_empty, --IN |
|
1045 | -- fifo_empty => FSM_DMA_fifo_empty, --IN | |
1046 | -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN |
|
1046 | -- fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, --IN | |
1047 | -- fifo_ren => FSM_DMA_fifo_ren, --OUT |
|
1047 | -- fifo_ren => FSM_DMA_fifo_ren, --OUT | |
1048 |
|
1048 | |||
1049 |
|
1049 | |||
1050 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma |
|
1050 | lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma | |
1051 | PORT MAP ( |
|
1051 | PORT MAP ( | |
1052 | clk => clk, |
|
1052 | clk => clk, | |
1053 | rstn => rstn, |
|
1053 | rstn => rstn, | |
1054 | run => run, |
|
1054 | run => run, | |
1055 |
|
1055 | |||
1056 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
1056 | fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
1057 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
1057 | fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
1058 | fifo_data => FSM_DMA_fifo_data, |
|
1058 | fifo_data => FSM_DMA_fifo_data, | |
1059 | fifo_empty => FSM_DMA_fifo_empty, |
|
1059 | fifo_empty => FSM_DMA_fifo_empty, | |
1060 | fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, |
|
1060 | fifo_empty_threshold => FSM_DMA_fifo_empty_threshold, | |
1061 | fifo_ren => FSM_DMA_fifo_ren, |
|
1061 | fifo_ren => FSM_DMA_fifo_ren, | |
1062 |
|
1062 | |||
1063 | dma_fifo_valid_burst => dma_fifo_burst_valid, |
|
1063 | dma_fifo_valid_burst => dma_fifo_burst_valid, | |
1064 | dma_fifo_data => dma_fifo_data, |
|
1064 | dma_fifo_data => dma_fifo_data, | |
1065 | dma_fifo_ren => dma_fifo_ren, |
|
1065 | dma_fifo_ren => dma_fifo_ren, | |
1066 | dma_buffer_new => dma_buffer_new, |
|
1066 | dma_buffer_new => dma_buffer_new, | |
1067 | dma_buffer_addr => dma_buffer_addr, |
|
1067 | dma_buffer_addr => dma_buffer_addr, | |
1068 | dma_buffer_length => dma_buffer_length, |
|
1068 | dma_buffer_length => dma_buffer_length, | |
1069 | dma_buffer_full => dma_buffer_full, |
|
1069 | dma_buffer_full => dma_buffer_full, | |
1070 | dma_buffer_full_err => dma_buffer_full_err, |
|
1070 | dma_buffer_full_err => dma_buffer_full_err, | |
1071 |
|
1071 | |||
1072 | status_ready_matrix_f0 => status_ready_matrix_f0, |
|
1072 | status_ready_matrix_f0 => status_ready_matrix_f0, | |
1073 | status_ready_matrix_f1 => status_ready_matrix_f1, |
|
1073 | status_ready_matrix_f1 => status_ready_matrix_f1, | |
1074 | status_ready_matrix_f2 => status_ready_matrix_f2, |
|
1074 | status_ready_matrix_f2 => status_ready_matrix_f2, | |
1075 | addr_matrix_f0 => addr_matrix_f0, |
|
1075 | addr_matrix_f0 => addr_matrix_f0, | |
1076 | addr_matrix_f1 => addr_matrix_f1, |
|
1076 | addr_matrix_f1 => addr_matrix_f1, | |
1077 | addr_matrix_f2 => addr_matrix_f2, |
|
1077 | addr_matrix_f2 => addr_matrix_f2, | |
1078 | length_matrix_f0 => length_matrix_f0, |
|
1078 | length_matrix_f0 => length_matrix_f0, | |
1079 | length_matrix_f1 => length_matrix_f1, |
|
1079 | length_matrix_f1 => length_matrix_f1, | |
1080 | length_matrix_f2 => length_matrix_f2, |
|
1080 | length_matrix_f2 => length_matrix_f2, | |
1081 | ready_matrix_f0 => ready_matrix_f0, |
|
1081 | ready_matrix_f0 => ready_matrix_f0, | |
1082 | ready_matrix_f1 => ready_matrix_f1, |
|
1082 | ready_matrix_f1 => ready_matrix_f1, | |
1083 | ready_matrix_f2 => ready_matrix_f2, |
|
1083 | ready_matrix_f2 => ready_matrix_f2, | |
1084 | matrix_time_f0 => matrix_time_f0, |
|
1084 | matrix_time_f0 => matrix_time_f0, | |
1085 | matrix_time_f1 => matrix_time_f1, |
|
1085 | matrix_time_f1 => matrix_time_f1, | |
1086 | matrix_time_f2 => matrix_time_f2, |
|
1086 | matrix_time_f2 => matrix_time_f2, | |
1087 | error_buffer_full => error_buffer_full); |
|
1087 | error_buffer_full => error_buffer_full); | |
1088 |
|
1088 | |||
1089 |
|
1089 | |||
1090 |
|
1090 | |||
1091 |
|
1091 | |||
1092 |
|
1092 | |||
1093 | --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO |
|
1093 | --dma_fifo_burst_valid: OUT STD_LOGIC; --TODO | |
1094 | --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
1094 | --dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
1095 | --dma_fifo_ren : IN STD_LOGIC; --TODO |
|
1095 | --dma_fifo_ren : IN STD_LOGIC; --TODO | |
1096 | --dma_buffer_new : OUT STD_LOGIC; --TODO |
|
1096 | --dma_buffer_new : OUT STD_LOGIC; --TODO | |
1097 | --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO |
|
1097 | --dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --TODO | |
1098 | --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO |
|
1098 | --dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); --TODO | |
1099 | --dma_buffer_full : IN STD_LOGIC; --TODO |
|
1099 | --dma_buffer_full : IN STD_LOGIC; --TODO | |
1100 | --dma_buffer_full_err : IN STD_LOGIC; --TODO |
|
1100 | --dma_buffer_full_err : IN STD_LOGIC; --TODO | |
1101 |
|
1101 | |||
1102 | ---- Reg out |
|
1102 | ---- Reg out | |
1103 | --ready_matrix_f0 : OUT STD_LOGIC; -- TODO |
|
1103 | --ready_matrix_f0 : OUT STD_LOGIC; -- TODO | |
1104 | --ready_matrix_f1 : OUT STD_LOGIC; -- TODO |
|
1104 | --ready_matrix_f1 : OUT STD_LOGIC; -- TODO | |
1105 | --ready_matrix_f2 : OUT STD_LOGIC; -- TODO |
|
1105 | --ready_matrix_f2 : OUT STD_LOGIC; -- TODO | |
1106 | --error_bad_component_error : OUT STD_LOGIC; -- TODO |
|
1106 | --error_bad_component_error : OUT STD_LOGIC; -- TODO | |
1107 | --error_buffer_full : OUT STD_LOGIC; -- TODO |
|
1107 | --error_buffer_full : OUT STD_LOGIC; -- TODO | |
1108 |
|
1108 | |||
1109 | ---- Reg In |
|
1109 | ---- Reg In | |
1110 | --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO |
|
1110 | --status_ready_matrix_f0 : IN STD_LOGIC; -- TODO | |
1111 | --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO |
|
1111 | --status_ready_matrix_f1 : IN STD_LOGIC; -- TODO | |
1112 | --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO |
|
1112 | --status_ready_matrix_f2 : IN STD_LOGIC; -- TODO | |
1113 |
|
1113 | |||
1114 | --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1114 | --addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1115 | --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1115 | --addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1116 | --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO |
|
1116 | --addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO | |
1117 |
|
1117 | |||
1118 | --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
1118 | --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
1119 | --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO |
|
1119 | --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO | |
1120 | --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO |
|
1120 | --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- TODO | |
1121 | ----------------------------------------------------------------------------- |
|
1121 | ----------------------------------------------------------------------------- | |
1122 |
|
1122 | |||
1123 | ----------------------------------------------------------------------------- |
|
1123 | ----------------------------------------------------------------------------- | |
1124 | --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma |
|
1124 | --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma | |
1125 | -- PORT MAP ( |
|
1125 | -- PORT MAP ( | |
1126 | -- HCLK => clk, |
|
1126 | -- HCLK => clk, | |
1127 | -- HRESETn => rstn, |
|
1127 | -- HRESETn => rstn, | |
1128 |
|
1128 | |||
1129 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), |
|
1129 | -- fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4), | |
1130 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), |
|
1130 | -- fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0), | |
1131 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), |
|
1131 | -- fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6), | |
1132 | -- fifo_data => FSM_DMA_fifo_data, |
|
1132 | -- fifo_data => FSM_DMA_fifo_data, | |
1133 | -- fifo_empty => FSM_DMA_fifo_empty, |
|
1133 | -- fifo_empty => FSM_DMA_fifo_empty, | |
1134 | -- fifo_ren => FSM_DMA_fifo_ren, |
|
1134 | -- fifo_ren => FSM_DMA_fifo_ren, | |
1135 |
|
1135 | |||
1136 | -- dma_addr => dma_addr, |
|
1136 | -- dma_addr => dma_addr, | |
1137 | -- dma_data => dma_data, |
|
1137 | -- dma_data => dma_data, | |
1138 | -- dma_valid => dma_valid, |
|
1138 | -- dma_valid => dma_valid, | |
1139 | -- dma_valid_burst => dma_valid_burst, |
|
1139 | -- dma_valid_burst => dma_valid_burst, | |
1140 | -- dma_ren => dma_ren, |
|
1140 | -- dma_ren => dma_ren, | |
1141 | -- dma_done => dma_done, |
|
1141 | -- dma_done => dma_done, | |
1142 |
|
1142 | |||
1143 | -- ready_matrix_f0 => ready_matrix_f0, |
|
1143 | -- ready_matrix_f0 => ready_matrix_f0, | |
1144 | -- ready_matrix_f1 => ready_matrix_f1, |
|
1144 | -- ready_matrix_f1 => ready_matrix_f1, | |
1145 | -- ready_matrix_f2 => ready_matrix_f2, |
|
1145 | -- ready_matrix_f2 => ready_matrix_f2, | |
1146 |
|
1146 | |||
1147 | -- error_bad_component_error => error_bad_component_error, |
|
1147 | -- error_bad_component_error => error_bad_component_error, | |
1148 | -- error_buffer_full => error_buffer_full, |
|
1148 | -- error_buffer_full => error_buffer_full, | |
1149 |
|
1149 | |||
1150 | -- debug_reg => debug_reg, |
|
1150 | -- debug_reg => debug_reg, | |
1151 | -- status_ready_matrix_f0 => status_ready_matrix_f0, |
|
1151 | -- status_ready_matrix_f0 => status_ready_matrix_f0, | |
1152 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
|
1152 | -- status_ready_matrix_f1 => status_ready_matrix_f1, | |
1153 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
|
1153 | -- status_ready_matrix_f2 => status_ready_matrix_f2, | |
1154 |
|
1154 | |||
1155 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
|
1155 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, | |
1156 | -- config_active_interruption_onError => config_active_interruption_onError, |
|
1156 | -- config_active_interruption_onError => config_active_interruption_onError, | |
1157 |
|
1157 | |||
1158 | -- addr_matrix_f0 => addr_matrix_f0, |
|
1158 | -- addr_matrix_f0 => addr_matrix_f0, | |
1159 | -- addr_matrix_f1 => addr_matrix_f1, |
|
1159 | -- addr_matrix_f1 => addr_matrix_f1, | |
1160 | -- addr_matrix_f2 => addr_matrix_f2, |
|
1160 | -- addr_matrix_f2 => addr_matrix_f2, | |
1161 |
|
1161 | |||
1162 | -- matrix_time_f0 => matrix_time_f0, |
|
1162 | -- matrix_time_f0 => matrix_time_f0, | |
1163 | -- matrix_time_f1 => matrix_time_f1, |
|
1163 | -- matrix_time_f1 => matrix_time_f1, | |
1164 | -- matrix_time_f2 => matrix_time_f2 |
|
1164 | -- matrix_time_f2 => matrix_time_f2 | |
1165 | -- ); |
|
1165 | -- ); | |
1166 | ----------------------------------------------------------------------------- |
|
1166 | ----------------------------------------------------------------------------- | |
1167 |
|
1167 | |||
1168 |
|
1168 | |||
1169 |
|
1169 | |||
1170 |
|
1170 | |||
1171 |
|
1171 | |||
1172 |
|
1172 | |||
1173 | ----------------------------------------------------------------------------- |
|
1173 | ----------------------------------------------------------------------------- | |
1174 | -- TIME MANAGMENT |
|
1174 | -- TIME MANAGMENT | |
1175 | ----------------------------------------------------------------------------- |
|
1175 | ----------------------------------------------------------------------------- | |
1176 | all_time <= coarse_time & fine_time; |
|
1176 | all_time <= coarse_time & fine_time; | |
1177 | -- |
|
1177 | -- | |
1178 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; |
|
1178 | f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0'; | |
1179 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; |
|
1179 | f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0'; | |
1180 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; |
|
1180 | f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0'; | |
1181 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; |
|
1181 | f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0'; | |
1182 |
|
1182 | |||
1183 | all_time_reg: FOR I IN 0 TO 3 GENERATE |
|
1183 | all_time_reg: FOR I IN 0 TO 3 GENERATE | |
1184 |
|
1184 | |||
1185 | PROCESS (clk, rstn) |
|
1185 | PROCESS (clk, rstn) | |
1186 | BEGIN |
|
1186 | BEGIN | |
1187 | IF rstn = '0' THEN |
|
1187 | IF rstn = '0' THEN | |
1188 | f_empty_reg(I) <= '1'; |
|
1188 | f_empty_reg(I) <= '1'; | |
1189 | ELSIF clk'event AND clk = '1' THEN |
|
1189 | ELSIF clk'event AND clk = '1' THEN | |
1190 | f_empty_reg(I) <= f_empty(I); |
|
1190 | f_empty_reg(I) <= f_empty(I); | |
1191 | END IF; |
|
1191 | END IF; | |
1192 | END PROCESS; |
|
1192 | END PROCESS; | |
1193 |
|
1193 | |||
1194 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; |
|
1194 | time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0'; | |
1195 |
|
1195 | |||
1196 | s_m_t_m_f0_A : spectral_matrix_time_managment |
|
1196 | s_m_t_m_f0_A : spectral_matrix_time_managment | |
1197 | PORT MAP ( |
|
1197 | PORT MAP ( | |
1198 | clk => clk, |
|
1198 | clk => clk, | |
1199 | rstn => rstn, |
|
1199 | rstn => rstn, | |
1200 | time_in => all_time, |
|
1200 | time_in => all_time, | |
1201 | update_1 => time_update_f(I), |
|
1201 | update_1 => time_update_f(I), | |
1202 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) |
|
1202 | time_out => time_reg_f((I+1)*48-1 DOWNTO I*48) | |
1203 | ); |
|
1203 | ); | |
1204 |
|
1204 | |||
1205 | END GENERATE all_time_reg; |
|
1205 | END GENERATE all_time_reg; | |
1206 |
|
1206 | |||
1207 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); |
|
1207 | time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48); | |
1208 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); |
|
1208 | time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48); | |
1209 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); |
|
1209 | time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48); | |
1210 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); |
|
1210 | time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48); | |
1211 |
|
1211 | |||
1212 | ----------------------------------------------------------------------------- |
|
1212 | ----------------------------------------------------------------------------- | |
1213 |
|
1213 | |||
1214 | END Behavioral; |
|
1214 | END Behavioral; |
@@ -1,100 +1,106 | |||||
1 | LIBRARY ieee; |
|
1 | LIBRARY ieee; | |
2 | USE ieee.std_logic_1164.ALL; |
|
2 | USE ieee.std_logic_1164.ALL; | |
3 |
|
3 | |||
4 | ENTITY lpp_lfr_ms_reg_head IS |
|
4 | ENTITY lpp_lfr_ms_reg_head IS | |
5 |
|
5 | |||
6 | PORT ( |
|
6 | PORT ( | |
7 | clk : IN STD_LOGIC; |
|
7 | clk : IN STD_LOGIC; | |
8 | rstn : IN STD_LOGIC; |
|
8 | rstn : IN STD_LOGIC; | |
9 |
|
9 | |||
10 | in_wen : IN STD_LOGIC; |
|
10 | in_wen : IN STD_LOGIC; | |
11 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
11 | in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
12 | in_full : IN STD_LOGIC; |
|
12 | in_full : IN STD_LOGIC; | |
13 | in_empty : IN STD_LOGIC; |
|
13 | in_empty : IN STD_LOGIC; | |
14 |
|
14 | |||
15 | out_write_error : OUT STD_LOGIC; |
|
15 | out_write_error : OUT STD_LOGIC; | |
16 |
|
16 | |||
17 | out_wen : OUT STD_LOGIC; |
|
17 | out_wen : OUT STD_LOGIC; | |
18 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
18 | out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
19 | out_full : OUT STD_LOGIC |
|
19 | out_full : OUT STD_LOGIC | |
20 | ); |
|
20 | ); | |
21 |
|
21 | |||
22 | END lpp_lfr_ms_reg_head; |
|
22 | END lpp_lfr_ms_reg_head; | |
23 |
|
23 | |||
24 | ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS |
|
24 | ARCHITECTURE Beh OF lpp_lfr_ms_reg_head IS | |
25 | TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2); |
|
25 | TYPE fsm_state_reg_head IS (REG_EMPTY, REG_ONE_DATA, REG_FULL, REG_FULL_2); | |
26 | SIGNAL fsm_state : fsm_state_reg_head; |
|
26 | SIGNAL fsm_state : fsm_state_reg_head; | |
27 |
|
27 | |||
28 | SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
28 | SIGNAL reg_data2 : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
29 | SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); |
|
29 | SIGNAL reg_data : STD_LOGIC_VECTOR(5*16-1 DOWNTO 0); | |
30 | SIGNAL out_wen_s : STD_LOGIC; |
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30 | SIGNAL out_wen_s : STD_LOGIC; | |
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31 | ||||
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32 | SIGNAL in_full_s : STD_LOGIC; | |||
31 | BEGIN -- Beh |
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33 | BEGIN -- Beh | |
32 |
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34 | |||
33 | PROCESS (clk, rstn) |
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35 | PROCESS (clk, rstn) | |
34 | BEGIN |
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36 | BEGIN | |
35 | IF rstn = '0' THEN |
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37 | IF rstn = '0' THEN | |
36 | fsm_state <= REG_EMPTY; |
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38 | fsm_state <= REG_EMPTY; | |
37 | reg_data <= (OTHERS => '0'); |
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39 | reg_data <= (OTHERS => '0'); | |
38 | reg_data2 <= (OTHERS => '0'); |
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40 | reg_data2 <= (OTHERS => '0'); | |
39 | out_wen_s <= '1'; |
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41 | out_wen_s <= '1'; | |
40 | out_write_error <= '0'; |
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42 | out_write_error <= '0'; | |
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43 | in_full_s <= '0'; | |||
41 | ELSIF clk'event AND clk = '1' THEN |
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44 | ELSIF clk'event AND clk = '1' THEN | |
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45 | in_full_s <= in_full; | |||
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46 | ||||
42 |
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47 | out_wen_s <= '1'; | |
43 | out_write_error <= '0'; |
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48 | out_write_error <= '0'; | |
44 | CASE fsm_state IS |
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49 | CASE fsm_state IS | |
45 | WHEN REG_EMPTY => |
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50 | WHEN REG_EMPTY => | |
46 | reg_data <= in_data; |
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51 | reg_data <= in_data; | |
47 | IF in_wen = '0' AND in_full = '1' THEN |
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52 | IF in_wen = '0' AND in_full_s = '1' THEN | |
48 | fsm_state <= REG_ONE_DATA; |
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53 | fsm_state <= REG_ONE_DATA; | |
49 | END IF; |
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54 | END IF; | |
50 |
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55 | |||
51 | WHEN REG_ONE_DATA => |
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56 | WHEN REG_ONE_DATA => | |
52 | reg_data2 <= in_data; |
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57 | reg_data2 <= in_data; | |
53 | IF in_wen = '0' AND in_full = '1' THEN |
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58 | IF in_wen = '0' AND in_full_s = '1' THEN | |
54 | fsm_state <= REG_FULL; |
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59 | fsm_state <= REG_FULL; | |
55 | ELSIF in_empty = '1' THEN |
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60 | ELSIF in_empty = '1' THEN | |
56 | out_wen_s <= '0'; |
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61 | out_wen_s <= '0'; | |
57 | IF in_wen = '0' THEN |
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62 | IF in_wen = '0' THEN | |
58 | reg_data <= in_data; |
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63 | reg_data <= in_data; | |
59 | ELSE |
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64 | ELSE | |
60 | fsm_state <= REG_EMPTY; |
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65 | fsm_state <= REG_EMPTY; | |
61 | END IF; |
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66 | END IF; | |
62 | END IF; |
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67 | END IF; | |
63 |
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68 | |||
64 | WHEN REG_FULL => |
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69 | WHEN REG_FULL => | |
65 | IF in_empty = '1' THEN |
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70 | IF in_empty = '1' THEN | |
66 | out_wen_s <= '0'; |
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71 | out_wen_s <= '0'; | |
67 | IF in_wen = '0' THEN |
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72 | IF in_wen = '0' THEN | |
68 | reg_data2 <= in_data; |
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73 | reg_data2 <= in_data; | |
69 | ELSE |
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74 | ELSE | |
70 | fsm_state <= REG_FULL_2; |
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75 | fsm_state <= REG_FULL_2; | |
71 | END IF; |
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76 | END IF; | |
72 | ELSE |
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77 | ELSE | |
73 | IF in_wen = '0' THEN |
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78 | IF in_wen = '0' THEN | |
74 | out_write_error <= '1'; |
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79 | out_write_error <= '1'; | |
75 | END IF; |
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80 | END IF; | |
76 | END IF; |
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81 | END IF; | |
77 |
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82 | |||
78 | WHEN REG_FULL_2 => |
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83 | WHEN REG_FULL_2 => | |
79 | out_wen_s <= '0'; |
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84 | out_wen_s <= '0'; | |
80 | fsm_state <= REG_EMPTY; |
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85 | fsm_state <= REG_EMPTY; | |
81 |
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86 | |||
82 | WHEN OTHERS => NULL; |
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87 | WHEN OTHERS => NULL; | |
83 | END CASE; |
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88 | END CASE; | |
84 |
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89 | |||
85 | END IF; |
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90 | END IF; | |
86 | END PROCESS; |
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91 | END PROCESS; | |
87 |
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92 | |||
88 | out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full; |
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93 | out_full <= '1' WHEN fsm_state = REG_FULL ELSE in_full_s; | |
89 |
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94 | |||
90 | out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE |
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95 | out_data <= reg_data2 WHEN fsm_state = REG_FULL ELSE | |
91 | reg_data WHEN fsm_state = REG_ONE_DATA ELSE |
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96 | reg_data WHEN fsm_state = REG_ONE_DATA ELSE | |
92 | reg_data WHEN fsm_state = REG_FULL_2 ELSE |
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97 | reg_data WHEN fsm_state = REG_FULL_2 ELSE | |
93 | in_data; |
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98 | in_data; | |
94 |
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99 | |||
95 | out_wen <= '0' WHEN out_wen_s = '0' ELSE |
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100 | out_wen <= '0' WHEN out_wen_s = '0' ELSE | |
96 | '1' WHEN fsm_state = REG_ONE_DATA ELSE |
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101 | '1' WHEN fsm_state = REG_ONE_DATA ELSE | |
97 | '1' WHEN fsm_state = REG_FULL ELSE |
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102 | '1' WHEN fsm_state = REG_FULL ELSE | |
98 | in_wen; |
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103 | '1' WHEN in_full_s = '1' ELSE | |
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104 | in_wen; | |||
99 |
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105 | |||
100 | END Beh; |
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106 | END Beh; |
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