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MINI-LFR 0.1.16
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_time_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 177 -----------------------------------------------------------------------------
176 178
177 179 BEGIN -- beh
178 180
179 181 -----------------------------------------------------------------------------
180 182 -- CLK
181 183 -----------------------------------------------------------------------------
182 184
183 185 PROCESS(clk_50)
184 186 BEGIN
185 187 IF clk_50'EVENT AND clk_50 = '1' THEN
186 188 clk_50_s <= NOT clk_50_s;
187 189 END IF;
188 190 END PROCESS;
189 191
190 192 PROCESS(clk_50_s)
191 193 BEGIN
192 194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
193 195 clk_25 <= NOT clk_25;
194 196 END IF;
195 197 END PROCESS;
196 198
197 199 PROCESS(clk_49)
198 200 BEGIN
199 201 IF clk_49'EVENT AND clk_49 = '1' THEN
200 202 clk_24 <= NOT clk_24;
201 203 END IF;
202 204 END PROCESS;
203 205
204 206 -----------------------------------------------------------------------------
205 207
206 208 PROCESS (clk_25, reset)
207 209 BEGIN -- PROCESS
208 210 IF reset = '0' THEN -- asynchronous reset (active low)
209 211 LED0 <= '0';
210 212 LED1 <= '0';
211 213 LED2 <= '0';
212 214 --IO1 <= '0';
213 215 --IO2 <= '1';
214 216 --IO3 <= '0';
215 217 --IO4 <= '0';
216 218 --IO5 <= '0';
217 219 --IO6 <= '0';
218 220 --IO7 <= '0';
219 221 --IO8 <= '0';
220 222 --IO9 <= '0';
221 223 --IO10 <= '0';
222 224 --IO11 <= '0';
223 225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
224 226 LED0 <= '0';
225 227 LED1 <= '1';
226 228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
227 229 --IO1 <= '1';
228 230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
229 231 --IO3 <= ADC_SDO(0);
230 232 --IO4 <= ADC_SDO(1);
231 233 --IO5 <= ADC_SDO(2);
232 234 --IO6 <= ADC_SDO(3);
233 235 --IO7 <= ADC_SDO(4);
234 236 --IO8 <= ADC_SDO(5);
235 237 --IO9 <= ADC_SDO(6);
236 238 --IO10 <= ADC_SDO(7);
237 239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
238 240 END IF;
239 241 END PROCESS;
240 242
241 243 PROCESS (clk_24, reset)
242 244 BEGIN -- PROCESS
243 245 IF reset = '0' THEN -- asynchronous reset (active low)
244 246 I00_s <= '0';
245 247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
246 248 I00_s <= NOT I00_s ;
247 249 END IF;
248 250 END PROCESS;
249 251 -- IO0 <= I00_s;
250 252
251 253 --UARTs
252 254 nCTS1 <= '1';
253 255 nCTS2 <= '1';
254 256 nDCD2 <= '1';
255 257
256 258 --EXT CONNECTOR
257 259
258 260 --SPACE WIRE
259 261
260 262 leon3_soc_1 : leon3_soc
261 263 GENERIC MAP (
262 264 fabtech => apa3e,
263 265 memtech => apa3e,
264 266 padtech => inferred,
265 267 clktech => inferred,
266 268 disas => 0,
267 269 dbguart => 0,
268 270 pclow => 2,
269 271 clk_freq => 25000,
270 272 NB_CPU => 1,
271 273 ENABLE_FPU => 1,
272 274 FPU_NETLIST => 0,
273 275 ENABLE_DSU => 1,
274 276 ENABLE_AHB_UART => 1,
275 277 ENABLE_APB_UART => 1,
276 278 ENABLE_IRQMP => 1,
277 279 ENABLE_GPT => 1,
278 280 NB_AHB_MASTER => NB_AHB_MASTER,
279 281 NB_AHB_SLAVE => NB_AHB_SLAVE,
280 282 NB_APB_SLAVE => NB_APB_SLAVE)
281 283 PORT MAP (
282 284 clk => clk_25,
283 285 reset => reset,
284 286 errorn => errorn,
285 287 ahbrxd => TXD1,
286 288 ahbtxd => RXD1,
287 289 urxd1 => TXD2,
288 290 utxd1 => RXD2,
289 291 address => SRAM_A,
290 292 data => SRAM_DQ,
291 293 nSRAM_BE0 => SRAM_nBE(0),
292 294 nSRAM_BE1 => SRAM_nBE(1),
293 295 nSRAM_BE2 => SRAM_nBE(2),
294 296 nSRAM_BE3 => SRAM_nBE(3),
295 297 nSRAM_WE => SRAM_nWE,
296 298 nSRAM_CE => SRAM_CE,
297 299 nSRAM_OE => SRAM_nOE,
298 300
299 301 apbi_ext => apbi_ext,
300 302 apbo_ext => apbo_ext,
301 303 ahbi_s_ext => ahbi_s_ext,
302 304 ahbo_s_ext => ahbo_s_ext,
303 305 ahbi_m_ext => ahbi_m_ext,
304 306 ahbo_m_ext => ahbo_m_ext);
305 307
306 308 -------------------------------------------------------------------------------
307 309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
308 310 -------------------------------------------------------------------------------
309 311 apb_lfr_time_management_1 : apb_lfr_time_management
310 312 GENERIC MAP (
311 313 pindex => 6,
312 314 paddr => 6,
313 315 pmask => 16#fff#,
314 316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
315 317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
316 318 PORT MAP (
317 319 clk25MHz => clk_25,
318 320 clk24_576MHz => clk_24, -- 49.152MHz/2
319 321 resetn => reset,
320 322 grspw_tick => swno.tickout,
321 323 apbi => apbi_ext,
322 324 apbo => apbo_ext(6),
323 325 coarse_time => coarse_time,
324 326 fine_time => fine_time);
325 327
326 328 -----------------------------------------------------------------------
327 329 --- SpaceWire --------------------------------------------------------
328 330 -----------------------------------------------------------------------
329 331
330 332 SPW_EN <= '1';
331 333
332 334 spw_clk <= clk_50_s;
333 335 spw_rxtxclk <= spw_clk;
334 336 spw_rxclkn <= NOT spw_rxtxclk;
335 337
336 338 -- PADS for SPW1
337 339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
338 340 PORT MAP (SPW_NOM_DIN, dtmp(0));
339 341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
340 342 PORT MAP (SPW_NOM_SIN, stmp(0));
341 343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
342 344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
343 345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
344 346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
345 347 -- PADS FOR SPW2
346 348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 349 PORT MAP (SPW_RED_SIN, dtmp(1));
348 350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 351 PORT MAP (SPW_RED_DIN, stmp(1));
350 352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
351 353 PORT MAP (SPW_RED_DOUT, swno.d(1));
352 354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
353 355 PORT MAP (SPW_RED_SOUT, swno.s(1));
354 356
355 357 -- GRSPW PHY
356 358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
357 359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
358 360 spw_phy0 : grspw_phy
359 361 GENERIC MAP(
360 362 tech => apa3e,
361 363 rxclkbuftype => 1,
362 364 scantest => 0)
363 365 PORT MAP(
364 366 rxrst => swno.rxrst,
365 367 di => dtmp(j),
366 368 si => stmp(j),
367 369 rxclko => spw_rxclk(j),
368 370 do => swni.d(j),
369 371 ndo => swni.nd(j*5+4 DOWNTO j*5),
370 372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
371 373 END GENERATE spw_inputloop;
372 374
373 375 -- SPW core
374 376 sw0 : grspwm GENERIC MAP(
375 377 tech => apa3e,
376 378 hindex => 1,
377 379 pindex => 5,
378 380 paddr => 5,
379 381 pirq => 11,
380 382 sysfreq => 25000, -- CPU_FREQ
381 383 rmap => 1,
382 384 rmapcrc => 1,
383 385 fifosize1 => 16,
384 386 fifosize2 => 16,
385 387 rxclkbuftype => 1,
386 388 rxunaligned => 0,
387 389 rmapbufs => 4,
388 390 ft => 0,
389 391 netlist => 0,
390 392 ports => 2,
391 393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
392 394 memtech => apa3e,
393 395 destkey => 2,
394 396 spwcore => 1
395 397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
396 398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
397 399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
398 400 )
399 401 PORT MAP(reset, clk_25, spw_rxclk(0),
400 402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
401 403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
402 404 swni, swno);
403 405
404 406 swni.tickin <= '0';
405 407 swni.rmapen <= '1';
406 408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
407 409 swni.tickinraw <= '0';
408 410 swni.timein <= (OTHERS => '0');
409 411 swni.dcrstval <= (OTHERS => '0');
410 412 swni.timerrstval <= (OTHERS => '0');
411 413
412 414 -------------------------------------------------------------------------------
413 415 -- LFR ------------------------------------------------------------------------
414 416 -------------------------------------------------------------------------------
415 417 lpp_lfr_1 : lpp_lfr
416 418 GENERIC MAP (
417 419 Mem_use => use_RAM,
418 420 nb_data_by_buffer_size => 32,
419 421 nb_word_by_buffer_size => 30,
420 422 nb_snapshot_param_size => 32,
421 423 delta_vector_size => 32,
422 424 delta_vector_size_f0_2 => 7, -- log2(96)
423 425 pindex => 15,
424 426 paddr => 15,
425 427 pmask => 16#fff#,
426 428 pirq_ms => 6,
427 429 pirq_wfp => 14,
428 430 hindex => 2,
429 431 top_lfr_version => X"000110") -- aa.bb.cc version
430 432 PORT MAP (
431 433 clk => clk_25,
432 434 rstn => reset,
433 435 sample_B => sample_s(2 DOWNTO 0),
434 436 sample_E => sample_s(7 DOWNTO 3),
435 437 sample_val => sample_val,
436 438 apbi => apbi_ext,
437 439 apbo => apbo_ext(15),
438 440 ahbi => ahbi_m_ext,
439 441 ahbo => ahbo_m_ext(2),
440 442 coarse_time => coarse_time,
441 443 fine_time => fine_time,
442 444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
443 447 observation_reg => observation_reg);
444 448
445 449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 451 END GENERATE all_sample;
448 452
449 453
450 454
451 455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 456 GENERIC MAP(
453 457 ChannelCount => 8,
454 458 SampleNbBits => 14,
455 459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 461 PORT MAP (
458 462 -- CONV
459 463 cnv_clk => clk_24,
460 464 cnv_rstn => reset,
461 465 cnv => ADC_nCS_sig,
462 466 -- DATA
463 467 clk => clk_25,
464 468 rstn => reset,
465 469 sck => ADC_CLK_sig,
466 470 sdo => ADC_SDO_sig,
467 471 -- SAMPLE
468 472 sample => sample,
469 473 sample_val => sample_val);
470 474
471 475 --IO10 <= ADC_SDO_sig(5);
472 476 --IO9 <= ADC_SDO_sig(4);
473 477 --IO8 <= ADC_SDO_sig(3);
474 478
475 479 ADC_nCS <= ADC_nCS_sig;
476 480 ADC_CLK <= ADC_CLK_sig;
477 481 ADC_SDO_sig <= ADC_SDO;
478 482
479 483 ----------------------------------------------------------------------
480 484 --- GPIO -----------------------------------------------------------
481 485 ----------------------------------------------------------------------
482 486
483 487 grgpio0 : grgpio
484 488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486 490
487 491 --pio_pad_0 : iopad
488 492 -- GENERIC MAP (tech => CFG_PADTECH)
489 493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 494 --pio_pad_1 : iopad
491 495 -- GENERIC MAP (tech => CFG_PADTECH)
492 496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 497 --pio_pad_2 : iopad
494 498 -- GENERIC MAP (tech => CFG_PADTECH)
495 499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 500 --pio_pad_3 : iopad
497 501 -- GENERIC MAP (tech => CFG_PADTECH)
498 502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 503 --pio_pad_4 : iopad
500 504 -- GENERIC MAP (tech => CFG_PADTECH)
501 505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 506 --pio_pad_5 : iopad
503 507 -- GENERIC MAP (tech => CFG_PADTECH)
504 508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 509 --pio_pad_6 : iopad
506 510 -- GENERIC MAP (tech => CFG_PADTECH)
507 511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 512 --pio_pad_7 : iopad
509 513 -- GENERIC MAP (tech => CFG_PADTECH)
510 514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511 515
512 516 PROCESS (clk_25, reset)
513 517 BEGIN -- PROCESS
514 518 IF reset = '0' THEN -- asynchronous reset (active low)
515 519 IO0 <= '0';
516 520 IO1 <= '0';
517 521 IO2 <= '0';
518 522 IO3 <= '0';
519 523 IO4 <= '0';
520 524 IO5 <= '0';
521 525 IO6 <= '0';
522 526 IO7 <= '0';
523 527 IO8 <= '0';
524 528 IO9 <= '0';
525 529 IO10 <= '0';
526 530 IO11 <= '0';
527 531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 CASE gpioo.dout(1 DOWNTO 0) IS
529 WHEN "00" =>
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "000" =>
530 534 IO0 <= observation_reg(0 );
531 535 IO1 <= observation_reg(1 );
532 536 IO2 <= observation_reg(2 );
533 537 IO3 <= observation_reg(3 );
534 538 IO4 <= observation_reg(4 );
535 539 IO5 <= observation_reg(5 );
536 540 IO6 <= observation_reg(6 );
537 541 IO7 <= observation_reg(7 );
538 542 IO8 <= observation_reg(8 );
539 543 IO9 <= observation_reg(9 );
540 544 IO10 <= observation_reg(10);
541 545 IO11 <= observation_reg(11);
542 WHEN "01" =>
546 WHEN "001" =>
543 547 IO0 <= observation_reg(0 + 12);
544 548 IO1 <= observation_reg(1 + 12);
545 549 IO2 <= observation_reg(2 + 12);
546 550 IO3 <= observation_reg(3 + 12);
547 551 IO4 <= observation_reg(4 + 12);
548 552 IO5 <= observation_reg(5 + 12);
549 553 IO6 <= observation_reg(6 + 12);
550 554 IO7 <= observation_reg(7 + 12);
551 555 IO8 <= observation_reg(8 + 12);
552 556 IO9 <= observation_reg(9 + 12);
553 557 IO10 <= observation_reg(10 + 12);
554 558 IO11 <= observation_reg(11 + 12);
555 WHEN "10" =>
559 WHEN "010" =>
556 560 IO0 <= observation_reg(0 + 12 + 12);
557 561 IO1 <= observation_reg(1 + 12 + 12);
558 562 IO2 <= observation_reg(2 + 12 + 12);
559 563 IO3 <= observation_reg(3 + 12 + 12);
560 564 IO4 <= observation_reg(4 + 12 + 12);
561 565 IO5 <= observation_reg(5 + 12 + 12);
562 566 IO6 <= observation_reg(6 + 12 + 12);
563 567 IO7 <= observation_reg(7 + 12 + 12);
564 568 IO8 <= '0';
565 569 IO9 <= '0';
566 570 IO10 <= '0';
567 571 IO11 <= '0';
568 WHEN "11" =>
569 IO0 <= '0';
570 IO1 <= '0';
571 IO2 <= '0';
572 IO3 <= '0';
573 IO4 <= '0';
574 IO5 <= '0';
575 IO6 <= '0';
576 IO7 <= '0';
577 IO8 <= '0';
578 IO9 <= '0';
579 IO10 <= '0';
580 IO11 <= '0';
572 WHEN "011" =>
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
581 598 WHEN OTHERS => NULL;
582 599 END CASE;
583 600
584 601 END IF;
585 602 END PROCESS;
586 603
587 604 END beh;
Show file before | Show file after | Hide comments
@@ -1,230 +1,232
1 1 onerror {resume}
2 2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
3 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -group debug /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -group debug /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -group debug /tb/ready_reg
16 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_0
21 add wave -noupdate -expand /tb/lpp_lfr_ms_1/observation_vector_1
20 22 add wave -noupdate -divider {New Divider}
21 23 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
22 24 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
23 25 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
24 26 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
25 27 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
26 28 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
27 29 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
28 30 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
29 31 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
30 32 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
31 33 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
32 34 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
33 35 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
34 36 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
35 37 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
36 38 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
37 39 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
38 40 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
39 41 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
40 42 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
41 43 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
42 44 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
43 45 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
44 46 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
45 47 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
46 48 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
47 49 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
48 50 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
49 51 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
50 52 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
51 53 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
52 54 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
53 55 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
54 56 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
55 57 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
56 58 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
57 59 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
58 60 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
59 61 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
60 62 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
61 63 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
62 64 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
63 65 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
64 66 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
65 67 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
66 68 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
67 69 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
68 70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
69 71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
70 72 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
71 73 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
72 74 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
73 75 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
74 76 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
75 77 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
76 78 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
77 79 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
78 80 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
79 81 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
80 82 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
81 83 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
82 84 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
83 85 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
84 86 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
85 87 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
86 88 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
87 89 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
88 90 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
89 91 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
90 92 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
91 93 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
92 94 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
93 95 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
94 96 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
95 97 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
96 98 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
97 99 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
98 100 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
99 101 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
100 102 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
101 103 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
102 104 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
103 105 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
104 106 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
105 107 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
106 108 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
107 109 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
108 110 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
109 111 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
110 112 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
111 113 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
112 114 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
113 115 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
114 116 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
115 117 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
116 118 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
117 119 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
118 120 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
119 121 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
120 122 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
121 123 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
122 124 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
123 125 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
124 126 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
125 127 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
126 128 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
127 129 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
128 130 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
129 131 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
130 132 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
131 133 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
132 134 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
133 135 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
134 136 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
135 137 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
136 138 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
137 139 add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
138 140 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
139 141 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
140 142 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
141 143 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
142 144 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
143 145 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
144 146 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
145 147 add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
146 148 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
147 149 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
148 150 add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
149 151 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
150 152 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
151 153 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
152 154 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
153 155 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
154 156 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
155 157 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
156 158 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
157 159 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
158 160 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp
159 161 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
160 162 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
161 163 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
162 164 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
163 165 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
164 166 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
165 167 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
166 168 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
167 169 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
168 170 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
169 171 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
170 172 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
171 173 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
172 174 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
173 175 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
174 176 add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time
175 177 add wave -noupdate /tb/lpp_lfr_ms_1/fine_time
176 178 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time
177 179 add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
178 180 add wave -noupdate /tb/lpp_lfr_ms_1/status_component
179 181 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
180 182 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
181 183 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms
182 184 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component
183 185 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel
184 186 add wave -noupdate /tb/lpp_lfr_ms_1/all_time
185 187 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a
186 188 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b
187 189 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1
188 190 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2
189 191 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen
190 192 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren
191 193 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata
192 194 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full
193 195 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty
194 196 add wave -noupdate /tb/matrix_time_f0
195 197 add wave -noupdate /tb/matrix_time_f1
196 198 add wave -noupdate /tb/matrix_time_f2
197 199 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
198 200 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
199 201 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
200 202 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
201 203 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
202 204 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
203 205 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
204 206 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
205 207 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
206 208 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
207 209 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
208 210 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
209 211 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
210 212 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
211 213 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
212 214 TreeUpdate [SetDefaultTree]
213 WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0}
215 WaveRestoreCursors {{Cursor 1} {137412164208 ps} 0}
214 216 configure wave -namecolwidth 486
215 217 configure wave -valuecolwidth 112
216 218 configure wave -justifyvalue left
217 219 configure wave -signalnamewidth 0
218 220 configure wave -snapdistance 10
219 221 configure wave -datasetprefix 0
220 222 configure wave -rowmargin 4
221 223 configure wave -childrowmargin 2
222 224 configure wave -gridoffset 0
223 225 configure wave -gridperiod 1
224 226 configure wave -griddelta 40
225 227 configure wave -timeline 0
226 228 configure wave -timelineunits ps
227 229 update
228 WaveRestoreZoom {124629370639 ps} {125891337681 ps}
230 WaveRestoreZoom {0 ps} {787501102500 ps}
229 231 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
230 232 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,942 +1,954
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_memory.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.spectral_matrix_package.ALL;
9 9 USE lpp.lpp_dma_pkg.ALL;
10 10 USE lpp.lpp_Header.ALL;
11 11 USE lpp.lpp_matrix.ALL;
12 12 USE lpp.lpp_matrix.ALL;
13 13 USE lpp.lpp_lfr_pkg.ALL;
14 14 USE lpp.lpp_fft.ALL;
15 15 USE lpp.fft_components.ALL;
16 16
17 17 ENTITY lpp_lfr_ms IS
18 18 GENERIC (
19 19 Mem_use : INTEGER := use_RAM
20 20 );
21 21 PORT (
22 22 clk : IN STD_LOGIC;
23 23 rstn : IN STD_LOGIC;
24 24
25 25 ---------------------------------------------------------------------------
26 26 -- DATA INPUT
27 27 ---------------------------------------------------------------------------
28 28 -- TIME
29 29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 31 --
32 32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 34 --
35 35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 37 --
38 38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40 40
41 41 ---------------------------------------------------------------------------
42 42 -- DMA
43 43 ---------------------------------------------------------------------------
44 44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 46 dma_valid : OUT STD_LOGIC;
47 47 dma_valid_burst : OUT STD_LOGIC;
48 48 dma_ren : IN STD_LOGIC;
49 49 dma_done : IN STD_LOGIC;
50 50
51 51 -- Reg out
52 52 ready_matrix_f0 : OUT STD_LOGIC;
53 53 ready_matrix_f1 : OUT STD_LOGIC;
54 54 ready_matrix_f2 : OUT STD_LOGIC;
55 55 error_bad_component_error : OUT STD_LOGIC;
56 56 error_buffer_full : OUT STD_LOGIC;
57 57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58 58
59 59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 60 --
61 61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
63 63
64 64 -- Reg In
65 65 status_ready_matrix_f0 : IN STD_LOGIC;
66 66 status_ready_matrix_f1 : IN STD_LOGIC;
67 67 status_ready_matrix_f2 : IN STD_LOGIC;
68 68
69 69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
70 70 config_active_interruption_onError : IN STD_LOGIC;
71 71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74 74
75 75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78 78
79 79 );
80 80 END;
81 81
82 82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 83
84 84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 89
90 90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
91 91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 95
96 96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 100
101 101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 102
103 103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
104 104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 107
108 108 SIGNAL error_wen_f0 : STD_LOGIC;
109 109 SIGNAL error_wen_f1 : STD_LOGIC;
110 110 SIGNAL error_wen_f2 : STD_LOGIC;
111 111
112 112 SIGNAL one_sample_f1_full : STD_LOGIC;
113 113 SIGNAL one_sample_f1_wen : STD_LOGIC;
114 114 SIGNAL one_sample_f2_full : STD_LOGIC;
115 115 SIGNAL one_sample_f2_wen : STD_LOGIC;
116 116
117 117 -----------------------------------------------------------------------------
118 118 -- FSM / SWITCH SELECT CHANNEL
119 119 -----------------------------------------------------------------------------
120 120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
121 121 SIGNAL state_fsm_select_channel : fsm_select_channel;
122 122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
123 123
124 124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
125 125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
128 128
129 129 -----------------------------------------------------------------------------
130 130 -- FSM LOAD FFT
131 131 -----------------------------------------------------------------------------
132 132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
133 133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
134 134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
135 135
136 136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
137 137 SIGNAL sample_load : STD_LOGIC;
138 138 SIGNAL sample_valid : STD_LOGIC;
139 139 SIGNAL sample_valid_r : STD_LOGIC;
140 140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
141 141
142 142
143 143 -----------------------------------------------------------------------------
144 144 -- FFT
145 145 -----------------------------------------------------------------------------
146 146 SIGNAL fft_read : STD_LOGIC;
147 147 SIGNAL fft_pong : STD_LOGIC;
148 148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 150 SIGNAL fft_data_valid : STD_LOGIC;
151 151 SIGNAL fft_ready : STD_LOGIC;
152 152 -----------------------------------------------------------------------------
153 153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
154 154 -----------------------------------------------------------------------------
155 155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
156 156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
157 157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
158 158 SIGNAL current_fifo_empty : STD_LOGIC;
159 159 SIGNAL current_fifo_locked : STD_LOGIC;
160 160 SIGNAL current_fifo_full : STD_LOGIC;
161 161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 162
163 163 -----------------------------------------------------------------------------
164 164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
170 170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 172 -----------------------------------------------------------------------------
173 173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
174 174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 176
177 177 SIGNAL SM_correlation_start : STD_LOGIC;
178 178 SIGNAL SM_correlation_auto : STD_LOGIC;
179 179 SIGNAL SM_correlation_done : STD_LOGIC;
180 180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
181 181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
182 182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
183 183 SIGNAL SM_correlation_begin : STD_LOGIC;
184 184
185 185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
186 186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
188 188
189 189 SIGNAL current_matrix_write : STD_LOGIC;
190 190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
191 191 -----------------------------------------------------------------------------
192 192 SIGNAL fifo_0_ready : STD_LOGIC;
193 193 SIGNAL fifo_1_ready : STD_LOGIC;
194 194 SIGNAL fifo_ongoing : STD_LOGIC;
195 195
196 196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
197 197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
198 198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
200 200 -----------------------------------------------------------------------------
201 201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
205 205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 207
208 208 -----------------------------------------------------------------------------
209 209 -- TIME REG & INFOs
210 210 -----------------------------------------------------------------------------
211 211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 212
213 213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
216 216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
217 217
218 218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
222 222
223 223 --SIGNAL time_update_f0_A : STD_LOGIC;
224 224 --SIGNAL time_update_f0_B : STD_LOGIC;
225 225 --SIGNAL time_update_f1 : STD_LOGIC;
226 226 --SIGNAL time_update_f2 : STD_LOGIC;
227 227 --
228 228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
230 230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
231 231
232 232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
234 234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
235 235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
236 236 -----------------------------------------------------------------------------
237 237
238 238 BEGIN
239 239
240 240
241 241 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
242 242
243 243
244 244 switch_f0_inst : spectral_matrix_switch_f0
245 245 PORT MAP (
246 246 clk => clk,
247 247 rstn => rstn,
248 248
249 249 sample_wen => sample_f0_wen,
250 250
251 251 fifo_A_empty => sample_f0_A_empty,
252 252 fifo_A_full => sample_f0_A_full,
253 253 fifo_A_wen => sample_f0_A_wen,
254 254
255 255 fifo_B_empty => sample_f0_B_empty,
256 256 fifo_B_full => sample_f0_B_full,
257 257 fifo_B_wen => sample_f0_B_wen,
258 258
259 259 error_wen => error_wen_f0); -- TODO
260 260
261 261 -----------------------------------------------------------------------------
262 262 -- FIFO IN
263 263 -----------------------------------------------------------------------------
264 264 lppFIFOxN_f0_a : lppFIFOxN
265 265 GENERIC MAP (
266 266 tech => 0,
267 267 Mem_use => Mem_use,
268 268 Data_sz => 16,
269 269 Addr_sz => 8,
270 270 FifoCnt => 5)
271 271 PORT MAP (
272 272 clk => clk,
273 273 rstn => rstn,
274 274
275 275 ReUse => (OTHERS => '0'),
276 276
277 277 wen => sample_f0_A_wen,
278 278 wdata => sample_f0_wdata,
279 279
280 280 ren => sample_f0_A_ren,
281 281 rdata => sample_f0_A_rdata,
282 282
283 283 empty => sample_f0_A_empty,
284 284 full => sample_f0_A_full,
285 285 almost_full => OPEN);
286 286
287 287 lppFIFOxN_f0_b : lppFIFOxN
288 288 GENERIC MAP (
289 289 tech => 0,
290 290 Mem_use => Mem_use,
291 291 Data_sz => 16,
292 292 Addr_sz => 8,
293 293 FifoCnt => 5)
294 294 PORT MAP (
295 295 clk => clk,
296 296 rstn => rstn,
297 297
298 298 ReUse => (OTHERS => '0'),
299 299
300 300 wen => sample_f0_B_wen,
301 301 wdata => sample_f0_wdata,
302 302 ren => sample_f0_B_ren,
303 303 rdata => sample_f0_B_rdata,
304 304 empty => sample_f0_B_empty,
305 305 full => sample_f0_B_full,
306 306 almost_full => OPEN);
307 307
308 308 lppFIFOxN_f1 : lppFIFOxN
309 309 GENERIC MAP (
310 310 tech => 0,
311 311 Mem_use => Mem_use,
312 312 Data_sz => 16,
313 313 Addr_sz => 8,
314 314 FifoCnt => 5)
315 315 PORT MAP (
316 316 clk => clk,
317 317 rstn => rstn,
318 318
319 319 ReUse => (OTHERS => '0'),
320 320
321 321 wen => sample_f1_wen,
322 322 wdata => sample_f1_wdata,
323 323 ren => sample_f1_ren,
324 324 rdata => sample_f1_rdata,
325 325 empty => sample_f1_empty,
326 326 full => sample_f1_full,
327 327 almost_full => sample_f1_almost_full);
328 328
329 329
330 330 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
331 331
332 332 PROCESS (clk, rstn)
333 333 BEGIN -- PROCESS
334 334 IF rstn = '0' THEN -- asynchronous reset (active low)
335 335 one_sample_f1_full <= '0';
336 336 error_wen_f1 <= '0';
337 337 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
338 338 IF sample_f1_full = "00000" THEN
339 339 one_sample_f1_full <= '0';
340 340 ELSE
341 341 one_sample_f1_full <= '1';
342 342 END IF;
343 343 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
344 344 END IF;
345 345 END PROCESS;
346 346
347 347
348 348 lppFIFOxN_f2 : lppFIFOxN
349 349 GENERIC MAP (
350 350 tech => 0,
351 351 Mem_use => Mem_use,
352 352 Data_sz => 16,
353 353 Addr_sz => 8,
354 354 FifoCnt => 5)
355 355 PORT MAP (
356 356 clk => clk,
357 357 rstn => rstn,
358 358
359 359 ReUse => (OTHERS => '0'),
360 360
361 361 wen => sample_f2_wen,
362 362 wdata => sample_f2_wdata,
363 363 ren => sample_f2_ren,
364 364 rdata => sample_f2_rdata,
365 365 empty => sample_f2_empty,
366 366 full => sample_f2_full,
367 367 almost_full => OPEN);
368 368
369 369
370 370 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
371 371
372 372 PROCESS (clk, rstn)
373 373 BEGIN -- PROCESS
374 374 IF rstn = '0' THEN -- asynchronous reset (active low)
375 375 one_sample_f2_full <= '0';
376 376 error_wen_f2 <= '0';
377 377 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
378 378 IF sample_f2_full = "00000" THEN
379 379 one_sample_f2_full <= '0';
380 380 ELSE
381 381 one_sample_f2_full <= '1';
382 382 END IF;
383 383 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
384 384 END IF;
385 385 END PROCESS;
386 386
387 387 -----------------------------------------------------------------------------
388 388 -- FSM SELECT CHANNEL
389 389 -----------------------------------------------------------------------------
390 390 PROCESS (clk, rstn)
391 391 BEGIN
392 392 IF rstn = '0' THEN
393 393 state_fsm_select_channel <= IDLE;
394 394 ELSIF clk'EVENT AND clk = '1' THEN
395 395 CASE state_fsm_select_channel IS
396 396 WHEN IDLE =>
397 397 IF sample_f1_full = "11111" THEN
398 398 state_fsm_select_channel <= SWITCH_F1;
399 399 ELSIF sample_f1_almost_full = "00000" THEN
400 400 IF sample_f0_A_full = "11111" THEN
401 401 state_fsm_select_channel <= SWITCH_F0_A;
402 402 ELSIF sample_f0_B_full = "11111" THEN
403 403 state_fsm_select_channel <= SWITCH_F0_B;
404 404 ELSIF sample_f2_full = "11111" THEN
405 405 state_fsm_select_channel <= SWITCH_F2;
406 406 END IF;
407 407 END IF;
408 408
409 409 WHEN SWITCH_F0_A =>
410 410 IF sample_f0_A_empty = "11111" THEN
411 411 state_fsm_select_channel <= IDLE;
412 412 END IF;
413 413 WHEN SWITCH_F0_B =>
414 414 IF sample_f0_B_empty = "11111" THEN
415 415 state_fsm_select_channel <= IDLE;
416 416 END IF;
417 417 WHEN SWITCH_F1 =>
418 418 IF sample_f1_empty = "11111" THEN
419 419 state_fsm_select_channel <= IDLE;
420 420 END IF;
421 421 WHEN SWITCH_F2 =>
422 422 IF sample_f2_empty = "11111" THEN
423 423 state_fsm_select_channel <= IDLE;
424 424 END IF;
425 425 WHEN OTHERS => NULL;
426 426 END CASE;
427 427
428 428 END IF;
429 429 END PROCESS;
430 430
431 431 PROCESS (clk, rstn)
432 432 BEGIN
433 433 IF rstn = '0' THEN
434 434 pre_state_fsm_select_channel <= IDLE;
435 435 ELSIF clk'EVENT AND clk = '1' THEN
436 436 pre_state_fsm_select_channel <= state_fsm_select_channel;
437 437 END IF;
438 438 END PROCESS;
439 439
440 440
441 441 -----------------------------------------------------------------------------
442 442 -- SWITCH SELECT CHANNEL
443 443 -----------------------------------------------------------------------------
444 444 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
445 445 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
446 446 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
447 447 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
448 448 (OTHERS => '1');
449 449
450 450 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
451 451 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
452 452 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
453 453 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
454 454 (OTHERS => '0');
455 455
456 456 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
457 457 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
458 458 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
459 459 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
460 460
461 461
462 462 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
463 463 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
464 464 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
465 465 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
466 466
467 467
468 468 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
469 469 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
470 470 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
471 471 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
472 472
473 473 -----------------------------------------------------------------------------
474 474 -- FSM LOAD FFT
475 475 -----------------------------------------------------------------------------
476 476
477 477 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
478 478
479 479 PROCESS (clk, rstn)
480 480 BEGIN
481 481 IF rstn = '0' THEN
482 482 sample_ren_s <= (OTHERS => '1');
483 483 state_fsm_load_FFT <= IDLE;
484 484 status_MS_input <= (OTHERS => '0');
485 485 --next_state_fsm_load_FFT <= IDLE;
486 486 --sample_valid <= '0';
487 487 ELSIF clk'EVENT AND clk = '1' THEN
488 488 CASE state_fsm_load_FFT IS
489 489 WHEN IDLE =>
490 490 --sample_valid <= '0';
491 491 sample_ren_s <= (OTHERS => '1');
492 492 IF sample_full = "11111" AND sample_load = '1' THEN
493 493 state_fsm_load_FFT <= FIFO_1;
494 494 status_MS_input <= status_channel;
495 495 END IF;
496 496
497 497 WHEN FIFO_1 =>
498 498 sample_ren_s <= "1111" & NOT(sample_load);
499 499 IF sample_empty(0) = '1' THEN
500 500 sample_ren_s <= (OTHERS => '1');
501 501 state_fsm_load_FFT <= FIFO_2;
502 502 END IF;
503 503
504 504 WHEN FIFO_2 =>
505 505 sample_ren_s <= "111" & NOT(sample_load) & '1';
506 506 IF sample_empty(1) = '1' THEN
507 507 sample_ren_s <= (OTHERS => '1');
508 508 state_fsm_load_FFT <= FIFO_3;
509 509 END IF;
510 510
511 511 WHEN FIFO_3 =>
512 512 sample_ren_s <= "11" & NOT(sample_load) & "11";
513 513 IF sample_empty(2) = '1' THEN
514 514 sample_ren_s <= (OTHERS => '1');
515 515 state_fsm_load_FFT <= FIFO_4;
516 516 END IF;
517 517
518 518 WHEN FIFO_4 =>
519 519 sample_ren_s <= '1' & NOT(sample_load) & "111";
520 520 IF sample_empty(3) = '1' THEN
521 521 sample_ren_s <= (OTHERS => '1');
522 522 state_fsm_load_FFT <= FIFO_5;
523 523 END IF;
524 524
525 525 WHEN FIFO_5 =>
526 526 sample_ren_s <= NOT(sample_load) & "1111";
527 527 IF sample_empty(4) = '1' THEN
528 528 sample_ren_s <= (OTHERS => '1');
529 529 state_fsm_load_FFT <= IDLE;
530 530 END IF;
531 531 WHEN OTHERS => NULL;
532 532 END CASE;
533 533 END IF;
534 534 END PROCESS;
535 535
536 536 PROCESS (clk, rstn)
537 537 BEGIN
538 538 IF rstn = '0' THEN
539 539 sample_valid_r <= '0';
540 540 next_state_fsm_load_FFT <= IDLE;
541 541 ELSIF clk'EVENT AND clk = '1' THEN
542 542 next_state_fsm_load_FFT <= state_fsm_load_FFT;
543 543 IF sample_ren_s = "11111" THEN
544 544 sample_valid_r <= '0';
545 545 ELSE
546 546 sample_valid_r <= '1';
547 547 END IF;
548 548 END IF;
549 549 END PROCESS;
550 550
551 551 sample_valid <= sample_valid_r AND sample_load;
552 552
553 553 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
554 554 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
555 555 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
556 556 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
557 557 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
558 558
559 559 -----------------------------------------------------------------------------
560 560 -- FFT
561 561 -----------------------------------------------------------------------------
562 562 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
563 563 PORT MAP (
564 564 clk => clk,
565 565 rstn => rstn,
566 566 sample_valid => sample_valid,
567 567 fft_read => fft_read,
568 568 sample_data => sample_data,
569 569 sample_load => sample_load,
570 570 fft_pong => fft_pong,
571 571 fft_data_im => fft_data_im,
572 572 fft_data_re => fft_data_re,
573 573 fft_data_valid => fft_data_valid,
574 574 fft_ready => fft_ready);
575 575
576 576 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
577 577 fft_data_valid & --4
578 578 fft_pong & --3
579 579 sample_load & --2
580 580 fft_read & --1
581 581 sample_valid; --0
582 582
583 583
584 584 -----------------------------------------------------------------------------
585 585 PROCESS (clk, rstn)
586 586 BEGIN
587 587 IF rstn = '0' THEN
588 588 state_fsm_load_MS_memory <= IDLE;
589 589 current_fifo_load <= "00001";
590 590 ELSIF clk'EVENT AND clk = '1' THEN
591 591 CASE state_fsm_load_MS_memory IS
592 592 WHEN IDLE =>
593 593 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
594 594 state_fsm_load_MS_memory <= LOAD_FIFO;
595 595 END IF;
596 596 WHEN LOAD_FIFO =>
597 597 IF current_fifo_full = '1' THEN
598 598 state_fsm_load_MS_memory <= TRASH_FFT;
599 599 END IF;
600 600 WHEN TRASH_FFT =>
601 601 IF fft_ready = '0' THEN
602 602 state_fsm_load_MS_memory <= IDLE;
603 603 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
604 604 END IF;
605 605 WHEN OTHERS => NULL;
606 606 END CASE;
607 607
608 608 END IF;
609 609 END PROCESS;
610 610
611 611 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
612 612 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
613 613 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
614 614 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
615 615 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
616 616
617 617 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
618 618 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
619 619 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
620 620 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
621 621 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
622 622
623 623 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
624 624 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
625 625 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
626 626 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
627 627 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
628 628
629 629 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
630 630
631 631 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
632 632 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
633 633 AND state_fsm_load_MS_memory = LOAD_FIFO
634 634 AND current_fifo_load(I) = '1'
635 635 ELSE '1';
636 636 END GENERATE all_fifo;
637 637
638 638 PROCESS (clk, rstn)
639 639 BEGIN
640 640 IF rstn = '0' THEN
641 641 MEM_IN_SM_wen <= (OTHERS => '1');
642 642 ELSIF clk'EVENT AND clk = '1' THEN
643 643 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
644 644 END IF;
645 645 END PROCESS;
646 646
647 647 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
648 648 (fft_data_im & fft_data_re) &
649 649 (fft_data_im & fft_data_re) &
650 650 (fft_data_im & fft_data_re) &
651 651 (fft_data_im & fft_data_re);
652 652 -----------------------------------------------------------------------------
653 653
654 654
655 655 -----------------------------------------------------------------------------
656 656 Mem_In_SpectralMatrix : lppFIFOxN
657 657 GENERIC MAP (
658 658 tech => 0,
659 659 Mem_use => Mem_use,
660 660 Data_sz => 32, --16,
661 661 Addr_sz => 7, --8
662 662 FifoCnt => 5)
663 663 PORT MAP (
664 664 clk => clk,
665 665 rstn => rstn,
666 666
667 667 ReUse => MEM_IN_SM_ReUse,
668 668
669 669 wen => MEM_IN_SM_wen,
670 670 wdata => MEM_IN_SM_wData,
671 671
672 672 ren => MEM_IN_SM_ren,
673 673 rdata => MEM_IN_SM_rData,
674 674 full => MEM_IN_SM_Full,
675 675 empty => MEM_IN_SM_Empty,
676 676 almost_full => OPEN);
677 677
678 678 -----------------------------------------------------------------------------
679
680 observation_vector_1(11 DOWNTO 0) <= "0000" &
681 SM_correlation_start & --7
682 status_MS_input(1 DOWNTO 0)& --6..5
683 MEM_IN_SM_locked(4 DOWNTO 0); --4..0
684
685 observation_vector_0(11 DOWNTO 6) <= MEM_IN_SM_locked(0) &
686 SM_correlation_done & --4
687 SM_correlation_auto & --3
688 SM_correlation_start & --2
689 status_component(5 DOWNTO 4); --1..0
690 -----------------------------------------------------------------------------
679 691 MS_control_1 : MS_control
680 692 PORT MAP (
681 693 clk => clk,
682 694 rstn => rstn,
683 695
684 696 current_status_ms => status_MS_input,
685 697
686 698 fifo_in_lock => MEM_IN_SM_locked,
687 699 fifo_in_data => MEM_IN_SM_rdata,
688 700 fifo_in_full => MEM_IN_SM_Full,
689 701 fifo_in_empty => MEM_IN_SM_Empty,
690 702 fifo_in_ren => MEM_IN_SM_ren,
691 703 fifo_in_reuse => MEM_IN_SM_ReUse,
692 704
693 705 fifo_out_data => SM_in_data,
694 706 fifo_out_ren => SM_in_ren,
695 707 fifo_out_empty => SM_in_empty,
696 708
697 709 current_status_component => status_component,
698 710
699 711 correlation_start => SM_correlation_start,
700 712 correlation_auto => SM_correlation_auto,
701 713 correlation_done => SM_correlation_done);
702 714
703 715
704 716 MS_calculation_1 : MS_calculation
705 717 PORT MAP (
706 718 clk => clk,
707 719 rstn => rstn,
708 720
709 721 fifo_in_data => SM_in_data,
710 722 fifo_in_ren => SM_in_ren,
711 723 fifo_in_empty => SM_in_empty,
712 724
713 725 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
714 726 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
715 727 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
716 728
717 729 correlation_start => SM_correlation_start,
718 730 correlation_auto => SM_correlation_auto,
719 731 correlation_begin => SM_correlation_begin,
720 732 correlation_done => SM_correlation_done);
721 733
722 734 -----------------------------------------------------------------------------
723 735 PROCESS (clk, rstn)
724 736 BEGIN -- PROCESS
725 737 IF rstn = '0' THEN -- asynchronous reset (active low)
726 738 current_matrix_write <= '0';
727 739 current_matrix_wait_empty <= '1';
728 740 status_component_fifo_0 <= (OTHERS => '0');
729 741 status_component_fifo_1 <= (OTHERS => '0');
730 742 status_component_fifo_0_end <= '0';
731 743 status_component_fifo_1_end <= '0';
732 744 SM_correlation_done_reg1 <= '0';
733 745 SM_correlation_done_reg2 <= '0';
734 746 SM_correlation_done_reg3 <= '0';
735 747
736 748 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
737 749 SM_correlation_done_reg1 <= SM_correlation_done;
738 750 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
739 751 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
740 752 status_component_fifo_0_end <= '0';
741 753 status_component_fifo_1_end <= '0';
742 754 IF SM_correlation_begin = '1' THEN
743 755 IF current_matrix_write = '0' THEN
744 756 status_component_fifo_0 <= status_component;
745 757 ELSE
746 758 status_component_fifo_1 <= status_component;
747 759 END IF;
748 760 END IF;
749 761
750 762 IF SM_correlation_done_reg3 = '1' THEN
751 763 IF current_matrix_write = '0' THEN
752 764 status_component_fifo_0_end <= '1';
753 765 ELSE
754 766 status_component_fifo_1_end <= '1';
755 767 END IF;
756 768 current_matrix_wait_empty <= '1';
757 769 current_matrix_write <= NOT current_matrix_write;
758 770 END IF;
759 771
760 772 IF current_matrix_wait_empty <= '1' THEN
761 773 IF current_matrix_write = '0' THEN
762 774 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
763 775 ELSE
764 776 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
765 777 END IF;
766 778 END IF;
767 779
768 780 END IF;
769 781 END PROCESS;
770 782
771 783 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
772 784 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
773 785 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
774 786 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
775 787 '1' WHEN current_matrix_wait_empty = '1' ELSE
776 788 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
777 789 MEM_OUT_SM_Full(1);
778 790
779 791 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
780 792 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
781 793
782 794 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
783 795 -----------------------------------------------------------------------------
784 796
785 797 Mem_Out_SpectralMatrix : lppFIFOxN
786 798 GENERIC MAP (
787 799 tech => 0,
788 800 Mem_use => Mem_use,
789 801 Data_sz => 32,
790 802 Addr_sz => 8,
791 803 FifoCnt => 2)
792 804 PORT MAP (
793 805 clk => clk,
794 806 rstn => rstn,
795 807
796 808 ReUse => (OTHERS => '0'),
797 809
798 810 wen => MEM_OUT_SM_Write,
799 811 wdata => MEM_OUT_SM_Data_in,
800 812
801 813 ren => MEM_OUT_SM_Read,
802 814 rdata => MEM_OUT_SM_Data_out,
803 815
804 816 full => MEM_OUT_SM_Full,
805 817 empty => MEM_OUT_SM_Empty,
806 818 almost_full => OPEN);
807 819
808 820 -----------------------------------------------------------------------------
809 821 -- MEM_OUT_SM_Read <= "00";
810 822 PROCESS (clk, rstn)
811 823 BEGIN
812 824 IF rstn = '0' THEN
813 825 fifo_0_ready <= '0';
814 826 fifo_1_ready <= '0';
815 827 fifo_ongoing <= '0';
816 828 ELSIF clk'EVENT AND clk = '1' THEN
817 829 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
818 830 fifo_ongoing <= '1';
819 831 fifo_0_ready <= '0';
820 832 ELSIF status_component_fifo_0_end = '1' THEN
821 833 fifo_0_ready <= '1';
822 834 END IF;
823 835
824 836 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
825 837 fifo_ongoing <= '0';
826 838 fifo_1_ready <= '0';
827 839 ELSIF status_component_fifo_1_end = '1' THEN
828 840 fifo_1_ready <= '1';
829 841 END IF;
830 842
831 843 END IF;
832 844 END PROCESS;
833 845
834 846 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
835 847 '1' WHEN fifo_0_ready = '0' ELSE
836 848 FSM_DMA_fifo_ren;
837 849
838 850 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
839 851 '1' WHEN fifo_1_ready = '0' ELSE
840 852 FSM_DMA_fifo_ren;
841 853
842 854 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
843 855 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
844 856 '1';
845 857
846 858 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
847 859 status_component_fifo_1;
848 860
849 861 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
850 862 MEM_OUT_SM_Data_out(63 DOWNTO 32);
851 863
852 864 -----------------------------------------------------------------------------
853 865 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
854 866 PORT MAP (
855 867 HCLK => clk,
856 868 HRESETn => rstn,
857 869
858 870 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
859 871 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
860 872 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
861 873 fifo_data => FSM_DMA_fifo_data,
862 874 fifo_empty => FSM_DMA_fifo_empty,
863 875 fifo_ren => FSM_DMA_fifo_ren,
864 876
865 877 dma_addr => dma_addr,
866 878 dma_data => dma_data,
867 879 dma_valid => dma_valid,
868 880 dma_valid_burst => dma_valid_burst,
869 881 dma_ren => dma_ren,
870 882 dma_done => dma_done,
871 883
872 884 ready_matrix_f0 => ready_matrix_f0,
873 885 ready_matrix_f1 => ready_matrix_f1,
874 886 ready_matrix_f2 => ready_matrix_f2,
875 887
876 888 error_bad_component_error => error_bad_component_error,
877 889 error_buffer_full => error_buffer_full,
878 890
879 891 debug_reg => debug_reg,
880 892 status_ready_matrix_f0 => status_ready_matrix_f0,
881 893 status_ready_matrix_f1 => status_ready_matrix_f1,
882 894 status_ready_matrix_f2 => status_ready_matrix_f2,
883 895
884 896 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
885 897 config_active_interruption_onError => config_active_interruption_onError,
886 898
887 899 addr_matrix_f0 => addr_matrix_f0,
888 900 addr_matrix_f1 => addr_matrix_f1,
889 901 addr_matrix_f2 => addr_matrix_f2,
890 902
891 903 matrix_time_f0 => matrix_time_f0,
892 904 matrix_time_f1 => matrix_time_f1,
893 905 matrix_time_f2 => matrix_time_f2
894 906 );
895 907 -----------------------------------------------------------------------------
896 908
897 909
898 910
899 911
900 912
901 913 -----------------------------------------------------------------------------
902 914 -- TIME MANAGMENT
903 915 -----------------------------------------------------------------------------
904 916 all_time <= coarse_time & fine_time;
905 917 --
906 918 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
907 919 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
908 920 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
909 921 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
910 922
911 923 all_time_reg: FOR I IN 0 TO 3 GENERATE
912 924
913 925 PROCESS (clk, rstn)
914 926 BEGIN
915 927 IF rstn = '0' THEN
916 928 f_empty_reg(I) <= '1';
917 929 ELSIF clk'event AND clk = '1' THEN
918 930 f_empty_reg(I) <= f_empty(I);
919 931 END IF;
920 932 END PROCESS;
921 933
922 934 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
923 935
924 936 s_m_t_m_f0_A : spectral_matrix_time_managment
925 937 PORT MAP (
926 938 clk => clk,
927 939 rstn => rstn,
928 940 time_in => all_time,
929 941 update_1 => time_update_f(I),
930 942 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
931 943 );
932 944
933 945 END GENERATE all_time_reg;
934 946
935 947 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
936 948 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
937 949 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
938 950 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
939 951
940 952 -----------------------------------------------------------------------------
941 953
942 954 END Behavioral;
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