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EM version (to test)...
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r194:541358270fe7 JC
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1 1 leon3mp_em_JCPE_02-07-2013.pdb
2 2 + UART ok
3 3 + SPW ok
4 4 + Leon3 ok
5 5
6 6 leon3mp_em_JCPE_05-07-2013.pdb
7 7 + UART ok
8 8 + SPW ok
9 9 + Leon3 ok
10 10 + Waveform ok
11 11 -> No filter
12 12 -> Inverted ADC Input Channel
13 13
14 14 leon3mp_em_JCPE_08-07-2013.pdb
15 15 + UART ??
16 16 + SPW ??
17 17 + Leon3 ??
18 18 + Waveform ??
19 19 -> No filter
20 20
21 leon3mp_em_JCPE_09-07-2013.pdb
22 + UART ??
23 + SPW ??
24 + Leon3 ??
25 + Waveform ??
26 + Filter
21 27
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@@ -1,516 +1,516
1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 USE work.config.ALL;
37 37 LIBRARY lpp;
38 38 --use lpp.lpp_amba.all;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_top_lfr_pkg.ALL;
42 42 --use lpp.lpp_uart.all;
43 43 --use lpp.lpp_matrix.all;
44 44 --use lpp.lpp_delay.all;
45 45 --use lpp.lpp_fft.all;
46 46 --use lpp.fft_components.all;
47 47 use lpp.iir_filter.all;
48 48 USE lpp.general_purpose.ALL;
49 49 --use lpp.Filtercfg.all;
50 50 USE lpp.lpp_lfr_time_management.ALL; -- PLE
51 51 --use lpp.lpp_lfr_spectral_matrices_DMA.all; -- PLE
52 52
53 53 ENTITY leon3mp IS
54 54 GENERIC (
55 55 fabtech : INTEGER := CFG_FABTECH;
56 56 memtech : INTEGER := CFG_MEMTECH;
57 57 padtech : INTEGER := CFG_PADTECH;
58 58 clktech : INTEGER := CFG_CLKTECH;
59 59 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
60 60 dbguart : INTEGER := CFG_DUART; -- Print UART on console
61 61 pclow : INTEGER := CFG_PCLOW
62 62 );
63 63 PORT (
64 64 clk50MHz : IN STD_ULOGIC;
65 65 clk49_152MHz : IN STD_ULOGIC;
66 66 reset : IN STD_ULOGIC;
67 67
68 68 errorn : OUT STD_ULOGIC;
69 69
70 70 -- UART AHB ---------------------------------------------------------------
71 71 ahbrxd : IN STD_ULOGIC; -- DSU rx data
72 72 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
73 73
74 74 -- UART APB ---------------------------------------------------------------
75 75 urxd1 : IN STD_ULOGIC; -- UART1 rx data
76 76 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
77 77
78 78 -- RAM --------------------------------------------------------------------
79 79 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
80 80 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 81 nSRAM_BE0 : OUT STD_LOGIC;
82 82 nSRAM_BE1 : OUT STD_LOGIC;
83 83 nSRAM_BE2 : OUT STD_LOGIC;
84 84 nSRAM_BE3 : OUT STD_LOGIC;
85 85 nSRAM_WE : OUT STD_LOGIC;
86 86 nSRAM_CE : OUT STD_LOGIC;
87 87 nSRAM_OE : OUT STD_LOGIC;
88 88
89 89 -- SPW --------------------------------------------------------------------
90 90 spw1_din : IN STD_LOGIC; -- PLE
91 91 spw1_sin : IN STD_LOGIC; -- PLE
92 92 spw1_dout : OUT STD_LOGIC; -- PLE
93 93 spw1_sout : OUT STD_LOGIC; -- PLE
94 94
95 95 -- ADC --------------------------------------------------------------------
96 96 bias_fail_sw : OUT STD_LOGIC;
97 97 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
98 98 ADC_smpclk : OUT STD_LOGIC;
99 99 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
100 100
101 101 ---------------------------------------------------------------------------
102 102 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
103 103 );
104 104 END;
105 105
106 106 ARCHITECTURE Behavioral OF leon3mp IS
107 107
108 108 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
109 109 -- CFG_GRETH+CFG_AHB_JTAG;
110 110 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
111 111 CFG_AHB_UART+
112 112 CFG_GRETH+
113 113 CFG_AHB_JTAG
114 114 +2; -- 1 is for the SpaceWire module grspw2, which is a master
115 115 CONSTANT maxahbm : INTEGER := maxahbmsp;
116 116
117 117 --Clk & Rst g�n�
118 118 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 119 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 120 SIGNAL resetnl : STD_ULOGIC;
121 121 SIGNAL clk2x : STD_ULOGIC;
122 122 SIGNAL lclk2x : STD_ULOGIC;
123 123 SIGNAL lclk25MHz : STD_ULOGIC;
124 124 SIGNAL lclk50MHz : STD_ULOGIC;
125 125 SIGNAL lclk100MHz : STD_ULOGIC;
126 126 SIGNAL clkm : STD_ULOGIC;
127 127 SIGNAL rstn : STD_ULOGIC;
128 128 SIGNAL rstraw : STD_ULOGIC;
129 129 SIGNAL pciclk : STD_ULOGIC;
130 130 SIGNAL sdclkl : STD_ULOGIC;
131 131 SIGNAL cgi : clkgen_in_type;
132 132 SIGNAL cgo : clkgen_out_type;
133 133 --- AHB / APB
134 134 SIGNAL apbi : apb_slv_in_type;
135 135 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
136 136 SIGNAL ahbsi : ahb_slv_in_type;
137 137 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
138 138 SIGNAL ahbmi : ahb_mst_in_type;
139 139 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
140 140 --UART
141 141 SIGNAL ahbuarti : uart_in_type;
142 142 SIGNAL ahbuarto : uart_out_type;
143 143 SIGNAL apbuarti : uart_in_type;
144 144 SIGNAL apbuarto : uart_out_type;
145 145 --MEM CTRLR
146 146 SIGNAL memi : memory_in_type;
147 147 SIGNAL memo : memory_out_type;
148 148 SIGNAL wpo : wprot_out_type;
149 149 SIGNAL sdo : sdram_out_type;
150 150 SIGNAL ramcs : STD_ULOGIC;
151 151 --IRQ
152 152 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
153 153 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
154 154 --Timer
155 155 SIGNAL gpti : gptimer_in_type;
156 156 SIGNAL gpto : gptimer_out_type;
157 157 --GPIO
158 158 SIGNAL gpioi : gpio_in_type;
159 159 SIGNAL gpioo : gpio_out_type;
160 160 --DSU
161 161 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
162 162 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
163 163 SIGNAL dsui : dsu_in_type;
164 164 SIGNAL dsuo : dsu_out_type;
165 165
166 166 ---------------------------------------------------------------------
167 167 --- AJOUT TEST ------------------------Signaux----------------------
168 168 ---------------------------------------------------------------------
169 169
170 170 ---------------------------------------------------------------------
171 171 CONSTANT IOAEN : INTEGER := CFG_CAN;
172 172 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
173 173
174 174 -- time management signal
175 175 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 176 SIGNAL fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 177
178 178 -- Spacewire signals
179 179 SIGNAL dtmp : STD_ULOGIC; -- PLE
180 180 SIGNAL stmp : STD_ULOGIC; -- PLE
181 181 SIGNAL rxclko : STD_ULOGIC; -- PLE
182 182 SIGNAL swni : grspw_in_type; -- PLE
183 183 SIGNAL swno : grspw_out_type; -- PLE
184 184 SIGNAL clkmn : STD_ULOGIC; -- PLE
185 185 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
186 186
187 187 -- AD Converter RHF1401
188 188 SIGNAL sample : Samples14v(7 DOWNTO 0);
189 189 SIGNAL sample_val : STD_LOGIC;
190 190 -----------------------------------------------------------------------------
191 191 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
192 192
193 193 BEGIN
194 194
195 195
196 196 ----------------------------------------------------------------------
197 197 --- Reset and Clock generation -------------------------------------
198 198 ----------------------------------------------------------------------
199 199
200 200 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
201 201 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
202 202
203 203 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
204 204
205 205
206 206 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk50MHz, lclk100MHz);
207 207
208 208 clkgen0 : clkgen -- clock generator
209 209 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
210 210 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
211 211 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
212 212
213 213 PROCESS(lclk100MHz)
214 214 BEGIN
215 215 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
216 216 lclk50MHz <= NOT lclk50MHz;
217 217 END IF;
218 218 END PROCESS;
219 219
220 220 PROCESS(lclk50MHz)
221 221 BEGIN
222 222 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
223 223 lclk25MHz <= NOT lclk25MHz;
224 224 END IF;
225 225 END PROCESS;
226 226
227 227 lclk2x <= lclk50MHz;
228 228
229 229 ----------------------------------------------------------------------
230 230 --- LEON3 processor / DSU / IRQ ------------------------------------
231 231 ----------------------------------------------------------------------
232 232
233 233 l3 : IF CFG_LEON3 = 1 GENERATE
234 234 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
235 235 u0 : leon3s -- LEON3 processor
236 236 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
237 237 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
238 238 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
239 239 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
240 240 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
241 241 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
242 242 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
243 243 irqi(i), irqo(i), dbgi(i), dbgo(i));
244 244 END GENERATE;
245 245 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
246 246
247 247 dsugen : IF CFG_DSU = 1 GENERATE
248 248 dsu0 : dsu3 -- LEON3 Debug Support Unit
249 249 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
250 250 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
251 251 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
252 252 dsui.enable <= '1';
253 253 dsui.break <= '0';
254 254 led(2) <= dsuo.active;
255 255 END GENERATE;
256 256 END GENERATE;
257 257
258 258 nodsu : IF CFG_DSU = 0 GENERATE
259 259 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
260 260 END GENERATE;
261 261
262 262 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
263 263 irqctrl0 : irqmp -- interrupt controller
264 264 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
265 265 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
266 266 END GENERATE;
267 267 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
268 268 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
269 269 irqi(i).irl <= "0000";
270 270 END GENERATE;
271 271 apbo(2) <= apb_none;
272 272 END GENERATE;
273 273
274 274 ----------------------------------------------------------------------
275 275 --- Memory controllers ---------------------------------------------
276 276 ----------------------------------------------------------------------
277 277 memctrlr : mctrl GENERIC MAP (
278 278 hindex => 0,
279 279 pindex => 0,
280 280 paddr => 0,
281 281 srbanks => 1
282 282 )
283 283 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
284 284
285 285 memi.brdyn <= '1';
286 286 memi.bexcn <= '1';
287 287 memi.writen <= '1';
288 288 memi.wrn <= "1111";
289 289 memi.bwidth <= "10";
290 290
291 291 bdr : FOR i IN 0 TO 3 GENERATE
292 292 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
293 293 PORT MAP (
294 294 data(31-i*8 DOWNTO 24-i*8),
295 295 memo.data(31-i*8 DOWNTO 24-i*8),
296 296 memo.bdrive(i),
297 297 memi.data(31-i*8 DOWNTO 24-i*8));
298 298 END GENERATE;
299 299
300 300 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
301 301 PORT MAP (address, memo.address(21 DOWNTO 2));
302 302
303 303 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
304 304 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
305 305 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
306 306 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
307 307 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
308 308 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
309 309 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
310 310
311 311 ----------------------------------------------------------------------
312 312 --- AHB CONTROLLER -------------------------------------------------
313 313 ----------------------------------------------------------------------
314 314 ahb0 : ahbctrl -- AHB arbiter/multiplexer
315 315 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
316 316 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
317 317 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
318 318 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
319 319
320 320 ----------------------------------------------------------------------
321 321 --- AHB UART -------------------------------------------------------
322 322 ----------------------------------------------------------------------
323 323 dcomgen : IF CFG_AHB_UART = 1 GENERATE
324 324 dcom0 : ahbuart
325 325 GENERIC MAP ( hindex => 3, pindex => 4, paddr => 4)
326 326 PORT MAP ( rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
327 327 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
328 328 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
329 329 led(0) <= NOT ahbuarti.rxd;
330 330 led(1) <= NOT ahbuarto.txd;
331 331 END GENERATE;
332 332 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
333 333
334 334 ----------------------------------------------------------------------
335 335 --- APB Bridge -----------------------------------------------------
336 336 ----------------------------------------------------------------------
337 337 apb0 : apbctrl -- AHB/APB bridge
338 338 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
339 339 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
340 340
341 341 ----------------------------------------------------------------------
342 342 --- GPT Timer ------------------------------------------------------
343 343 ----------------------------------------------------------------------
344 344 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
345 345 timer0 : gptimer -- timer unit
346 346 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
347 347 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
348 348 nbits => CFG_GPT_TW)
349 349 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
350 350 gpti.dhalt <= dsuo.tstop;
351 351 gpti.extclk <= '0';
352 352 END GENERATE;
353 353 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
354 354
355 355
356 356 ----------------------------------------------------------------------
357 357 --- APB UART -------------------------------------------------------
358 358 ----------------------------------------------------------------------
359 359 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
360 360 uart1 : apbuart -- UART 1
361 361 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
362 362 fifosize => CFG_UART1_FIFO)
363 363 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
364 364 apbuarti.rxd <= urxd1;
365 365 apbuarti.extclk <= '0';
366 366 utxd1 <= apbuarto.txd;
367 367 apbuarti.ctsn <= '0';
368 368 END GENERATE;
369 369 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
370 370
371 371 -------------------------------------------------------------------------------
372 372 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
373 373 -------------------------------------------------------------------------------
374 374 lfrtimemanagement0 : apb_lfr_time_management
375 375 GENERIC MAP(pindex => 6, paddr => 6, pmask => 16#fff#,
376 376 masterclk => 25000000, timeclk => 49152000, finetimeclk => 65536,
377 377 pirq => 12)
378 378 PORT MAP(clkm, clk49_152MHz, rstn, swno.tickout, apbi, apbo(6),
379 379 coarse_time, fine_time);
380 380
381 381 -----------------------------------------------------------------------
382 382 --- SpaceWire --------------------------------------------------------
383 383 -----------------------------------------------------------------------
384 384 spw_phy0 : grspw2_phy
385 385 GENERIC MAP(
386 386 scantest => 0,
387 387 tech => memtech,
388 388 input_type => 0) -- self_clocking mode
389 389 PORT MAP(
390 390 rstn => rstn,
391 391 rxclki => clkm,
392 392 rxclkin => clkmn,
393 393 nrxclki => clkm, -- not used in self-clocking
394 394 di => dtmp,
395 395 si => stmp,
396 396 do => swni.d(1 DOWNTO 0),
397 397 dov => swni.dv(1 DOWNTO 0),
398 398 dconnect => swni.dconnect(1 DOWNTO 0),
399 399 rxclko => rxclko);
400 400
401 401 sw0 : grspwm
402 402 GENERIC MAP(
403 403 tech => apa3e,
404 404 hindex => 1,
405 405 pindex => 5,
406 406 paddr => 5,
407 407 pirq => 11,
408 408 sysfreq => 25000,
409 409 usegen => 1, -- sysfreq not used by the core version 2? usegen?
410 410 nsync => 1, -- nsync not used by the core version 2?
411 411 rmap => 1,
412 412 rmapcrc => 1,
413 413 fifosize1 => 16,
414 414 fifosize2 => 16,
415 415 rxclkbuftype => 2,
416 416 rxunaligned => 0,
417 417 spwcore => 2,
418 418 memtech => apa3e,
419 419 nodeaddr => 254,
420 420 destkey => 2, -- added nodeaddr and destkey parameters
421 421 rmapbufs => 4,
422 422 netlist => 0,
423 423 ft => 0,
424 424 ports => 2)
425 425 PORT MAP(
426 426 rstn, clkm,
427 427 rxclko, rxclko,
428 428 txclk, txclk,
429 429 ahbmi, ahbmo(1),
430 430 apbi, apbo(5),
431 431 swni, swno);
432 432
433 433 swni.tickin <= '0';
434 434 swni.rmapen <= '1';
435 435 swni.clkdiv10 <= "00001001";
436 436
437 437 spw1_dout <= swno.d(0);
438 438 spw1_sout <= swno.s(0);
439 439 dtmp <= spw1_din;
440 440 stmp <= spw1_sin;
441 441
442 442 txclk <= lclk100MHz;
443 443
444 444
445 445 -------------------------------------------------------------------------------
446 446 -- WAVEFORM PICKER
447 447 -------------------------------------------------------------------------------
448 448 -- sdo_adc(4 DOWNTO 0) <= bias_adc(4 DOWNTO 0);
449 449 -- sdo_adc(7 DOWNTO 5) <= scm_adc(2 DOWNTO 0);
450 450
451 451 waveform_picker0 : top_wf_picker
452 452 GENERIC MAP(
453 453 hindex => 2,
454 454 pindex => 15,
455 455 paddr => 15,
456 456 pmask => 16#fff#,
457 457 pirq => 14,
458 458 tech => CFG_FABTECH,
459 459 nb_burst_available_size => 12, -- size of the register holding the nb of burst
460 460 nb_snapshot_param_size => 12, -- size of the register holding the snapshots size
461 461 delta_snapshot_size => 16, -- snapshots period
462 462 delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts
463 463 delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot
464 ENABLE_FILTER => '0'
464 ENABLE_FILTER => '1'
465 465 )
466 466 PORT MAP(
467 467 sample => sample,
468 468 sample_val => sample_val,
469 469 --
470 470 cnv_clk => clk49_152MHz,
471 471 cnv_rstn => rstn,
472 472 -- AMBA AHB system signals
473 473 HCLK => clkm,
474 474 HRESETn => rstn,
475 475 -- AMBA APB Slave Interface
476 476 apbi => apbi,
477 477 apbo => apbo(15),
478 478 -- AMBA AHB Master Interface
479 479 AHB_Master_In => ahbmi,
480 480 AHB_Master_Out => ahbmo(2),
481 481 --
482 482 coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time
483 483 --
484 484 data_shaping_BW => bias_fail_sw
485 485 );
486 486
487 487 top_ad_conv_RHF1401_1: top_ad_conv_RHF1401
488 488 GENERIC MAP (
489 489 ChanelCount => 8,
490 490 ncycle_cnv_high => 79,
491 491 ncycle_cnv => 500)
492 492 PORT MAP (
493 493 cnv_clk => clk49_152MHz,
494 494 cnv_rstn => rstn,
495 495
496 496 cnv => ADC_smpclk,
497 497
498 498 clk => clkm,
499 499 rstn => rstn,
500 500 ADC_data => ADC_data,
501 501 --ADC_smpclk => ,
502 502 ADC_nOE => ADC_OEB_bar_CH_s,
503 503 sample => sample,
504 504 sample_val => sample_val);
505 505
506 506 ADC_OEB_bar_CH(0) <= ADC_OEB_bar_CH_s(5); -- B1
507 507 ADC_OEB_bar_CH(1) <= ADC_OEB_bar_CH_s(6); -- B2
508 508 ADC_OEB_bar_CH(2) <= ADC_OEB_bar_CH_s(7); -- B3
509 509
510 510 ADC_OEB_bar_CH(3) <= ADC_OEB_bar_CH_s(0); -- V1
511 511 ADC_OEB_bar_CH(4) <= ADC_OEB_bar_CH_s(1); -- V2
512 512 ADC_OEB_bar_CH(5) <= ADC_OEB_bar_CH_s(2); -- V3
513 513 ADC_OEB_bar_CH(6) <= ADC_OEB_bar_CH_s(3); -- V4
514 514 ADC_OEB_bar_CH(7) <= ADC_OEB_bar_CH_s(4); -- V5
515 515
516 END Behavioral; No newline at end of file
516 END Behavioral;
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@@ -1,343 +1,343
1 1 LIBRARY ieee;
2 2 USE ieee.std_logic_1164.ALL;
3 3 USE ieee.numeric_std.ALL;
4 4
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.iir_filter.ALL;
8 8 USE lpp.FILTERcfg.ALL;
9 9 USE lpp.lpp_memory.ALL;
10 10 USE lpp.lpp_waveform_pkg.ALL;
11 11 USE lpp.lpp_top_lfr_pkg.ALL;
12 12
13 13 LIBRARY techmap;
14 14 USE techmap.gencomp.ALL;
15 15
16 16 LIBRARY grlib;
17 17 USE grlib.amba.ALL;
18 18 USE grlib.stdlib.ALL;
19 19 USE grlib.devices.ALL;
20 20 USE GRLIB.DMA2AHB_Package.ALL;
21 21
22 22 ENTITY top_wf_picker IS
23 23 GENERIC (
24 24 hindex : INTEGER := 2;
25 25 pindex : INTEGER := 15;
26 26 paddr : INTEGER := 15;
27 27 pmask : INTEGER := 16#fff#;
28 28 pirq : INTEGER := 15;
29 29 tech : INTEGER := 0;
30 30 nb_burst_available_size : INTEGER := 11;
31 31 nb_snapshot_param_size : INTEGER := 11;
32 32 delta_snapshot_size : INTEGER := 16;
33 33 delta_f2_f0_size : INTEGER := 10;
34 34 delta_f2_f1_size : INTEGER := 10;
35 35 ENABLE_FILTER : STD_LOGIC := '1'
36 36 );
37 37 PORT (
38 38 cnv_clk : IN STD_LOGIC;
39 39 cnv_rstn : IN STD_LOGIC;
40 40 --
41 41 sample : IN Samples14v(7 DOWNTO 0);
42 42 sample_val : IN STD_LOGIC;
43 43
44 44 -- AMBA AHB system signals
45 45 HCLK : IN STD_ULOGIC;
46 46 HRESETn : IN STD_ULOGIC;
47 47
48 48 -- AMBA APB Slave Interface
49 49 apbi : IN apb_slv_in_type;
50 50 apbo : OUT apb_slv_out_type;
51 51
52 52 -- AMBA AHB Master Interface
53 53 AHB_Master_In : IN AHB_Mst_In_Type;
54 54 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 55
56 56 --
57 57 coarse_time_0 : IN STD_LOGIC;
58 58
59 59 --
60 60 data_shaping_BW : OUT STD_LOGIC
61 61 );
62 62 END top_wf_picker;
63 63
64 64 ARCHITECTURE tb OF top_wf_picker IS
65 65
66 66 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
67 67 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
68 68 SIGNAL ready_matrix_f1 : STD_LOGIC;
69 69 SIGNAL ready_matrix_f2 : STD_LOGIC;
70 70 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
71 71 SIGNAL error_bad_component_error : STD_LOGIC;
72 72 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 73 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
74 74 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
75 75 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
76 76 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
77 77 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
78 78 SIGNAL status_error_bad_component_error : STD_LOGIC;
79 79 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
80 80 SIGNAL config_active_interruption_onError : STD_LOGIC;
81 81 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
82 82 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 84 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 85
86 86 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 87 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 88 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 89 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 90 SIGNAL data_shaping_SP0 : STD_LOGIC;
91 91 SIGNAL data_shaping_SP1 : STD_LOGIC;
92 92 SIGNAL data_shaping_R0 : STD_LOGIC;
93 93 SIGNAL data_shaping_R1 : STD_LOGIC;
94 94 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
95 95 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
96 96 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
97 97 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
98 98 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
99 99 SIGNAL enable_f0 : STD_LOGIC;
100 100 SIGNAL enable_f1 : STD_LOGIC;
101 101 SIGNAL enable_f2 : STD_LOGIC;
102 102 SIGNAL enable_f3 : STD_LOGIC;
103 103 SIGNAL burst_f0 : STD_LOGIC;
104 104 SIGNAL burst_f1 : STD_LOGIC;
105 105 SIGNAL burst_f2 : STD_LOGIC;
106 106 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 107 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 108 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 109 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 110
111 111 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
112 112 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
113 113 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 114 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 115 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 116 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 118 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 119
120 120 CONSTANT ChanelCount : INTEGER := 8;
121 121 CONSTANT ncycle_cnv_high : INTEGER := 40;
122 122 CONSTANT ncycle_cnv : INTEGER := 250;
123 123
124 124 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
125 125
126 126 BEGIN
127 127
128 128 ready_matrix_f0_0 <= '0';
129 129 ready_matrix_f0_1 <= '0';
130 130 ready_matrix_f1 <= '0';
131 131 ready_matrix_f2 <= '0';
132 132 error_anticipating_empty_fifo <= '0';
133 133 error_bad_component_error <= '0';
134 134 debug_reg <= (OTHERS => '0');
135 135
136 136 lpp_top_apbreg_1 : lpp_top_apbreg
137 137 GENERIC MAP (
138 138 nb_burst_available_size => nb_burst_available_size,
139 139 nb_snapshot_param_size => nb_snapshot_param_size,
140 140 delta_snapshot_size => delta_snapshot_size,
141 141 delta_f2_f0_size => delta_f2_f0_size,
142 142 delta_f2_f1_size => delta_f2_f1_size,
143 143 pindex => pindex,
144 144 paddr => paddr,
145 145 pmask => pmask,
146 146 pirq => pirq)
147 147 PORT MAP (
148 148 HCLK => HCLK,
149 149 HRESETn => HRESETn,
150 150 apbi => apbi,
151 151 apbo => apbo,
152 152
153 153 ready_matrix_f0_0 => ready_matrix_f0_0,
154 154 ready_matrix_f0_1 => ready_matrix_f0_1,
155 155 ready_matrix_f1 => ready_matrix_f1,
156 156 ready_matrix_f2 => ready_matrix_f2,
157 157 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
158 158 error_bad_component_error => error_bad_component_error,
159 159 debug_reg => debug_reg,
160 160 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
161 161 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
162 162 status_ready_matrix_f1 => status_ready_matrix_f1,
163 163 status_ready_matrix_f2 => status_ready_matrix_f2,
164 164 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
165 165 status_error_bad_component_error => status_error_bad_component_error,
166 166 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
167 167 config_active_interruption_onError => config_active_interruption_onError,
168 168 addr_matrix_f0_0 => addr_matrix_f0_0,
169 169 addr_matrix_f0_1 => addr_matrix_f0_1,
170 170 addr_matrix_f1 => addr_matrix_f1,
171 171 addr_matrix_f2 => addr_matrix_f2,
172 172
173 173 status_full => status_full,
174 174 status_full_ack => status_full_ack,
175 175 status_full_err => status_full_err,
176 176 status_new_err => status_new_err,
177 177 data_shaping_BW => data_shaping_BW,
178 178 data_shaping_SP0 => data_shaping_SP0,
179 179 data_shaping_SP1 => data_shaping_SP1,
180 180 data_shaping_R0 => data_shaping_R0,
181 181 data_shaping_R1 => data_shaping_R1,
182 182 delta_snapshot => delta_snapshot,
183 183 delta_f2_f1 => delta_f2_f1,
184 184 delta_f2_f0 => delta_f2_f0,
185 185 nb_burst_available => nb_burst_available,
186 186 nb_snapshot_param => nb_snapshot_param,
187 187 enable_f0 => enable_f0,
188 188 enable_f1 => enable_f1,
189 189 enable_f2 => enable_f2,
190 190 enable_f3 => enable_f3,
191 191 burst_f0 => burst_f0,
192 192 burst_f1 => burst_f1,
193 193 burst_f2 => burst_f2,
194 194 addr_data_f0 => addr_data_f0,
195 195 addr_data_f1 => addr_data_f1,
196 196 addr_data_f2 => addr_data_f2,
197 197 addr_data_f3 => addr_data_f3);
198 198
199 199
200 200
201 201
202 202 --DIGITAL_acquisition : AD7688_drvr_sync
203 203 -- GENERIC MAP (
204 204 -- ChanelCount => ChanelCount,
205 205 -- ncycle_cnv_high => ncycle_cnv_high,
206 206 -- ncycle_cnv => ncycle_cnv)
207 207 -- PORT MAP (
208 208 -- cnv_clk => cnv_clk, --
209 209 -- cnv_rstn => cnv_rstn, --
210 210 -- cnv_run => cnv_run, --
211 211 -- cnv => cnv, --
212 212 -- sck => sck, --
213 213 -- sdo => sdo(ChanelCount-1 DOWNTO 0), --
214 214 -- sample => sample,
215 215 -- sample_val => sample_val);
216 216
217 217 all_channel: FOR i IN 7 DOWNTO 0 GENERATE
218 218 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
219 219 END GENERATE all_channel;
220 220
221 221
222 222 wf_picker_with_filter : IF ENABLE_FILTER = '1' GENERATE
223 223
224 224 lpp_top_lfr_wf_picker_ip_1 : lpp_top_lfr_wf_picker_ip
225 225 GENERIC MAP (
226 226 hindex => hindex,
227 227 nb_burst_available_size => nb_burst_available_size,
228 228 nb_snapshot_param_size => nb_snapshot_param_size,
229 229 delta_snapshot_size => delta_snapshot_size,
230 230 delta_f2_f0_size => delta_f2_f0_size,
231 231 delta_f2_f1_size => delta_f2_f1_size,
232 232 tech => tech,
233 233 Mem_use => use_RAM
234 234 )
235 235 PORT MAP (
236 236 sample => sample_s,
237 237 sample_val => sample_val,
238 238
239 cnv_clk => cnv_clk,
240 cnv_rstn => cnv_rstn,
239 cnv_clk => HCLK,--cnv_clk,
240 cnv_rstn => HRESETn,--cnv_rstn,
241 241
242 242 clk => HCLK,
243 243 rstn => HRESETn,
244 244
245 245 sample_f0_wen => sample_f0_wen,
246 246 sample_f0_wdata => sample_f0_wdata,
247 247 sample_f1_wen => sample_f1_wen,
248 248 sample_f1_wdata => sample_f1_wdata,
249 249 sample_f2_wen => sample_f2_wen,
250 250 sample_f2_wdata => sample_f2_wdata,
251 251 sample_f3_wen => sample_f3_wen,
252 252 sample_f3_wdata => sample_f3_wdata,
253 253 AHB_Master_In => AHB_Master_In,
254 254 AHB_Master_Out => AHB_Master_Out,
255 255 coarse_time_0 => coarse_time_0,
256 256 data_shaping_SP0 => data_shaping_SP0,
257 257 data_shaping_SP1 => data_shaping_SP1,
258 258 data_shaping_R0 => data_shaping_R0,
259 259 data_shaping_R1 => data_shaping_R1,
260 260 delta_snapshot => delta_snapshot,
261 261 delta_f2_f1 => delta_f2_f1,
262 262 delta_f2_f0 => delta_f2_f0,
263 263 enable_f0 => enable_f0,
264 264 enable_f1 => enable_f1,
265 265 enable_f2 => enable_f2,
266 266 enable_f3 => enable_f3,
267 267 burst_f0 => burst_f0,
268 268 burst_f1 => burst_f1,
269 269 burst_f2 => burst_f2,
270 270 nb_burst_available => nb_burst_available,
271 271 nb_snapshot_param => nb_snapshot_param,
272 272 status_full => status_full,
273 273 status_full_ack => status_full_ack,
274 274 status_full_err => status_full_err,
275 275 status_new_err => status_new_err,
276 276 addr_data_f0 => addr_data_f0,
277 277 addr_data_f1 => addr_data_f1,
278 278 addr_data_f2 => addr_data_f2,
279 279 addr_data_f3 => addr_data_f3);
280 280
281 281 END GENERATE wf_picker_with_filter;
282 282
283 283
284 284 wf_picker_without_filter : IF ENABLE_FILTER = '0' GENERATE
285 285
286 286 lpp_top_lfr_wf_picker_ip_2 : lpp_top_lfr_wf_picker_ip_whitout_filter
287 287 GENERIC MAP (
288 288 hindex => hindex,
289 289 nb_burst_available_size => nb_burst_available_size,
290 290 nb_snapshot_param_size => nb_snapshot_param_size,
291 291 delta_snapshot_size => delta_snapshot_size,
292 292 delta_f2_f0_size => delta_f2_f0_size,
293 293 delta_f2_f1_size => delta_f2_f1_size,
294 294 tech => tech
295 295 )
296 296 PORT MAP (
297 297 sample => sample_s,
298 298 sample_val => sample_val,
299 299
300 300 cnv_clk => cnv_clk,
301 301 cnv_rstn => cnv_rstn,
302 302
303 303 clk => HCLK,
304 304 rstn => HRESETn,
305 305
306 306 sample_f0_wen => sample_f0_wen,
307 307 sample_f0_wdata => sample_f0_wdata,
308 308 sample_f1_wen => sample_f1_wen,
309 309 sample_f1_wdata => sample_f1_wdata,
310 310 sample_f2_wen => sample_f2_wen,
311 311 sample_f2_wdata => sample_f2_wdata,
312 312 sample_f3_wen => sample_f3_wen,
313 313 sample_f3_wdata => sample_f3_wdata,
314 314 AHB_Master_In => AHB_Master_In,
315 315 AHB_Master_Out => AHB_Master_Out,
316 316 coarse_time_0 => coarse_time_0,
317 317 data_shaping_SP0 => data_shaping_SP0,
318 318 data_shaping_SP1 => data_shaping_SP1,
319 319 data_shaping_R0 => data_shaping_R0,
320 320 data_shaping_R1 => data_shaping_R1,
321 321 delta_snapshot => delta_snapshot,
322 322 delta_f2_f1 => delta_f2_f1,
323 323 delta_f2_f0 => delta_f2_f0,
324 324 enable_f0 => enable_f0,
325 325 enable_f1 => enable_f1,
326 326 enable_f2 => enable_f2,
327 327 enable_f3 => enable_f3,
328 328 burst_f0 => burst_f0,
329 329 burst_f1 => burst_f1,
330 330 burst_f2 => burst_f2,
331 331 nb_burst_available => nb_burst_available,
332 332 nb_snapshot_param => nb_snapshot_param,
333 333 status_full => status_full,
334 334 status_full_ack => status_full_ack,
335 335 status_full_err => status_full_err,
336 336 status_new_err => status_new_err,
337 337 addr_data_f0 => addr_data_f0,
338 338 addr_data_f1 => addr_data_f1,
339 339 addr_data_f2 => addr_data_f2,
340 340 addr_data_f3 => addr_data_f3);
341 341
342 342 END GENERATE wf_picker_without_filter;
343 343 END tb;
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