@@ -1,54 +1,54 | |||
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1 | 1 | onerror {resume} |
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2 | 2 | quietly WaveActivateNextPane {} 0 |
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3 | 3 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot |
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4 | 4 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/run |
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5 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
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6 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
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7 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
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5 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out | |
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6 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out | |
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7 | add wave -noupdate -group DATA_OUT /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out | |
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8 | 8 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f2/data_out_valid |
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9 | 9 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f1/data_out_valid |
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10 | 10 | add wave -noupdate /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/data_out_valid |
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11 |
add wave -noupdate -radix hexadecimal |
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11 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(0) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(1) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(2) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(3) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(4) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(5) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(6) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(7) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(8) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(9) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(10) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(11) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(12) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(13) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(14) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(15) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(16) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(17) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(18) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(19) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(20) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(21) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(22) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(23) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(24) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(25) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(26) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(27) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(28) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(29) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(30) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(31) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(32) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(33) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(34) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(35) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(36) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(37) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(38) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(39) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(40) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(41) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(42) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(43) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(44) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(45) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(46) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(47) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(48) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(49) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(50) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(51) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(52) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(53) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(54) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(55) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(56) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(57) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(58) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(59) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(60) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(61) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(62) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(63) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(64) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(65) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(66) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(67) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(68) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(69) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(70) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(71) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(72) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(73) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(74) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(75) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(76) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(77) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(78) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(79) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(80) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(81) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(82) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(83) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(84) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(85) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(86) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(87) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(88) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(89) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(90) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(91) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(92) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(93) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(94) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(95) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(96) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(97) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(98) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(99) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(100) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(101) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(102) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(103) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(104) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(105) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(106) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(107) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(108) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(109) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(110) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(111) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(112) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(113) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(114) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(115) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(116) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(117) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(118) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(119) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(120) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(121) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(122) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(123) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(124) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(125) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(126) {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd(127) {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_waveform_1/lpp_waveform_fifo_1/sram/inf/x0/rfd | |
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12 | 12 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/address |
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13 | 13 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in |
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14 | 14 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out |
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15 | 15 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/data |
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16 | 16 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay |
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17 | 17 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/done |
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18 | 18 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hindex |
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19 | 19 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/hresetn |
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20 | 20 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/ren |
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21 | 21 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/run |
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22 | 22 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/send |
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23 | 23 | add wave -noupdate -group DMA_S_or_B /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst |
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24 | 24 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbin |
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25 | 25 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/ahbout |
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26 | add wave -noupdate -subitemconfig {/testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.address {-height 15 -radix hexadecimal} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data {-height 15 -radix hexadecimal}} /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
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26 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain | |
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27 | 27 | add wave -noupdate -label data -radix hexadecimal /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmain.data |
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28 | 28 | add wave -noupdate -label grant /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout.grant |
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29 | 29 | add wave -noupdate /testbench/lpp_lfr_1/lpp_dma_singleorburst_1/dma2ahb_1/dmaout |
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30 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_0 | |
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31 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_0(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_0(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_0 | |
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32 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_1 | |
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33 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_1(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_1(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_1 | |
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34 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_2 | |
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35 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
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36 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
|
37 | add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/async_1mx16_1/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_3 | |
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30 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_0 | |
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31 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_0 | |
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32 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_1 | |
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33 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_1 | |
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34 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_0/mem_array_2 | |
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35 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_1/mem_array_2(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_1/mem_array_2(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_1/mem_array_2 | |
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36 | add wave -noupdate -radix hexadecimal -expand -subitemconfig {/testbench/async_1mx16_0/mem_array_3(31) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(30) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(29) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(28) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(27) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(26) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(25) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(24) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(23) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(22) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(21) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(20) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(19) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(18) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(17) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(16) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(15) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(14) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(13) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(12) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(11) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(10) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(9) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(8) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(7) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(6) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(5) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(4) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(3) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(2) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(1) {-height 15 -radix hexadecimal} /testbench/async_1mx16_0/mem_array_3(0) {-height 15 -radix hexadecimal}} /testbench/async_1mx16_0/mem_array_3 | |
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37 | add wave -noupdate -radix hexadecimal /testbench/async_1mx16_1/mem_array_3 | |
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38 | 38 | TreeUpdate [SetDefaultTree] |
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39 |
WaveRestoreCursors {{Cursor 1} { |
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39 | WaveRestoreCursors {{Cursor 1} {340947831721 ps} 0} | |
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40 | 40 | configure wave -namecolwidth 540 |
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41 | 41 | configure wave -valuecolwidth 316 |
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42 | 42 | configure wave -justifyvalue left |
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43 | 43 | configure wave -signalnamewidth 0 |
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44 | 44 | configure wave -snapdistance 10 |
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45 | 45 | configure wave -datasetprefix 0 |
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46 | 46 | configure wave -rowmargin 4 |
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47 | 47 | configure wave -childrowmargin 2 |
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48 | 48 | configure wave -gridoffset 0 |
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49 | 49 | configure wave -gridperiod 1 |
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50 | 50 | configure wave -griddelta 40 |
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51 | 51 | configure wave -timeline 0 |
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52 | 52 | configure wave -timelineunits ns |
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53 | 53 | update |
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54 |
WaveRestoreZoom {0 ps} {6 |
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54 | WaveRestoreZoom {0 ps} {628873035 ns} |
@@ -1,529 +1,513 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
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20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------- |
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22 | 22 | LIBRARY IEEE; |
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23 | 23 | USE IEEE.numeric_std.ALL; |
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24 | 24 | USE IEEE.std_logic_1164.ALL; |
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25 | 25 | LIBRARY grlib; |
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26 | 26 | USE grlib.amba.ALL; |
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27 | 27 | USE grlib.stdlib.ALL; |
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28 | 28 | LIBRARY techmap; |
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29 | 29 | USE techmap.gencomp.ALL; |
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30 | 30 | LIBRARY gaisler; |
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31 | 31 | USE gaisler.memctrl.ALL; |
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32 | 32 | USE gaisler.leon3.ALL; |
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33 | 33 | USE gaisler.uart.ALL; |
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34 | 34 | USE gaisler.misc.ALL; |
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35 | 35 | USE gaisler.spacewire.ALL; |
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36 | 36 | LIBRARY esa; |
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37 | 37 | USE esa.memoryctrl.ALL; |
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38 | 38 | LIBRARY lpp; |
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39 | 39 | USE lpp.lpp_memory.ALL; |
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40 | 40 | USE lpp.lpp_ad_conv.ALL; |
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41 | 41 | --USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
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42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker | |
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43 | 43 | USE lpp.iir_filter.ALL; |
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44 | 44 | USE lpp.general_purpose.ALL; |
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45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
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46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
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47 | 47 | |
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48 | 48 | ENTITY MINI_LFR_top IS |
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49 | 49 | |
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50 | 50 | PORT ( |
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51 | 51 | clk_50 : IN STD_LOGIC; |
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52 | 52 | clk_49 : IN STD_LOGIC; |
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53 | 53 | reset : IN STD_LOGIC; |
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54 | 54 | --BPs |
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55 | 55 | BP0 : IN STD_LOGIC; |
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56 | 56 | BP1 : IN STD_LOGIC; |
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57 | 57 | --LEDs |
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58 | 58 | LED0 : OUT STD_LOGIC; |
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59 | 59 | LED1 : OUT STD_LOGIC; |
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60 | 60 | LED2 : OUT STD_LOGIC; |
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61 | 61 | --UARTs |
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62 | 62 | TXD1 : IN STD_LOGIC; |
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63 | 63 | RXD1 : OUT STD_LOGIC; |
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64 |
nCTS1 : OUT STD_LOGIC; |
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65 |
nRTS1 : IN STD_LOGIC; |
|
|
64 | nCTS1 : OUT STD_LOGIC; | |
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65 | nRTS1 : IN STD_LOGIC; | |
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66 | 66 | |
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67 | 67 | TXD2 : IN STD_LOGIC; |
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68 | 68 | RXD2 : OUT STD_LOGIC; |
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69 |
nCTS2 : OUT STD_LOGIC; |
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|
70 |
nDTR2 : IN STD_LOGIC; |
|
|
71 |
nRTS2 : IN STD_LOGIC; |
|
|
72 |
nDCD2 : OUT STD_LOGIC; |
|
|
69 | nCTS2 : OUT STD_LOGIC; | |
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70 | nDTR2 : IN STD_LOGIC; | |
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71 | nRTS2 : IN STD_LOGIC; | |
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72 | nDCD2 : OUT STD_LOGIC; | |
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73 | 73 | |
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74 | 74 | --EXT CONNECTOR |
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75 | 75 | IO0 : INOUT STD_LOGIC; |
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76 | 76 | IO1 : INOUT STD_LOGIC; |
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77 | 77 | IO2 : INOUT STD_LOGIC; |
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78 | 78 | IO3 : INOUT STD_LOGIC; |
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79 | 79 | IO4 : INOUT STD_LOGIC; |
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80 | 80 | IO5 : INOUT STD_LOGIC; |
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81 | 81 | IO6 : INOUT STD_LOGIC; |
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82 | 82 | IO7 : INOUT STD_LOGIC; |
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83 | 83 | IO8 : INOUT STD_LOGIC; |
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84 | 84 | IO9 : INOUT STD_LOGIC; |
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85 | 85 | IO10 : INOUT STD_LOGIC; |
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86 | 86 | IO11 : INOUT STD_LOGIC; |
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87 | 87 | |
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88 | 88 | --SPACE WIRE |
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89 |
SPW_EN : OUT STD_LOGIC; |
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90 |
SPW_NOM_DIN : IN STD_LOGIC; |
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89 | SPW_EN : OUT STD_LOGIC; -- 0 => off | |
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90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK | |
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91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
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92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
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93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
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94 |
SPW_RED_DIN : IN STD_LOGIC; |
|
|
94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK | |
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95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
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96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
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97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
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98 | 98 | -- MINI LFR ADC INPUTS |
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99 | 99 | ADC_nCS : OUT STD_LOGIC; |
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100 | 100 | ADC_CLK : OUT STD_LOGIC; |
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101 |
ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
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101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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102 | 102 | |
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103 | 103 | -- SRAM |
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104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
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105 | 105 | SRAM_CE : OUT STD_LOGIC; |
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106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
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107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
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109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
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110 | 110 | ); |
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111 | 111 | |
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112 | 112 | END MINI_LFR_top; |
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113 | 113 | |
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114 | 114 | |
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115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
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116 | SIGNAL clk_50_s : STD_LOGIC := '0'; | |
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117 | SIGNAL clk_25 : STD_LOGIC := '0'; | |
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118 | 118 | ----------------------------------------------------------------------------- |
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119 |
SIGNAL coarse_time |
|
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120 |
SIGNAL fine_time |
|
|
119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
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121 | 121 | -- |
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122 | SIGNAL errorn : STD_LOGIC; | |
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122 | SIGNAL errorn : STD_LOGIC; | |
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123 | 123 | -- UART AHB --------------------------------------------------------------- |
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124 |
SIGNAL |
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125 |
SIGNAL |
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124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data | |
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125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data | |
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126 | 126 | |
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127 | 127 | -- UART APB --------------------------------------------------------------- |
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128 |
SIGNAL |
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129 |
SIGNAL |
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130 |
|
|
|
128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data | |
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129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data | |
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130 | -- | |
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131 | 131 | SIGNAL I00_s : STD_LOGIC; |
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132 | ||
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132 | ||
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133 | 133 | -- CONSTANTS |
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134 |
|
|
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134 | CONSTANT CFG_PADTECH : INTEGER := inferred; | |
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135 | 135 | -- |
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136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f | |
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137 | 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
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138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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139 | ||
|
140 |
SIGNAL |
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|
141 |
SIGNAL |
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|
142 |
SIGNAL |
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|
143 |
SIGNAL |
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144 |
SIGNAL |
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145 |
SIGNAL |
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146 | ||
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138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker | |
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139 | ||
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140 | SIGNAL apbi_ext : apb_slv_in_type; | |
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141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); | |
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142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; | |
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143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); | |
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144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; | |
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145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); | |
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146 | ||
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147 | 147 | -- Spacewire signals |
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148 |
SIGNAL dtmp |
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149 |
SIGNAL stmp |
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150 |
SIGNAL spw_rxclk |
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151 |
SIGNAL spw_rxtxclk |
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152 |
SIGNAL spw_rxclkn |
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153 |
SIGNAL spw_clk |
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154 |
SIGNAL swni |
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155 |
SIGNAL swno |
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156 |
-- SIGNAL clkmn |
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157 |
-- SIGNAL txclk |
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148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); | |
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151 | SIGNAL spw_rxtxclk : STD_ULOGIC; | |
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152 | SIGNAL spw_rxclkn : STD_ULOGIC; | |
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153 | SIGNAL spw_clk : STD_LOGIC; | |
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154 | SIGNAL swni : grspw_in_type; | |
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155 | SIGNAL swno : grspw_out_type; | |
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156 | -- SIGNAL clkmn : STD_ULOGIC; | |
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157 | -- SIGNAL txclk : STD_ULOGIC; | |
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158 | 158 | |
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159 | 159 | --GPIO |
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160 |
SIGNAL gpioi |
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161 |
SIGNAL gpioo |
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160 | SIGNAL gpioi : gpio_in_type; | |
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161 | SIGNAL gpioo : gpio_out_type; | |
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162 | 162 | |
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163 | 163 | -- AD Converter ADS7886 |
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164 |
SIGNAL sample |
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165 |
SIGNAL sample_val |
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166 |
SIGNAL ADC_nCS_sig |
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167 |
SIGNAL ADC_CLK_sig |
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168 |
SIGNAL ADC_SDO_sig |
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169 | ||
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170 |
SIGNAL |
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164 | SIGNAL sample : Samples14v(7 DOWNTO 0); | |
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165 | SIGNAL sample_val : STD_LOGIC; | |
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166 | SIGNAL ADC_nCS_sig : STD_LOGIC; | |
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167 | SIGNAL ADC_CLK_sig : STD_LOGIC; | |
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168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); | |
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169 | ||
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170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; | |
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171 | 171 | |
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172 | 172 | BEGIN -- beh |
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173 | 173 | |
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174 | 174 | ----------------------------------------------------------------------------- |
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175 | 175 | -- CLK |
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176 | 176 | ----------------------------------------------------------------------------- |
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177 | 177 | |
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178 | 178 | PROCESS(clk_50) |
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179 | 179 | BEGIN |
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180 | 180 | IF clk_50'EVENT AND clk_50 = '1' THEN |
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181 | 181 | clk_50_s <= NOT clk_50_s; |
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182 | 182 | END IF; |
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183 | 183 | END PROCESS; |
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184 | ||
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184 | ||
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185 | 185 | PROCESS(clk_50_s) |
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186 | 186 | BEGIN |
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187 | 187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
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188 | 188 | clk_25 <= NOT clk_25; |
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189 | 189 | END IF; |
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190 | 190 | END PROCESS; |
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191 | 191 | |
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192 | 192 | ----------------------------------------------------------------------------- |
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193 | ||
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193 | ||
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194 | 194 | PROCESS (clk_25, reset) |
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195 | 195 | BEGIN -- PROCESS |
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196 | 196 | IF reset = '0' THEN -- asynchronous reset (active low) |
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197 | 197 | LED0 <= '0'; |
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198 | 198 | LED1 <= '0'; |
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199 | 199 | LED2 <= '0'; |
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200 | 200 | --IO1 <= '0'; |
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201 | 201 | --IO2 <= '1'; |
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202 | 202 | --IO3 <= '0'; |
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203 | 203 | --IO4 <= '0'; |
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204 | 204 | --IO5 <= '0'; |
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205 | 205 | --IO6 <= '0'; |
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206 | 206 | --IO7 <= '0'; |
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207 | 207 | --IO8 <= '0'; |
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208 | 208 | --IO9 <= '0'; |
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209 | 209 | --IO10 <= '0'; |
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210 | 210 | --IO11 <= '0'; |
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211 |
ELSIF clk_25' |
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211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge | |
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212 | 212 | LED0 <= '0'; |
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213 | 213 | LED1 <= '1'; |
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214 | 214 | LED2 <= BP0; |
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215 | 215 | --IO1 <= '1'; |
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216 | 216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
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217 | 217 | --IO3 <= ADC_SDO(0); |
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218 | 218 | --IO4 <= ADC_SDO(1); |
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219 | 219 | --IO5 <= ADC_SDO(2); |
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220 | 220 | --IO6 <= ADC_SDO(3); |
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221 | 221 | --IO7 <= ADC_SDO(4); |
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222 | 222 | --IO8 <= ADC_SDO(5); |
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223 | 223 | --IO9 <= ADC_SDO(6); |
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224 | 224 | --IO10 <= ADC_SDO(7); |
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225 |
IO11 |
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225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; | |
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226 | 226 | END IF; |
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227 | 227 | END PROCESS; |
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228 | ||
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228 | ||
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229 | 229 | PROCESS (clk_49, reset) |
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230 | 230 | BEGIN -- PROCESS |
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231 | 231 | IF reset = '0' THEN -- asynchronous reset (active low) |
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232 |
I00_s |
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233 |
ELSIF clk_49' |
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234 |
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235 |
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232 | I00_s <= '0'; | |
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233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge | |
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234 | I00_s <= NOT I00_s; | |
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235 | END IF; | |
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236 | 236 | END PROCESS; |
|
237 | 237 | -- IO0 <= I00_s; |
|
238 | 238 | |
|
239 | 239 | --UARTs |
|
240 |
nCTS1 |
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241 |
nCTS2 |
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242 |
nDCD2 |
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240 | nCTS1 <= '1'; | |
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241 | nCTS2 <= '1'; | |
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242 | nDCD2 <= '1'; | |
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243 | 243 | |
|
244 | 244 | --EXT CONNECTOR |
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245 | 245 | |
|
246 | 246 | --SPACE WIRE |
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247 | 247 | |
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248 | leon3_soc_1: leon3_soc | |
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248 | leon3_soc_1 : leon3_soc | |
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249 | 249 | GENERIC MAP ( |
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250 | 250 | fabtech => apa3e, |
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251 | 251 | memtech => apa3e, |
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252 | 252 | padtech => inferred, |
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253 | 253 | clktech => inferred, |
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254 | 254 | disas => 0, |
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255 | 255 | dbguart => 0, |
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256 | 256 | pclow => 2, |
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257 | 257 | clk_freq => 25000, |
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258 | 258 | NB_CPU => 1, |
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259 | 259 | ENABLE_FPU => 1, |
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260 | 260 | FPU_NETLIST => 0, |
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261 | 261 | ENABLE_DSU => 1, |
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262 | 262 | ENABLE_AHB_UART => 1, |
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263 | 263 | ENABLE_APB_UART => 1, |
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264 | 264 | ENABLE_IRQMP => 1, |
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265 | 265 | ENABLE_GPT => 1, |
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266 | 266 | NB_AHB_MASTER => NB_AHB_MASTER, |
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267 | 267 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
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268 | 268 | NB_APB_SLAVE => NB_APB_SLAVE) |
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269 | 269 | PORT MAP ( |
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270 |
clk |
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271 |
reset |
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272 |
errorn |
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273 |
ahbrxd |
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274 |
ahbtxd |
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275 |
urxd1 |
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276 |
utxd1 |
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277 |
address |
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278 |
data |
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279 |
nSRAM_BE0 |
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280 |
nSRAM_BE1 |
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281 |
nSRAM_BE2 |
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282 |
nSRAM_BE3 |
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283 |
nSRAM_WE |
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284 |
nSRAM_CE |
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285 |
nSRAM_OE |
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286 | ||
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270 | clk => clk_25, | |
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271 | reset => reset, | |
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272 | errorn => errorn, | |
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273 | ahbrxd => TXD1, | |
|
274 | ahbtxd => RXD1, | |
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275 | urxd1 => TXD2, | |
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276 | utxd1 => RXD2, | |
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277 | address => SRAM_A, | |
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278 | data => SRAM_DQ, | |
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279 | nSRAM_BE0 => SRAM_nBE(0), | |
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280 | nSRAM_BE1 => SRAM_nBE(1), | |
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281 | nSRAM_BE2 => SRAM_nBE(2), | |
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282 | nSRAM_BE3 => SRAM_nBE(3), | |
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283 | nSRAM_WE => SRAM_nWE, | |
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284 | nSRAM_CE => SRAM_CE, | |
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285 | nSRAM_OE => SRAM_nOE, | |
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286 | ||
|
287 | 287 | apbi_ext => apbi_ext, |
|
288 | 288 | apbo_ext => apbo_ext, |
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289 | 289 | ahbi_s_ext => ahbi_s_ext, |
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290 | 290 | ahbo_s_ext => ahbo_s_ext, |
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291 | 291 | ahbi_m_ext => ahbi_m_ext, |
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292 | 292 | ahbo_m_ext => ahbo_m_ext); |
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293 | ||
|
293 | ||
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294 | 294 | ------------------------------------------------------------------------------- |
|
295 | 295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
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296 | 296 | ------------------------------------------------------------------------------- |
|
297 | apb_lfr_time_management_1: apb_lfr_time_management | |
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297 | apb_lfr_time_management_1 : apb_lfr_time_management | |
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298 | 298 | GENERIC MAP ( |
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299 | 299 | pindex => 6, |
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300 | 300 | paddr => 6, |
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301 | 301 | pmask => 16#fff#, |
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302 | 302 | pirq => 12) |
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303 | 303 | PORT MAP ( |
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304 | 304 | clk25MHz => clk_25, |
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305 | 305 | clk49_152MHz => clk_49, |
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306 | 306 | resetn => reset, |
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307 | 307 | grspw_tick => swno.tickout, |
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308 | 308 | apbi => apbi_ext, |
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309 | 309 | apbo => apbo_ext(6), |
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310 | 310 | coarse_time => coarse_time, |
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311 | 311 | fine_time => fine_time); |
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312 | ||
|
312 | ||
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313 | 313 | ----------------------------------------------------------------------- |
|
314 | 314 | --- SpaceWire -------------------------------------------------------- |
|
315 | 315 | ----------------------------------------------------------------------- |
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316 | 316 | |
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317 |
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318 | ||
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319 |
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320 |
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321 |
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322 | ||
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323 |
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324 |
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325 |
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326 |
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327 |
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328 |
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329 |
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330 |
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331 |
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332 |
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333 |
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334 |
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335 |
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336 |
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337 |
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338 |
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339 |
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340 |
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|
317 | SPW_EN <= '1'; | |
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318 | ||
|
319 | spw_clk <= clk_50_s; | |
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320 | spw_rxtxclk <= spw_clk; | |
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321 | spw_rxclkn <= NOT spw_rxtxclk; | |
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322 | ||
|
323 | -- PADS for SPW1 | |
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324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) | |
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325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); | |
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326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) | |
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327 | PORT MAP (SPW_NOM_SIN, stmp(0)); | |
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328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) | |
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329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); | |
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330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) | |
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331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); | |
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332 | -- PADS FOR SPW2 | |
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333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
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334 | PORT MAP (SPW_RED_SIN, dtmp(1)); | |
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335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ | |
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336 | PORT MAP (SPW_RED_DIN, stmp(1)); | |
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337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) | |
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338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); | |
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339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) | |
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340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); | |
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341 | 341 | |
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342 |
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343 |
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|
344 | spw_inputloop: for j in 0 to 1 generate | |
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345 |
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346 | generic map( | |
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347 |
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348 |
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349 |
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350 | port map( | |
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351 |
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352 |
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353 |
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354 |
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355 |
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356 |
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357 |
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|
358 | end generate spw_inputloop; | |
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342 | -- GRSPW PHY | |
|
343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate | |
|
344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE | |
|
345 | spw_phy0 : grspw_phy | |
|
346 | GENERIC MAP( | |
|
347 | tech => apa3e, | |
|
348 | rxclkbuftype => 1, | |
|
349 | scantest => 0) | |
|
350 | PORT MAP( | |
|
351 | rxrst => swno.rxrst, | |
|
352 | di => dtmp(j), | |
|
353 | si => stmp(j), | |
|
354 | rxclko => spw_rxclk(j), | |
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355 | do => swni.d(j), | |
|
356 | ndo => swni.nd(j*5+4 DOWNTO j*5), | |
|
357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); | |
|
358 | END GENERATE spw_inputloop; | |
|
359 | 359 | |
|
360 |
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|
361 | sw0 : grspwm generic map( | |
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362 |
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363 |
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364 |
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365 |
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|
366 | pirq => 11, | |
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367 |
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368 |
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369 |
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370 |
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371 |
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372 |
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373 |
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374 |
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|
375 | ft => 0, | |
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376 |
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377 |
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378 |
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379 |
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380 |
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381 |
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382 |
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383 |
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384 |
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385 | ) | |
|
386 |
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387 |
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388 |
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389 |
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390 | ||
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391 |
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392 |
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393 |
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394 |
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395 |
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396 |
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397 |
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398 | ||
|
360 | -- SPW core | |
|
361 | sw0 : grspwm GENERIC MAP( | |
|
362 | tech => apa3e, | |
|
363 | hindex => 1, | |
|
364 | pindex => 5, | |
|
365 | paddr => 5, | |
|
366 | pirq => 11, | |
|
367 | sysfreq => 25000, -- CPU_FREQ | |
|
368 | rmap => 1, | |
|
369 | rmapcrc => 1, | |
|
370 | fifosize1 => 16, | |
|
371 | fifosize2 => 16, | |
|
372 | rxclkbuftype => 1, | |
|
373 | rxunaligned => 0, | |
|
374 | rmapbufs => 4, | |
|
375 | ft => 0, | |
|
376 | netlist => 0, | |
|
377 | ports => 2, | |
|
378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 | |
|
379 | memtech => apa3e, | |
|
380 | destkey => 2, | |
|
381 | spwcore => 1 | |
|
382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 | |
|
383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 | |
|
384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 | |
|
385 | ) | |
|
386 | PORT MAP(reset, clk_25, spw_rxclk(0), | |
|
387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, | |
|
388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), | |
|
389 | swni, swno); | |
|
390 | ||
|
391 | swni.tickin <= '0'; | |
|
392 | swni.rmapen <= '1'; | |
|
393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz | |
|
394 | swni.tickinraw <= '0'; | |
|
395 | swni.timein <= (OTHERS => '0'); | |
|
396 | swni.dcrstval <= (OTHERS => '0'); | |
|
397 | swni.timerrstval <= (OTHERS => '0'); | |
|
398 | ||
|
399 | 399 | ------------------------------------------------------------------------------- |
|
400 | 400 | -- LFR ------------------------------------------------------------------------ |
|
401 | 401 | ------------------------------------------------------------------------------- |
|
402 | 402 | -- lpp_lfr_1 : lpp_lfr |
|
403 | 403 | -- GENERIC MAP ( |
|
404 | 404 | -- Mem_use => use_RAM, |
|
405 | 405 | -- nb_data_by_buffer_size => 32, |
|
406 | 406 | -- nb_word_by_buffer_size => 30, |
|
407 | 407 | -- nb_snapshot_param_size => 32, |
|
408 | 408 | -- delta_vector_size => 32, |
|
409 | 409 | -- delta_vector_size_f0_2 => 7, -- log2(96) |
|
410 | 410 | -- pindex => 6, |
|
411 | 411 | -- paddr => 6, |
|
412 | 412 | -- pmask => 16#fff#, |
|
413 | 413 | -- pirq_ms => 6, |
|
414 | 414 | -- pirq_wfp => 14, |
|
415 | 415 | -- hindex => 2, |
|
416 | 416 | -- top_lfr_version => X"00000005") |
|
417 | 417 | -- PORT MAP ( |
|
418 | 418 | -- clk => clk_25, |
|
419 | 419 | -- rstn => reset, |
|
420 | 420 | -- sample_B => sample(2 DOWNTO 0), |
|
421 | 421 | -- sample_E => sample(7 DOWNTO 3), |
|
422 | 422 | -- sample_val => sample_val, |
|
423 | 423 | -- apbi => apbi_ext, |
|
424 | 424 | -- apbo => apbo_ext(6), |
|
425 | 425 | -- ahbi => ahbi_m_ext, |
|
426 | 426 | -- ahbo => ahbo_m_ext(2), |
|
427 | 427 | -- coarse_time => coarse_time, |
|
428 | 428 | -- fine_time => fine_time, |
|
429 | 429 | -- data_shaping_BW => bias_fail_sw_sig); |
|
430 | 430 | |
|
431 |
|
|
|
431 | waveform_picker0 : top_wf_picker | |
|
432 | 432 | GENERIC MAP( |
|
433 | 433 | hindex => 2, |
|
434 | 434 | pindex => 15, |
|
435 | 435 | paddr => 15, |
|
436 | 436 | pmask => 16#fff#, |
|
437 | 437 | pirq => 14, |
|
438 | 438 | tech => apa3e, |
|
439 | 439 | nb_burst_available_size => 12, -- size of the register holding the nb of burst |
|
440 | 440 | nb_snapshot_param_size => 12, -- size of the register holding the snapshots size |
|
441 | delta_snapshot_size => 16, -- snapshots period | |
|
441 | delta_snapshot_size => 16, -- snapshots period | |
|
442 | 442 | delta_f2_f0_size => 20, -- initialize the counter when the f2 snapshot starts |
|
443 | 443 | delta_f2_f1_size => 16, -- nb f0 ticks before starting the f1 snapshot |
|
444 | 444 | ENABLE_FILTER => '1' |
|
445 | 445 | ) |
|
446 | 446 | PORT MAP( |
|
447 | 447 | cnv_clk => clk_25, |
|
448 | 448 | cnv_rstn => reset, |
|
449 | 449 | -- SAMPLES |
|
450 | sample_B => sample(2 DOWNTO 0), | |
|
451 | sample_E => sample(7 DOWNTO 3), | |
|
452 |
sample_val => sample_val, |
|
|
450 | sample_B => sample(2 DOWNTO 0), | |
|
451 | sample_E => sample(7 DOWNTO 3), | |
|
452 | sample_val => sample_val, | |
|
453 | 453 | -- AMBA AHB system signals |
|
454 | 454 | HCLK => clk_25, |
|
455 | 455 | HRESETn => reset, |
|
456 | 456 | -- AMBA APB Slave Interface |
|
457 | 457 | apbi => apbi_ext, |
|
458 | 458 | apbo => apbo_ext(15), |
|
459 | 459 | -- AMBA AHB Master Interface |
|
460 | 460 | AHB_Master_In => ahbi_m_ext, |
|
461 | 461 | AHB_Master_Out => ahbo_m_ext(2), |
|
462 | 462 | -- |
|
463 | 463 | coarse_time_0 => coarse_time(0), -- bit 0 of the coarse time |
|
464 | 464 | -- |
|
465 |
data_shaping_BW => bias_fail_sw_sig |
|
|
465 | data_shaping_BW => bias_fail_sw_sig | |
|
466 | 466 | ); |
|
467 | 467 | |
|
468 |
|
|
|
468 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 | |
|
469 | 469 | GENERIC MAP( |
|
470 |
|
|
|
471 |
|
|
|
472 |
ncycle_cnv_high => 80, |
|
|
473 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
|
470 | ChannelCount => 8, | |
|
471 | SampleNbBits => 14, | |
|
472 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 | |
|
473 | ncycle_cnv => 500) -- 49 152 000 / 98304 | |
|
474 | 474 | PORT MAP ( |
|
475 |
|
|
|
476 |
|
|
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
|
481 |
|
|
|
482 |
|
|
|
483 |
|
|
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
|
487 | ||
|
488 | IO10 <= ADC_SDO_sig(5); | |
|
489 | IO9 <= ADC_SDO_sig(4); | |
|
490 | IO8 <= ADC_SDO_sig(3); | |
|
475 | -- CONV | |
|
476 | cnv_clk => clk_49, | |
|
477 | cnv_rstn => reset, | |
|
478 | cnv => ADC_nCS_sig, | |
|
479 | -- DATA | |
|
480 | clk => clk_25, | |
|
481 | rstn => reset, | |
|
482 | sck => ADC_CLK_sig, | |
|
483 | sdo => ADC_SDO_sig, | |
|
484 | -- SAMPLE | |
|
485 | sample => sample, | |
|
486 | sample_val => sample_val); | |
|
491 | 487 | |
|
492 |
|
|
|
493 |
|
|
|
494 |
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|
|
495 | ||
|
488 | IO10 <= ADC_SDO_sig(5); | |
|
489 | IO9 <= ADC_SDO_sig(4); | |
|
490 | IO8 <= ADC_SDO_sig(3); | |
|
491 | ||
|
492 | ADC_nCS <= ADC_nCS_sig; | |
|
493 | ADC_CLK <= ADC_CLK_sig; | |
|
494 | ADC_SDO_sig <= ADC_SDO; | |
|
495 | ||
|
496 | 496 | ---------------------------------------------------------------------- |
|
497 | 497 | --- GPIO ----------------------------------------------------------- |
|
498 | 498 | ---------------------------------------------------------------------- |
|
499 | 499 | |
|
500 | grgpio0: grgpio | |
|
501 |
|
|
|
502 |
|
|
|
503 | ||
|
504 | pio_pad_0 : iopad | |
|
505 | generic map (tech => CFG_PADTECH) | |
|
506 | port map (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
|
507 | pio_pad_1 : iopad | |
|
508 | generic map (tech => CFG_PADTECH) | |
|
509 | port map (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
|
510 | pio_pad_2 : iopad | |
|
511 | generic map (tech => CFG_PADTECH) | |
|
512 | port map (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
|
513 | pio_pad_3 : iopad | |
|
514 | generic map (tech => CFG_PADTECH) | |
|
515 | port map (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
|
516 | pio_pad_4 : iopad | |
|
517 | generic map (tech => CFG_PADTECH) | |
|
518 | port map (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
|
519 | pio_pad_5 : iopad | |
|
520 | generic map (tech => CFG_PADTECH) | |
|
521 | port map (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
|
522 | pio_pad_6 : iopad | |
|
523 | generic map (tech => CFG_PADTECH) | |
|
524 | port map (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
|
525 | pio_pad_7 : iopad | |
|
526 | generic map (tech => CFG_PADTECH) | |
|
527 | port map (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
|
500 | grgpio0 : grgpio | |
|
501 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) | |
|
502 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); | |
|
503 | ||
|
504 | pio_pad_0 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); | |
|
505 | pio_pad_1 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); | |
|
506 | pio_pad_2 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); | |
|
507 | pio_pad_3 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); | |
|
508 | pio_pad_4 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); | |
|
509 | pio_pad_5 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); | |
|
510 | pio_pad_6 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); | |
|
511 | pio_pad_7 : iopad GENERIC MAP (tech => CFG_PADTECH) PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); | |
|
528 | 512 | |
|
529 | END beh; No newline at end of file | |
|
513 | END beh; |
@@ -1,492 +1,492 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------- |
|
19 | 19 | -- Author : Jean-christophe Pellion |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------- |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.numeric_std.ALL; |
|
24 | 24 | USE IEEE.std_logic_1164.ALL; |
|
25 | 25 | LIBRARY grlib; |
|
26 | 26 | USE grlib.amba.ALL; |
|
27 | 27 | USE grlib.stdlib.ALL; |
|
28 | 28 | LIBRARY techmap; |
|
29 | 29 | USE techmap.gencomp.ALL; |
|
30 | 30 | LIBRARY gaisler; |
|
31 | 31 | USE gaisler.memctrl.ALL; |
|
32 | 32 | USE gaisler.leon3.ALL; |
|
33 | 33 | USE gaisler.uart.ALL; |
|
34 | 34 | USE gaisler.misc.ALL; |
|
35 | 35 | USE gaisler.spacewire.ALL; |
|
36 | 36 | LIBRARY esa; |
|
37 | 37 | USE esa.memoryctrl.ALL; |
|
38 | 38 | LIBRARY lpp; |
|
39 | 39 | USE lpp.lpp_memory.ALL; |
|
40 | 40 | USE lpp.lpp_ad_conv.ALL; |
|
41 | 41 | USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib |
|
42 | 42 | USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker |
|
43 | 43 | USE lpp.iir_filter.ALL; |
|
44 | 44 | USE lpp.general_purpose.ALL; |
|
45 | 45 | USE lpp.lpp_lfr_time_management.ALL; |
|
46 | 46 | USE lpp.lpp_leon3_soc_pkg.ALL; |
|
47 | 47 | |
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | 51 | clk_50 : IN STD_LOGIC; |
|
52 | 52 | clk_49 : IN STD_LOGIC; |
|
53 | 53 | reset : IN STD_LOGIC; |
|
54 | 54 | --BPs |
|
55 | 55 | BP0 : IN STD_LOGIC; |
|
56 | 56 | BP1 : IN STD_LOGIC; |
|
57 | 57 | --LEDs |
|
58 | 58 | LED0 : OUT STD_LOGIC; |
|
59 | 59 | LED1 : OUT STD_LOGIC; |
|
60 | 60 | LED2 : OUT STD_LOGIC; |
|
61 | 61 | --UARTs |
|
62 | 62 | TXD1 : IN STD_LOGIC; |
|
63 | 63 | RXD1 : OUT STD_LOGIC; |
|
64 | 64 | nCTS1 : OUT STD_LOGIC; |
|
65 | 65 | nRTS1 : IN STD_LOGIC; |
|
66 | 66 | |
|
67 | 67 | TXD2 : IN STD_LOGIC; |
|
68 | 68 | RXD2 : OUT STD_LOGIC; |
|
69 | 69 | nCTS2 : OUT STD_LOGIC; |
|
70 | 70 | nDTR2 : IN STD_LOGIC; |
|
71 | 71 | nRTS2 : IN STD_LOGIC; |
|
72 | 72 | nDCD2 : OUT STD_LOGIC; |
|
73 | 73 | |
|
74 | 74 | --EXT CONNECTOR |
|
75 | 75 | IO0 : INOUT STD_LOGIC; |
|
76 | 76 | IO1 : INOUT STD_LOGIC; |
|
77 | 77 | IO2 : INOUT STD_LOGIC; |
|
78 | 78 | IO3 : INOUT STD_LOGIC; |
|
79 | 79 | IO4 : INOUT STD_LOGIC; |
|
80 | 80 | IO5 : INOUT STD_LOGIC; |
|
81 | 81 | IO6 : INOUT STD_LOGIC; |
|
82 | 82 | IO7 : INOUT STD_LOGIC; |
|
83 | 83 | IO8 : INOUT STD_LOGIC; |
|
84 | 84 | IO9 : INOUT STD_LOGIC; |
|
85 | 85 | IO10 : INOUT STD_LOGIC; |
|
86 | 86 | IO11 : INOUT STD_LOGIC; |
|
87 | 87 | |
|
88 | 88 | --SPACE WIRE |
|
89 | 89 | SPW_EN : OUT STD_LOGIC; -- 0 => off |
|
90 | 90 | SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK |
|
91 | 91 | SPW_NOM_SIN : IN STD_LOGIC; |
|
92 | 92 | SPW_NOM_DOUT : OUT STD_LOGIC; |
|
93 | 93 | SPW_NOM_SOUT : OUT STD_LOGIC; |
|
94 | 94 | SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK |
|
95 | 95 | SPW_RED_SIN : IN STD_LOGIC; |
|
96 | 96 | SPW_RED_DOUT : OUT STD_LOGIC; |
|
97 | 97 | SPW_RED_SOUT : OUT STD_LOGIC; |
|
98 | 98 | -- MINI LFR ADC INPUTS |
|
99 | 99 | ADC_nCS : OUT STD_LOGIC; |
|
100 | 100 | ADC_CLK : OUT STD_LOGIC; |
|
101 | 101 | ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
102 | 102 | |
|
103 | 103 | -- SRAM |
|
104 | 104 | SRAM_nWE : OUT STD_LOGIC; |
|
105 | 105 | SRAM_CE : OUT STD_LOGIC; |
|
106 | 106 | SRAM_nOE : OUT STD_LOGIC; |
|
107 | 107 | SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
108 | 108 | SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); |
|
109 | 109 | SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
110 | 110 | ); |
|
111 | 111 | |
|
112 | 112 | END MINI_LFR_top; |
|
113 | 113 | |
|
114 | 114 | |
|
115 | 115 | ARCHITECTURE beh OF MINI_LFR_top IS |
|
116 | 116 | SIGNAL clk_50_s : STD_LOGIC := '0'; |
|
117 | 117 | SIGNAL clk_25 : STD_LOGIC := '0'; |
|
118 | 118 | ----------------------------------------------------------------------------- |
|
119 | 119 | SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
120 | 120 | SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
121 | 121 | -- |
|
122 | 122 | SIGNAL errorn : STD_LOGIC; |
|
123 | 123 | -- UART AHB --------------------------------------------------------------- |
|
124 | 124 | SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data |
|
125 | 125 | SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data |
|
126 | 126 | |
|
127 | 127 | -- UART APB --------------------------------------------------------------- |
|
128 | 128 | SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data |
|
129 | 129 | SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data |
|
130 | 130 | -- |
|
131 | 131 | SIGNAL I00_s : STD_LOGIC; |
|
132 | 132 | |
|
133 | 133 | -- CONSTANTS |
|
134 | 134 | CONSTANT CFG_PADTECH : INTEGER := inferred; |
|
135 | 135 | -- |
|
136 | 136 | CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f |
|
137 | 137 | CONSTANT NB_AHB_SLAVE : INTEGER := 1; |
|
138 | 138 | CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker |
|
139 | 139 | |
|
140 | 140 | SIGNAL apbi_ext : apb_slv_in_type; |
|
141 | 141 | SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none); |
|
142 | 142 | SIGNAL ahbi_s_ext : ahb_slv_in_type; |
|
143 | 143 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none); |
|
144 | 144 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
|
145 | 145 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none); |
|
146 | 146 | |
|
147 | 147 | -- Spacewire signals |
|
148 | 148 | SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
149 | 149 | SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
150 | 150 | SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); |
|
151 | 151 | SIGNAL spw_rxtxclk : STD_ULOGIC; |
|
152 | 152 | SIGNAL spw_rxclkn : STD_ULOGIC; |
|
153 | 153 | SIGNAL spw_clk : STD_LOGIC; |
|
154 | 154 | SIGNAL swni : grspw_in_type; |
|
155 | 155 | SIGNAL swno : grspw_out_type; |
|
156 | 156 | -- SIGNAL clkmn : STD_ULOGIC; |
|
157 | 157 | -- SIGNAL txclk : STD_ULOGIC; |
|
158 | 158 | |
|
159 | 159 | --GPIO |
|
160 | 160 | SIGNAL gpioi : gpio_in_type; |
|
161 | 161 | SIGNAL gpioo : gpio_out_type; |
|
162 | 162 | |
|
163 | 163 | -- AD Converter ADS7886 |
|
164 | 164 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
|
165 | 165 | SIGNAL sample_val : STD_LOGIC; |
|
166 | 166 | SIGNAL ADC_nCS_sig : STD_LOGIC; |
|
167 | 167 | SIGNAL ADC_CLK_sig : STD_LOGIC; |
|
168 | 168 | SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0); |
|
169 | 169 | |
|
170 | 170 | SIGNAL bias_fail_sw_sig : STD_LOGIC; |
|
171 | 171 | |
|
172 | 172 | BEGIN -- beh |
|
173 | 173 | |
|
174 | 174 | ----------------------------------------------------------------------------- |
|
175 | 175 | -- CLK |
|
176 | 176 | ----------------------------------------------------------------------------- |
|
177 | 177 | |
|
178 | 178 | PROCESS(clk_50) |
|
179 | 179 | BEGIN |
|
180 | 180 | IF clk_50'EVENT AND clk_50 = '1' THEN |
|
181 | 181 | clk_50_s <= NOT clk_50_s; |
|
182 | 182 | END IF; |
|
183 | 183 | END PROCESS; |
|
184 | 184 | |
|
185 | 185 | PROCESS(clk_50_s) |
|
186 | 186 | BEGIN |
|
187 | 187 | IF clk_50_s'EVENT AND clk_50_s = '1' THEN |
|
188 | 188 | clk_25 <= NOT clk_25; |
|
189 | 189 | END IF; |
|
190 | 190 | END PROCESS; |
|
191 | 191 | |
|
192 | 192 | ----------------------------------------------------------------------------- |
|
193 | 193 | |
|
194 | 194 | PROCESS (clk_25, reset) |
|
195 | 195 | BEGIN -- PROCESS |
|
196 | 196 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
197 | 197 | LED0 <= '0'; |
|
198 | 198 | LED1 <= '0'; |
|
199 | 199 | LED2 <= '0'; |
|
200 | 200 | --IO1 <= '0'; |
|
201 | 201 | --IO2 <= '1'; |
|
202 | 202 | --IO3 <= '0'; |
|
203 | 203 | --IO4 <= '0'; |
|
204 | 204 | --IO5 <= '0'; |
|
205 | 205 | --IO6 <= '0'; |
|
206 | 206 | --IO7 <= '0'; |
|
207 | 207 | --IO8 <= '0'; |
|
208 | 208 | --IO9 <= '0'; |
|
209 | 209 | --IO10 <= '0'; |
|
210 | 210 | --IO11 <= '0'; |
|
211 | 211 | ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge |
|
212 | 212 | LED0 <= '0'; |
|
213 | 213 | LED1 <= '1'; |
|
214 | 214 | LED2 <= BP0; |
|
215 | 215 | --IO1 <= '1'; |
|
216 | 216 | --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN; |
|
217 | 217 | --IO3 <= ADC_SDO(0); |
|
218 | 218 | --IO4 <= ADC_SDO(1); |
|
219 | 219 | --IO5 <= ADC_SDO(2); |
|
220 | 220 | --IO6 <= ADC_SDO(3); |
|
221 | 221 | --IO7 <= ADC_SDO(4); |
|
222 | 222 | --IO8 <= ADC_SDO(5); |
|
223 | 223 | --IO9 <= ADC_SDO(6); |
|
224 | 224 | --IO10 <= ADC_SDO(7); |
|
225 | 225 | IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
|
226 | 226 | END IF; |
|
227 | 227 | END PROCESS; |
|
228 | 228 | |
|
229 | 229 | PROCESS (clk_49, reset) |
|
230 | 230 | BEGIN -- PROCESS |
|
231 | 231 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
232 | 232 | I00_s <= '0'; |
|
233 | 233 | ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge |
|
234 | 234 | I00_s <= NOT I00_s; |
|
235 | 235 | END IF; |
|
236 | 236 | END PROCESS; |
|
237 | 237 | -- IO0 <= I00_s; |
|
238 | 238 | |
|
239 | 239 | --UARTs |
|
240 | 240 | nCTS1 <= '1'; |
|
241 | 241 | nCTS2 <= '1'; |
|
242 | 242 | nDCD2 <= '1'; |
|
243 | 243 | |
|
244 | 244 | --EXT CONNECTOR |
|
245 | 245 | |
|
246 | 246 | --SPACE WIRE |
|
247 | 247 | |
|
248 | 248 | leon3_soc_1 : leon3_soc |
|
249 | 249 | GENERIC MAP ( |
|
250 | 250 | fabtech => apa3e, |
|
251 | 251 | memtech => apa3e, |
|
252 | 252 | padtech => inferred, |
|
253 | 253 | clktech => inferred, |
|
254 | 254 | disas => 0, |
|
255 | 255 | dbguart => 0, |
|
256 | 256 | pclow => 2, |
|
257 | 257 | clk_freq => 25000, |
|
258 | 258 | NB_CPU => 1, |
|
259 | 259 | ENABLE_FPU => 1, |
|
260 | 260 | FPU_NETLIST => 0, |
|
261 | 261 | ENABLE_DSU => 1, |
|
262 | 262 | ENABLE_AHB_UART => 1, |
|
263 | 263 | ENABLE_APB_UART => 1, |
|
264 | 264 | ENABLE_IRQMP => 1, |
|
265 | 265 | ENABLE_GPT => 1, |
|
266 | 266 | NB_AHB_MASTER => NB_AHB_MASTER, |
|
267 | 267 | NB_AHB_SLAVE => NB_AHB_SLAVE, |
|
268 | 268 | NB_APB_SLAVE => NB_APB_SLAVE) |
|
269 | 269 | PORT MAP ( |
|
270 | 270 | clk => clk_25, |
|
271 | 271 | reset => reset, |
|
272 | 272 | errorn => errorn, |
|
273 | 273 | ahbrxd => TXD1, |
|
274 | 274 | ahbtxd => RXD1, |
|
275 | 275 | urxd1 => TXD2, |
|
276 | 276 | utxd1 => RXD2, |
|
277 | 277 | address => SRAM_A, |
|
278 | 278 | data => SRAM_DQ, |
|
279 | 279 | nSRAM_BE0 => SRAM_nBE(0), |
|
280 | 280 | nSRAM_BE1 => SRAM_nBE(1), |
|
281 | 281 | nSRAM_BE2 => SRAM_nBE(2), |
|
282 | 282 | nSRAM_BE3 => SRAM_nBE(3), |
|
283 | 283 | nSRAM_WE => SRAM_nWE, |
|
284 | 284 | nSRAM_CE => SRAM_CE, |
|
285 | 285 | nSRAM_OE => SRAM_nOE, |
|
286 | 286 | |
|
287 | 287 | apbi_ext => apbi_ext, |
|
288 | 288 | apbo_ext => apbo_ext, |
|
289 | 289 | ahbi_s_ext => ahbi_s_ext, |
|
290 | 290 | ahbo_s_ext => ahbo_s_ext, |
|
291 | 291 | ahbi_m_ext => ahbi_m_ext, |
|
292 | 292 | ahbo_m_ext => ahbo_m_ext); |
|
293 | 293 | |
|
294 | 294 | ------------------------------------------------------------------------------- |
|
295 | 295 | -- APB_LFR_TIME_MANAGEMENT ---------------------------------------------------- |
|
296 | 296 | ------------------------------------------------------------------------------- |
|
297 | 297 | apb_lfr_time_management_1 : apb_lfr_time_management |
|
298 | 298 | GENERIC MAP ( |
|
299 | 299 | pindex => 6, |
|
300 | 300 | paddr => 6, |
|
301 | 301 | pmask => 16#fff#, |
|
302 | 302 | pirq => 12) |
|
303 | 303 | PORT MAP ( |
|
304 | 304 | clk25MHz => clk_25, |
|
305 | 305 | clk49_152MHz => clk_49, |
|
306 | 306 | resetn => reset, |
|
307 | 307 | grspw_tick => swno.tickout, |
|
308 | 308 | apbi => apbi_ext, |
|
309 | 309 | apbo => apbo_ext(6), |
|
310 | 310 | coarse_time => coarse_time, |
|
311 | 311 | fine_time => fine_time); |
|
312 | 312 | |
|
313 | 313 | ----------------------------------------------------------------------- |
|
314 | 314 | --- SpaceWire -------------------------------------------------------- |
|
315 | 315 | ----------------------------------------------------------------------- |
|
316 | 316 | |
|
317 | 317 | SPW_EN <= '1'; |
|
318 | 318 | |
|
319 | 319 | spw_clk <= clk_50_s; |
|
320 | 320 | spw_rxtxclk <= spw_clk; |
|
321 | 321 | spw_rxclkn <= NOT spw_rxtxclk; |
|
322 | 322 | |
|
323 | 323 | -- PADS for SPW1 |
|
324 | 324 | spw1_rxd_pad : inpad GENERIC MAP (tech => inferred) |
|
325 | 325 | PORT MAP (SPW_NOM_DIN, dtmp(0)); |
|
326 | 326 | spw1_rxs_pad : inpad GENERIC MAP (tech => inferred) |
|
327 | 327 | PORT MAP (SPW_NOM_SIN, stmp(0)); |
|
328 | 328 | spw1_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
329 | 329 | PORT MAP (SPW_NOM_DOUT, swno.d(0)); |
|
330 | 330 | spw1_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
331 | 331 | PORT MAP (SPW_NOM_SOUT, swno.s(0)); |
|
332 | 332 | -- PADS FOR SPW2 |
|
333 | 333 | spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
334 | 334 | PORT MAP (SPW_RED_SIN, dtmp(1)); |
|
335 | 335 | spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\ |
|
336 | 336 | PORT MAP (SPW_RED_DIN, stmp(1)); |
|
337 | 337 | spw2_txd_pad : outpad GENERIC MAP (tech => inferred) |
|
338 | 338 | PORT MAP (SPW_RED_DOUT, swno.d(1)); |
|
339 | 339 | spw2_txs_pad : outpad GENERIC MAP (tech => inferred) |
|
340 | 340 | PORT MAP (SPW_RED_SOUT, swno.s(1)); |
|
341 | 341 | |
|
342 | 342 | -- GRSPW PHY |
|
343 | 343 | --spw1_input: if CFG_SPW_GRSPW = 1 generate |
|
344 | 344 | spw_inputloop : FOR j IN 0 TO 1 GENERATE |
|
345 | 345 | spw_phy0 : grspw_phy |
|
346 | 346 | GENERIC MAP( |
|
347 | 347 | tech => apa3e, |
|
348 | 348 | rxclkbuftype => 1, |
|
349 | 349 | scantest => 0) |
|
350 | 350 | PORT MAP( |
|
351 | 351 | rxrst => swno.rxrst, |
|
352 | 352 | di => dtmp(j), |
|
353 | 353 | si => stmp(j), |
|
354 | 354 | rxclko => spw_rxclk(j), |
|
355 | 355 | do => swni.d(j), |
|
356 | 356 | ndo => swni.nd(j*5+4 DOWNTO j*5), |
|
357 | 357 | dconnect => swni.dconnect(j*2+1 DOWNTO j*2)); |
|
358 | 358 | END GENERATE spw_inputloop; |
|
359 | 359 | |
|
360 | 360 | -- SPW core |
|
361 | 361 | sw0 : grspwm GENERIC MAP( |
|
362 | 362 | tech => apa3e, |
|
363 | 363 | hindex => 1, |
|
364 | 364 | pindex => 5, |
|
365 | 365 | paddr => 5, |
|
366 | 366 | pirq => 11, |
|
367 | 367 | sysfreq => 25000, -- CPU_FREQ |
|
368 | 368 | rmap => 1, |
|
369 | 369 | rmapcrc => 1, |
|
370 | 370 | fifosize1 => 16, |
|
371 | 371 | fifosize2 => 16, |
|
372 | 372 | rxclkbuftype => 1, |
|
373 | 373 | rxunaligned => 0, |
|
374 | 374 | rmapbufs => 4, |
|
375 | 375 | ft => 0, |
|
376 | 376 | netlist => 0, |
|
377 | 377 | ports => 2, |
|
378 | 378 | --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1 |
|
379 | 379 | memtech => apa3e, |
|
380 | 380 | destkey => 2, |
|
381 | 381 | spwcore => 1 |
|
382 | 382 | --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1 |
|
383 | 383 | --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1 |
|
384 | 384 | --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1 |
|
385 | 385 | ) |
|
386 | 386 | PORT MAP(reset, clk_25, spw_rxclk(0), |
|
387 | 387 | spw_rxclk(1), spw_rxtxclk, spw_rxtxclk, |
|
388 | 388 | ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5), |
|
389 | 389 | swni, swno); |
|
390 | 390 | |
|
391 | 391 | swni.tickin <= '0'; |
|
392 | 392 | swni.rmapen <= '1'; |
|
393 | 393 | swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz |
|
394 | 394 | swni.tickinraw <= '0'; |
|
395 | 395 | swni.timein <= (OTHERS => '0'); |
|
396 | 396 | swni.dcrstval <= (OTHERS => '0'); |
|
397 | 397 | swni.timerrstval <= (OTHERS => '0'); |
|
398 | 398 | |
|
399 | 399 | ------------------------------------------------------------------------------- |
|
400 | 400 | -- LFR ------------------------------------------------------------------------ |
|
401 | 401 | ------------------------------------------------------------------------------- |
|
402 | 402 | lpp_lfr_1 : lpp_lfr |
|
403 | 403 | GENERIC MAP ( |
|
404 | 404 | Mem_use => use_RAM, |
|
405 | 405 | nb_data_by_buffer_size => 32, |
|
406 | 406 | nb_word_by_buffer_size => 30, |
|
407 | 407 | nb_snapshot_param_size => 32, |
|
408 | 408 | delta_vector_size => 32, |
|
409 | 409 | delta_vector_size_f0_2 => 7, -- log2(96) |
|
410 | 410 | pindex => 15, |
|
411 | 411 | paddr => 15, |
|
412 | 412 | pmask => 16#fff#, |
|
413 | 413 | pirq_ms => 6, |
|
414 | 414 | pirq_wfp => 14, |
|
415 | 415 | hindex => 2, |
|
416 |
top_lfr_version => X"0000000 |
|
|
416 | top_lfr_version => X"0000000B") | |
|
417 | 417 | PORT MAP ( |
|
418 | 418 | clk => clk_25, |
|
419 | 419 | rstn => reset, |
|
420 | 420 | sample_B => sample(2 DOWNTO 0), |
|
421 | 421 | sample_E => sample(7 DOWNTO 3), |
|
422 | 422 | sample_val => sample_val, |
|
423 | 423 | apbi => apbi_ext, |
|
424 | 424 | apbo => apbo_ext(15), |
|
425 | 425 | ahbi => ahbi_m_ext, |
|
426 | 426 | ahbo => ahbo_m_ext(2), |
|
427 | 427 | coarse_time => coarse_time, |
|
428 | 428 | fine_time => fine_time, |
|
429 | 429 | data_shaping_BW => bias_fail_sw_sig); |
|
430 | 430 | |
|
431 | 431 | top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2 |
|
432 | 432 | GENERIC MAP( |
|
433 | 433 | ChannelCount => 8, |
|
434 | 434 | SampleNbBits => 14, |
|
435 | 435 | ncycle_cnv_high => 80, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 = 63 |
|
436 | 436 | ncycle_cnv => 500) -- 49 152 000 / 98304 |
|
437 | 437 | PORT MAP ( |
|
438 | 438 | -- CONV |
|
439 | 439 | cnv_clk => clk_49, |
|
440 | 440 | cnv_rstn => reset, |
|
441 | 441 | cnv => ADC_nCS_sig, |
|
442 | 442 | -- DATA |
|
443 | 443 | clk => clk_25, |
|
444 | 444 | rstn => reset, |
|
445 | 445 | sck => ADC_CLK_sig, |
|
446 | 446 | sdo => ADC_SDO_sig, |
|
447 | 447 | -- SAMPLE |
|
448 | 448 | sample => sample, |
|
449 | 449 | sample_val => sample_val); |
|
450 | 450 | |
|
451 | 451 | IO10 <= ADC_SDO_sig(5); |
|
452 | 452 | IO9 <= ADC_SDO_sig(4); |
|
453 | 453 | IO8 <= ADC_SDO_sig(3); |
|
454 | 454 | |
|
455 | 455 | ADC_nCS <= ADC_nCS_sig; |
|
456 | 456 | ADC_CLK <= ADC_CLK_sig; |
|
457 | 457 | ADC_SDO_sig <= ADC_SDO; |
|
458 | 458 | |
|
459 | 459 | ---------------------------------------------------------------------- |
|
460 | 460 | --- GPIO ----------------------------------------------------------- |
|
461 | 461 | ---------------------------------------------------------------------- |
|
462 | 462 | |
|
463 | 463 | grgpio0 : grgpio |
|
464 | 464 | GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8) |
|
465 | 465 | PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo); |
|
466 | 466 | |
|
467 | 467 | pio_pad_0 : iopad |
|
468 | 468 | GENERIC MAP (tech => CFG_PADTECH) |
|
469 | 469 | PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0)); |
|
470 | 470 | pio_pad_1 : iopad |
|
471 | 471 | GENERIC MAP (tech => CFG_PADTECH) |
|
472 | 472 | PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1)); |
|
473 | 473 | pio_pad_2 : iopad |
|
474 | 474 | GENERIC MAP (tech => CFG_PADTECH) |
|
475 | 475 | PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2)); |
|
476 | 476 | pio_pad_3 : iopad |
|
477 | 477 | GENERIC MAP (tech => CFG_PADTECH) |
|
478 | 478 | PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3)); |
|
479 | 479 | pio_pad_4 : iopad |
|
480 | 480 | GENERIC MAP (tech => CFG_PADTECH) |
|
481 | 481 | PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4)); |
|
482 | 482 | pio_pad_5 : iopad |
|
483 | 483 | GENERIC MAP (tech => CFG_PADTECH) |
|
484 | 484 | PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5)); |
|
485 | 485 | pio_pad_6 : iopad |
|
486 | 486 | GENERIC MAP (tech => CFG_PADTECH) |
|
487 | 487 | PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6)); |
|
488 | 488 | pio_pad_7 : iopad |
|
489 | 489 | GENERIC MAP (tech => CFG_PADTECH) |
|
490 | 490 | PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7)); |
|
491 | 491 | |
|
492 | 492 | END beh; |
@@ -1,136 +1,133 | |||
|
1 | 1 | |
|
2 | 2 | LIBRARY IEEE; |
|
3 | 3 | USE IEEE.STD_LOGIC_1164.ALL; |
|
4 | 4 | USE IEEE.NUMERIC_STD.ALL; |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.general_purpose.SYNC_FF; |
|
8 | 8 | |
|
9 | 9 | ENTITY top_ad_conv_ADS7886_v2 IS |
|
10 | 10 | GENERIC( |
|
11 |
ChannelCount |
|
|
12 |
|
|
|
13 |
ncycle_cnv_high : INTEGER := 40; |
|
|
11 | ChannelCount : INTEGER := 8; | |
|
12 | SampleNbBits : INTEGER := 14; | |
|
13 | ncycle_cnv_high : INTEGER := 40; -- at least 32 cycles | |
|
14 | 14 | ncycle_cnv : INTEGER := 500); |
|
15 | 15 | PORT ( |
|
16 |
|
|
|
17 |
cnv_clk |
|
|
18 |
cnv_rstn |
|
|
19 |
cnv |
|
|
20 |
|
|
|
21 |
clk |
|
|
22 |
rstn |
|
|
23 |
|
|
|
24 |
|
|
|
25 |
|
|
|
16 | -- CONV | |
|
17 | cnv_clk : IN STD_LOGIC; | |
|
18 | cnv_rstn : IN STD_LOGIC; | |
|
19 | cnv : OUT STD_LOGIC; | |
|
20 | -- DATA | |
|
21 | clk : IN STD_LOGIC; | |
|
22 | rstn : IN STD_LOGIC; | |
|
23 | sck : OUT STD_LOGIC; | |
|
24 | sdo : IN STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0); | |
|
25 | -- SAMPLE | |
|
26 | 26 | sample : OUT Samples14v(ChannelCount-1 DOWNTO 0); |
|
27 | 27 | sample_val : OUT STD_LOGIC |
|
28 | 28 | ); |
|
29 | 29 | END top_ad_conv_ADS7886_v2; |
|
30 | 30 | |
|
31 | 31 | ARCHITECTURE ar_top_ad_conv_ADS7886_v2 OF top_ad_conv_ADS7886_v2 IS |
|
32 | 32 | |
|
33 | 33 | SIGNAL cnv_cycle_counter : INTEGER; |
|
34 | 34 | SIGNAL cnv_s : STD_LOGIC; |
|
35 | 35 | SIGNAL cnv_sync : STD_LOGIC; |
|
36 |
SIGNAL cnv_sync_not |
|
|
37 | ||
|
38 |
SIGNAL sample_adc |
|
|
39 |
SIGNAL sample_val_adc |
|
|
36 | SIGNAL cnv_sync_not : STD_LOGIC; | |
|
37 | ||
|
38 | SIGNAL sample_adc : Samples(ChannelCount-1 DOWNTO 0); | |
|
39 | SIGNAL sample_val_adc : STD_LOGIC; | |
|
40 | 40 | |
|
41 | 41 | BEGIN |
|
42 | 42 | |
|
43 | 43 | |
|
44 | 44 | ----------------------------------------------------------------------------- |
|
45 | 45 | -- CONV |
|
46 | 46 | ----------------------------------------------------------------------------- |
|
47 | 47 | PROCESS (cnv_clk, cnv_rstn) |
|
48 | 48 | BEGIN -- PROCESS |
|
49 | 49 | IF cnv_rstn = '0' THEN -- asynchronous reset (active low) |
|
50 | 50 | cnv_cycle_counter <= 0; |
|
51 | 51 | cnv_s <= '0'; |
|
52 | 52 | ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge |
|
53 | 53 | -- IF cnv_run = '1' THEN |
|
54 | 54 | IF cnv_cycle_counter < ncycle_cnv THEN |
|
55 | 55 | cnv_cycle_counter <= cnv_cycle_counter +1; |
|
56 | 56 | IF cnv_cycle_counter < ncycle_cnv_high THEN |
|
57 | 57 | cnv_s <= '1'; |
|
58 | 58 | ELSE |
|
59 | 59 | cnv_s <= '0'; |
|
60 | 60 | END IF; |
|
61 | 61 | ELSE |
|
62 | 62 | cnv_s <= '1'; |
|
63 | 63 | cnv_cycle_counter <= 0; |
|
64 | 64 | END IF; |
|
65 | 65 | --ELSE |
|
66 | 66 | -- cnv_s <= '0'; |
|
67 | 67 | -- cnv_cycle_counter <= 0; |
|
68 | 68 | --END IF; |
|
69 | 69 | END IF; |
|
70 | 70 | END PROCESS; |
|
71 | 71 | |
|
72 |
cnv |
|
|
72 | cnv <= NOT(cnv_s); | |
|
73 | 73 | |
|
74 | 74 | ----------------------------------------------------------------------------- |
|
75 | 75 | -- SYNC CNV |
|
76 | 76 | ----------------------------------------------------------------------------- |
|
77 | ||
|
77 | ||
|
78 | 78 | SYNC_FF_cnv : SYNC_FF |
|
79 | 79 | GENERIC MAP ( |
|
80 | 80 | NB_FF_OF_SYNC => 2) |
|
81 | 81 | PORT MAP ( |
|
82 | 82 | clk => clk, |
|
83 | 83 | rstn => rstn, |
|
84 |
A => cnv_s, |
|
|
84 | A => cnv_s, -- the data fetching begins immediately | |
|
85 | 85 | A_sync => cnv_sync); |
|
86 | 86 | |
|
87 | 87 | ----------------------------------------------------------------------------- |
|
88 | 88 | |
|
89 |
cnv_sync_not |
|
|
89 | cnv_sync_not <= NOT(cnv_sync); | |
|
90 | 90 | |
|
91 |
|
|
|
92 |
|
|
|
93 |
|
|
|
94 |
|
|
|
95 |
|
|
|
96 |
|
|
|
97 |
|
|
|
98 |
|
|
|
99 |
|
|
|
100 |
|
|
|
101 | rstn => rstn, | |
|
102 | sck => sck, | |
|
103 | sdo => sdo, | |
|
104 |
|
|
|
105 |
|
|
|
106 |
|
|
|
91 | ADS7886_drvr_v2_1 : ADS7886_drvr_v2 | |
|
92 | GENERIC MAP( | |
|
93 | ChannelCount => 8, | |
|
94 | NbBitsSamples => 16) | |
|
95 | PORT MAP( | |
|
96 | -- CONV -- | |
|
97 | cnv_clk => cnv_sync_not, | |
|
98 | cnv_rstn => rstn, | |
|
99 | -- DATA -- | |
|
100 | clk => clk, -- master clock, 25 MHz | |
|
101 | rstn => rstn, | |
|
102 | sck => sck, | |
|
103 | sdo => sdo, | |
|
104 | -- SAMPLE -- | |
|
105 | sample => sample_adc, | |
|
106 | sample_val => sample_val_adc); | |
|
107 | 107 | |
|
108 | PROCESS (clk, rstn) | |
|
108 | PROCESS (clk, rstn) | |
|
109 | 109 | BEGIN -- PROCESS |
|
110 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
111 |
|
|
|
112 |
|
|
|
113 |
|
|
|
114 |
|
|
|
110 | IF rstn = '0' THEN -- asynchronous reset (active low) | |
|
111 | FOR k IN 0 TO ChannelCount-1 LOOP | |
|
112 | sample(k)(13 DOWNTO 0) <= (OTHERS => '0'); | |
|
113 | END LOOP; | |
|
114 | sample_val <= '0'; | |
|
115 | 115 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
116 |
|
|
|
117 |
|
|
|
118 |
|
|
|
119 |
|
|
|
120 |
|
|
|
121 |
|
|
|
122 |
|
|
|
123 |
|
|
|
124 |
|
|
|
125 |
|
|
|
126 | -- FOR k IN 0 TO ChannelCount-1 LOOP | |
|
127 | -- sample(k) <= sample_adc(k)(13 downto 0); | |
|
128 | -- END LOOP; | |
|
129 | sample_val <= sample_val_adc; | |
|
130 | ELSE | |
|
131 | sample_val <= '0'; | |
|
132 | END IF; | |
|
116 | IF sample_val_adc = '1' THEN | |
|
117 | FOR k IN 0 TO ChannelCount-1 LOOP | |
|
118 | IF (UNSIGNED(sample_adc(k)(11 DOWNTO 0)) >= 2048) THEN | |
|
119 | sample(k)(13 DOWNTO 0) <= "00" & | |
|
120 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
|
121 | ELSE | |
|
122 | sample(k)(13 DOWNTO 0) <= "11" & | |
|
123 | STD_LOGIC_VECTOR(UNSIGNED(sample_adc(k)(11 DOWNTO 0)) - 2048); | |
|
124 | END IF; | |
|
125 | END LOOP; | |
|
126 | sample_val <= sample_val_adc; | |
|
127 | ELSE | |
|
128 | sample_val <= '0'; | |
|
129 | END IF; | |
|
133 | 130 | END IF; |
|
134 | END PROCESS; | |
|
131 | END PROCESS; | |
|
135 | 132 | |
|
136 | END ar_top_ad_conv_ADS7886_v2; No newline at end of file | |
|
133 | END ar_top_ad_conv_ADS7886_v2; |
@@ -1,708 +1,714 | |||
|
1 | 1 | LIBRARY ieee; |
|
2 | 2 | USE ieee.std_logic_1164.ALL; |
|
3 | 3 | USE ieee.numeric_std.ALL; |
|
4 | 4 | |
|
5 | 5 | LIBRARY lpp; |
|
6 | 6 | USE lpp.lpp_ad_conv.ALL; |
|
7 | 7 | USE lpp.iir_filter.ALL; |
|
8 | 8 | USE lpp.FILTERcfg.ALL; |
|
9 | 9 | USE lpp.lpp_memory.ALL; |
|
10 | 10 | USE lpp.lpp_waveform_pkg.ALL; |
|
11 | 11 | USE lpp.lpp_dma_pkg.ALL; |
|
12 | 12 | USE lpp.lpp_top_lfr_pkg.ALL; |
|
13 | 13 | USE lpp.lpp_lfr_pkg.ALL; |
|
14 | 14 | USE lpp.general_purpose.ALL; |
|
15 | 15 | |
|
16 | 16 | LIBRARY techmap; |
|
17 | 17 | USE techmap.gencomp.ALL; |
|
18 | 18 | |
|
19 | 19 | LIBRARY grlib; |
|
20 | 20 | USE grlib.amba.ALL; |
|
21 | 21 | USE grlib.stdlib.ALL; |
|
22 | 22 | USE grlib.devices.ALL; |
|
23 | 23 | USE GRLIB.DMA2AHB_Package.ALL; |
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24 | 24 | |
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25 | 25 | ENTITY lpp_lfr IS |
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26 | 26 | GENERIC ( |
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27 | 27 | Mem_use : INTEGER := use_RAM; |
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28 | 28 | nb_data_by_buffer_size : INTEGER := 11; |
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29 | 29 | nb_word_by_buffer_size : INTEGER := 11; |
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30 | 30 | nb_snapshot_param_size : INTEGER := 11; |
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31 | 31 | delta_vector_size : INTEGER := 20; |
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32 | 32 | delta_vector_size_f0_2 : INTEGER := 7; |
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33 | 33 | |
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34 | 34 | pindex : INTEGER := 4; |
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35 | 35 | paddr : INTEGER := 4; |
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36 | 36 | pmask : INTEGER := 16#fff#; |
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37 | 37 | pirq_ms : INTEGER := 0; |
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38 | 38 | pirq_wfp : INTEGER := 1; |
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39 | 39 | |
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40 | 40 | hindex : INTEGER := 2; |
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41 | 41 | |
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42 | 42 | top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0') |
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43 | 43 | |
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44 | 44 | ); |
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45 | 45 | PORT ( |
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46 | 46 | clk : IN STD_LOGIC; |
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47 | 47 | rstn : IN STD_LOGIC; |
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48 | 48 | -- SAMPLE |
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49 | 49 | sample_B : IN Samples14v(2 DOWNTO 0); |
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50 | 50 | sample_E : IN Samples14v(4 DOWNTO 0); |
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51 | 51 | sample_val : IN STD_LOGIC; |
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52 | 52 | -- APB |
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53 | 53 | apbi : IN apb_slv_in_type; |
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54 | 54 | apbo : OUT apb_slv_out_type; |
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55 | 55 | -- AHB |
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56 | 56 | ahbi : IN AHB_Mst_In_Type; |
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57 | 57 | ahbo : OUT AHB_Mst_Out_Type; |
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58 | 58 | -- TIME |
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59 | 59 | coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo |
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60 | 60 | fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo |
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61 | 61 | -- |
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62 | 62 | data_shaping_BW : OUT STD_LOGIC; |
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63 | 63 | |
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64 | 64 | --debug |
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65 | 65 | debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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66 | 66 | debug_f0_data_valid : OUT STD_LOGIC; |
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67 | 67 | debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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68 | 68 | debug_f1_data_valid : OUT STD_LOGIC; |
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69 | 69 | debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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70 | 70 | debug_f2_data_valid : OUT STD_LOGIC; |
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71 | 71 | debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); |
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72 | 72 | debug_f3_data_valid : OUT STD_LOGIC; |
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73 | 73 | |
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74 | 74 | -- debug FIFO_IN |
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75 | 75 | debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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76 | 76 | debug_f0_data_fifo_in_valid : OUT STD_LOGIC; |
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77 | 77 | debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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78 | 78 | debug_f1_data_fifo_in_valid : OUT STD_LOGIC; |
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79 | 79 | debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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80 | 80 | debug_f2_data_fifo_in_valid : OUT STD_LOGIC; |
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81 | 81 | debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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82 | 82 | debug_f3_data_fifo_in_valid : OUT STD_LOGIC; |
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83 | 83 | |
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84 | 84 | --debug FIFO OUT |
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85 | 85 | debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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86 | 86 | debug_f0_data_fifo_out_valid : OUT STD_LOGIC; |
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87 | 87 | debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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88 | 88 | debug_f1_data_fifo_out_valid : OUT STD_LOGIC; |
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89 | 89 | debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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90 | 90 | debug_f2_data_fifo_out_valid : OUT STD_LOGIC; |
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91 | 91 | debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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92 | 92 | debug_f3_data_fifo_out_valid : OUT STD_LOGIC; |
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93 | ||
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93 | ||
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94 | 94 | --debug DMA IN |
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95 | 95 | debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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96 | 96 | debug_f0_data_dma_in_valid : OUT STD_LOGIC; |
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97 | 97 | debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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98 | 98 | debug_f1_data_dma_in_valid : OUT STD_LOGIC; |
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99 | 99 | debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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100 | 100 | debug_f2_data_dma_in_valid : OUT STD_LOGIC; |
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101 | 101 | debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); |
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102 | 102 | debug_f3_data_dma_in_valid : OUT STD_LOGIC |
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103 | 103 | ); |
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104 | 104 | END lpp_lfr; |
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105 | 105 | |
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106 | 106 | ARCHITECTURE beh OF lpp_lfr IS |
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107 | 107 | SIGNAL sample : Samples14v(7 DOWNTO 0); |
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108 | 108 | SIGNAL sample_s : Samples(7 DOWNTO 0); |
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109 | 109 | -- |
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110 | 110 | SIGNAL data_shaping_SP0 : STD_LOGIC; |
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111 | 111 | SIGNAL data_shaping_SP1 : STD_LOGIC; |
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112 | 112 | SIGNAL data_shaping_R0 : STD_LOGIC; |
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113 | 113 | SIGNAL data_shaping_R1 : STD_LOGIC; |
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114 | 114 | -- |
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115 | 115 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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116 | 116 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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117 | 117 | SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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118 | 118 | -- |
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119 | 119 | SIGNAL sample_f0_val : STD_LOGIC; |
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120 | 120 | SIGNAL sample_f1_val : STD_LOGIC; |
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121 | 121 | SIGNAL sample_f2_val : STD_LOGIC; |
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122 | 122 | SIGNAL sample_f3_val : STD_LOGIC; |
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123 | 123 | -- |
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124 | 124 | SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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125 | 125 | SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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126 | 126 | SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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127 | 127 | SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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128 | 128 | -- |
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129 | 129 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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130 | 130 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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131 | 131 | SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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132 | 132 | |
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133 | 133 | -- SM |
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134 | 134 | SIGNAL ready_matrix_f0_0 : STD_LOGIC; |
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135 | 135 | SIGNAL ready_matrix_f0_1 : STD_LOGIC; |
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136 | 136 | SIGNAL ready_matrix_f1 : STD_LOGIC; |
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137 | 137 | SIGNAL ready_matrix_f2 : STD_LOGIC; |
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138 | 138 | SIGNAL error_anticipating_empty_fifo : STD_LOGIC; |
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139 | 139 | SIGNAL error_bad_component_error : STD_LOGIC; |
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140 | 140 | SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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141 | 141 | SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; |
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142 | 142 | SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; |
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143 | 143 | SIGNAL status_ready_matrix_f1 : STD_LOGIC; |
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144 | 144 | SIGNAL status_ready_matrix_f2 : STD_LOGIC; |
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145 | 145 | SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; |
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146 | 146 | SIGNAL status_error_bad_component_error : STD_LOGIC; |
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147 | 147 | SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; |
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148 | 148 | SIGNAL config_active_interruption_onError : STD_LOGIC; |
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149 | 149 | SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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150 | 150 | SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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151 | 151 | SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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152 | 152 | SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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153 | 153 | |
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154 | 154 | -- WFP |
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155 | 155 | SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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156 | 156 | SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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157 | 157 | SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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158 | 158 | SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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159 | 159 | SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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160 | 160 | SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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161 | 161 | SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
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162 | 162 | SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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163 | 163 | SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
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164 | 164 | |
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165 | 165 | SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
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166 | 166 | SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
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167 | 167 | SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
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168 | 168 | SIGNAL enable_f0 : STD_LOGIC; |
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169 | 169 | SIGNAL enable_f1 : STD_LOGIC; |
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170 | 170 | SIGNAL enable_f2 : STD_LOGIC; |
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171 | 171 | SIGNAL enable_f3 : STD_LOGIC; |
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172 | 172 | SIGNAL burst_f0 : STD_LOGIC; |
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173 | 173 | SIGNAL burst_f1 : STD_LOGIC; |
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174 | 174 | SIGNAL burst_f2 : STD_LOGIC; |
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175 | 175 | SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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176 | 176 | SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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177 | 177 | SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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178 | 178 | SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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179 | 179 | |
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180 | 180 | SIGNAL run : STD_LOGIC; |
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181 | 181 | SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
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182 | 182 | |
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183 | 183 | SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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184 | 184 | SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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185 | 185 | SIGNAL data_f0_data_out_valid : STD_LOGIC; |
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186 | 186 | SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; |
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187 | 187 | SIGNAL data_f0_data_out_ren : STD_LOGIC; |
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188 | 188 | --f1 |
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189 | 189 | SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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190 | 190 | SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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191 | 191 | SIGNAL data_f1_data_out_valid : STD_LOGIC; |
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192 | 192 | SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; |
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193 | 193 | SIGNAL data_f1_data_out_ren : STD_LOGIC; |
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194 | 194 | --f2 |
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195 | 195 | SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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196 | 196 | SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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197 | 197 | SIGNAL data_f2_data_out_valid : STD_LOGIC; |
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198 | 198 | SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; |
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199 | 199 | SIGNAL data_f2_data_out_ren : STD_LOGIC; |
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200 | 200 | --f3 |
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201 | 201 | SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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202 | 202 | SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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203 | 203 | SIGNAL data_f3_data_out_valid : STD_LOGIC; |
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204 | 204 | SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; |
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205 | 205 | SIGNAL data_f3_data_out_ren : STD_LOGIC; |
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206 | 206 | |
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207 | 207 | ----------------------------------------------------------------------------- |
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208 | 208 | -- |
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209 | 209 | ----------------------------------------------------------------------------- |
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210 | 210 | SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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211 | 211 | SIGNAL data_f0_data_out_valid_s : STD_LOGIC; |
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212 | 212 | SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC; |
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213 | 213 | --f1 |
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214 | 214 | SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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215 | 215 | SIGNAL data_f1_data_out_valid_s : STD_LOGIC; |
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216 | 216 | SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC; |
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217 | 217 | --f2 |
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218 | 218 | SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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219 | 219 | SIGNAL data_f2_data_out_valid_s : STD_LOGIC; |
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220 | 220 | SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC; |
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221 | 221 | --f3 |
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222 | 222 | SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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223 | 223 | SIGNAL data_f3_data_out_valid_s : STD_LOGIC; |
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224 | 224 | SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC; |
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225 | 225 | |
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226 | 226 | ----------------------------------------------------------------------------- |
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227 | 227 | -- DMA RR |
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228 | 228 | ----------------------------------------------------------------------------- |
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229 | 229 | SIGNAL dma_sel_valid : STD_LOGIC; |
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230 | 230 | SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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231 | 231 | SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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232 | 232 | SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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233 | 233 | |
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234 | 234 | ----------------------------------------------------------------------------- |
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235 | 235 | -- DMA_REG |
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236 | 236 | ----------------------------------------------------------------------------- |
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237 | 237 | SIGNAL ongoing_reg : STD_LOGIC; |
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238 | 238 | SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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239 | 239 | SIGNAL dma_send_reg : STD_LOGIC; |
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240 | 240 | SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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241 | 241 | SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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242 | 242 | SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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243 | 243 | |
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244 | 244 | |
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245 | 245 | ----------------------------------------------------------------------------- |
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246 | 246 | -- DMA |
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247 | 247 | ----------------------------------------------------------------------------- |
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248 | 248 | SIGNAL dma_send : STD_LOGIC; |
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249 | 249 | SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE) |
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250 | 250 | SIGNAL dma_done : STD_LOGIC; |
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251 | 251 | SIGNAL dma_ren : STD_LOGIC; |
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252 | 252 | SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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253 | 253 | SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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254 | 254 | SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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255 | 255 | |
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256 | 256 | ----------------------------------------------------------------------------- |
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257 | 257 | -- DEBUG |
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258 | 258 | ----------------------------------------------------------------------------- |
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259 | 259 | -- |
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260 | 260 | SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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261 | 261 | SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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262 | 262 | SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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263 | 263 | SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); |
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264 | 264 | |
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265 | 265 | SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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266 | 266 | SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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267 | 267 | SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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268 | 268 | SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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269 | 269 | SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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270 | 270 | SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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271 | 271 | SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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272 | 272 | SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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273 | 273 | |
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274 | 274 | BEGIN |
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275 | 275 | |
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276 | 276 | sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0); |
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277 | 277 | sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0); |
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278 | 278 | |
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279 | 279 | all_channel : FOR i IN 7 DOWNTO 0 GENERATE |
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280 | 280 | sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i); |
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281 | 281 | END GENERATE all_channel; |
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282 | 282 | |
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283 | 283 | ----------------------------------------------------------------------------- |
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284 | 284 | lpp_lfr_filter_1 : lpp_lfr_filter |
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285 | 285 | GENERIC MAP ( |
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286 | 286 | Mem_use => Mem_use) |
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287 | 287 | PORT MAP ( |
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288 | 288 | sample => sample_s, |
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289 | 289 | sample_val => sample_val, |
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290 | 290 | clk => clk, |
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291 | 291 | rstn => rstn, |
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292 | 292 | data_shaping_SP0 => data_shaping_SP0, |
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293 | 293 | data_shaping_SP1 => data_shaping_SP1, |
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294 | 294 | data_shaping_R0 => data_shaping_R0, |
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295 | 295 | data_shaping_R1 => data_shaping_R1, |
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296 | 296 | sample_f0_val => sample_f0_val, |
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297 | 297 | sample_f1_val => sample_f1_val, |
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298 | 298 | sample_f2_val => sample_f2_val, |
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299 | 299 | sample_f3_val => sample_f3_val, |
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300 | 300 | sample_f0_wdata => sample_f0_data, |
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301 | 301 | sample_f1_wdata => sample_f1_data, |
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302 | 302 | sample_f2_wdata => sample_f2_data, |
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303 | 303 | sample_f3_wdata => sample_f3_data); |
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304 | 304 | |
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305 | 305 | ----------------------------------------------------------------------------- |
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306 | 306 | lpp_lfr_apbreg_1 : lpp_lfr_apbreg |
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307 | 307 | GENERIC MAP ( |
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308 | 308 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
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309 | 309 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
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310 | 310 | nb_snapshot_param_size => nb_snapshot_param_size, |
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311 | 311 | delta_vector_size => delta_vector_size, |
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312 | 312 | delta_vector_size_f0_2 => delta_vector_size_f0_2, |
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313 | 313 | pindex => pindex, |
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314 | 314 | paddr => paddr, |
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315 | 315 | pmask => pmask, |
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316 | 316 | pirq_ms => pirq_ms, |
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317 | 317 | pirq_wfp => pirq_wfp, |
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318 | 318 | top_lfr_version => top_lfr_version) |
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319 | 319 | PORT MAP ( |
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320 | 320 | HCLK => clk, |
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321 | 321 | HRESETn => rstn, |
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322 | 322 | apbi => apbi, |
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323 | 323 | apbo => apbo, |
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324 | 324 | ready_matrix_f0_0 => ready_matrix_f0_0, |
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325 | 325 | ready_matrix_f0_1 => ready_matrix_f0_1, |
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326 | 326 | ready_matrix_f1 => ready_matrix_f1, |
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327 | 327 | ready_matrix_f2 => ready_matrix_f2, |
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328 | 328 | error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
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329 | 329 | error_bad_component_error => error_bad_component_error, |
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330 | 330 | debug_reg => debug_reg, |
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331 | 331 | status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
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332 | 332 | status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
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333 | 333 | status_ready_matrix_f1 => status_ready_matrix_f1, |
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334 | 334 | status_ready_matrix_f2 => status_ready_matrix_f2, |
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335 | 335 | status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
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336 | 336 | status_error_bad_component_error => status_error_bad_component_error, |
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337 | 337 | config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
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338 | 338 | config_active_interruption_onError => config_active_interruption_onError, |
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339 | 339 | addr_matrix_f0_0 => addr_matrix_f0_0, |
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340 | 340 | addr_matrix_f0_1 => addr_matrix_f0_1, |
|
341 | 341 | addr_matrix_f1 => addr_matrix_f1, |
|
342 | 342 | addr_matrix_f2 => addr_matrix_f2, |
|
343 | 343 | status_full => status_full, |
|
344 | 344 | status_full_ack => status_full_ack, |
|
345 | 345 | status_full_err => status_full_err, |
|
346 | 346 | status_new_err => status_new_err, |
|
347 | 347 | data_shaping_BW => data_shaping_BW, |
|
348 | 348 | data_shaping_SP0 => data_shaping_SP0, |
|
349 | 349 | data_shaping_SP1 => data_shaping_SP1, |
|
350 | 350 | data_shaping_R0 => data_shaping_R0, |
|
351 | 351 | data_shaping_R1 => data_shaping_R1, |
|
352 | 352 | delta_snapshot => delta_snapshot, |
|
353 | 353 | delta_f0 => delta_f0, |
|
354 | 354 | delta_f0_2 => delta_f0_2, |
|
355 | 355 | delta_f1 => delta_f1, |
|
356 | 356 | delta_f2 => delta_f2, |
|
357 | 357 | nb_data_by_buffer => nb_data_by_buffer, |
|
358 | 358 | nb_word_by_buffer => nb_word_by_buffer, |
|
359 | 359 | nb_snapshot_param => nb_snapshot_param, |
|
360 | 360 | enable_f0 => enable_f0, |
|
361 | 361 | enable_f1 => enable_f1, |
|
362 | 362 | enable_f2 => enable_f2, |
|
363 | 363 | enable_f3 => enable_f3, |
|
364 | 364 | burst_f0 => burst_f0, |
|
365 | 365 | burst_f1 => burst_f1, |
|
366 | 366 | burst_f2 => burst_f2, |
|
367 | 367 | run => run, |
|
368 | 368 | addr_data_f0 => addr_data_f0, |
|
369 | 369 | addr_data_f1 => addr_data_f1, |
|
370 | 370 | addr_data_f2 => addr_data_f2, |
|
371 | 371 | addr_data_f3 => addr_data_f3, |
|
372 | 372 | start_date => start_date, |
|
373 | 373 | --------------------------------------------------------------------------- |
|
374 | 374 | debug_reg0 => debug_reg0, |
|
375 | 375 | debug_reg1 => debug_reg1, |
|
376 | 376 | debug_reg2 => debug_reg2, |
|
377 | 377 | debug_reg3 => debug_reg3, |
|
378 | 378 | debug_reg4 => debug_reg4, |
|
379 | 379 | debug_reg5 => debug_reg5, |
|
380 | 380 | debug_reg6 => debug_reg6, |
|
381 | 381 | debug_reg7 => debug_reg7); |
|
382 | 382 | |
|
383 | 383 | debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0); |
|
384 | 384 | debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1); |
|
385 | 385 | debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2); |
|
386 | 386 | ----------------------------------------------------------------------------- |
|
387 | 387 | --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug |
|
388 | 388 | --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug |
|
389 | 389 | --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug |
|
390 | 390 | --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug |
|
391 | 391 | |
|
392 | 392 | |
|
393 | 393 | ----------------------------------------------------------------------------- |
|
394 | 394 | lpp_waveform_1 : lpp_waveform |
|
395 | 395 | GENERIC MAP ( |
|
396 | 396 | tech => inferred, |
|
397 | 397 | data_size => 6*16, |
|
398 | 398 | nb_data_by_buffer_size => nb_data_by_buffer_size, |
|
399 | 399 | nb_word_by_buffer_size => nb_word_by_buffer_size, |
|
400 | 400 | nb_snapshot_param_size => nb_snapshot_param_size, |
|
401 | 401 | delta_vector_size => delta_vector_size, |
|
402 | 402 | delta_vector_size_f0_2 => delta_vector_size_f0_2 |
|
403 | 403 | ) |
|
404 | 404 | PORT MAP ( |
|
405 | 405 | clk => clk, |
|
406 | 406 | rstn => rstn, |
|
407 | 407 | |
|
408 | 408 | reg_run => run, |
|
409 | 409 | reg_start_date => start_date, |
|
410 | 410 | reg_delta_snapshot => delta_snapshot, |
|
411 | 411 | reg_delta_f0 => delta_f0, |
|
412 | 412 | reg_delta_f0_2 => delta_f0_2, |
|
413 | 413 | reg_delta_f1 => delta_f1, |
|
414 | 414 | reg_delta_f2 => delta_f2, |
|
415 | 415 | |
|
416 | 416 | enable_f0 => enable_f0, |
|
417 | 417 | enable_f1 => enable_f1, |
|
418 | 418 | enable_f2 => enable_f2, |
|
419 | 419 | enable_f3 => enable_f3, |
|
420 | 420 | burst_f0 => burst_f0, |
|
421 | 421 | burst_f1 => burst_f1, |
|
422 | 422 | burst_f2 => burst_f2, |
|
423 | 423 | |
|
424 | 424 | nb_data_by_buffer => nb_data_by_buffer, |
|
425 | 425 | nb_word_by_buffer => nb_word_by_buffer, |
|
426 | 426 | nb_snapshot_param => nb_snapshot_param, |
|
427 | 427 | status_full => status_full, |
|
428 | 428 | status_full_ack => status_full_ack, |
|
429 | 429 | status_full_err => status_full_err, |
|
430 | 430 | status_new_err => status_new_err, |
|
431 | 431 | |
|
432 | 432 | coarse_time => coarse_time, |
|
433 | 433 | fine_time => fine_time, |
|
434 | 434 | |
|
435 | 435 | --f0 |
|
436 | 436 | addr_data_f0 => addr_data_f0, |
|
437 | 437 | data_f0_in_valid => sample_f0_val, |
|
438 | 438 | data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug |
|
439 | 439 | --f1 |
|
440 | 440 | addr_data_f1 => addr_data_f1, |
|
441 | 441 | data_f1_in_valid => sample_f1_val, |
|
442 | 442 | data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug, |
|
443 | 443 | --f2 |
|
444 | 444 | addr_data_f2 => addr_data_f2, |
|
445 | 445 | data_f2_in_valid => sample_f2_val, |
|
446 | 446 | data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug, |
|
447 | 447 | --f3 |
|
448 | 448 | addr_data_f3 => addr_data_f3, |
|
449 | 449 | data_f3_in_valid => sample_f3_val, |
|
450 | 450 | data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug, |
|
451 | 451 | -- OUTPUT -- DMA interface |
|
452 | 452 | --f0 |
|
453 | 453 | data_f0_addr_out => data_f0_addr_out_s, |
|
454 | 454 | data_f0_data_out => data_f0_data_out, |
|
455 | 455 | data_f0_data_out_valid => data_f0_data_out_valid_s, |
|
456 | 456 | data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s, |
|
457 | 457 | data_f0_data_out_ren => data_f0_data_out_ren, |
|
458 | 458 | --f1 |
|
459 | 459 | data_f1_addr_out => data_f1_addr_out_s, |
|
460 | 460 | data_f1_data_out => data_f1_data_out, |
|
461 | 461 | data_f1_data_out_valid => data_f1_data_out_valid_s, |
|
462 | 462 | data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s, |
|
463 | 463 | data_f1_data_out_ren => data_f1_data_out_ren, |
|
464 | 464 | --f2 |
|
465 | 465 | data_f2_addr_out => data_f2_addr_out_s, |
|
466 | 466 | data_f2_data_out => data_f2_data_out, |
|
467 | 467 | data_f2_data_out_valid => data_f2_data_out_valid_s, |
|
468 | 468 | data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s, |
|
469 | 469 | data_f2_data_out_ren => data_f2_data_out_ren, |
|
470 | 470 | --f3 |
|
471 | 471 | data_f3_addr_out => data_f3_addr_out_s, |
|
472 | 472 | data_f3_data_out => data_f3_data_out, |
|
473 | 473 | data_f3_data_out_valid => data_f3_data_out_valid_s, |
|
474 | 474 | data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s, |
|
475 | 475 | data_f3_data_out_ren => data_f3_data_out_ren, |
|
476 | 476 | |
|
477 | 477 | -- debug SNAPSHOT_OUT |
|
478 | 478 | debug_f0_data => debug_f0_data, |
|
479 | 479 | debug_f0_data_valid => debug_f0_data_valid , |
|
480 | 480 | debug_f1_data => debug_f1_data , |
|
481 | 481 | debug_f1_data_valid => debug_f1_data_valid, |
|
482 | 482 | debug_f2_data => debug_f2_data , |
|
483 | 483 | debug_f2_data_valid => debug_f2_data_valid , |
|
484 | 484 | debug_f3_data => debug_f3_data , |
|
485 | 485 | debug_f3_data_valid => debug_f3_data_valid, |
|
486 | 486 | |
|
487 | 487 | -- debug FIFO_IN |
|
488 | 488 | debug_f0_data_fifo_in => debug_f0_data_fifo_in , |
|
489 | 489 | debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid, |
|
490 | 490 | debug_f1_data_fifo_in => debug_f1_data_fifo_in , |
|
491 | 491 | debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid, |
|
492 | 492 | debug_f2_data_fifo_in => debug_f2_data_fifo_in , |
|
493 | 493 | debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid, |
|
494 | 494 | debug_f3_data_fifo_in => debug_f3_data_fifo_in , |
|
495 | 495 | debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid |
|
496 | 496 | |
|
497 | 497 | ); |
|
498 | 498 | |
|
499 | 499 | |
|
500 | 500 | ----------------------------------------------------------------------------- |
|
501 | 501 | -- DEBUG -- WFP OUT |
|
502 | 502 | debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren; |
|
503 | 503 | debug_f0_data_fifo_out <= data_f0_data_out; |
|
504 | 504 | debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren; |
|
505 | 505 | debug_f1_data_fifo_out <= data_f1_data_out; |
|
506 | 506 | debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren; |
|
507 | 507 | debug_f2_data_fifo_out <= data_f2_data_out; |
|
508 | 508 | debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren; |
|
509 | 509 | debug_f3_data_fifo_out <= data_f3_data_out; |
|
510 | 510 | ----------------------------------------------------------------------------- |
|
511 | 511 | |
|
512 | 512 | |
|
513 | 513 | ----------------------------------------------------------------------------- |
|
514 | 514 | -- TEMP |
|
515 | 515 | ----------------------------------------------------------------------------- |
|
516 | 516 | |
|
517 | 517 | PROCESS (clk, rstn) |
|
518 | 518 | BEGIN -- PROCESS |
|
519 | 519 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
520 | 520 | data_f0_data_out_valid <= '0'; |
|
521 | 521 | data_f0_data_out_valid_burst <= '0'; |
|
522 | 522 | data_f1_data_out_valid <= '0'; |
|
523 | 523 | data_f1_data_out_valid_burst <= '0'; |
|
524 | 524 | data_f2_data_out_valid <= '0'; |
|
525 | 525 | data_f2_data_out_valid_burst <= '0'; |
|
526 | 526 | data_f3_data_out_valid <= '0'; |
|
527 | 527 | data_f3_data_out_valid_burst <= '0'; |
|
528 | 528 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
529 | 529 | data_f0_data_out_valid <= data_f0_data_out_valid_s; |
|
530 | 530 | data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s; |
|
531 | 531 | data_f1_data_out_valid <= data_f1_data_out_valid_s; |
|
532 | 532 | data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s; |
|
533 | 533 | data_f2_data_out_valid <= data_f2_data_out_valid_s; |
|
534 | 534 | data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s; |
|
535 | 535 | data_f3_data_out_valid <= data_f3_data_out_valid_s; |
|
536 | 536 | data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s; |
|
537 | 537 | END IF; |
|
538 | 538 | END PROCESS; |
|
539 | 539 | |
|
540 | 540 | data_f0_addr_out <= data_f0_addr_out_s; |
|
541 | 541 | data_f1_addr_out <= data_f1_addr_out_s; |
|
542 | 542 | data_f2_addr_out <= data_f2_addr_out_s; |
|
543 | 543 | data_f3_addr_out <= data_f3_addr_out_s; |
|
544 | 544 | |
|
545 | 545 | ----------------------------------------------------------------------------- |
|
546 | 546 | -- RoundRobin Selection For DMA |
|
547 | 547 | ----------------------------------------------------------------------------- |
|
548 | 548 | |
|
549 | 549 | dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst; |
|
550 | 550 | dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst; |
|
551 | 551 | dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst; |
|
552 | 552 | dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst; |
|
553 | 553 | |
|
554 | 554 | RR_Arbiter_4_1 : RR_Arbiter_4 |
|
555 | 555 | PORT MAP ( |
|
556 | 556 | clk => clk, |
|
557 | 557 | rstn => rstn, |
|
558 | 558 | in_valid => dma_rr_valid, |
|
559 | 559 | out_grant => dma_rr_grant); |
|
560 | 560 | |
|
561 | 561 | |
|
562 | 562 | ----------------------------------------------------------------------------- |
|
563 | 563 | -- in : dma_rr_grant |
|
564 | 564 | -- send |
|
565 | 565 | -- out : dma_sel |
|
566 | 566 | -- dma_valid_burst |
|
567 | 567 | -- dma_sel_valid |
|
568 | 568 | ----------------------------------------------------------------------------- |
|
569 | 569 | PROCESS (clk, rstn) |
|
570 | 570 | BEGIN -- PROCESS |
|
571 | 571 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
572 | 572 | dma_sel <= (OTHERS => '0'); |
|
573 | 573 | dma_send <= '0'; |
|
574 | 574 | dma_valid_burst <= '0'; |
|
575 | 575 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge |
|
576 | IF run = '1' THEN | |
|
576 | 577 | -- IF dma_sel = "0000" OR dma_send = '1' THEN |
|
577 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
|
578 | dma_sel <= dma_rr_grant; | |
|
579 | IF dma_rr_grant(0) = '1' THEN | |
|
580 | dma_send <= '1'; | |
|
581 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
582 | dma_sel_valid <= data_f0_data_out_valid; | |
|
583 | ELSIF dma_rr_grant(1) = '1' THEN | |
|
584 | dma_send <= '1'; | |
|
585 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
|
586 | dma_sel_valid <= data_f1_data_out_valid; | |
|
587 | ELSIF dma_rr_grant(2) = '1' THEN | |
|
588 | dma_send <= '1'; | |
|
589 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
|
590 | dma_sel_valid <= data_f2_data_out_valid; | |
|
591 | ELSIF dma_rr_grant(3) = '1' THEN | |
|
592 | dma_send <= '1'; | |
|
593 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
|
594 | dma_sel_valid <= data_f3_data_out_valid; | |
|
578 | IF dma_sel = "0000" OR dma_done = '1' THEN | |
|
579 | dma_sel <= dma_rr_grant; | |
|
580 | IF dma_rr_grant(0) = '1' THEN | |
|
581 | dma_send <= '1'; | |
|
582 | dma_valid_burst <= data_f0_data_out_valid_burst; | |
|
583 | dma_sel_valid <= data_f0_data_out_valid; | |
|
584 | ELSIF dma_rr_grant(1) = '1' THEN | |
|
585 | dma_send <= '1'; | |
|
586 | dma_valid_burst <= data_f1_data_out_valid_burst; | |
|
587 | dma_sel_valid <= data_f1_data_out_valid; | |
|
588 | ELSIF dma_rr_grant(2) = '1' THEN | |
|
589 | dma_send <= '1'; | |
|
590 | dma_valid_burst <= data_f2_data_out_valid_burst; | |
|
591 | dma_sel_valid <= data_f2_data_out_valid; | |
|
592 | ELSIF dma_rr_grant(3) = '1' THEN | |
|
593 | dma_send <= '1'; | |
|
594 | dma_valid_burst <= data_f3_data_out_valid_burst; | |
|
595 | dma_sel_valid <= data_f3_data_out_valid; | |
|
596 | END IF; | |
|
597 | ELSE | |
|
598 | dma_sel <= dma_sel; | |
|
599 | dma_send <= '0'; | |
|
595 | 600 | END IF; |
|
596 | 601 | ELSE |
|
597 | dma_sel <= dma_sel; | |
|
598 | dma_send <= '0'; | |
|
602 | dma_sel <= (OTHERS => '0'); | |
|
603 | dma_send <= '0'; | |
|
604 | dma_valid_burst <= '0'; | |
|
599 | 605 | END IF; |
|
600 | 606 | END IF; |
|
601 | 607 | END PROCESS; |
|
602 | 608 | |
|
603 | 609 | |
|
604 | 610 | dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE |
|
605 | 611 | data_f1_addr_out WHEN dma_sel(1) = '1' ELSE |
|
606 | 612 | data_f2_addr_out WHEN dma_sel(2) = '1' ELSE |
|
607 | 613 | data_f3_addr_out; |
|
608 | 614 | |
|
609 | 615 | dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE |
|
610 | 616 | data_f1_data_out WHEN dma_sel(1) = '1' ELSE |
|
611 | 617 | data_f2_data_out WHEN dma_sel(2) = '1' ELSE |
|
612 | 618 | data_f3_data_out; |
|
613 | 619 | |
|
614 | 620 | data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1'; |
|
615 | 621 | data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1'; |
|
616 | 622 | data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1'; |
|
617 | 623 | data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1'; |
|
618 | 624 | |
|
619 | 625 | dma_data_2 <= dma_data; |
|
620 | 626 | |
|
621 | 627 | |
|
622 | ||
|
628 | ||
|
623 | 629 | |
|
624 | 630 | |
|
625 | 631 | ----------------------------------------------------------------------------- |
|
626 | 632 | -- DEBUG -- DMA IN |
|
627 | 633 | debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren; |
|
628 | 634 | debug_f0_data_dma_in <= dma_data; |
|
629 | 635 | debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren; |
|
630 | 636 | debug_f1_data_dma_in <= dma_data; |
|
631 | 637 | debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren; |
|
632 | 638 | debug_f2_data_dma_in <= dma_data; |
|
633 | 639 | debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren; |
|
634 | 640 | debug_f3_data_dma_in <= dma_data; |
|
635 | 641 | ----------------------------------------------------------------------------- |
|
636 | ||
|
642 | ||
|
637 | 643 | ----------------------------------------------------------------------------- |
|
638 | 644 | -- DMA |
|
639 | 645 | ----------------------------------------------------------------------------- |
|
640 | 646 | lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst |
|
641 | 647 | GENERIC MAP ( |
|
642 | 648 | tech => inferred, |
|
643 | 649 | hindex => hindex) |
|
644 | 650 | PORT MAP ( |
|
645 | 651 | HCLK => clk, |
|
646 | 652 | HRESETn => rstn, |
|
647 | 653 | run => run, |
|
648 | 654 | AHB_Master_In => ahbi, |
|
649 | 655 | AHB_Master_Out => ahbo, |
|
650 | 656 | |
|
651 |
send => dma_send, |
|
|
652 |
valid_burst => dma_valid_burst, |
|
|
657 | send => dma_send, | |
|
658 | valid_burst => dma_valid_burst, | |
|
653 | 659 | done => dma_done, |
|
654 | 660 | ren => dma_ren, |
|
655 |
address => dma_address, |
|
|
661 | address => dma_address, | |
|
656 | 662 | data => dma_data_2); |
|
657 | 663 | |
|
658 | 664 | ----------------------------------------------------------------------------- |
|
659 | 665 | -- Matrix Spectral - TODO |
|
660 | 666 | ----------------------------------------------------------------------------- |
|
661 | 667 | ----------------------------------------------------------------------------- |
|
662 | 668 | --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & |
|
663 | 669 | -- NOT(sample_f0_val) & NOT(sample_f0_val) ; |
|
664 | 670 | --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
|
665 | 671 | -- NOT(sample_f1_val) & NOT(sample_f1_val) ; |
|
666 | 672 | --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) & |
|
667 | 673 | -- NOT(sample_f3_val) & NOT(sample_f3_val) ; |
|
668 | 674 | |
|
669 | 675 | --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
|
670 | 676 | --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
|
671 | 677 | --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16)); |
|
672 | 678 | ------------------------------------------------------------------------------- |
|
673 | 679 | --lpp_lfr_ms_1: lpp_lfr_ms |
|
674 | 680 | -- GENERIC MAP ( |
|
675 | 681 | -- hindex => hindex_ms) |
|
676 | 682 | -- PORT MAP ( |
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677 | 683 | -- clk => clk, |
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678 | 684 | -- rstn => rstn, |
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679 | 685 | -- sample_f0_wen => sample_f0_wen, |
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680 | 686 | -- sample_f0_wdata => sample_f0_wdata, |
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681 | 687 | -- sample_f1_wen => sample_f1_wen, |
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682 | 688 | -- sample_f1_wdata => sample_f1_wdata, |
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683 | 689 | -- sample_f3_wen => sample_f3_wen, |
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684 | 690 | -- sample_f3_wdata => sample_f3_wdata, |
|
685 | 691 | -- AHB_Master_In => ahbi_ms, |
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686 | 692 | -- AHB_Master_Out => ahbo_ms, |
|
687 | 693 | |
|
688 | 694 | -- ready_matrix_f0_0 => ready_matrix_f0_0, |
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689 | 695 | -- ready_matrix_f0_1 => ready_matrix_f0_1, |
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690 | 696 | -- ready_matrix_f1 => ready_matrix_f1, |
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691 | 697 | -- ready_matrix_f2 => ready_matrix_f2, |
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692 | 698 | -- error_anticipating_empty_fifo => error_anticipating_empty_fifo, |
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693 | 699 | -- error_bad_component_error => error_bad_component_error, |
|
694 | 700 | -- debug_reg => debug_reg, |
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695 | 701 | -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0, |
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696 | 702 | -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1, |
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697 | 703 | -- status_ready_matrix_f1 => status_ready_matrix_f1, |
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698 | 704 | -- status_ready_matrix_f2 => status_ready_matrix_f2, |
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699 | 705 | -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, |
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700 | 706 | -- status_error_bad_component_error => status_error_bad_component_error, |
|
701 | 707 | -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, |
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702 | 708 | -- config_active_interruption_onError => config_active_interruption_onError, |
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703 | 709 | -- addr_matrix_f0_0 => addr_matrix_f0_0, |
|
704 | 710 | -- addr_matrix_f0_1 => addr_matrix_f0_1, |
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705 | 711 | -- addr_matrix_f1 => addr_matrix_f1, |
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706 | 712 | -- addr_matrix_f2 => addr_matrix_f2); |
|
707 | 713 | |
|
708 | 714 | END beh; |
@@ -1,200 +1,218 | |||
|
1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
18 | 18 | ------------------------------------------------------------------------------ |
|
19 | 19 | -- Author : Jean-christophe PELLION |
|
20 | 20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr |
|
21 | 21 | ------------------------------------------------------------------------------ |
|
22 | 22 | LIBRARY IEEE; |
|
23 | 23 | USE IEEE.std_logic_1164.ALL; |
|
24 | 24 | USE IEEE.numeric_std.ALL; |
|
25 | 25 | LIBRARY lpp; |
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26 | 26 | USE lpp.lpp_memory.ALL; |
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27 | 27 | USE lpp.iir_filter.ALL; |
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28 | 28 | USE lpp.lpp_waveform_pkg.ALL; |
|
29 | 29 | |
|
30 | 30 | LIBRARY techmap; |
|
31 | 31 | USE techmap.gencomp.ALL; |
|
32 | 32 | |
|
33 | 33 | ENTITY lpp_waveform_fifo_headreg IS |
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34 | 34 | GENERIC( |
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35 | 35 | tech : INTEGER := 0 |
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36 | 36 | ); |
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37 | 37 | PORT( |
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38 | 38 | clk : IN STD_LOGIC; |
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39 | 39 | rstn : IN STD_LOGIC; |
|
40 | 40 | --------------------------------------------------------------------------- |
|
41 | 41 | run : IN STD_LOGIC; |
|
42 | 42 | --------------------------------------------------------------------------- |
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43 | 43 | o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b |
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44 | 44 | o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
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45 | 45 | o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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46 | 46 | o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
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47 | 47 | o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
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48 | 48 | o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
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49 | 49 | o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- |
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50 | 50 | --------------------------------------------------------------------------- |
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51 | 51 | i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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52 | 52 | i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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53 | 53 | i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- |
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54 | 54 | i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
|
55 | 55 | ); |
|
56 | 56 | END ENTITY; |
|
57 | 57 | |
|
58 | 58 | |
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59 | 59 | ARCHITECTURE ar_lpp_waveform_fifo_headreg OF lpp_waveform_fifo_headreg IS |
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60 | 60 | SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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61 | 61 | SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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62 | 62 | SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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63 | 63 | SIGNAL one_ren_and_notEmpty : STD_LOGIC; |
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64 | 64 | SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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65 | 65 | SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); |
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66 | 66 | SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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67 | 67 | SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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68 | 68 | SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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69 | 69 | SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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70 | 70 | BEGIN |
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71 | 71 | |
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72 | 72 | ----------------------------------------------------------------------------- |
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73 | 73 | -- DATA_REN_FIFO |
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74 | 74 | ----------------------------------------------------------------------------- |
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75 | 75 | i_data_ren <= s_ren; |
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76 | 76 | PROCESS (clk, rstn) |
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77 | 77 | BEGIN |
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78 | 78 | IF rstn = '0' THEN |
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79 | 79 | s_ren_reg <= (OTHERS => '1'); |
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80 | 80 | ELSIF clk'EVENT AND clk = '1' THEN |
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81 | s_ren_reg <= s_ren; | |
|
81 | IF run = '1' THEN | |
|
82 | s_ren_reg <= s_ren; | |
|
83 | ELSE | |
|
84 | s_ren_reg <= (OTHERS => '1'); | |
|
85 | END IF; | |
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82 | 86 | END IF; |
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83 | 87 | END PROCESS; |
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84 | 88 | |
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85 | 89 | s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE |
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86 | 90 | NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); |
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87 | 91 | s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE |
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88 | 92 | '1' WHEN s_ren(0) = '0' ELSE |
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89 | 93 | NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); |
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90 | 94 | s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE |
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91 | 95 | '1' WHEN s_ren(0) = '0' ELSE |
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92 | 96 | '1' WHEN s_ren(1) = '0' ELSE |
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93 | 97 | NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); |
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94 | 98 | s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE |
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95 | 99 | '1' WHEN s_ren(0) = '0' ELSE |
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96 | 100 | '1' WHEN s_ren(1) = '0' ELSE |
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97 | 101 | '1' WHEN s_ren(2) = '0' ELSE |
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98 | 102 | NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); |
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99 | 103 | ----------------------------------------------------------------------------- |
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100 | 104 | all_ren : FOR I IN 3 DOWNTO 0 GENERATE |
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101 | 105 | ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I)); |
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102 | 106 | END GENERATE all_ren; |
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103 | 107 | one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1'; |
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104 | 108 | |
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105 | 109 | ----------------------------------------------------------------------------- |
|
106 | 110 | -- DATA |
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107 | 111 | ----------------------------------------------------------------------------- |
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108 | 112 | o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0; |
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109 | 113 | o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1; |
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110 | 114 | o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2; |
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111 | 115 | o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3; |
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112 | 116 | |
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113 | 117 | PROCESS (clk, rstn) |
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114 | 118 | BEGIN |
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115 | 119 | IF rstn = '0' THEN |
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116 | 120 | s_rdata_0 <= (OTHERS => '0'); |
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117 | 121 | s_rdata_1 <= (OTHERS => '0'); |
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118 | 122 | s_rdata_2 <= (OTHERS => '0'); |
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119 | 123 | s_rdata_3 <= (OTHERS => '0'); |
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120 | 124 | ELSIF clk'EVENT AND clk = '1' THEN |
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121 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; | |
|
122 |
IF s_ren_reg( |
|
|
123 |
IF s_ren_reg( |
|
|
124 |
IF s_ren_reg( |
|
|
125 | IF run = '1' THEN | |
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126 | IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; | |
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127 | IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF; | |
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128 | IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; | |
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129 | IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; | |
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130 | ELSE | |
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131 | s_rdata_0 <= (OTHERS => '0'); | |
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132 | s_rdata_1 <= (OTHERS => '0'); | |
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133 | s_rdata_2 <= (OTHERS => '0'); | |
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134 | s_rdata_3 <= (OTHERS => '0'); | |
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135 | END IF; | |
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125 | 136 | END IF; |
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126 | 137 | END PROCESS; |
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127 | 138 | |
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128 | 139 | all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE |
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129 | 140 | PROCESS (clk, rstn) |
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130 | 141 | BEGIN |
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131 | 142 | IF rstn = '0' THEN |
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132 | 143 | reg_full(I) <= '0'; |
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133 | 144 | ELSIF clk'EVENT AND clk = '1' THEN |
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134 | 145 | -- IF s_ren_reg(I) = '0' THEN |
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135 |
IF |
|
|
136 |
|
|
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137 | ELSIF o_data_ren(I) = '0' THEN | |
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146 | IF run = '1' THEN | |
|
147 | IF s_ren(I) = '0' THEN | |
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148 | reg_full(I) <= '1'; | |
|
149 | ELSIF o_data_ren(I) = '0' THEN | |
|
150 | reg_full(I) <= '0'; | |
|
151 | END IF; | |
|
152 | ELSE | |
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138 | 153 | reg_full(I) <= '0'; |
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139 | 154 | END IF; |
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140 | 155 | END IF; |
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141 | 156 | END PROCESS; |
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142 | 157 | END GENERATE all_reg_full; |
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143 | 158 | |
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144 | 159 | ----------------------------------------------------------------------------- |
|
145 | 160 | -- EMPTY |
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146 | 161 | ----------------------------------------------------------------------------- |
|
147 | 162 | o_empty <= NOT reg_full; |
|
148 | 163 | |
|
149 | 164 | ----------------------------------------------------------------------------- |
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150 | 165 | -- EMPTY_ALMOST |
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151 | 166 | ----------------------------------------------------------------------------- |
|
152 | 167 | o_empty_almost <= s_empty_almost; |
|
153 | 168 | |
|
154 | 169 | all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE |
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155 | 170 | PROCESS (clk, rstn) |
|
156 | 171 | BEGIN -- PROCESS |
|
157 | 172 | IF rstn = '0' THEN -- asynchronous reset (active low) |
|
158 | 173 | s_empty_almost(I) <= '1'; |
|
159 | 174 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge |
|
160 |
|
|
|
161 | IF s_ren(I) = '0' THEN | |
|
162 | s_empty_almost(I) <= i_empty_almost(I); | |
|
163 | ELSIF o_data_ren(I) = '0' THEN | |
|
175 | IF run = '1' THEN | |
|
176 | IF s_ren(I) = '0' THEN | |
|
177 | s_empty_almost(I) <= i_empty_almost(I); | |
|
178 | ELSIF o_data_ren(I) = '0' THEN | |
|
179 | s_empty_almost(I) <= '1'; | |
|
180 | ELSE | |
|
181 | IF i_empty_almost(I) = '0' THEN | |
|
182 | s_empty_almost(I) <= '0'; | |
|
183 | END IF; | |
|
184 | END IF; | |
|
185 | ELSE | |
|
164 | 186 | s_empty_almost(I) <= '1'; |
|
165 | ELSE | |
|
166 | IF i_empty_almost(I) = '0' THEN | |
|
167 | s_empty_almost(I) <= '0'; | |
|
168 | END IF; | |
|
169 | 187 | END IF; |
|
170 | 188 | END IF; |
|
171 | 189 | END PROCESS; |
|
172 | 190 | END GENERATE all_empty_almost; |
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173 | 191 | |
|
174 | 192 | END ARCHITECTURE; |
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175 | 193 | |
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176 | 194 | |
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177 | 195 | |
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178 | 196 | |
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179 | 197 | |
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180 | 198 | |
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181 | 199 | |
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182 | 200 | |
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183 | 201 | |
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184 | 202 | |
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185 | 203 | |
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186 | 204 | |
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187 | 205 | |
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188 | 206 | |
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189 | 207 | |
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190 | 208 | |
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194 | 212 | |
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195 | 213 | |
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196 | 214 | |
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198 | 216 | |
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199 | 217 | |
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200 | 218 |
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